JP2018025391A - Speed detector and speed control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an offset error in speed detection without changing interrupt cycles.SOLUTION: Provided is a speed detector comprising: pulse information acquisition units (51-58) for acquiring pulse information for each set sampling cycle on the basis of output pulses of a pulse encoder 50; a pulse phase buffer 61 for storing the pulse phase information for each sampling cycle; a pulse time buffer 62 for storing pulse occurrence time information; past information selection units (64, 65) for selecting pulse phase information prior to a plurality of sampling cycles in the buffer 61 and selecting pulse occurrence time information prior to the plurality of sampling cycles in the buffer 62 by a selection signal Sel that selects the pulse information acquired and stored before the plurality of sampling cycles; and speed detection computation units (66-68) for computing a speed detection value on the basis of a difference between the latest pulse phase and a pulse phase prior to the plurality of sampling cycles and a difference between the latest pulse occurrence time and a pulse occurrence time prior to the plurality of sampling cycles.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for detecting the rotational speed of a rotating machine (motor, generator, etc.), such as a variable speed device, and a speed control system therefor. The rotational position sensor targeted by the present invention is a two-phase pulse encoder having a phase difference of 90 degrees, and detects the speed from the number of generated pulses and the time difference. The advantages and disadvantages change when the length of the speed detection period is changed. The present invention relates to a detection method and a speed control method that make use of only these advantages.

  As a prior art document, there is Patent Document 1, and this principle is described in Non-Patent Document 1. Patent Document 1 proposes a method of detecting speed at a constant period (speed calculation period signal SMPL) in an encoder that outputs a two-phase square wave signal having a 90 ° phase difference.

  The feature of Patent Document 1 is that a 90 ° phase difference error of a two-phase signal is large, so four detection circuits corresponding to four types of pulse edges are mounted, and data of the same edge type is obtained from these four types of detection values. The accuracy of speed detection is improved by selecting and calculating the phase difference and time difference.

  The present invention basically detects the speed by dividing the phase difference of the generated pulse by the time difference in the same manner as in the conventional example, but does not require the feature of the 4-multiplex system as in Patent Document 1. . Instead, it proposes a method that allows a general speed detection period to be variably set or a combination of a plurality of speed detections having different speed detection periods.

  Therefore, in order to simplify the explanation, an example of a one-phase pulse signal is adopted and explained. If this principle can be easily extended to the 4-multiplex system as in Patent Document 1, description of combining different systems is omitted here.

Japanese Patent No. 3173174

The Institute of Electrical Engineers of Japan, Electrical Theory D, Vol.155, No.11, pp 1316-1324

  In the conventional speed detection method, the pulse signal output from the encoder is sequentially measured by a digital circuit that operates with a high-speed clock, and the pulse generation time and pulse counter value (phase information) are measured. Stored in a latch (register). Simultaneously with this sample signal, an interrupt signal is given to an arithmetic processing unit such as a CPU. When the speed detection process is activated by this interrupt signal, the latch data is read out, and the speed detection calculation is performed from the difference from the time and phase detection information read up to the previous time.

  The problem addressed in this specification is a phenomenon in which an offset error occurs in speed detection when a fluctuation of the generation time called jitter occurs in the pulse signal generated by this encoder, and speed detection is performed to suppress this error. It is proposed to select an appropriate one with variable duration.

  For example, in the case of a one-phase pulse signal at a constant speed as shown in FIG. 10A, the speed can be detected from detection information between pulses P1a and P1b and the other pulse P1b and P1c. On the other hand, in order to show the principle that an error is generated due to fluctuations in the pulse generation time due to jitter, it is assumed that the generation time of the pulse P1b is shifted by ΔT and generated at the time of the pulse P2b as shown in FIG. To explain.

  In FIG. 10A where there is no ideal jitter error, the speed can be detected twice. The equation (1a) is obtained between the pulses P1a and P1b, and the equation (1b) is obtained between the pulses P1b and P1c. Similarly, in the case of FIG. 10B, the calculation is performed as equations (2a) and (2b).

ω1ab = (θ1b−θ1a) / (t1b−t1a) (1a)
ω1bc = (θ1c−θ1b) / (t1c−t1b) (1b)
ω2ab = (θ2b−θ2a) / (t2b−t2a) (2a)
ω2bc = (θ2c−θ2b) / (t2c−t2b) (2b)
Here, in order to specifically show the influence of the error, a temporary numerical value is substituted. In the speed calculation, it is assumed that the generated phase difference of the encoder pulse is constant. Therefore, the phase difference between the pulses is equal as shown in the equation (3) in FIG. 10 (a) and FIG. 10 (b). Here, the value is assumed to be “1”.

(Θ1b−θ1a) = (θ1c−θ1b) = (θ2b−θ2a) = (θ2c−θ2b) = 1 (3)
Regarding the time difference, the ideal time pulse with no jitter shown in FIG. 10A has the same time difference between the two as shown in equation (4).

(T1b-t1a) = (t1c-t1b) = 1 (4)
On the other hand, on the side of FIG. 10 (b), assuming that the time fluctuation (deviation of the generation time) due to jitter is ΔT = 0.3, the two time differences are as shown in equations (5a) and (5b). It becomes a different value.

(T2b-t2a) = 1 + 0.3 = 1.3 (5a)
(T2c-t2b) = 1-0.3 = 0.7 (5b)
Under this assumption, when calculating the four velocities of (1a), (1b), (2a) and (2b), the following values are obtained, and (1a ′) It becomes clear that the speed detection error caused by the jitter is included in the expressions (2a ′) and (2b ′) with respect to the true speed 1.0 indicated by the expression (1b ′).

ω1ab = (θ1b−θ1a) / (t1b−t1a) = 1/1 = 1.0 (1a ′)
ω1bc = (θ1c−θ1b) / (t1c−t1b) = 1/1 = 1.0 (1b ′)
ω2ab = (θ2b−θ2a) / (t2b−t2a) = 1 / 1.3≈0.76923 (2a ′)
ω2bc = (θ2c−θ2b) / (t2c−t2b) = 1 / 0.7≈1.42857 (2b ′)
Next, as a conventional example, a method of suppressing this speed detection error by a statistical method, that is, a method of taking the simplest two average values will be considered.

  In the case of an ideal pulse, the average value of the equations (1a ′) and (1b ′) is the equation (6), which is still a true value.

ω1ave_ac = (ω1ab + ω1bc) / 2 = (1.0 + 1.0) /2=1.0 (6)
In the case of a pulse including jitter, the average value of the equations (2a ′) and (2b ′) is the equation (7) and does not match the true value, so the error does not become zero.

ω2ave_ac = (ω2ab + ω2bc) / 2≈ (0.76923 + 1.428857) /2=1.0989 (7)
Since it is only the timing of the intermediate pulse P1b that includes a time error due to jitter, it is often assumed that the error can be made zero by intuitively averaging the speeds on both sides. In practice, however, an offset error remains in statistical processing. This is the real problem to be solved by the present invention. Now, why the average value does not become zero will be described below.

  Although numerical examples have been shown so far, the graph of FIG. 11 is used for explaining the offset error. In FIG. 11, the horizontal axis represents the time difference (T) like the denominator of the expressions (2a ′) and (2b ′), and the vertical axis represents the speed detection that is the calculation result of the expressions (2a ′) and (2b ′). (Ω) is plotted. Since there is an error time (+ ΔT, -ΔT) due to jitter, when a perpendicular line is drawn from two points on the horizontal axis and the velocity detection values are plotted on this perpendicular line, these exist on the characteristics that are inversely proportional to the origin. Will do.

  Since the error component exists only in the fractional denominator, it is easy to imagine that the error distribution is inversely proportional. If the error distribution exists on a "straight line of -1", the error becomes zero if the average value of the two points is taken. However, like the speed error in the equations (2a ′) and (2b ′), the speed detection based on the jitter includes an inverse proportional characteristic, that is, an error in a direction in which the amplitude is always larger than the “−1 slope straight line”. Therefore, even if a large amount of average processing is performed, the error cannot be made zero, and an offset error that the amplitude always becomes larger than the true value remains. This is a problem and will be referred to herein as “speed offset error due to jitter” or simply “offset error”.

  The above problem is caused by a variation in pulse generation time called jitter, and if the error is relatively small and the speed is detected at a time interval that can be ignored, a large speed error should not occur. Rather than performing statistical processing, the numerator phase difference (pulse count difference) should be increased so that the value of the time difference of the denominator in the speed detection calculation is increased. For example, in the example of FIG. 10 (b), rather than statistically processing speed detection in a short detection period as in equation (7), at a long interval of 3 pulses from P2a to P2c as in equation (8), It is more effective to suppress the offset error by dividing the numerator and denominator separately.

ω2ave_ac ′ = (θ2c−θ2a) / (t2c−t2a) (8)
Conventionally, an empirical rule that “the longer the detection period is, the better the accuracy” is known. However, strictly speaking, it seems that the principle of “offset error” is not generally recognized. Therefore, it is easy to be misunderstood that the measurement time can be shortened and solved by statistical processing. Therefore, by explaining in detail as described above, it has been clarified that there is a limit to the importance of appropriate selection of measurement time and the effect of statistical processing on this subject. Up to this point, it was a limited part of speed detection, but from now on, we will expand the field of view to the speed control system and propose a method for suppressing this offset error.

  In Patent Document 1, the sample time (CPU interruption period) dominates this speed detection time. To increase the accuracy simply, the time difference in speed detection may be increased, but at the same time, the detection delay (waste time) also increases, which becomes a factor that limits the responsiveness of speed control. Conversely, if the speed detection time is shortened, although the speed detection error is large, the time delay (waste time) is reduced, so that the responsiveness can be improved. However, since the variation in speed detection error due to jitter increases, a large pulsation component is generated in the torque command that is the speed control output during motor control, resulting in a problem that the torque quality deteriorates.

  Considering the cause of this jitter, the amount of jitter is not constant because it is caused by variations in the principle type of encoder and assembly accuracy. Therefore, in order to satisfy the conflicting requirement that “speed control accuracy and response performance can be compatible”, it is necessary to adjust and change the speed detection time (interrupt cycle) according to the situation of the individual system. However, if the CPU interrupt cycle itself is changed, there is a fear that the characteristic may be changed for control operations other than speed control executed by the same interrupt processing.

  SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object of the present invention is to provide a speed detection device and a speed control system capable of improving speed detection accuracy by suppressing an offset error in speed detection without changing an interrupt cycle. It is to provide.

The speed detection device according to claim 1 for solving the above problem is a speed detection device for detecting a rotation speed of a rotating machine,
Based on the output pulse of the pulse encoder that detects the rotation angle of the rotating machine, for each set sample period, a pulse information acquisition unit that acquires pulse presence information, pulse phase information, and pulse generation time information;
A pulse phase buffer for storing each of the pulse phase information acquired for each sample period;
A pulse time buffer for storing each of the pulse generation time information acquired for each sample period;
A selection signal setting unit for setting a selection signal for selecting pulse information acquired and stored before a plurality of sample periods;
Past selecting pulse phase information before a plurality of sample periods in the pulse phase buffer according to a selection signal set by the selection signal setting unit, and selecting pulse generation time information before a plurality of sample periods in the pulse time buffer An information selector,
The difference between the latest pulse phase in the pulse phase buffer and the pulse phase before a plurality of sample periods selected by the past information selection unit, the latest pulse generation time in the pulse time buffer, and the past information selection unit are selected. A speed detection calculation unit that calculates a speed detection value based on a difference from a pulse generation time before a plurality of sample periods;
It is provided with.

The speed detection device according to claim 2 is the method according to claim 1,
The pulse information acquisition unit
A waveform shaping circuit that shapes the output pulse from the pulse encoder to detect rising and falling edges of the pulse; and
A pulse phase up / down counter that counts up / down at the rising edge and falling edge of the pulse detected by the waveform shaping circuit and outputs the count value as a pulse phase value;
A timer circuit that counts the reference clock, outputs time data, and outputs an interrupt signal for each set sample period;
A pulse generation time measuring circuit that stores and holds time data of the timer circuit when a detection signal of each edge of a pulse is input from the waveform shaping circuit, and outputs the pulse generation time;
Set by the detection signal at each edge of the pulse from the waveform shaping circuit, reset by the interrupt signal from the timer circuit, and the presence / absence of a pulse indicating whether or not a pulse has occurred during the generation period of the interrupt signal A flip-flop circuit that outputs a signal;
Using the interrupt signal from the timer circuit as an enable signal, the pulse phase value sent from the pulse phase up / down counter, the pulse generation time sent from the pulse generation time measuring circuit, and the pulse sent from the flip-flop circuit A read buffer for holding presence / absence signals,
The pulse phase buffer and the pulse time buffer use the AND signal of the interrupt signal from the timer circuit and the pulse presence / absence signal from the read buffer as an enable signal, and determine the pulse phase value and pulse generation time of the read buffer. Each of the latest information storage buffer and the n-stage (n is an integer) past information storage buffer is configured to read and store,
The selection signal of the selection signal setting unit is set to a signal for designating any one of the n stages of past information storage buffers,
The past information selection unit selects information of a buffer at a stage specified by a selection signal of the selection signal setting unit from among the n stages of past information storage buffers;
It is characterized by that.

  According to the above configuration, the speed detection period from the pulse information before a plurality of pulse periods to the latest pulse information can be lengthened (set by the selection signal setting unit), and due to fluctuations in pulse signal generation time in speed detection It is possible to improve the speed detection accuracy by suppressing the offset error.

The speed detection device according to claim 3 is the method according to claim 1.
The selection signal setting unit includes:
A first selection signal for selecting pulse information acquired and stored before the first sample period, and a pulse acquired and stored before the second sample period before the first sample period And a second selection signal for selecting information,
The past information selection unit
First past information selection for selecting pulse phase information before the first sample period in the pulse phase buffer and pulse time information before the first sample period in the pulse time buffer by the first selection signal And
Second past information selection for selecting the pulse phase information before the second sample period in the pulse phase buffer and the pulse time information before the second sample period in the pulse time buffer by the second selection signal And
The speed detection calculation unit
The difference between the latest pulse phase in the pulse phase buffer and the pulse phase before the first sample period selected by the first past information selection unit, the latest pulse generation time in the pulse time buffer, and the first A first speed detection calculation unit that calculates a first speed detection value based on a difference from a pulse generation time before the first sample period selected by the past information selection unit;
The difference between the latest pulse phase in the pulse phase buffer and the pulse phase before the second sample period selected by the second past information selection unit, the latest pulse generation time in the pulse time buffer, and the second A second speed detection calculation unit that calculates a second speed detection value based on a difference from a pulse generation time before the second sample period selected by the past information selection unit. And

A speed detection device according to claim 4 is the speed detection device according to claim 2,
The selection signal setting unit includes:
A first selection signal that designates one of the n stages of past information storage buffers acquired and stored before the first sample period, and a first selection signal before the first sample period; A second selection signal that designates any one of the n stages of past information storage buffers obtained and stored before two sample periods;
The past information selection unit
The pulse phase information before the first sampling period in the past information storage buffer of the pulse phase buffer and the first in the past information storage buffer of the pulse time buffer at the stage specified by the first selection signal. A first past information selection unit for selecting pulse time information before the sample period;
The pulse phase information before the second sample period in the past information storage buffer of the pulse phase buffer and the second in the past information storage buffer of the pulse time buffer at the stage specified by the second selection signal. A second past information selection unit for selecting the pulse time information before the sample period,
The speed detection calculation unit
The difference between the latest pulse phase in the latest information storage buffer of the pulse phase buffer and the pulse phase before the first sample period selected by the first past information selection unit, and the latest information storage of the pulse time buffer A first speed for calculating a first speed detection value based on a difference between the latest pulse generation time in the buffer and a pulse generation time before the first sample period selected by the first past information selection unit A detection calculation unit;
The difference between the latest pulse phase in the latest information storage buffer of the pulse phase buffer and the pulse phase before the second sample period selected by the second past information selection unit, and the latest information storage of the pulse time buffer Second speed for calculating the second speed detection value based on the difference between the latest pulse generation time in the buffer and the pulse generation time before the second sample period selected by the second past information selection unit And a detection calculation unit.

  The speed detection period is longer between the time before the second sample period set by the second selection signal and the latest time than between the time before the first sample period set by the first selection signal and the latest time. . For this reason, according to the above configuration, it is possible to perform speed detection calculation using two different speed detection periods. For example, a speed detection calculation (first speed detection calculation unit) based on a short speed detection period and a speed detection period set long. Speed detection calculation (second speed detection calculation unit) by performing a speed detection value (first speed detection value) that satisfies fast response performance and a speed detection value (second speed) that satisfies high speed detection accuracy. Both speed detection values) can be obtained.

The speed control system according to claim 5 is:
A proportional control term that performs proportional control with respect to the deviation between the speed command of the rotating machine and the detected speed value of the rotating machine, and an integral control term that performs integral control with respect to the deviation between the speed command of the rotating machine and the detected speed value of the rotating machine. And a speed control system for controlling the speed of the rotating machine,
The speed detection device according to claim 3 or 4,
As the speed detection value of the rotating machine in the proportional control term, using the first speed detection value calculated by the first speed detection calculation unit of the speed detection device,
As the speed detection value of the rotating machine in the integral control term, the second speed detection value calculated by the second speed detection calculation unit of the speed detection device is used.
It is characterized by that.

  According to the above configuration, since the first speed detection value that satisfies the quick response performance with a short speed detection period is used as the speed detection value of the proportional control term, the waste time is reduced and the response performance is improved.

  Further, since the second speed detection value that has a long speed detection period and satisfies the high speed detection accuracy is used as the speed detection value of the integral control term, the speed control accuracy is improved (the speed detection period is long and the waste time is large). Even if it becomes, there is little adverse effect on the control of the integral term). Therefore, it is possible to construct a control system that achieves both speed control accuracy and response performance.

Further, the speed control system according to claim 6 is:
A proportional control term that performs proportional control with respect to the deviation between the speed command of the rotating machine and the detected speed value of the rotating machine, and an integral control term that performs integral control with respect to the deviation between the speed command of the rotating machine and the detected speed value of the rotating machine. And a speed control system for controlling the speed of the rotating machine,
A speed detection device according to claim 4,
A speed command / phase command conversion circuit that obtains a phase command by integrating the speed command of the rotating machine over time is provided.
A phase command read buffer for holding an interrupt signal from the timer circuit of the speed detection device as an enable signal and holding the phase command obtained by the speed command / phase command conversion circuit;
The latest information storage buffer and the n-stage (n is an integer) past information storage buffer, and a pulse presence / absence signal from the read buffer of the speed detection device is used as an enable signal in the phase command read buffer. A phase command buffer for reading and storing the phase command;
A phase command for selecting the phase command before the second sample period in the past information storage buffer of the phase command buffer at the stage specified by the second selection signal set by the selection signal setting unit of the speed detection device. 3 past information selection sections;
The difference between the latest phase command in the latest information storage buffer of the phase command buffer and the phase command before the second sample period selected by the third past information selection unit is calculated as a second value of the speed detection device. An arithmetic circuit that divides by the difference between the latest pulse generation time and the pulse generation time before the second sample period in the speed detection calculation unit,
An average speed command calculation unit for obtaining an average speed command is further provided.
As the speed command of the rotating machine in the integral control term, using the averaged speed command obtained by the averaged speed command calculation unit,
As the speed detection value of the rotating machine in the proportional control term, using the first speed detection value calculated by the first speed detection calculation unit of the speed detection device,
The second speed detection value calculated by the second speed detection calculation unit of the speed detection device is used as the speed detection value of the rotating machine in the integral control term.

  According to the above configuration, in the integral control term, during acceleration, the difference between the second speed detection value having a long speed detection period and a large waste time and the average speed command becomes small, and the influence of the speed detection delay time is reduced. it can. For this reason, the amount of the detection time delay component that accumulates in the integrator during acceleration is suppressed, and overshoot due to the release of the amount accumulated in the integrator when shifting to a constant speed can be suppressed. This improves the accuracy of speed control.

(1) According to the first to sixth aspects of the invention, the offset error in the speed detection is suppressed, and the speed detection accuracy is improved.
(2) According to the third and fourth aspects of the invention, speed detection calculation can be performed by two different speed detection periods. For example, speed detection calculation by a short speed detection period (first speed detection calculation unit) And a speed detection calculation (second speed detection calculation unit) with a long speed detection period, a speed detection value (first speed detection value) that satisfies fast response performance and high speed detection accuracy. Both satisfying speed detection values (second speed detection values) can be obtained.
(3) According to the invention described in claim 5, since the first speed detection value that satisfies the quick response performance with a short speed detection period is used as the speed detection value of the proportional control term, the waste time is reduced. Response performance is improved.

Further, since the second speed detection value that has a long speed detection period and satisfies the high speed detection accuracy is used as the speed detection value of the integral control term, the speed control accuracy is improved (the speed detection period is long and the waste time is large). Even if it becomes, there is little adverse effect on the control of the integral term). Therefore, it is possible to construct a control system that achieves both speed control accuracy and response performance.
(4) According to the invention described in claim 6, in the integral control term, the amount of the detection time delay component accumulated in the integrator during acceleration is suppressed, and accumulated in the integrator when shifting to a constant speed. Overshoot due to the release of the amount can be suppressed. This improves the accuracy of speed control.

1 is an overall configuration diagram of a speed detection device according to a first embodiment of the present invention. The principal part block diagram in Example 1 of this invention. The time chart explaining operation | movement of the speed detection apparatus of Example 1 of this invention. The block diagram of the speed detection apparatus by Example 2 of this invention. The block diagram of the speed control system by Example 2 of this invention. The speed-time characteristic figure explaining the problem which arises because of the difference with the speed command by speed detection delay time. The block diagram of the speed detection apparatus by Example 3 of this invention. The block diagram of the speed control system by Example 3 of this invention. The speed-time characteristic view explaining the effect by Example 3 of this invention. Explanatory drawing which shows the relationship between the pulse signal which an encoder generate | occur | produces, a phase, and time. Explanatory drawing showing that the offset error of speed detection cannot be eliminated by the averaging process when the pulse generation time fluctuates.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments because the digital circuit and the CPU operation can be replaced with each other. . In the present embodiment, first, a method is proposed as Example 1 in which the speed detection time can be arbitrarily variably set in an individual apparatus while the interrupt period is fixed. Then, in the second and subsequent embodiments, a further improvement measure “which can achieve both speed control accuracy and response performance” is proposed.

  FIG. 1 shows the configuration of the speed detection apparatus of the first embodiment. The configuration of FIG. 1 is roughly divided into a “digital detection circuit” on the left side and a “CPU calculation” on the right side. The part of the digital detection circuit is basically the same as the detection circuit of Patent Document 1 or Non-Patent Document 1. However, since it becomes complicated when considering the switching between the 4-multiplex system circuit and the forward rotation and the reverse rotation, in the present invention, in order to simplify the explanation, the output of the waveform shaping circuit that shapes the output pulse from the pulse encoder is Only one-phase pulse signals with only forward rotation pulses (Edg_up) as shown in FIG.

  In FIG. 1, reference numeral 50 denotes a pulse encoder that detects the rotation angle of a rotating machine, and generates a pulse signal in accordance with the phase of a rotating body such as a motor.

  A waveform shaping circuit 51 shapes the output pulse from the pulse encoder 50. The rising and falling edges of the output pulse of the pulse encoder 50 are detected, and the UP / DOWN signal (Edg_up / Edg_dw).

  52 is an OR circuit that performs an OR operation on the UP / DOWN signal of the counter output from the waveform shaping circuit 51 and outputs a pulse generation signal Edg. Hereinafter, the “pulse generation signal” may be used simply as “pulse”.

  53 is a pulse phase up / down counter that counts up / down at the rising and falling edges of the pulse detected by the waveform shaping circuit 51 and outputs the count value as a pulse phase value (θpp). The counter value θpp is incremented (Up) / decremented (Dw) by the signal (Edg_up / Edg_dw).

  A timer circuit 54 generates a reference time for measuring the pulse generation time, counts the reference clock of the digital circuit, and outputs time data t. The timer circuit 54 also has a function of outputting an interrupt signal Smpl (m) for each sample period in accordance with the sample period setting input from the CPU via the D-type flip-flop 55.

  Here, (m) of Smpl (m) is an identifier for indicating the timing of occurrence, and specific values of m are represented as “m1, m2, m3...”. 56 is a pulse generation time measuring circuit that stores and holds the time data t output from the timer circuit 54 when the pulse generation signal Edg is generated, and outputs it as the pulse generation time tpp. The output (Edg) of the OR circuit 52 ) Is a latch circuit (DEN-ff) using an enable signal.

  57 is set by the pulse generation signal Edg from the OR circuit 52, reset by the interrupt signal Smpl (m) from the timer circuit 54, and a pulse edge (Edg) is generated during the generation period of the interrupt signal. It is a flip-flop circuit that detects whether or not. This flip-flop circuit 57 is a set-priority SR-flip flop (SRff) circuit. If no pulse edge (Edg) occurs between the interrupt signals Smpl (m), the flip-flop circuit 57 is “0”. A pulse presence / absence flag of “1” is output and output to the next-stage read buffer 58 (strictly speaking, data is transferred when an EN (enable) signal on the receiving side is generated).

  As described above, the interrupt signal Smpl (m) is not only used by the flip-flop circuit 57 for determining whether the speed detection calculation is possible or not, but also a read buffer 58 including a multistage buffer described later. It is also used to control data transfer. Accordingly, the three types of “pulse presence / absence flag, pulse phase value θpp, and pulse generation time tpp” are updated simultaneously.

  The read buffer 58 uses the interrupt signal Smpl (m) from the timer circuit 54 as an enable signal, the pulse phase value θpp sent from the pulse phase up / down counter 53, and the pulse sent from the pulse generation time measuring circuit 56. The generation time tpp and the pulse presence / absence flag (pulse presence / absence signal) sent from the flip-flop circuit 57 are held.

  The read buffer 58 stores three instantaneous values of “pulse presence / absence flag”, “pulse phase value θpp”, and “pulse generation time tpp” at the generation time of the interrupt signal Smpl (m). 58c (Dff1 to Dff3 in the figure).

  The output side of the latch circuits 58a to 58c is read as a measured value from the CPU or the like, and the interrupt signal Smpl ( The latches are simultaneously latched at the occurrence timing of m), and the values are held in other periods.

  The waveform shaping circuit 51, the OR circuit 52, the pulse phase up / down counter 53, the timer circuit 54, the D-type flip-flop 55, the pulse generation time measuring circuit 56, the flip-flop circuit 57, and the reading buffer 58 are used to obtain a pulse information acquisition unit. Is configured.

  61 is a pulse phase buffer (multi-stage buffer; Buff2) for reading and storing the register value (pulse phase value θpp) of the latch circuit 58b (Dff2), and 62 is a register value (pulse generation) of the latch circuit 58c (Dff3). This is a pulse time buffer (multi-stage buffer; Buff3) for reading and storing time (tpp).

  63 is a selection signal (Sel) for selecting pulse information (pulse phase value θpp, pulse generation time tpp) acquired before a plurality of sample periods and stored in the pulse phase buffer 61 and the pulse time buffer 62. It is a speed difference data selection circuit (selection signal setting unit). Specifically, the selection signal Sel is a value of (m) that is an identifier of the interrupt signal Smpl (m) output for each sample period, and is set to a value corresponding to a plurality of sample periods before.

  64 is a previous value selection selector (Select2) (past information) for selecting (previous) pulse phase information before a plurality of sample periods indicated by the selection signal Sel among the pulse phase information stored in the pulse phase buffer 61. Selection section).

  65 is a previous value selection selector (Select3) for selecting (previous) pulse time information before a plurality of sample periods indicated by the selection signal Sel among the pulse time information stored in the pulse time buffer 62 (past information). Selection section).

  In the conventional pulse phase buffer 61 and the pulse time buffer 62, for example, in Patent Document 1, the latest pulse information is stored in the first stage buffer, and the past pulse information is stored in the second stage buffer. In the present invention, as shown in FIG. 2, the present invention is extended to a stack memory (multistage buffer) that performs a multistage FIFO (first in first out) operation. .

  In FIG. 2, 71 is an AND circuit that calculates the logical product of the interrupt signal Smpl (m) (output of the timer circuit 54) and the pulse presence / absence signal (output of the latch circuit Dff1) of FIG.

  72 is a multistage buffer for storing pulse phase information and pulse generation time information (detection data) read from the read buffer 58 of FIG. 1, and a latch circuit 72-0 (Dff0) (latest information) for storing the latest information. (Information storage buffer) and n stages (n is an integer) of latch circuits 72-1 to 72-5 (Dff1 to Dff5) (past information storage buffer) for storing past information.

  In this embodiment, the n-stage latch circuit, which is a past information storage buffer, is configured as five, but may be configured by other plural stages. Further, Dff1 to Dff3 of the latch circuits 58a to 58c of the read buffer 58 of FIG. 1 and Dff1 to Dff3 of the latch circuits 72-1 to 72-3 of FIG. Are different circuits.

  The output (pulse phase information) of the latch circuit 58b of the read buffer 58 or the output (pulse time information) of the latch circuit 58c is input as detection data to the D terminal of the latch circuit 72-0.

  The Q output of the latch circuit 72-0 is input to the D terminal of the latch circuit 72-1, the Q output of the latch circuit 72-1 is input to the D terminal of the latch circuit 72-2, and the Q output of the latch circuit 72-2. Is input to the D terminal of the latch circuit 72-3, the Q output of the latch circuit 72-3 is input to the D terminal of the latch circuit 72-4, and the Q output of the latch circuit 72-4 is the D output of the latch circuit 72-5. Input to the terminal.

  Each of the latch circuits 72-0 to 72-5 uses the output of the AND circuit 71, which is the logical product of the interrupt signal and the pulse presence / absence signal, as an enable signal to write read data or between buffers (latch circuits 72-0 to 72-0). 72-5) is executed by the interrupt process.

  Since the logical product signal of the interrupt signal and the pulse presence / absence signal is used as the enable signal in this way, each buffer (latch circuit 72-0 to 72-5) is used only when the pulse presence / absence signal (pulse presence / absence flag) is “generated”. ) Is operated, and when there is no pulse, the past value can be held. Since the data transfer limiting function based on such a pulse presence / absence signal is provided, it is possible to cope with a case where the rotation speed is lowered and the pulse generation period becomes longer than the interrupt signal period to enter the “pulse pause” state.

  Reference numeral 73 in FIG. 2 denotes a previous value selection selector that realizes the functions of the previous value selection selectors 64 and 65 (Select 2 and Select 3) in FIG. 1, and the Q outputs of the latch circuits 72-1 to 72-5. Among the data Data (1) to Data (5), data before a plurality of sample periods indicated by the selection signal Sel from the speed difference data selection circuit 63 (stack buffer) is selected.

  By switching the selection signal Sel according to the setting of the CPU (changing the selection signal in the speed difference data selection circuit 63), even if the data is latched at a fixed sample period, at a time before an arbitrary number of samples. It is possible to extract information on the generated pulse.

  66 in FIG. 1 is a subtracter (Sub2) that calculates the difference between the latest pulse phase in the pulse phase buffer 61 and the pulse phase before the plurality of sample periods selected by the previous value selection selector 64. The subtracter (Sub3) calculates the difference between the latest pulse time in the pulse time buffer 62 and the pulse time before the plurality of sample periods selected by the previous value selection selector 65.

  Reference numeral 68 denotes a divider that divides the phase difference output from the subtractor 66 by the time difference output from the subtractor 67 and outputs speed detection 1 (speed detection value). The subtractors 66 and 67 and the divider 68 constitute a speed detection calculation unit of the present invention.

  The pulse phase buffer 61, the pulse time buffer 62, the speed difference data selection circuit 63, the previous value selection selectors 64 and 65, the subtractors 66 and 67, and the divider 68 are implemented as software as components of the CPU calculation function. Assumes that.

  As described in the section “Problems to be solved by the invention”, how to select the selection signal Sel of the speed difference data selection circuit 63 depends on a shorter time interval for calculating the speed calculation. In view of the fact that the performance can be improved and the accuracy is better when the length is longer, a method of setting empirically from the type of encoder, the number of pulses, the amount of jitter generated, and the like can be considered.

  Next, the operation of the apparatus configured as described above will be described with reference to the time chart of FIG. FIG. 3 shows an example of a state in which a rotating machine such as a motor is rotating at a constant speed in the forward direction, and (a) is an up signal output from the waveform shaping circuit 51 to the pulse phase up / down counter 53. A certain Edg_up is shown.

  FIG. 3B shows the phase counter value of the pulse phase up / down counter 53, that is, the time phase characteristic which is the relationship between the pulse phase value θpp and time t, and FIG. 3C shows the interrupt output from the timer circuit 54. 3D shows the signal Smpl (m), FIG. 3D shows the update status of the latest data of the phase θ (m) of the pulse phase buffer 61, and FIG. 3E shows the pulse time t (m) of the pulse time buffer 62. The latest data update status is shown.

  FIG. 3F shows a speed detection value according to a conventional method for detecting speed from phase and time information read out in two consecutive sample periods as in Patent Document 1, as speed detection 1 ′. g) shows the speed detection value according to the embodiment of FIG.

  In FIG. 3, Edg_up pulses are generated at substantially constant intervals, and the phase counter value θpp (θ1, θ2, θ3,...) Is incremented every time the pulse is generated. Here, an identification number is assigned to each Edg_up pulse for the following description. Simultaneously with the generation of the pulse, the time data tpp (t1, t2, t3,...) Is also latched in the pulse generation time measuring circuit 56 (DEN-ff).

  On the other hand, at the timing when the interrupt signal Smpl (m1, m2, m3,...) Is generated, θpp is latched in the latch circuit 58b (Dff2) and tpp is latched in the latch circuit 58c (Dff3). Data is read out and stored in a buffer (pulse phase buffer 61, pulse time buffer 62) that performs a FIFO stack operation. In FIG. 3, the update status of the latest data in the buffer is indicated by θ (m) and t (m). If multiple pulses occur during the period of the sample interrupt signal (Smpl), The pulse information of the latest time latched in the period is read out.

  For example, since the three pulses 7, 8, and 9 of Edg_up shown in FIG. 3A are generated between m3 and m4 of Smpl in FIG. 3C, the pulse of the last latched pulse 9 is generated. Information is read out and updated from θ6 → θ9 and t6 → t9 in FIGS. 3 (d) and 3 (e).

  In the speed detection 1 'according to the conventional method, the speed calculation is performed from the phase and time information read out at two consecutive sample periods. In FIG. 3 (f), it is clearly shown at which time the sample information is used for the calculation.

  For example, at the time of Smpl (m4), the latest phase θ9 and the latest time t9 are read, and the speed detection ω1 ′ (m4) = (θ9−θ6) / (t9) from the difference between the previous buffer values θ6 and t6. -T6) was calculated. If this is illustrated in the time phase characteristic of FIG. 3B, it corresponds to speed detection between pulses as indicated by a solid arrow.

  On the other hand, the speed detection 1 according to the first embodiment makes the speed measurement period equivalently longer by setting the past information as “information before a plurality of samples”. In FIG. The information is used to specify when the calculation is performed.

  In the example of FIG. 3G, the value of the selection signal Sel that designates “before a plurality of sample periods” set in the speed difference data selection circuit 63 of FIG. 1 is set to “four sample periods before”. .

  For example, at the time of Smpl (m4), for the latest information θ9 and t9, the phase θ0 and the time t0 that are information read at the sample timing of Smpl (4-4) = Smpl (0) are selected as the previous values. The speed detection 1 is calculated as ω1 (m4) = (θ9−θ0) / (t9−t0).

  Similarly, at the next sample timing Smpl (5), the difference between the latest information θ11, t11 and the information read at the sample timing Smpl (5-4) = Smpl (1) as the previous value is θ1, t1. Speed detection 1 is updated.

  If this is illustrated in the time phase characteristic of FIG. 3B, it corresponds to the speed detection between pulses as indicated by the dashed arrow.

  According to the first embodiment, instead of changing the sample period (interrupt period) itself to a long time, it is set to a constant sample period, and a buffer in which past information can be stacked and arbitrary data are selected therefrom. By using this function, it is possible to detect speed as accurately as if the sample period was extended.

  Furthermore, if the sample period itself is lengthened, the update period of the speed detection value is also extended in the same manner, and the speed detection waveform changes roughly on both the time axis and the speed axis. On the other hand, in the method of the first embodiment, the speed detection data is updated in small increments with the cycle of the sample interrupt signal Smpl (m) as shown in FIG. 3, so that both the time axis and the velocity axis change in small increments. It becomes like this. This means that the waste time component due to a long data update cycle can be suppressed, and the speed response can be improved by that amount.

  Furthermore, since the cycle of Smpl (m) is also the cycle of speed command and speed control calculation, it is desired to keep it as short and constant as possible in the control apparatus regardless of the performance (pulse resolution and variation) of the encoder. In this respect as well, in the method of the present invention, since the sample period can be fixed and only the speed detection period can be arbitrarily lengthened, it is viewed from the control system of the entire apparatus that does not affect the control system other than the speed detection. There are also advantages.

  In the first embodiment, the configuration in which the speed detection period can be made variable even in the fixed interrupt cycle is shown. This can be easily realized by effectively using a memory function in the CPU. Furthermore, if the number of speed calculations is increased, a plurality of speed detection calculations having different speed detection periods can be executed. Therefore, effective use of a plurality of speed detection is the point of the second embodiment, and the function is improved by combining these with speed control.

  FIG. 4 shows an example in which two speed detection calculations of speed detection 1 and speed detection 2 are executed. In FIG. 4, a different part from FIG. 1 will be described. As a selection signal setting unit, instead of the speed difference data selection circuit 63 of FIG. 1, pulse information acquired and stored before the first sample period is selected. The first selection signal Sel1 (previous 1) and the second selection signal Sel2 (previous 2) for selecting pulse information acquired and stored before the second sample period before the first sample period. ) Is set. A speed difference data selection circuit 83 is provided.

  In addition, as the first past information selection unit, the previous value 1 selection selector 64-1 for selecting the pulse phase information before the first sample period in the pulse phase buffer 61 by the first selection signal Sel1, and the pulse time A previous value 1 selection selector 65-1 for selecting the pulse time information before the first sample period in the buffer 62 is provided.

  In addition, as a second past information selection unit, the previous value 2 selection selector 64-2 for selecting the pulse phase information before the second sample period in the pulse phase buffer 61 by the second selection signal Sel2, and the pulse time A previous value 2 selection selector 65-2 for selecting pulse time information before the second sample period in the buffer 62 is provided.

  Further, as a first velocity detection calculation unit, a subtractor that calculates a difference between the latest pulse phase of the pulse phase buffer 61 and the pulse phase before the first sample period selected by the previous value 1 selection selector 64-1. 66-1, a subtractor 67-1 for calculating a difference between the latest pulse generation time of the pulse time buffer 62 and the pulse generation time before the first sample period selected by the previous value 1 selection selector 65-1. The divider 68-1 that divides the phase difference that is the deviation output of the subtractor 66-1 by the time difference that is the deviation output of the subtractor 67-1 and outputs the speed detection 1 (first speed detection value). And are provided.

  Further, as a second speed detection calculation unit, a subtractor that calculates a difference between the latest pulse phase of the pulse phase buffer 61 and the pulse phase before the second sample period selected by the previous value 2 selection selector 64-2. 66-2, a subtractor 67-2 for calculating a difference between the latest pulse generation time of the pulse time buffer 62 and the pulse generation time before the second sample period selected by the previous value 2 selection selector 65-2; The divider 68-2 outputs the speed detection 2 (second speed detection value) by dividing the phase difference, which is the deviation output of the subtractor 66-2, by the time difference, which is the deviation output of the subtractor 67-2. And are provided.

  The other parts are the same as in FIG.

  In the configuration of FIG. 4, the operations up to the speed detection calculation are the same as in FIG. 1, and speed detection 1 and speed detection 2 calculated in different speed detection periods can be obtained.

  In this way, different speed detection periods are set in the two types of speed detection, and the advantages of the respective speed detections are utilized, so that “the speed detection cycle is short” shown in the column of the problem to be solved by the invention. The problem that the speed error due to jitter becomes large, and conversely, if it is long, the waste time becomes long and the response performance is limited, can be addressed. FIG. 5 is a configuration diagram of a speed control system of a rotating machine that has taken such measures, and is an example in which the present invention is applied to a speed control method called general proportional integral (differential) control (PI (D) control). .

  In FIG. 5, the CPU calculation part is expressed as a frame and arranged in the center, and the left side outside this frame corresponds to the digital detection circuit of FIGS. The circuit is a speed detection circuit 100.

  An ASR control unit (Automatic Speed Regulator; automatic speed control unit) 200 of the CPU calculation part is configured as follows.

  The speed command generator 201 outputs the target speed of the rotating machine as a speed command according to time, and the speed control performs an operation following this.

  The speed detection calculation unit 210 corresponds to the CPU calculation part on the right side of FIG. 4 and outputs two types of speed detection values, speed detection 1 and speed detection 2, with different speed detection periods.

  The subtractor 202 takes the deviation between the speed command and the speed detection 1, and the subtracter 203 takes the deviation between the speed command and the speed detection 2.

  Reference numeral 204 denotes a P (D) control unit as a proportional control term that performs proportional (differential) control on the deviation output of the subtractor 202, and 205 indicates an integral control term that performs integral control on the deviation output of the subtractor 203. As an I control unit.

  The PI control output obtained by adding the outputs of the P (D) control unit 204 and the I control unit 205 by the adder 206 corresponds to a torque command to be generated by the rotating machine.

  Reference numeral 300 denotes a torque / current command conversion unit that converts a torque command, which is an output of the adder 206, into a current command that flows to the rotating machine.

  The output of the torque / current command conversion unit 300 is deviated from the detected current value (actual current) by the subtractor 400.

  The ACR control unit 500 performs ACR control on the deviation output of the subtractor 400 and outputs an output voltage command, and performs current control (ACR) so that the actual current follows the current command.

  In the above configuration, the PI control in the ASR control unit 200 is a control method that combines two types of functions: “P control realizes high-speed response performance and I control slowly corrects steady errors”. is there. Therefore, it is sufficient to use speed detection information that takes a deviation from the speed command, and that has a property that can sufficiently exhibit a function corresponding to the speed detection information.

  Therefore, in the present embodiment, the first selection signal Sel1 for obtaining the speed detection 1 in FIG. 4 is set to a selection signal for selecting, for example, pulse information two sample periods before, and the speed detection 2 is obtained. The second selection signal Sel2 is set as a selection signal for selecting, for example, pulse information eight samples before. Thus, the speed detection 1 has a short detection period, and the speed detection 2 has a long detection period.

  Since the proportional control (P (D) control unit 204) in the ASR control unit 200 of FIG. 5 affects the performance of responsiveness, the waste time is reduced by using information with a short detection period of the speed detection 1, and the proportional term is used. The control gain is set as high as possible to improve response performance.

  On the other hand, the time constant of the integral term is a value determined by the moment of inertia of the machine, and is usually longer than the speed detection cycle. Therefore, for the speed detection of the integral term (I control unit 205), the fact that there is little adverse effect even if a signal with a large waste time is used, the measurement time of speed detection 2 is long (the waste time is large but the accuracy is high). Use good) information.

  In this way, a control system that achieves both "speed control accuracy and response performance" is constructed by using different speed information depending on the control term so that the features of the two types of speed detection can be demonstrated. be able to.

  In FIG. 4 and FIG. 5 of the second embodiment, the PI control method in which two types of speed detection are combined is presented, but the latest latest speed command common to the speed commands is used. However, considering the case where the vehicle is accelerating at a constant acceleration as shown in FIG. 6 showing the relationship between speed and time, if the speed detection time is set longer as in speed detection 2, the waste time also becomes longer, and therefore changes. The follow-up delay of speed detection (broken line) becomes larger than the speed command (solid line).

  This follow-up delay component is accumulated in the I control (205), and the halftone portion is accumulated during acceleration. Next, when the speed command shifts to a constant speed, it is necessary to discharge the integrated integral term, and therefore overshoots as indicated by the hatched portion of the constant speed command. In Example 3, measures are taken to suppress this overshoot after acceleration / deceleration. Specifically, as in the second embodiment, the speed detection on the integral (I) control side of the PI control is set as the speed detection 2, and the speed command for the integral control is further improved.

  A configuration example of the speed command correction method is shown in FIG. In FIG. 7, a different part from FIG. 4 will be described. First, a speed command is written in a flip-flop 90 (DEN-ff) in the digital circuit, and the output of the flip-flop 90 is multiplied by a clock cycle Tc of the digital circuit by a multiplier 91. .

  The output (phase component) of the multiplier 91 is an adder 92 for adding the previous phase value θref_clk (Q output of the phase command integrator 93) and the phase increment (output of the multiplier 91), and a D-type flip-flop. The integrated circuit (speed command / phase command conversion circuit) composed of the phase command integrator 93 and the flip-flop circuit 94 that uses the output of the OR circuit 52 as an enable signal is input to the Q output of the flip-flop circuit 94. Obtains a phase command θref obtained by time-integrating the speed command. For this reason, the integration circuit can be regarded as a simulated rotational phase command generator.

  58d is a latch circuit (Dff4) (phase command read buffer) that latches the phase command θref, and enables the interrupt signal Smpl (m) in the same manner as the latch circuit 58b that latches the output of the pulse phase up / down counter 53. It is a signal.

  Reference numeral 95 denotes a phase command buffer (Buff4) that reads out the Q output (phase command) of the latch circuit 58d and stacks it in multiple stages. Like the pulse phase buffer 61 on the speed detection side, for example, the latest information storage buffer and n stages ( n is an integer) past information storage buffer.

  96 selects the phase command before the second sample period in the past information storage buffer of the phase command buffer 95 at the stage specified by the second selection signal Sel2 output from the speed difference data selection circuit 83. This is a phase command selection selector (third past information selection unit).

  Note that the phase command buffer 95 is composed of, for example, a multistage buffer similar to that shown in FIG.

  A subtractor 97 calculates a difference between the latest phase command in the latest information storage buffer of the phase command buffer 95 and the phase command before the second sample period selected by the phase command selection selector 96. .

  Reference numeral 98 denotes a divider that divides the phase command difference, which is the output of the subtractor 97, by the time difference, which is the output of the subtractor 67-2, and outputs an average speed command.

  The latch circuit 58d, the phase command buffer 95, the phase command selection selector 96, the subtractor 97, and the divider 98 constitute the average speed command calculation unit of the present invention.

  The other parts are the same as in FIG.

  FIG. 8 shows a configuration example in which the apparatus configured as shown in FIG. 7 is applied to a speed control system similar to that shown in FIG. 220 in the ASR control unit 200 'in FIG. 8 represents the speed detection calculation unit and the averaged speed command calculation unit in FIG.

  In FIG. 8, the I control unit 205 performs integration control on the deviation between the averaged speed command and the speed detection 2 that is the output of the subtractor 213, and the other parts are configured in the same manner as in FIG. Yes.

  In the third embodiment, a phase that is latched at a time synchronized with the speed detection 2 when the speed command is converted into a phase command by performing an integral operation and then restored to the original speed information. Since the average speed command is calculated using the information in the command buffer 95, the thick solid line is averaged even during acceleration of the thin solid speed command as shown in FIG. 9 showing the relationship between the speed and time. The speed command has a delay time substantially equal to the time delay of the broken line speed detection 2.

  As a result, by changing the integral (I) control so that the difference between the average speed command and the speed detection 2 is calculated, the detected time delay component is integrated into the integrator of the I control unit 205 during acceleration. The amount of overshoot is suppressed, and the amount of overshoot when shifting to a constant speed can be suppressed. The delay is inserted into the averaged speed command, as in the second embodiment. “The time constant of the integral term is a value determined by the moment of inertia of the machine, and is usually longer than the speed detection cycle.” Is to use that.

  In a pulse encoder including jitter, in order to suppress the occurrence of an offset error in the detection speed, for example, if the detection period of speed detection used for integral control is lengthened as in the second embodiment, acceleration / deceleration is caused by an increased time delay component. In the state, the value accumulated in the integral term increases, and the overshoot at the time of shifting to a constant speed increases. On the other hand, in the third embodiment, a speed command having a delay time substantially equal to the speed detection, that is, an “averaged speed command” is generated, and the difference from the speed detection is taken. Therefore, as described in FIG. The amount of overshoot of the speed after acceleration / deceleration can be reduced. That is, the accuracy of speed control is improved.

DESCRIPTION OF SYMBOLS 50 ... Pulse encoder 51 ... Waveform shaping circuit 52 ... OR circuit 53 ... Pulse phase up / down counter 54 ... Timer circuit 55 ... D-type flip-flop 56 ... Pulse generation time measuring circuit 57, 94 ... Flip-flop circuit 58 ... Reading buffer 58a 58d, 72-0 to 72-5 ... Latch circuit 61 ... Pulse phase buffer 62 ... Pulse time buffer 63,83 ... Speed difference data selection circuit 64,65,73 ... Previous value selection selector 64-1,65-1 ... previous value 1 selection selector 64-2, 65-2 ... previous value 2 selection selector 66, 66-1, 66-2, 67, 67-1, 67-2, 97, 202, 203, 213, 400 ... Subtractor 71 ... AND circuit 68, 68-1, 68-2, 98 ... Divider 91 ... Multiplier 93 ... Phase command integrator 95 ... Rank Phase command buffer 100 ... Speed detection circuit 200, 200 '... ASR control unit 201 ... Speed command generation unit 204 ... P (D) control unit 205 ... I control unit 300 ... Torque / current command conversion unit 500 ... ACR control unit

Claims (6)

A speed detection device for detecting the rotation speed of a rotating machine,
Based on the output pulse of the pulse encoder that detects the rotation angle of the rotating machine, for each set sample period, a pulse information acquisition unit that acquires pulse presence information, pulse phase information, and pulse generation time information;
A pulse phase buffer for storing each of the pulse phase information acquired for each sample period;
A pulse time buffer for storing each of the pulse generation time information acquired for each sample period;
A selection signal setting unit for setting a selection signal for selecting pulse information acquired and stored before a plurality of sample periods;
Past selecting pulse phase information before a plurality of sample periods in the pulse phase buffer according to a selection signal set by the selection signal setting unit, and selecting pulse generation time information before a plurality of sample periods in the pulse time buffer An information selector,
The difference between the latest pulse phase in the pulse phase buffer and the pulse phase before a plurality of sample periods selected by the past information selection unit, the latest pulse generation time in the pulse time buffer, and the past information selection unit are selected. A speed detection calculation unit that calculates a speed detection value based on a difference from a pulse generation time before a plurality of sample periods;
A speed detection device comprising: The pulse information acquisition unit
A waveform shaping circuit that shapes the output pulse from the pulse encoder to detect rising and falling edges of the pulse; and
A pulse phase up / down counter that counts up / down at the rising edge and falling edge of the pulse detected by the waveform shaping circuit and outputs the count value as a pulse phase value;
A timer circuit that counts the reference clock, outputs time data, and outputs an interrupt signal for each set sample period;
A pulse generation time measuring circuit that stores and holds time data of the timer circuit when a detection signal of each edge of a pulse is input from the waveform shaping circuit, and outputs the pulse generation time;
Set by the detection signal at each edge of the pulse from the waveform shaping circuit, reset by the interrupt signal from the timer circuit, and the presence / absence of a pulse indicating whether or not a pulse has occurred during the generation period of the interrupt signal A flip-flop circuit that outputs a signal;
Using the interrupt signal from the timer circuit as an enable signal, the pulse phase value sent from the pulse phase up / down counter, the pulse generation time sent from the pulse generation time measuring circuit, and the pulse sent from the flip-flop circuit A read buffer for holding presence / absence signals,
The pulse phase buffer and the pulse time buffer use the AND signal of the interrupt signal from the timer circuit and the pulse presence / absence signal from the read buffer as an enable signal, and determine the pulse phase value and pulse generation time of the read buffer. Each of the latest information storage buffer and the n-stage (n is an integer) past information storage buffer is configured to read and store,
The selection signal of the selection signal setting unit is set to a signal for designating any one of the n stages of past information storage buffers,
The past information selection unit selects information of a buffer at a stage specified by a selection signal of the selection signal setting unit from among the n stages of past information storage buffers;
The speed detection apparatus according to claim 1, wherein: The selection signal setting unit includes:
A first selection signal for selecting pulse information acquired and stored before the first sample period, and a pulse acquired and stored before the second sample period before the first sample period And a second selection signal for selecting information,
The past information selection unit
First past information selection for selecting pulse phase information before the first sample period in the pulse phase buffer and pulse time information before the first sample period in the pulse time buffer by the first selection signal And
Second past information selection for selecting the pulse phase information before the second sample period in the pulse phase buffer and the pulse time information before the second sample period in the pulse time buffer by the second selection signal And
The speed detection calculation unit
The difference between the latest pulse phase in the pulse phase buffer and the pulse phase before the first sample period selected by the first past information selection unit, the latest pulse generation time in the pulse time buffer, and the first A first speed detection calculation unit that calculates a first speed detection value based on a difference from a pulse generation time before the first sample period selected by the past information selection unit;
The difference between the latest pulse phase in the pulse phase buffer and the pulse phase before the second sample period selected by the second past information selection unit, the latest pulse generation time in the pulse time buffer, and the second A second speed detection calculation unit that calculates a second speed detection value based on a difference from a pulse generation time before the second sample period selected by the past information selection unit. The speed detection device according to claim 1. The selection signal setting unit includes:
A first selection signal that designates one of the n stages of past information storage buffers acquired and stored before the first sample period, and a first selection signal before the first sample period; A second selection signal that designates any one of the n stages of past information storage buffers obtained and stored before two sample periods;
The past information selection unit
The pulse phase information before the first sampling period in the past information storage buffer of the pulse phase buffer and the first in the past information storage buffer of the pulse time buffer at the stage specified by the first selection signal. A first past information selection unit for selecting pulse time information before the sample period;
The pulse phase information before the second sample period in the past information storage buffer of the pulse phase buffer and the second in the past information storage buffer of the pulse time buffer at the stage specified by the second selection signal. A second past information selection unit for selecting the pulse time information before the sample period,
The speed detection calculation unit
The difference between the latest pulse phase in the latest information storage buffer of the pulse phase buffer and the pulse phase before the first sample period selected by the first past information selection unit, and the latest information storage of the pulse time buffer A first speed for calculating a first speed detection value based on a difference between the latest pulse generation time in the buffer and a pulse generation time before the first sample period selected by the first past information selection unit A detection calculation unit;
The difference between the latest pulse phase in the latest information storage buffer of the pulse phase buffer and the pulse phase before the second sample period selected by the second past information selection unit, and the latest information storage of the pulse time buffer Second speed for calculating the second speed detection value based on the difference between the latest pulse generation time in the buffer and the pulse generation time before the second sample period selected by the second past information selection unit The speed detection device according to claim 2, further comprising a detection calculation unit. A proportional control term that performs proportional control with respect to the deviation between the speed command of the rotating machine and the detected speed value of the rotating machine, and an integral control term that performs integral control with respect to the deviation between the speed command of the rotating machine and the detected speed value of the rotating machine. And a speed control system for controlling the speed of the rotating machine,
The speed detection device according to claim 3 or 4,
As the speed detection value of the rotating machine in the proportional control term, using the first speed detection value calculated by the first speed detection calculation unit of the speed detection device,
As the speed detection value of the rotating machine in the integral control term, the second speed detection value calculated by the second speed detection calculation unit of the speed detection device is used.
A speed control system characterized by that. A proportional control term that performs proportional control with respect to the deviation between the speed command of the rotating machine and the detected speed value of the rotating machine, and an integral control term that performs integral control with respect to the deviation between the speed command of the rotating machine and the detected speed value of the rotating machine. And a speed control system for controlling the speed of the rotating machine,
A speed detection device according to claim 4,
A speed command / phase command conversion circuit that obtains a phase command by integrating the speed command of the rotating machine over time is provided.
A phase command read buffer for holding an interrupt signal from the timer circuit of the speed detection device as an enable signal and holding the phase command obtained by the speed command / phase command conversion circuit;
The latest information storage buffer and the n-stage (n is an integer) past information storage buffer, and a pulse presence / absence signal from the read buffer of the speed detection device is used as an enable signal in the phase command read buffer. A phase command buffer for reading and storing the phase command;
A phase command for selecting the phase command before the second sample period in the past information storage buffer of the phase command buffer at the stage specified by the second selection signal set by the selection signal setting unit of the speed detection device. 3 past information selection sections;
The difference between the latest phase command in the latest information storage buffer of the phase command buffer and the phase command before the second sample period selected by the third past information selection unit is calculated as a second value of the speed detection device. An arithmetic circuit that divides by the difference between the latest pulse generation time and the pulse generation time before the second sample period in the speed detection calculation unit,
An average speed command calculation unit for obtaining an average speed command is further provided.
As the speed command of the rotating machine in the integral control term, using the averaged speed command obtained by the averaged speed command calculation unit,
As the speed detection value of the rotating machine in the proportional control term, using the first speed detection value calculated by the first speed detection calculation unit of the speed detection device,
A speed control system using a second speed detection value calculated by a second speed detection calculation unit of the speed detection device as the speed detection value of the rotating machine in the integral control term.

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