JP2019029469A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

To provide a semiconductor device and a manufacturing method of the same which can prevent local thermal failure due to concentration of Hall current without increasing forward voltage.SOLUTION: A semiconductor device at least comprises: a first conductivity type semiconductor substrate; a first part which is formed on part of the semiconductor substrate on one principal surface side and has a second conductivity type opposite to the first conductivity type; an electrode layer joined to the first part; and a conductive mask layer formed on the electrode layer in an overlapping manner. The electrode layer is formed to be overlapped on the one principal surface side at a position from a circumference toward the center of the semiconductor substrate; and on the semiconductor substrate, a reconnection layer extending from the circumference toward the center is formed; and one end of the reconnection layer lies on the joint surface of the first part with the semiconductor substrate and near an end of the semiconductor substrate on the circumference side in a shape following a surface shape of the conductive mask layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device such as a diode and a manufacturing method thereof.

  A planar diode, which is an example of a semiconductor device, forms an oxide film (passivation) on, for example, an n-type silicon substrate, and diffuses impurities in a predetermined position using the oxide film as a mask layer for impurity diffusion to form a p-type region ( It is obtained by forming an active layer. Such a planar diode is known to have a high current density due to the concentration of hole current at the connection between the p-type region and the passivation during transient operation.

  There is a possibility that the planar diode may be thermally damaged by the concentration of the hole current. In order to prevent thermal damage of the planar diode due to the concentration of the hole current, for example, in Patent Document 1, a defect called a low lifetime region extending near the interface between the p-type region and the n-type region (semiconductor substrate) is known. A region is formed, and the concentration of the hole current is mitigated by such a defect region.

JP 2005-340528 A

  However, in the semiconductor device having the structure disclosed in Patent Document 1, since the defect region is formed inside the p-type region, the lifetime of charge carriers in the active layer is affected, and the forward voltage increases. There was a problem.

  The present invention has been made in view of the above-described situation, and provides a semiconductor device capable of preventing thermal damage due to concentration of hole current without increasing a forward voltage, and a method for manufacturing the same. With the goal.

  In order to solve the above-described problems, a semiconductor device of the present invention is formed on a semiconductor substrate having a first conductivity type and a part of one main surface side of the semiconductor substrate, and having a conductivity opposite to that of the first conductivity type. A first part that is a second conductivity type of the mold, an electrode layer joined to the first part, and a conductive mask layer formed on the electrode layer, wherein the electrode layer includes A recombination layer extending from the periphery to the center is formed on the semiconductor substrate at a position from the periphery to the center of the semiconductor substrate, and the semiconductor substrate is formed with a recombination layer extending from the periphery to the center. One end of the layer is in the vicinity of the edge on the peripheral side of the semiconductor substrate in the bonding surface of the first part with the semiconductor substrate, and has a shape that follows the surface shape of the conductive mask layer. It is formed.

  In a semiconductor device, for example, a planar type diode, a recombination layer is formed so that one end is in contact with the bonding surface of the first part, but the recombination layer is not extended to the inside of the first part. This prevents the lifetime of the charge carriers in the first part from being shortened. That is, if the recombination layer is formed to the inside of the first part, the lifetime of the charge carriers in the first part may be shortened and the forward voltage may increase. By adopting a configuration that does not extend, it is possible to prevent an increase in forward voltage at the first portion.

  In addition, for example, during transient operation, the hole current concentrates on the first part and the current density increases, but by forming a recombination layer so that one end is in contact with the joint surface of the first part. The lifetime of charge carriers in the peripheral portion of the semiconductor substrate is shortened, and the holes in the peripheral portion of the semiconductor substrate disappear quickly. Thereby, the hole current concentration in the peripheral portion of the semiconductor substrate is reduced, and the semiconductor device can be prevented from being thermally damaged.

  In the present invention, the one end portion of the recombination layer is in contact with the first portion.

  In the present invention, the one end portion of the recombination layer is inclined in a direction shallower than a bottom surface of the first portion.

  In the present invention, the conductive mask layer is made of a solder material, and the conductive mask layer is formed so that the height gradually increases from the periphery of the conductive mask layer toward the center. Features.

  In the present invention, the second region of the second conductivity type further extending in the depth direction from one main surface side of the semiconductor substrate is further formed on the semiconductor substrate outside the first region. The recombination layer is characterized by spreading to a position that is the same as or deeper than the bottom surface of the second part.

  The method for manufacturing a semiconductor device according to the present invention is the method for manufacturing a semiconductor device according to each of the above items, wherein the first portion of the second conductivity type is formed on a part of one main surface side of the semiconductor substrate. A second conductive type diffusion layer forming step, an electrode layer forming step of forming the electrode layer so as to be in contact with the first part, a mask layer forming step of forming a conductive mask layer on the electrode layer, And a recombination layer forming step of forming the recombination layer by irradiating high energy particles in the depth direction of the semiconductor substrate using a conductive mask layer as an irradiation mask. .

  In the recombination layer forming step, lattice defects of the semiconductor substrate are formed with high density by irradiating high energy particles from one main surface side of the semiconductor substrate. The formation position of the recombination layer in the depth direction of the semiconductor substrate is determined by the irradiation energy of high-energy particles. That is, the formation position of the recombination layer can be controlled by the thickness of the conductive mask layer serving as a mask for such high-energy particles. This makes it possible to form a recombination layer at an arbitrary depth position of the semiconductor substrate.

  In the present invention, the high-energy particles are irradiated with helium or protons in the recombination layer forming step.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can prevent the thermal damage by the concentration of a hole current, and its manufacturing method can be provided, without increasing a forward voltage.

It is a principal part expanded sectional view which shows the cross section along the lamination direction (thickness direction) of the peripheral part of the semiconductor substrate in the planar type diode (semiconductor device) of 1st embodiment of this invention. It is a principal part expanded sectional view which shows the cross section along the lamination direction (thickness direction) of the peripheral part of the semiconductor substrate in the planar type diode (semiconductor device) of 2nd embodiment of this invention. It is a flowchart explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing which showed the manufacturing method of the semiconductor device of this invention in steps. It is sectional drawing which showed the manufacturing method of the semiconductor device of this invention in steps. It is the schematic cross section which showed the recombination layer formation process typically.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. Each embodiment described below is specifically described for better understanding of the gist of the invention, and does not limit the present invention unless otherwise specified. In addition, in the drawings used in the following description, in order to make the features of the present invention easier to understand, there is a case where a main part is shown in an enlarged manner for convenience, and the dimensional ratio of each component is the same as the actual one. Not necessarily.

(Semiconductor device: first embodiment)
As an example of the semiconductor device of the present invention, the structure of a planar diode will be described in detail with reference to the drawings. The planar diode described below will be described with reference to a structural example of a peripheral portion of a semiconductor substrate in a planar diode provided with a guard ring. Therefore, the configuration on the center side of these peripheral portions is not particularly limited. Here, the peripheral portion refers to a region extending from one peripheral edge of the semiconductor substrate with an arbitrary width toward the center of the semiconductor substrate.

  First, an outline of the overall configuration of a planar diode as an example of a semiconductor device described in this embodiment will be described.

FIG. 1 is an enlarged cross-sectional view of a main part showing a cross section along the stacking direction (thickness direction) in the peripheral portion of the planar diode (semiconductor device) of the first embodiment. In FIG. 1, the right side toward the paper surface may be referred to as the peripheral side, and the left side may be referred to as the center side.
A planar diode (semiconductor device) 10 according to the present embodiment is formed on a semiconductor substrate 11 that is an n− type (first conductivity type) and a part on the one main surface 11a side of the semiconductor substrate 11, and is n−. An active layer (first portion) 12 that is a p + type (second conductivity type) opposite to the type, an anode electrode (electrode layer) 13 joined to the active layer 12, and an anode electrode 13 are formed. And the anode electrode 13 is formed so as to overlap one main surface 11a at a position from the periphery to the center of the semiconductor substrate 11, and the semiconductor substrate 11 includes: A recombination layer 21 extending from the peripheral side toward the center side is formed, and one end portion 21a of the recombination layer 21 is an end of the active layer 12 connected to the bonding surface 12a of the active layer 12 with the semiconductor substrate 11. Semiconductor substrate 1 Of in the area 29 near the periphery side of the end portion 12as, it is formed in a shape following the surface shape of the conductive mask layer 16 (e.g., the surface shape at the peripheral 16as the conductive mask layer 16). The region 29 is, for example, a region in the vicinity of the corner between the joint surface 12a of the active layer 12 and the end portion (end surface) 12as of the active layer 12 connected to the joint surface 12a, outside the active layer 12. Good.

  More specifically, the planar diode 10 of the present invention includes an n− type semiconductor substrate 11. The semiconductor substrate 11 is made of, for example, a Si wafer. For example, a SiC wafer can be used as the semiconductor substrate 11 in addition to the Si wafer.

  An active layer (first portion) 12 having a p + type opposite to the first conductivity type is formed on a part of the main surface 11a side of the semiconductor substrate 11. The active layer 12 is located at a predetermined distance from the peripheral side to the center side of the semiconductor substrate 11 and is formed from one main surface 11a of the semiconductor substrate 11 to a predetermined depth along the thickness direction. ing. In the semiconductor substrate 11, one main surface 11a side is an n− type semiconductor region, and the other main surface 11b side is formed with a cathode region 14 which is an n + type diffusion layer. The bottom surface 12ae of the active layer 12 is formed at a position shallower than the cathode region 14 (on one main surface 11a side of the semiconductor substrate 11).

  Of the one main surface 11 a of the semiconductor substrate 11, the active layer 12 is formed in the first main surface 11 a of the semiconductor substrate 11 on the peripheral side (peripheral region) of the first conductive type. An n + -type channel stopper layer 19 having an impurity concentration higher than that of the semiconductor substrate 11 is formed. The bottom surface of the channel stopper layer 19 is formed at a position shallower than the bottom surface 12ae of the active layer 12. Such a channel stopper layer 19 prevents a depletion layer extending from the active layer 12 to the periphery thereof from reaching the periphery of the semiconductor substrate 11.

An oxide film (passivation) 17 is formed between the active layer 12 and the channel stopper layer 19 in one main surface 11 a of the semiconductor substrate 11. More specifically, one end of the oxide film 17 is in contact with the end of the active layer 12 by being formed so as to overlap. The other end of the oxide film 17 is in contact with the end portion of the channel stopper layer 19 so as to overlap. Such an oxide film 17 is made of, for example, SiO ₂ .

The anode electrode 13 is formed so as to overlap with one main surface 11 a of the semiconductor substrate 11, a part of which is in contact with the active layer 12, and the remaining part thereof is overlapped with one end side of the oxide film 17. The anode electrode 13 is made of, for example, Al.
Note that a Ti layer and a Ni layer are formed on the anode electrode 13, and then a conductive mask layer 16 made of, for example, a solder material is formed.

  A conductive mask layer 16 is formed on the anode electrode 13. This conductive mask layer 16 functions as a mask at the time of high-energy particle irradiation used when forming the recombination layer 21 in the planar diode 10 manufacturing method described later. The conductive mask layer 16 is made of, for example, a solder material.

  As an example of the solder material constituting the conductive mask layer 16, Pb-containing solder or Pb-free solder can be used.

  The conductive mask layer 16 is formed so that the height gradually increases from the peripheral edge 16as toward the center. More specifically, a curved inclined surface whose thickness increases relatively abruptly at the peripheral edge 16as of the conductive mask layer 16 is formed, and further toward the center of the conductive mask layer 16 so as to continue to the curved inclined surface. It is preferably formed in a shape that gradually increases in thickness or becomes substantially constant.

  The entire main surface 11b of the semiconductor substrate 11 has a high impurity concentration n + type (first conductivity type) cathode region 14 that has an impurity concentration higher than that of the n− type semiconductor of the semiconductor substrate 11 and provides ohmic properties. Is formed. In addition, a cathode electrode 15 is formed on the entire other main surface 11 b of the semiconductor substrate 11 so as to be in contact with the cathode region 14. The cathode electrode 15 is made of, for example, Ni.

In addition, in one main surface 11a of the semiconductor substrate 11, it is on the peripheral side of the active layer 12 and on the center side of the channel stopper layer 19, in the depth direction from the one main surface 11a side of the semiconductor substrate 11. A p + type guard ring (second portion) 18 is further formed. The guard ring 18 is formed in an annular shape so as to surround the active layer 12 on the peripheral side of the semiconductor substrate 11 relative to the active layer 12 in contact with the anode electrode 13 when the semiconductor substrate 11 is viewed in plan. In the first embodiment, two guard rings are formed so as to be separated along one main surface 11 a of the semiconductor substrate 11.
Such a guard ring 18 relaxes the electric field concentration by acting so that the depletion layer extends from the active layer 12 to the peripheral side of the semiconductor substrate 11.

  One or three or more guard rings 18 may be formed. Each guard ring 18 can also be formed so as to contact without being separated from each other. Each guard ring 18 may have a multilayer structure of two or more layers having different impurity concentrations.

  A recombination layer 21 extending from the peripheral edge 11e of the semiconductor substrate 11 toward the center is formed on the semiconductor substrate 11 of the planar diode 10 of the first embodiment. Note that the center of the semiconductor substrate 11 indicates the center between the peripheral edge 11e of the semiconductor substrate 11 shown in FIG. More specifically, in the recombination layer 21, the other end 21b on the side of the peripheral edge 11e of the semiconductor substrate 11 extends to the peripheral edge 11e of the semiconductor substrate 11, and the other end 21b is on the opposite side. One end portion 21 a extends to an end portion 12 as on the peripheral edge 11 e side of the semiconductor substrate 11 in the bonding surface 12 a of the active layer 12 to the semiconductor substrate 11.

  One end 21 a of the recombination layer 21 is formed in a shape that follows the surface shape of the conductive mask layer 16. More specifically, one end portion 21 a of the recombination layer 21 has a shape that approximates the curved surface shape of the peripheral edge 16 as of the conductive mask layer 16. That is, one end 21 a of the recombination layer 21 is inclined so as to bend in a direction shallower than the bottom surface 12 ae of the bonding surface 12 a of the active layer 12 toward the center of the semiconductor substrate 11.

  In the semiconductor device manufacturing method described later, the conductive mask layer 16 is used as a mask at the time of high-energy particle irradiation used when forming the recombination layer 21. Thereby, the shape of the one end portion 21 a of the recombination layer 21 becomes a shape that follows the shape of the conductive mask layer 16.

  In the present embodiment, the end surface 21af of the one end portion 21a of the recombination layer 21 is a corner portion between the bonding surface 12a of the active layer 12 and the end portion (end surface) 12as of the active layer 12 connected to the bonding surface 12a. The recombination layer 21 is not formed inside the active layer 12.

  The recombination layer 21 extends linearly from one end 21 a toward the center of the semiconductor substrate 11 at a position deeper than the bottom surface of the guard ring 18. Note that the region on the peripheral side of the curved end portion of the recombination layer 21 can also be formed with a depth in contact with the bottom surface of the guard ring 18.

  The recombination layer 21 is a layer that is formed by irradiating the semiconductor substrate 11 with high-energy particles such as helium or protons and that includes crystal lattice defects at a high density. Such a recombination layer 21 shortens the lifetime of the charge carriers.

The operation of the planar diode 10 of the first embodiment configured as described above will be described.
According to the planar diode 10 of the present invention, the recombination layer 21 is not extended to the inside of the active layer 12 while the recombination layer 21 is formed so that one end thereof is in contact with the junction surface 12a of the active layer 12. By adopting the configuration, the lifetime of the charge carriers in the active layer 12 is prevented from being shortened. That is, if the recombination layer 21 is formed to the inside of the active layer 12, the lifetime of charge carriers in the active layer 12 is shortened, and the forward voltage may increase. However, the configuration in which the recombination layer 21 does not extend to the inside of the active layer 12 as in the planar diode 10 of the present invention can prevent an increase in forward voltage in the active layer 12.

  In addition, for example, during transient operation, the hole current concentrates at the connection portion between the active layer 12 and the oxide film 17 and the current density increases. However, the lifetime of charge carriers in the portion of the semiconductor substrate 11 where the recombination layer 21 is formed can be reduced by forming the end surface 21a of the recombination layer 21 in contact with the bonding surface 12a of the active layer 12. Shortened. The recombination layer 21 quickly disappears the portion of the semiconductor substrate 11 where the recombination layer 21 is formed, and the concentration of hole current at the connection portion between the active layer 12 and the oxide film 17 is relaxed. Thereby, the thermal damage of the planar diode 10 can be prevented.

(Semiconductor device: Second embodiment)
FIG. 2 is an enlarged cross-sectional view of a main part showing a cross section along the stacking direction in the peripheral portion of the semiconductor substrate of the planar diode (semiconductor device) of the second embodiment. In addition, the same number is attached | subjected to the structure similar to 1st embodiment, and the detailed description is abbreviate | omitted.
A recombination layer 31 extending from the peripheral edge 11e of the semiconductor substrate 11 toward the center is formed on the semiconductor substrate 11 of the planar diode 30 of the second embodiment. More specifically, in the recombination layer 31, the other end 31b on the side of the peripheral edge 11e of the semiconductor substrate 11 extends to the peripheral edge 11e of the semiconductor substrate 11, and is on the opposite side to the other end 31b. The end surface 31af of the one end portion 31a is formed so as to be separated from the bonding surface 12a of the active layer 12 with a predetermined interval.

  Further, one end 31 a of the recombination layer 31 has a shape that approximates the curved surface shape of the peripheral edge 16 as of the conductive mask layer 16. That is, one end 31 a of the recombination layer 31 is inclined so as to bend in a direction shallower than the bottom surface 12 ae of the bonding surface 12 a of the active layer 12 toward the center of the semiconductor substrate 11.

  In the planar diode 30 of the second embodiment, the recombination layer 31 is formed to the vicinity of the junction surface 12a of the active layer 12, and the active layer 12 is maintained at a predetermined distance to the inside of the active layer. The configuration in which the recombination layer 31 is not extended prevents the lifetime of charge carriers in the active layer 12 from being shortened. That is, if the recombination layer 31 is formed as far as the inside of the active layer 12, the lifetime of charge carriers in the active layer 12 is shortened and the forward voltage may increase. However, it is possible to prevent an increase in forward voltage in the active layer 12 by adopting a configuration in which the recombination layer 31 does not extend to the inside of the active layer 12 as in the planar diode 30 of the present invention.

  Further, for example, in a switching power supply including a planar diode 10, hole current concentrates on the connection portion between the active layer 12 and the oxide film 17 during a transient operation such as emergency stop in an emergency, and the current density Becomes higher. However, by extending one end 31a of the recombination layer 31 to the vicinity of the bonding surface 12a of the active layer 12, the lifetime of the charge carriers in the portion of the semiconductor substrate 11 where the recombination layer 31 is formed is shortened. The Holes in the portion where the recombination layer 31 of the semiconductor substrate 11 is formed by the recombination layer 31 are quickly lost, the rate of change in reverse recovery current is increased, and the hole current in the connection portion between the active layer 12 and the oxide film 17 is increased. Concentration is relaxed. As a result, an increase in leakage current at the peripheral portion of the semiconductor substrate 11 is suppressed, and the planar diode 30 can be prevented from being thermally damaged.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device of the present invention will be described. In the following embodiments, a method for manufacturing the planar diode 10 having the configuration shown in FIG. 1 is illustrated as an example of a method for manufacturing a semiconductor device.
FIG. 3 is a flowchart for explaining a method of manufacturing a planar diode which is an example of the semiconductor device of the present invention. 4 and 5 are cross-sectional views showing in steps a method for manufacturing a planar diode which is an example of the semiconductor device of the present invention. FIG. 6 is a cross-sectional view schematically showing the recombination layer forming step.
First, when manufacturing the planar diode 10, an n-type semiconductor substrate 11, for example, a Si wafer is prepared. The n-type impurity concentration is, for example, about 2 × 10 ¹⁴ atoms / cm ³ .

Next, as shown in FIG. 4A, p-type diffusion layers such as an active layer (first portion) 12 and a guard ring 18 are formed in a predetermined region on the one main surface 11a side of the semiconductor substrate 11 (see FIG. 4A). p-type diffusion layer forming step S1). In this p-type diffusion layer forming step S1, first, an oxide film is formed on the entire main surface 11a of the semiconductor substrate 11, and this oxide film is formed on the active layer 12 and the guard by a photolithography process up to photographic exposure and etching. Only the portion excluding the formation position of the ring 18 is masked. Then, using this oxide film after etching as a mask, p-type impurities such as boron and aluminum are thermally diffused, and a p + -type active layer 12 or the like is formed in a predetermined region on one main surface 11a side of the semiconductor substrate 11. A guard ring 18 is formed. The impurity concentration of such a p + type diffusion layer is, for example, about 1 × 10 ¹⁹ atoms / cm ³ .

  Next, as shown in FIG. 4B, a channel stopper layer 19 is formed in the peripheral portion of one main surface 11a of the semiconductor substrate 11, and a predetermined depth from the other main surface 11b of the semiconductor substrate 11 is formed. The cathode region 14 which is the n + type diffusion layer of the first conductivity type high-concentration impurity is formed up to this range (n-type diffusion layer forming step S2). In the n-type diffusion layer forming step S2, an oxide film generated on one main surface 11a of the semiconductor substrate 11 is used by utilizing the oxide film generated at the time of thermal diffusion of the p-type impurity in the p-type diffusion layer forming step S1, which is the previous step. Only a portion other than the formation position of the channel stopper layer 19 is masked by a photolithography process up to photographic exposure and etching. Then, using the etched oxide film as a mask, for example, n-type impurities such as phosphorus and arsenic are thermally diffused to form an n + -type channel stopper layer 19 in the peripheral portion of one main surface 11 a of the semiconductor substrate 11. .

Further, an n-type impurity is thermally diffused on the other main surface 11b of the semiconductor substrate 11 without particularly forming a mask such as an oxide film, and the other main surface 11b of the semiconductor substrate 11 is directed to the one main surface 11a. Thus, the n + type cathode region 14 is formed to a predetermined depth range. The n + type impurity concentration is, for example, about 1 × 10 ²⁰ atoms / cm ³ .

  In the present embodiment, in the n-type diffusion layer forming step S2, the n + type cathode region 14 is formed by thermally diffusing n-type impurities on the other main surface 11b of the n− type semiconductor substrate 11. In addition to this, a semiconductor substrate in which an n + -type impurity diffusion layer (which becomes the cathode region 14) is formed in advance on the other main surface 11b side can also be used. In this case, the step of forming the cathode region 14 may not be performed in the n-type diffusion layer forming step S2.

Next, as shown in FIG. 4C, an oxide film 17 is formed on one main surface 11a side of the semiconductor substrate 11 (oxide film forming step S3). In forming the oxide film 17, for example, SiO ₂ or the like is formed on one main surface 11 a side of the semiconductor substrate 11. Then, an oxide film 17 having a predetermined shape is formed by a photolithography process up to photographic exposure and etching. In this oxide film forming step S3, an oxide film generated on one main surface 11a of the semiconductor substrate 11 at the time of thermal diffusion of the n-type impurity in the n-type diffusion layer forming step S2 which is the previous step can be used.

  Next, as shown in FIG. 5A, the anode electrode 13 is formed on one main surface 11a side of the semiconductor substrate 11 (electrode layer forming step S4). In forming the anode electrode 13, for example, an Al layer is formed on one main surface 11 a side of the semiconductor substrate 11. Then, an anode electrode 13 having a predetermined shape is formed by a photolithography process up to photographic exposure and etching.

Note that it is preferable to form a Ti layer and a Ni layer so as to increase the wettability with respect to the conductive mask layer 16 to be formed in a later step, overlaid on Al constituting the anode electrode 13. Al constituting the anode electrode 13 generally has low wettability with respect to the solder material constituting the conductive mask layer 16, and as it is, it may be difficult to form the conductive mask layer 16 on the anode electrode 13 in a later step. However, by forming a Ni thin film having high wettability with respect to the solder material via the Ti thin film, the conductive mask layer 16 is brought into close contact with the anode electrode 13 in a subsequent process so as to overlap the anode electrode 13. Thus, the conductive mask layer 16 can be formed.
Alternatively, the anode electrode 13 can be formed of Ni having high wettability with respect to the solder material constituting the conductive mask layer 16. In this case, the anode electrode 13 need not have a multilayer structure.

  Next, as shown in FIG. 5B, a conductive mask layer 16 is formed so as to overlap the anode electrode 13 (mask layer forming step S5). In forming the conductive mask layer 16, a solder paste is applied on the anode electrode 13. At this time, the solder paste is applied so that the thickness of the solder paste decreases from the center of the anode electrode 13 toward the periphery. Then, the conductive mask layer 16 is formed by melting the solder paste applied on the anode electrode 13. The conductive mask layer 16 thus formed has a convex shape that rises from the peripheral edge 16as toward the center.

  Next, as shown in FIG.5 (c), using this electroconductive mask layer 16 as a mask (irradiation mask), the recombination layer 21 is formed by irradiation of a high energy particle (recombination layer formation process S6). . As shown in FIG. 6, in the recombination layer forming step S7, the semiconductor substrate 11 is irradiated with high-energy particles such as helium or protons (helium in FIG. 6) from one main surface 11a side of the semiconductor substrate 11. Lattice defects of the silicon crystal to be formed are formed with high density.

  The formation position of the recombination layer 21 in the thickness direction (depth direction) of the semiconductor substrate 11 is determined by the thickness of the conductive mask layer 16 if the irradiation energy of helium is uniform. That is, the formation position in the thickness direction (depth direction) of the recombination layer 21 can be controlled by the thickness of the conductive mask layer 16 serving as a helium mask. Specifically, as the thickness of the conductive mask layer 16 increases (as it goes toward the center side of the semiconductor substrate 11), the recombination layer 21 is formed toward the one main surface 11a side of the semiconductor substrate 11. At a position where the thickness of the conductive mask layer 16 becomes a certain thickness or more, no helium is present in the semiconductor substrate 11 at all (so that the position becomes shallower toward the center side of the semiconductor substrate 11). Thus, the recombination layer 21 is not formed in the semiconductor substrate 11.

  Due to the action of the conductive mask layer 16, a portion of the semiconductor substrate 11 where the active layer 12 is formed (a central side of the semiconductor substrate 11) is a portion where the active layer 12 is not formed (a peripheral side of the semiconductor substrate 11). Since the conductive mask layer 16 is formed thicker than that, the helium does not reach the active layer 12 even when irradiated with helium, so that the recombination layer 21 is not formed in the active layer 12.

  On the other hand, the peripheral edge 16as of the conductive mask layer 16 gradually decreases as the thickness goes toward the peripheral edge of the semiconductor substrate 11, and therefore, from a predetermined depth position of the semiconductor substrate 11 according to the thickness of the conductive mask layer 16, A recombination layer 21 curved so as to gradually become deeper toward the peripheral side of the semiconductor substrate 11 is formed. One end portion 21 a of the recombination layer 21 is formed in a shape that follows the surface shape of the conductive mask layer 16 because of the characteristic that the reach depth of helium varies depending on the thickness of the conductive mask layer 16. That is, one end 21 a of the recombination layer 21 is formed in a shape that approximates the curved surface shape of the peripheral edge 16 as of the conductive mask layer 16.

  Since the conductive mask layer 16 is not formed on the one main surface 11a of the semiconductor substrate 11 in the portion from the one end portion 21a toward the other end portion 21b of the recombination layer 21, the recombination layer 21 is , Formed in a straight line with a certain depth. In the present embodiment, the recombination layer 21 is formed so as to extend linearly toward the other end surface at a position deeper than the bottom surfaces of the guard rings 18 and 18.

Thereafter, a cathode electrode 15 made of, for example, Ni is formed on the other main surface 11b of the semiconductor substrate 11 so as to overlap the cathode region 14, thereby manufacturing the planar diode 10 which is an example of the semiconductor device of the present invention. (See FIG. 1).
The cathode electrode 15 can also be formed together with the anode electrode 13 in the electrode layer forming step S4 described above. In this case, an electrode layer made of Ni is simultaneously formed on one main surface 11a and the other main surface 11b of the semiconductor substrate 11, and the entire process is further simplified.

  Thereafter, defect annealing of the recombination layer 21 is performed by heat treatment during product assembly.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

10 Planar type diode (semiconductor device)
11 Semiconductor substrate 12 Active layer (first part)
13 Anode electrode (electrode layer)
14 Cathode region 15 Cathode electrode 16 Conductive mask layer (solder layer)
17 Oxide film (passivation)
18 Guard ring (second part)
21 Recombination layer

Claims (7)

A semiconductor substrate having a first conductivity type, a first portion formed on a part of one main surface side of the semiconductor substrate, and having a second conductivity type opposite to the first conductivity type; An electrode layer bonded to one part, and a conductive mask layer formed to overlap the electrode layer,
The electrode layer is formed to overlap the one main surface side at a position from the periphery of the semiconductor substrate toward the center,
The semiconductor substrate is formed with a recombination layer extending from the periphery toward the center,
One end portion of the recombination layer is in the vicinity of an end portion on the peripheral side of the semiconductor substrate in a bonding surface of the first portion with the semiconductor substrate, and follows the surface shape of the conductive mask layer. A semiconductor device characterized by being formed in a different shape.   The semiconductor device according to claim 1, wherein the one end portion of the recombination layer is in contact with the first portion.   3. The semiconductor device according to claim 1, wherein the one end portion of the recombination layer is inclined in a direction shallower than a bottom surface of the first portion.   2. The conductive mask layer is made of a solder material, and the conductive mask layer is formed so as to gradually increase in height from the periphery of the conductive mask layer toward the center. 4. The semiconductor device according to any one of claims 3 to 3. The semiconductor substrate is further formed with a second portion of the second conductivity type that extends outside the first portion and extends in the depth direction from one main surface side of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the recombination layer extends to a position that is the same as or deeper than a bottom surface of the second portion. A method of manufacturing a semiconductor device according to any one of claims 1 to 5,
A second conductivity type diffusion layer forming step of forming the first portion of the second conductivity type on a part of one main surface side of the semiconductor substrate;
An electrode layer forming step of forming the electrode layer so as to be in contact with the first portion;
A mask layer forming step of forming a conductive mask layer on the electrode layer;
A recombination layer forming step of forming the recombination layer by irradiating high energy particles in the depth direction of the semiconductor substrate using the conductive mask layer as an irradiation mask. A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 6, wherein in the recombination layer forming step, helium or proton is irradiated as the high energy particles.

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