JP2019021745A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

To provide a semiconductor device and a manufacturing method therefor capable of realizing good contact between an electrode portion and a through electrode without affecting a device provided on a semiconductor substrate.SOLUTION: A semiconductor device includes a semiconductor substrate, an insulating film disposed on the semiconductor substrate, a pad electrode disposed on the insulating film, and a conductive member that is provided in an opening that penetrates the semiconductor substrate and reaches the pad electrode and that is electrically connected to the pad electrode, and the pad electrode includes a conductive oxide layer provided at least at a connection portion with the conductive member, a metal layer electrically connected to the conductive oxide layer, and a barrier metal layer provided between the conductive oxide layer and the insulating film.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device having a through electrode and a manufacturing method.

  A semiconductor device such as a solid-state imaging device includes a semiconductor substrate provided with elements such as transistors and wiring portions connected to these elements. The wiring part includes a wiring pattern for connecting a certain element to another element, a wiring pattern for supplying power to the element, and the like. The semiconductor device further includes an electrode portion for connecting a part of the wiring portion to an external device (another semiconductor device, a circuit board, or the like).

  When a semiconductor device is connected to an external device by, for example, flip-chip connection or the like, an electrode provided across the electrode portion from the back side of the semiconductor substrate (the side opposite to the front surface side of the semiconductor substrate on which the wiring portion is provided) In some cases, the semiconductor device and the external device are electrically connected to each other. This electrode is referred to as a “penetrating electrode” because it is formed so as to penetrate the semiconductor substrate. The through electrode is formed, for example, by etching from the back side of the semiconductor substrate to form an opening through which the electrode portion is exposed through the semiconductor substrate and the wiring interlayer insulating film, and then a conductive member is embedded in the opening. The

JP 2011-040457 A

  However, during etching to form an opening that reaches the electrode from the back side of the semiconductor substrate, the surface of the electrode exposed at the bottom of the opening is oxidized, increasing the contact resistance between the electrode and the through electrode There was something to do. The oxide film formed on the surface of the electrode part can be removed by reverse sputtering before forming the through electrode, but it is formed at the bottom of the deep, large aspect ratio opening that penetrates the semiconductor substrate. It was difficult to uniformly remove the formed oxide film within the surface. Although it is conceivable to perform reverse sputtering under over-etching conditions so that no residue is generated at the bottom of the opening, damage to the electrode increases, and in the worst case, the electrode may be penetrated.

  An object of the present invention is to provide a semiconductor device capable of realizing a good contact between an electrode portion and a through electrode without affecting elements provided on a semiconductor substrate and a method for manufacturing the same.

  According to an aspect of the present invention, a semiconductor substrate, an insulating film disposed on the semiconductor substrate, a pad electrode disposed on the insulating film, and the pad electrode penetrating the semiconductor substrate. And a conductive member electrically connected to the pad electrode, the pad electrode comprising at least a conductive oxide layer provided at a connection portion with the conductive member And a metal layer electrically connected to the conductive oxide layer, and further comprising a barrier metal layer provided between the conductive oxide layer and the insulating film. The

  According to another aspect of the present invention, a semiconductor substrate, an insulating film disposed on the semiconductor substrate, a semiconductor element disposed on the semiconductor substrate, and the semiconductor element are electrically connected. And a conductive member provided in an opening reaching the pad electrode through the semiconductor substrate and electrically connected to the pad electrode, the pad electrode comprising at least the pad electrode A conductive oxide layer provided at a connection portion with the conductive member; and a metal layer electrically connected to the conductive oxide layer, wherein the semiconductor element and the conductive oxide layer There is provided a semiconductor device further having a barrier portion made of a barrier metal material disposed therebetween.

  According to still another aspect of the present invention, a step of forming an insulating film on a semiconductor substrate, a metal layer on the insulating film, and a conductive layer electrically connected to the metal layer Forming a pad electrode including an oxide layer and a barrier metal layer disposed between the insulating film and the conductive oxide layer; and passing through the semiconductor substrate and the insulating film to conduct the conductive There is provided a method for manufacturing a semiconductor device, which includes a step of forming an opening reaching the conductive oxide layer, and a step of forming a conductive member electrically connected to the pad electrode in the opening.

  According to the present invention, it is possible to realize a good contact between the electrode portion and the through electrode without affecting the elements provided on the semiconductor substrate.

It is a schematic sectional drawing which shows the structure of the semiconductor device by 1st Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by 1st Embodiment of this invention. FIG. 9 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention; It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor device by 1st Embodiment of this invention. FIG. 9 is a process cross-sectional view (No. 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention; It is a schematic sectional drawing which shows the structure of the semiconductor device by 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device by 2nd Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device by 3rd Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by 3rd Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor device by 3rd Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device by 4th Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device by 4th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device by 5th Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device by 5th Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device by 6th Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device by 6th Embodiment of this invention.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. 2 to 5 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.
The semiconductor device according to the present embodiment includes a semiconductor substrate 10. A semiconductor element 16 is provided on the first surface 12 side which is one surface of the semiconductor substrate 10. An interlayer insulating film 20 is provided on the first surface 12 of the semiconductor substrate 10 on which the semiconductor element 16 is provided. A contact plug 24 that is electrically connected to the semiconductor element 16 is disposed in the interlayer insulating film 20. On the interlayer insulating film 20, a wiring layer 38 electrically connected to the semiconductor element 16 through the contact plug 24, and a pad electrode 42 which is an electrode part for performing electrical connection with an external device, Is provided. An interlayer insulating film 44 is provided on the interlayer insulating film 20. A support substrate 50 is bonded onto the interlayer insulating film 44 via an adhesive layer 48.

  A via hole 54 that is an opening reaching the pad electrode 42 is provided in the semiconductor substrate 10 and the interlayer insulating film 20. The via hole 54 penetrates the semiconductor substrate 10 and the interlayer insulating film 20 from the second surface 14 side and reaches the pad electrode 42. An insulating film 52 is provided on the second surface 14 of the semiconductor substrate 10. An insulating film 56 is provided on the side surface of the via hole 54. A conductive member that is electrically connected to the pad electrode 42 is disposed in the via hole 54 provided with the insulating film 56. The conductive member is a through electrode 60 arranged so as to penetrate the semiconductor substrate 10. The through electrode 60 has one end electrically connected to the pad electrode 42 and the other end extending on the insulating film 52 disposed on the second surface 14 of the semiconductor substrate 10. A solder ball 64 is provided on the other end portion of the through electrode 60.

  The pad electrode 42 includes at least a conductive oxide layer 28 provided at a connection portion with the through electrode 60 and an electrode layer 40 electrically connected to the conductive oxide layer 28. In the semiconductor device of this embodiment, the conductive oxide layer 28 is disposed between the electrode layer 40 and the semiconductor substrate 10. Metal diffusion for preventing the metal material constituting the conductive oxide layer 28 from diffusing into the interlayer insulating films 20 and 44 between the conductive oxide layer 28 and the interlayer insulating films 20 and 44. Barrier metal layers 26 and 30 are provided as prevention layers. The barrier metal layer 26 is disposed so as to cover the lower surface (the surface on the first surface 12 side of the semiconductor substrate 10) of the conductive oxide layer 28 excluding the connection portion with the through electrode 60. The barrier metal layer 30 is disposed so as to cover the upper surface (the surface opposite to the first surface 12 side) and the side surface (the surface between the upper surface and the lower surface) of the conductive oxide layer 28. ing. The conductive oxide layer 28 and the electrode layer 40 are stacked via the barrier metal layer 30. The through electrode 60 penetrates the barrier metal layer 26 from the first surface 12 side of the semiconductor substrate 10 and is in contact with the conductive oxide layer 28. In this specification, the barrier metal layers 26 and 30 may be described as a part of the pad electrode 42.

  The semiconductor substrate 10 is a silicon substrate, for example. The semiconductor element 16 is an element for realizing a predetermined function of the semiconductor device, and includes a MOS transistor, a diode, and the like. The semiconductor substrate 10 may be further provided with an element other than the semiconductor element 16, for example, a capacitor element or a resistance element. The interlayer insulating films 20 and 44 are provided on the entire surface of the semiconductor substrate 10 including the semiconductor element 16 on the first surface 12 side, and are made of, for example, an insulating material such as silicon oxide or silicon nitride.

  The wiring layer 38 includes wiring patterns for connecting elements, wiring patterns for supplying power to the elements, and the like disposed in the interlayer insulating films 20 and 44. Although only one wiring layer 38 is shown in FIG. 1, a plurality of wiring layers may be arranged. In that case, the wiring layers are connected to each other via via plugs. The wiring layer 38 can be made of a conductive material mainly composed of a metal such as copper or aluminum. The contact plug 24 can be made of, for example, a metal material such as tungsten. The contact plug 24 is a barrier made of a conductive material such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN) so that the constituent metal does not diffuse into the semiconductor substrate 10. You may further have a metal layer.

  The electrode layer 40 is a lead electrode portion that is electrically connected to a part of the wiring pattern of the wiring layer 38. Similarly to the wiring layer 38, the electrode layer 40 is made of a conductive material mainly composed of a metal such as copper or aluminum, and includes a metal layer such as copper or aluminum. The electrode layer 40 is preferably formed of the same material and the same material as any of the wiring layers 38 from the viewpoint of process reduction. However, the electrode layer 40 is not necessarily the same layer as any one of the wiring layers 38, and may be a layer different from the wiring layer 38. The electrode layer 40 may further include other layers such as a contact layer, a barrier metal layer, and an antireflection film in addition to the metal layer described above.

  The conductive oxide layer 28 is made of a conductive oxide material that is less susceptible to alteration or characteristic variation due to exposure to an atmosphere containing oxygen, fluorine, or the like. As the conductive oxide layer 28, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), or the like is applicable. The conductive oxide layer 28 only needs to include at least one conductive oxide material selected from the group including ITO, IZO, IGZO, and the like, and may be a laminated film of these conductive oxide materials.

  The barrier metal layers 26 and 30 are made of a metal material constituting the conductive oxide layer 28, for example, a conductive material that can suppress diffusion of In, Sn, Zn, or the like. As the barrier metal layers 26 and 30, for example, conductive materials such as Ti, Ta, TiN, and TaN are applicable. The barrier metal layers 26 and 30 may include at least one conductive material selected from the group including Ti, Ta, TiN, and TaN, and may be a laminated film of these conductive materials.

  The through electrode 60 extends from the second surface 14 side of the semiconductor substrate 10 toward the pad electrode 42 formed on the first surface 12 side of the semiconductor substrate 10. The through electrode 60 is configured by embedding a conductive member in a via hole 54 provided in the semiconductor substrate 10, the interlayer insulating film 20, and the barrier metal layer 26. As the conductive member, copper, aluminum, or the like can be used, and a barrier metal made of a conductive material such as Ti, Ta, TiN, or TaN is further provided so that these metal materials do not diffuse into the semiconductor substrate 10. May be.

  The insulating films 52 and 56 are insulating members for maintaining insulation between the semiconductor substrate 10 and the through electrode 60. As the insulating films 52 and 56, for example, an insulating material such as silicon oxide or silicon nitride can be used.

  The drawings of the present application are conceptual diagrams drawn so that the structure of each part can be easily understood, and the ratio of the size of each part does not necessarily conform to the scale of an actual semiconductor device. For example, in an actual semiconductor device, the thickness of the interlayer insulating film 20 is, for example, about several microns or less, whereas the thickness of the semiconductor substrate 10 is, for example, several tens of microns or more.

  As described above, in the semiconductor device according to the present embodiment, the pad electrode 42 includes the conductive oxide layer 28 disposed between the electrode layer 40 and the semiconductor substrate 10. The through electrode 60 is electrically connected to the electrode layer 40 through the conductive oxide layer 28. Therefore, the electrode layer 40 is not directly exposed to the etching atmosphere when the via hole 54 for embedding the through electrode 60 is opened, and the contact characteristics between the electrode layer 40 and the through electrode 60 are prevented from deteriorating. be able to.

  In the semiconductor device according to the present embodiment, the barrier metal layers 26 and 30 are provided around the conductive oxide layer 28, and the metal material constituting the conductive oxide layer 28 diffuses into the interlayer insulating films 20 and 44. Is suppressed. This is because when the metal material constituting the conductive oxide layer 28 diffuses in the interlayer insulating films 20 and 44 and reaches the semiconductor element 16, the characteristics of the semiconductor element 16 may be affected. For example, in a solid-state imaging device, there is a possibility that dark current increases due to metal impurities mixed into the photoelectric conversion element, and the image is degraded.

  Therefore, according to the configuration of the semiconductor device according to the present embodiment, the contact characteristics between the electrode layer 40 and the through electrode 60 can be improved without affecting the characteristics of the semiconductor element 16.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. A known semiconductor manufacturing process can be used for manufacturing the semiconductor device. Moreover, although description is abbreviate | omitted here, you may perform another process, for example, a heat treatment process, a washing process process, etc. between each process mentioned later as needed.

  First, a predetermined semiconductor element 16 corresponding to the semiconductor device to be manufactured is formed on the first surface 12 side, which is one surface of the semiconductor substrate 10 (FIG. 2A). An element isolation portion 18 may be formed on the semiconductor substrate 10 by an STI (Shallow Trench Isolation) method or the like. Each semiconductor element 16 can be electrically isolated from other adjacent elements by the element isolation unit 18. FIG. 2A shows a MOS transistor as an example of the semiconductor element 16 provided in the active region defined by the element isolation portion 18.

  Next, the interlayer insulating film 20 and the contact plug 24 disposed in the interlayer insulating film 20 are formed on the semiconductor substrate 10 on which the semiconductor element 16 is formed (FIG. 2B). As the interlayer insulating film 20, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride can be used.

  For example, first, an insulating film such as silicon oxide, silicon nitride, or silicon oxynitride is deposited on the semiconductor substrate 10 provided with the semiconductor element 16 by a CVD method to form the interlayer insulating film 20. Next, a contact hole 22 reaching the electrode of the semiconductor element 16 is formed in the interlayer insulating film 20 using photolithography and dry etching. Next, a contact plug 24 is formed by embedding a conductive material such as tungsten in the contact hole 22.

  Next, a barrier metal layer 26 as a metal diffusion prevention layer for preventing diffusion of the metal material is formed on the interlayer insulating film 20 (FIG. 2C). As the barrier metal layer 26, a conductive material such as Ti, Ta, TiN, or TaN can be applied.

  For example, first, a titanium film of, eg, a 50 nm-thickness is deposited on the interlayer insulating film 20 by sputtering. Next, the titanium film is patterned using photolithography and dry etching using chlorine gas to form the barrier metal layer 26. The barrier metal layer 26 is formed in a region where the pad electrode 42 connected to the through electrode 60 is disposed.

  Next, a conductive oxide layer 28 is formed on the barrier metal layer 26 (FIG. 2D). As the conductive oxide layer 28, ITO, IZO, IGZO, or the like can be applied.

  For example, first, an ITO film having a thickness of, for example, 200 nm is deposited on the interlayer insulating film 20 provided with the barrier metal layer 26 by a sputtering method. Next, the ITO film is patterned using photolithography and wet etching using an aqueous oxalic acid solution to form a conductive oxide layer 28 made of the ITO film on the barrier metal layer 26.

  Although an example in which the barrier metal layer 26 and the conductive oxide layer 28 are deposited and patterned on the interlayer insulating film 20 is shown here, the barrier metal layer 26 and the conductive oxide layer 28 are so-called damascene method. May be formed. For example, a wiring groove is formed in the surface portion of the interlayer insulating film 20, and after the barrier metal layer 26 and the conductive oxide layer 28 are formed in this order in the wiring groove, these conductive layers on the interlayer insulating film 20 are formed. The film may be removed by a CMP method or the like.

  Next, a barrier metal layer 30 is formed as a metal diffusion preventing layer for preventing diffusion of the metal material so as to cover the side surface and the upper surface of the conductive oxide layer 28 (FIG. 3A). As the barrier metal layer 30, a conductive material such as Ti, Ta, TiN, or TaN can be applied. As a result, the periphery of the conductive oxide layer 28 is surrounded by the barrier metal layers 26 and 30.

  For example, first, a titanium film of, eg, a 50 nm-thickness is deposited on the interlayer insulating film 20 on which the barrier metal layer 26 and the conductive oxide layer 28 are disposed by sputtering. Next, the titanium film is patterned using photolithography and dry etching using chlorine gas, thereby forming a barrier metal layer 30 that covers the side and upper surfaces of the conductive oxide layer 28.

  Next, a wiring layer 38 electrically connected to the semiconductor element 16 through the contact plug 24 is formed on the interlayer insulating film 20. On the barrier metal layer 30, the electrode layer 40 that forms the pad electrode 42 together with the barrier metal layers 26 and 30 and the conductive oxide layer 28 is formed. Thus, the wiring layer 38 and the pad electrode 42 are formed on the interlayer insulating film 20 (FIG. 3B).

  For example, first, a conductive layer mainly composed of aluminum having a thickness of, for example, 500 nm is deposited by sputtering. Next, the conductive layer is patterned using photolithography and dry etching to form the wiring layer 38 and the electrode layer 40. The wiring layer 38 and the electrode layer 40 may be formed by patterning one conductive layer, or may be formed by patterning conductive layers arranged in different layers with an insulating film interposed therebetween. . The wiring layer 38 and the electrode layer 40 may be formed by a so-called damascene method.

  The film forming temperature of aluminum in the sputtering method is about 280 ° C., for example. The metal material (In or Sn in the case of ITO) constituting the conductive oxide layer 28 may diffuse into the interlayer insulating film 20 due to the temperature at the time of film formation or heat treatment in a later process. However, in this embodiment, since the conductive oxide layer 28 is surrounded by the barrier metal layers 26 and 30, the metal material constituting the conductive oxide layer 28 is prevented from diffusing into the interlayer insulating film 20. Can be suppressed.

  Next, an interlayer insulating film 44 is formed on the interlayer insulating film 20 provided with the wiring layer 38 and the pad electrode 42 (FIG. 3C). As the interlayer insulating film 44, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride can be used.

  For example, first, a silicon oxide film having a thickness of, for example, 600 nm is deposited on the interlayer insulating film 20 provided with the wiring layer 38 and the pad electrode 42 by a plasma CVD method to form the interlayer insulating film 44.

  Next, if necessary, the support substrate 50 is bonded to the first surface 12 side of the semiconductor substrate 10 on which the semiconductor element 16, the pad electrode 42, the interlayer insulating films 20 and 44, etc. are formed via the adhesive layer 48. The support substrate 50 is not particularly limited. For example, a quartz glass substrate having a thickness of 0.5 mm can be used.

  Next, if necessary, the semiconductor substrate 10 is back-grinded from the second surface 14 side of the semiconductor substrate 10 which is the surface opposite to the first surface 12 to thin the semiconductor substrate 10 (FIG. 4). (A)). For example, the semiconductor substrate 10 is thinned to a thickness of about 0.2 mm by back grinding. Thinning the semiconductor substrate 10 is preferable because it facilitates formation of the through electrode 60 in a subsequent process. In the present specification, a new surface that appears by performing back grinding on the second surface 14 of the semiconductor substrate 10 is also referred to as the second surface 14 as before the back grinding.

  Next, an insulating film 52 such as a silicon nitride film is deposited on the second surface 14 of the semiconductor substrate 10 by, for example, plasma CVD, and then the insulating film 52 is patterned using photolithography and dry etching. Thereby, the insulating film 52 having an opening in the region where the through electrode 60 is to be formed is formed. The insulating film 52 is a film used as a mask when forming the via hole 54, and has a thickness that does not disappear at least by etching when forming the via hole 54.

  Next, using the insulating film 52 as a mask, the semiconductor substrate 10, the interlayer insulating film 20, and the barrier metal layer 26 are sequentially dry-etched from the second surface 14 side of the semiconductor substrate 10, and the via hole 54 reaching the conductive oxide layer 28. Is formed (FIG. 4B).

  The via hole 54 can be formed by, for example, two-stage etching including a step of etching the semiconductor substrate 10 and a step of etching the interlayer insulating film 20 and the barrier metal layer 26.

  The semiconductor substrate 10 can be etched by, for example, dry etching using a so-called Bosch method. According to dry etching using the Bosch method, a through-hole perpendicular to the surface of the semiconductor substrate 10 can be easily formed. In the dry etching using the Bosch method, the etching rate of silicon oxide or silicon nitride is very small as compared with the etching rate of silicon. Therefore, the etching can be stopped when the interlayer insulating film 20 is exposed.

The Bosch method consists of three steps of (1) isotropic etching step, (2) protective film forming step, and (3) protective film removal step on the bottom of the via as one cycle, and each step is performed at high speed for a short time. This is a technique for repeating this cycle. In the isotropic etching step, gas such as SF ₆ is used, and etching proceeds mainly using radicals as reactive species. If this step is performed for a long time, the side etching becomes large. Therefore, the protective film forming step is switched in a short time (about several seconds). In the protective film formation step, a CF polymer film is deposited by decomposing a gas such as C ₄ F ₈ in plasma. This step is also switched to the next step in a short time of about several seconds. In the step of removing the protective film on the bottom surface of the via, a gas such as SF ₆ is used and a relatively high bias power is applied to the stage side on which the semiconductor substrate 10 is installed, so that ions having anisotropy can be generated. The protective film on the bottom surface is removed. At this time, since the ions hardly enter the side surface portion, the side surface protective film is not removed. In the isotropic etching step of the next cycle, the side surface portion is protected from etching by the protective film, and the etching proceeds only on the bottom surface of the via hole 54. By repeating this cycle, the etching can be performed little by little in the depth direction of the semiconductor substrate 10.

The interlayer insulating film 20 and the barrier metal layer 26 can be etched by capacitively coupled RIE using, for example, a CF ₄ / C ₄ F ₈ / O ₂ / Ar mixed gas as an etching gas. Under this condition, the barrier metal layer 26 can also be etched following the etching of the interlayer insulating film 20.

  In this manner, a via hole 54 penetrating the semiconductor substrate 10, the interlayer insulating film 20 and the barrier metal layer 26 is formed, and the pad electrode 42 (conductive oxide layer 28) is exposed at the bottom of the via hole 54.

  When the pad electrode 42 exposed at the bottom of the via hole 54 is exposed to the process gas, the surface state changes depending on the constituent material of the exposed portion of the pad electrode 42, which increases the contact resistance. For example, when the electrode layer 40 including a metal layer such as aluminum is exposed at the bottom of the via hole 54, a thin oxide film or fluoride film is formed on the surface thereof, and the contact resistance between the pad electrode 42 and the through electrode 60 increases. To do.

  In this regard, in this embodiment, since the conductive oxide layer 28 is provided below the electrode layer 40 via the barrier metal layer 30, the conductive oxide layer 28 is formed before the via hole 54 reaches the electrode layer 40. Exposed. By stopping the etching of the via hole 54 at the conductive oxide layer 28, it is possible to prevent the electrode layer 40 from being exposed at the bottom of the via hole 54. Since the conductive oxide layer 28 has higher oxidation resistance and fluorination resistance than a metal material such as aluminum, an oxide film or a fluorination film is formed between the pad electrode 42 and the through electrode 60 to increase contact resistance. Can be suppressed.

  From such a point of view, the etching time of the interlayer insulating film 20 and the barrier metal layer 26 is set to the material constituting the conductive oxide layer 28 so that the etching of the via hole 54 stops in the middle of the conductive oxide layer 28. It is determined appropriately in consideration of the etching selectivity.

  For example, the total film thickness of the interlayer insulating film 20 and the barrier metal layer 26 is 1.2 μm, and the etching rate thereof is 400 nm / min. Further, it is assumed that the conductive oxide layer 28 has a thickness of 100 nm and an etching rate of 80 nm / min (that is, the selection ratio is 5). In this case, the interlayer insulating film 20 and the barrier metal layer 26 disappear in just 3 minutes, and the conductive oxide layer 28 disappears in 1 minute 15 seconds thereafter. That is, the via hole 54 can be prevented from reaching the electrode layer 40 by making the total etching time shorter than 4 minutes 15 seconds.

  When over-etching is performed assuming that the interlayer insulating film 20 and the barrier metal layer 26 have a film thickness distribution and an etching rate distribution, the film thickness of the conductive oxide layer 28 is set in consideration of the amount of over-etching. It is desirable to do. For example, when 50% overetching is performed in the above example, the etching time of the interlayer insulating film 20 and the barrier metal layer 26 is increased by 1 minute 30 seconds, and etching is performed for 4 minutes 30 seconds. Therefore, in order to prevent the conductive oxide layer 28 from disappearing by this overetching for 1 minute 30 seconds, the conductive oxide layer 28 is thicker than the film thickness (120 nm) that would be lost by overetching. Form it.

  Next, an insulating film 56 is formed on the second surface 14 side of the semiconductor substrate 10 including the side surface and the bottom surface of the via hole 54 (exposed surface of the conductive oxide layer 28) (FIG. 4C). An insulating material such as silicon oxide or silicon nitride can be used for the insulating film 56.

  Next, the insulating film 56 is etched back by dry etching, and the insulating film 56 on the bottom surface of the via hole 54 is removed while leaving the insulating film 56 on the side surface of the via hole 54 (FIG. 5A). At this time, the insulating film 56 on the second surface 14 of the semiconductor substrate 10 may not necessarily be completely removed. As a result, the pad electrode 42 (conductive oxide layer 28) is exposed on the bottom surface of the via hole 54.

  Next, a metal material such as copper or aluminum is embedded in the via hole 54 to form the through electrode 60 connected to the pad electrode 42 (FIG. 5B). For example, after forming a metal seed layer (not shown) made of copper by sputtering or the like, copper is formed by electrolytic plating using a photoresist film (not shown) that exposes a region where the through electrode 60 is to be formed as a mask. . After removing the resist film, the unnecessary portion of the metal seed layer is removed, thereby forming the through electrode 60 made of copper.

  5B shows a state in which the via hole 54 is completely filled with the conductive member, the conductive member may be formed conformally along the side surface and the bottom surface of the via hole 54. Further, a conductive material such as titanium, tantalum, titanium nitride, or tantalum nitride is provided between the insulating film 56 and the through electrode 60 so that the metal material embedded in the via hole 54 does not diffuse into the semiconductor substrate 10. A barrier metal layer may be provided.

  Next, a solder resist 62 is applied to the second surface 14 side of the semiconductor substrate 10 to form an opening that exposes the through electrode 60 by patterning, and then solder balls 64 are placed on the exposed through electrode 60 (FIG. 5). (C)). Thereafter, the semiconductor device according to the present embodiment is completed through processes such as dicing.

  Thus, according to the present embodiment, it is possible to suppress an increase in contact resistance between the pad electrode 42 disposed on the first surface 12 side of the semiconductor substrate 10 and the through electrode 60. Further, the diffusion of metal from the conductive oxide layer 28 can be suppressed, and the characteristic deterioration of the semiconductor element 16 can be suppressed.

[Second Embodiment]
A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 6 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. FIG. 7 is a process cross-sectional view illustrating the semiconductor device manufacturing method according to the present embodiment.

  In the semiconductor device according to the present embodiment, as shown in FIG. 6, the barrier metal layer 30 is not disposed between the conductive oxide layer 28 and the electrode layer 40, and the upper surface of the conductive oxide layer 28 and the electrode This is different from the semiconductor device according to the first embodiment in that the lower surface of the layer 40 is in direct contact.

  Diffusion of the metal material constituting the conductive oxide layer 28 can be suppressed not only by the barrier metal layers 26 and 30 but also by the electrode layer 40. Therefore, even when the conductive oxide layer 28 is surrounded by the barrier metal layers 26 and 30 and the electrode layer 40 as in the semiconductor device according to the present embodiment, the metal material constituting the conductive oxide layer 28 is interlayer-insulated. Diffusion into the films 20 and 44 can be suppressed.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, in the same manner as the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 2A to 2D, the semiconductor element 16 and the interlayer insulating film 20 are formed on the first surface 12 side of the semiconductor substrate 10. Then, a barrier metal layer 26, a conductive oxide layer 28, and the like are formed.

  Next, a barrier metal layer 30 is formed on the side surface of the conductive oxide layer 28 as a metal diffusion prevention layer for preventing diffusion of the metal material (FIG. 7A).

  For example, first, a titanium film of, eg, a 50 nm-thickness is deposited on the interlayer insulating film 20 on which the barrier metal layer 26 and the conductive oxide layer 28 are disposed by sputtering. Next, the titanium film is etched back by dry etching using chlorine gas, and the barrier metal layer 30 made of the titanium film is selectively left on the side surface of the conductive oxide layer 28. By doing in this way, the photolithography process for patterning the barrier metal layer 30 becomes unnecessary, and the manufacturing cost can be reduced.

  Next, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIG. 3B, a wiring layer electrically connected to the semiconductor element 16 via the contact plug 24 on the interlayer insulating film 20. 38 is formed. Further, the electrode layer 40 is formed on the conductive oxide layer 28 so as to cover the entire upper surface (FIG. 7B). Thereby, the periphery of the conductive oxide layer 28 is surrounded by the barrier metal layers 26 and 30 and the electrode layer 40.

  Thereafter, through electrodes 60 and the like are formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 3C to 5C, thereby completing the semiconductor device according to the present embodiment (FIG. 7 (c)).

  Thus, according to the present embodiment, it is possible to suppress an increase in contact resistance between the pad electrode 42 disposed on the first surface 12 side of the semiconductor substrate 10 and the through electrode 60. Further, the diffusion of metal from the conductive oxide layer 28 can be suppressed, and the characteristic deterioration of the semiconductor element 16 can be suppressed.

[Third Embodiment]
A semiconductor device and a manufacturing method thereof according to the third embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device according to the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 8 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. 9 and 10 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  In the semiconductor device according to the present embodiment, the barrier metal layer 30 is not disposed between the conductive oxide layer 28 and the electrode layer 40 as shown in FIG. Is different from the semiconductor device according to the first embodiment in that is covered with the electrode layer 40.

  Also in the semiconductor device according to the present embodiment, since the conductive oxide layer 28 is surrounded by the barrier metal layer 26 and the electrode layer 40, the metal material constituting the conductive oxide layer 28 is the interlayer insulating films 20 and 44. Diffusion inside can be suppressed. A barrier metal layer (not shown) that covers the upper surface and side surfaces of the electrode layer 40 is further provided to further suppress the diffusion of the metal material constituting the conductive oxide layer 28 into the interlayer insulating films 20 and 44. You may do it.

  In the first and second embodiments, since the insulating film 56 is provided on the entire side surface of the via hole 54, there is a slight region where the conductive oxide layer 28 and the insulating film 56 are in contact with each other at the bottom of the via hole 54. To do. For this reason, the metal material constituting the conductive oxide layer 28 may diffuse into the interlayer insulating film 20 through the insulating film 56. However, in the present embodiment, since the insulating film 56 provided on the side surface of the via hole 54 is spaced apart from the conductive oxide layer 28, the metal material constituting the conductive oxide layer 28 is the insulating film 56. It is possible to suppress the diffusion into the interlayer insulating films 20 and 44 via.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, in the same manner as the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 2A to 2D, the semiconductor element 16 and the interlayer insulating film 20 are formed on the first surface 12 side of the semiconductor substrate 10. Then, a barrier metal layer 26, a conductive oxide layer 28, and the like are formed.

  Next, a wiring layer 38 electrically connected to the semiconductor element 16 through the contact plug 24 is formed on the interlayer insulating film 20. Further, the electrode layer 40 is formed on the barrier metal layer 26 on which the conductive oxide layer 28 is disposed so as to cover the side surface and the upper surface of the conductive oxide layer 28 (FIG. 9A). Thereby, the periphery of the conductive oxide layer 28 is surrounded by the barrier metal layer 26 and the electrode layer 40. By doing in this way, the process of forming the barrier metal layer 30 becomes unnecessary, and manufacturing cost can be reduced.

  Next, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. The support substrate 50 is bonded, and the back grinding process is performed from the second surface 14 side.

  Next, an insulating film 52 such as a silicon nitride film is deposited on the second surface 14 of the semiconductor substrate 10 by, for example, plasma CVD, and then the insulating film 52 is patterned using photolithography and dry etching. Thereby, the insulating film 52 having an opening in the region where the through electrode 60 is to be formed is formed.

  Next, using the insulating film 52 as a mask, the semiconductor substrate 10 is dry-etched from the second surface 14 side of the semiconductor substrate 10 to form a via hole 54 so as to reach the middle of the interlayer insulating film 20 (FIG. 9B). )).

  As in the case of the first embodiment, the semiconductor substrate 10 can be etched by dry etching using the Bosch method. According to dry etching using the Bosch method, a through-hole perpendicular to the surface of the semiconductor substrate 10 can be easily formed. In the dry etching using the Bosch method, the etching rate of silicon oxide or silicon nitride is very small with respect to the etching rate of silicon, so that the etching stops in the middle of the interlayer insulating film 20. The state at this time is shown in FIG.

  Next, an insulating film 56 is formed on the second surface 14 side of the semiconductor substrate 10 including the side surface and the bottom surface of the via hole 54 (FIG. 9C).

  Next, the insulating film 56 is etched back by dry etching, and the insulating film 56 on the bottom surface of the via hole 54 is removed while leaving the insulating film 56 on the side surface of the via hole 54.

  Next, by dry etching the interlayer insulating film 20 and the barrier metal layer 26 using the insulating films 52 and 56 as a mask, the via hole 54 is further dug up to the conductive oxide layer 28, and the via hole 54 reaching the conductive oxide layer 28. Is formed (FIG. 10A). The etching time of the interlayer insulating film 20 and the barrier metal layer 26 is configured so that the etching of the via hole 54 stops in the middle of the conductive oxide layer 28 as in the case of the first embodiment. It is determined appropriately in consideration of the etching selectivity with respect to the material to be processed.

  Next, a barrier metal layer 58 is formed on the second surface 14 side of the semiconductor substrate 10 including the side surface and the bottom surface on which the insulating film 56 of the via hole 54 is disposed (FIG. 10B). The barrier metal layer 58 can be formed by depositing a conductive material such as Ti, Ta, TiN, and TaN by a sputtering method, similarly to the barrier metal layers 26 and 30.

  Next, a metal material such as copper or aluminum is buried in the via hole 54 in which the barrier metal layer 58 is disposed, and the through electrode 60 electrically connected to the pad electrode 42 through the barrier metal layer 58 is formed. For example, after forming a metal seed layer (not shown) made of copper by sputtering or the like, copper is formed by electrolytic plating using a photoresist film (not shown) that exposes a region where the through electrode 60 is to be formed as a mask. . After removing the resist film, unnecessary portions of the metal seed layer and the barrier metal layer 58 are removed to form the through electrode 60.

  Next, after applying a solder resist 62 on the second surface 14 side of the semiconductor substrate 10 to form an opening that exposes the through electrode 60 by patterning, a solder ball 64 is placed on the exposed through electrode 60 (FIG. 10). (C)). Thereafter, the semiconductor device according to the present embodiment is completed through processes such as dicing.

  Thus, according to the present embodiment, it is possible to suppress an increase in contact resistance between the pad electrode 42 disposed on the first surface 12 side of the semiconductor substrate 10 and the through electrode 60. Further, the diffusion of metal from the conductive oxide layer 28 can be suppressed, and the characteristic deterioration of the semiconductor element 16 can be suppressed.

[Fourth Embodiment]
A semiconductor device and a manufacturing method thereof according to the fourth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device according to the first to third embodiments are denoted by the same reference numerals, and the description thereof is omitted or simplified.

  FIG. 11 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. FIG. 12 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment.

  In the first embodiment, the electrode layer 40 is stacked on the conductive oxide layer 28 via the barrier metal layer 30. In the second and third embodiments, the electrode layer 40 is laminated directly on the conductive oxide layer 28. However, the conductive oxide layer 28 and the electrode layer 40 are not necessarily laminated, and may be electrically connected via another conductive member.

  In the semiconductor device according to the present embodiment, as shown in FIG. 11, the conductive oxide layer 28 and the electrode layer 40 are electrically connected via the via plug 36. In this way, the conductive oxide layer 28 can be disposed in any layer below the electrode layer 40, and the via hole 54 can be shallowed.

  In FIG. 11, the via plug 36 is in contact with the conductive oxide layer 28, but the via plug 36 may be in contact with the upper surface of the barrier metal layer 30. Further, a barrier metal layer (not shown) may be provided on at least the bottom of the via plug 36. In any case, the entire upper surface of the conductive oxide layer 28 can be covered with the barrier metal layer, and the effect of preventing the diffusion of the metal material constituting the conductive oxide layer 28 can be further enhanced.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, in the same manner as the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 2A to 3A, the semiconductor element 16 and the interlayer insulating film 20 are formed on the first surface 12 side of the semiconductor substrate 10. Then, the barrier metal layer 26, the conductive oxide layer 28, the barrier metal layer 30 and the like are formed.

  Next, an interlayer insulating film 32 is formed on the interlayer insulating film 20 on which the barrier metal layer 26, the conductive oxide layer 28, and the barrier metal layer 30 are disposed. As the interlayer insulating film 32, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride can be used.

  Next, contact holes 22 reaching the electrodes of the semiconductor element 16 are formed in the interlayer insulating films 32 and 20 using photolithography and dry etching. In addition, a via hole 34 reaching the conductive oxide layer 28 is formed in the interlayer insulating film 32 and the barrier metal layer 30.

  Next, a contact plug 24 is formed by embedding a conductive material such as tungsten in the contact hole 22. Further, a via plug 36 is formed by embedding a conductive material such as tungsten in the via hole 34 (FIG. 12A).

  Note that the contact plug 24 and the via plug 36 may be formed simultaneously or separately. Further, the contact plug 24 is not necessarily connected directly to the semiconductor element 16, and may be configured to be electrically connected to the semiconductor element 16 through a plurality of contact plugs or wiring layers. Similarly, the via plug 36 is not necessarily connected directly to the conductive oxide layer 28, and is configured to be electrically connected to the conductive oxide layer 28 via a plurality of via plugs and wiring layers. It may be.

  Next, a wiring layer 38 electrically connected to the semiconductor element 16 through the contact plug 24 and an electrode electrically connected to the conductive oxide layer 28 through the via plug 36 on the interlayer insulating film 32. The layer 40 is formed (FIG. 12B).

  Thereafter, through electrodes 60 and the like are formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 3C to 5C, thereby completing the semiconductor device according to the present embodiment (FIG. 12 (c)).

  Thus, according to the present embodiment, it is possible to suppress an increase in contact resistance between the pad electrode 42 disposed on the first surface 12 side of the semiconductor substrate 10 and the through electrode 60. Further, the diffusion of metal from the conductive oxide layer 28 can be suppressed, and the characteristic deterioration of the semiconductor element 16 can be suppressed.

[Fifth Embodiment]
A semiconductor device and a manufacturing method thereof according to the fifth embodiment of the present invention will be described with reference to FIGS. Constituent elements similar to those of the semiconductor device according to the first to fourth embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 13 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. FIG. 14 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment.

  In the first to fourth embodiments, the conductive oxide layer 28 is disposed between the electrode layer 40 and the first surface 12 of the semiconductor substrate 10, and the electrode layer 40 and the through electrode are interposed via the conductive oxide layer 28. 60 was electrically connected. However, the conductive oxide layer 28 is not necessarily disposed between the electrode layer 40 and the first surface 12 of the semiconductor substrate 10.

  In the semiconductor device according to the present embodiment, as shown in FIG. 13, the electrode layer 40 is disposed between the conductive oxide layer 28 and the first surface 12 of the semiconductor substrate 10, and the upper surface of the electrode layer 40 is electrically conductive. The lower surface of the conductive oxide layer 28 is in contact. The via hole 54 penetrates the semiconductor substrate 10, the interlayer insulating film 20, and the electrode layer 40 from the second surface 14 side of the semiconductor substrate 10 and reaches the conductive oxide layer 28. The upper and side surfaces of the conductive oxide layer 28 are covered with a barrier metal layer 30.

  Also in the semiconductor device according to the present embodiment, since the conductive oxide layer 28 is surrounded by the barrier metal layer 30 and the electrode layer 40, the metal material constituting the conductive oxide layer 28 is the interlayer insulating films 20 and 44. Diffusion inside can be suppressed.

  In the example of FIG. 13, the conductive oxide layer 28 is directly disposed on the electrode layer 40, but the electrode layer 40 and the conductive oxide layer 28 are not necessarily in direct contact with each other. . For example, a barrier metal layer may be disposed between the electrode layer 40 and the conductive oxide layer 28. Alternatively, the lower surface of the conductive oxide layer 28 may be covered with a barrier metal layer, and the conductive oxide layer 28 and the electrode layer 40 may be electrically connected via via plugs.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 2A and 2B, the semiconductor element 16 and the interlayer insulating film 20 are formed on the first surface 12 side of the semiconductor substrate 10. Etc.

  Next, a wiring layer 38 electrically connected to the semiconductor element 16 through the contact plug 24 is formed on the interlayer insulating film 20. In addition, the electrode layer 40 is formed in a region on the interlayer insulating film 20 where the pad electrode 42 connected to the through electrode 60 is disposed.

  Next, an oxide conductive material is deposited and patterned to form a conductive oxide layer 28 on the electrode layer 40.

  Next, a barrier metal material is deposited and patterned to form a barrier metal layer 30 that covers at least the upper and side surfaces of the conductive oxide layer 28. Thereby, the pad electrode 42 including the conductive oxide layer 28, the barrier metal layer 30, and the electrode layer 40 is formed (FIG. 14A).

  Next, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 3C to 4A, the interlayer insulating film 44 is formed and then formed on the first surface 12 side of the semiconductor substrate 10. The support substrate 50 is bonded, and the back grinding process is performed from the second surface 14 side.

  Next, an insulating film 52 such as a silicon nitride film is deposited on the second surface 14 of the semiconductor substrate 10 by, for example, plasma CVD, and then the insulating film 52 is patterned using photolithography and dry etching. Thereby, the insulating film 52 having an opening in the region where the through electrode 60 is to be formed is formed.

  Next, using the insulating film 52 as a mask, the semiconductor substrate 10, the interlayer insulating film 20 and the electrode layer 40 are dry-etched from the second surface 14 side of the semiconductor substrate 10 to form a via hole 54 reaching the conductive oxide layer 28. (FIG. 14B).

  At this time, the side surface of the electrode layer 40 exposed in the via hole 54 may be exposed to the etching atmosphere, and an oxide film or a fluoride film may be formed. However, the contact portion of the through electrode 60 with respect to the pad electrode 42 is the conductive oxide layer 28 exposed at the bottom of the via hole 54, and the oxide film or the fluoride film is a contact between the pad electrode 42 and the through electrode 60. It does not affect the characteristics.

  Thereafter, through electrodes 60 and the like are formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 4C to 5C, and the semiconductor device according to the present embodiment is completed (FIG. 14 (c)).

  Thus, according to the present embodiment, it is possible to suppress an increase in contact resistance between the pad electrode 42 disposed on the first surface 12 side of the semiconductor substrate 10 and the through electrode 60. Further, the diffusion of metal from the conductive oxide layer 28 can be suppressed, and the characteristic deterioration of the semiconductor element 16 can be suppressed.

[Sixth Embodiment]
A semiconductor device and a manufacturing method thereof according to the sixth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device according to the first to fifth embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 15 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. FIG. 16 is a process cross-sectional view illustrating the semiconductor device manufacturing method according to the present embodiment.

  In the first to fifth embodiments, the conductive oxide layer 28 is covered with the barrier metal layers 26, 30, 58 and the electrode layer 40, so that the metal material constituting the conductive oxide layer 28 is the interlayer insulating film 20. , 44 etc. were prevented from diffusing. However, the barrier metal layer does not necessarily need to cover the conductive oxide layer 28, and is disposed between the semiconductor element 16 and the conductive oxide layer 28, where the influence of the metal material is a concern. Also good.

  In the semiconductor device according to the present embodiment, as shown in FIG. 15, the regions are separated into the interlayer insulating films 20 and 44 between the region where the semiconductor element 16 is provided and the region where the pad electrode 42 is provided. A barrier portion 46 made of a barrier metal material is provided. By providing the barrier portion 46 between the semiconductor element 16 and the conductive oxide layer 28, the metal material constituting the conductive oxide layer 28 is prevented from diffusing up to the semiconductor element 16 and affecting the element characteristics. can do.

  By providing the barrier portion 46, the pad electrode 42 can be configured with a simple laminated structure of the conductive oxide layer 28 and the electrode layer 40, and the manufacturing process can be simplified.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, in the same manner as the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 2A to 2B, the semiconductor element 16 and the interlayer insulating film 20 are formed on the first surface 12 side of the semiconductor substrate 10. Etc.

  Next, a conductive oxide layer 28 is formed on the interlayer insulating film 20 in the same manner as in the first embodiment.

  Next, a wiring layer 38 electrically connected to the semiconductor element 16 through the contact plug 24 is formed on the interlayer insulating film 20 in the same manner as the semiconductor device manufacturing method according to the first embodiment. Further, an electrode layer 40 is formed on the conductive oxide layer 28, and a pad electrode 42 having a laminated structure of the conductive oxide layer 28 and the electrode layer 40 is formed (FIG. 16A).

  Next, an interlayer insulating film 44 is formed on the interlayer insulating film 20 on which the wiring layer 38, the conductive oxide layer 28, and the electrode layer 40 are disposed in the same manner as in the semiconductor device manufacturing method according to the first embodiment. .

  Next, openings are formed in the interlayer insulating films 20 and 44 between the region where the semiconductor element 16 is provided and the region where the pad electrode 42 is provided by photolithography and dry etching so as to separate these regions. .

  Next, a barrier metal material such as titanium, tantalum, titanium nitride, or tantalum nitride is embedded in the opening to form the barrier portion 46. For example, after a titanium film is deposited on the interlayer insulating film 44 and in the opening by a sputtering method, the titanium film on the interlayer insulating film 44 is removed by a CMP method, an etch back method, or the like to be embedded in the opening. The formed barrier portion 46 is formed (FIG. 16B).

  Thereafter, through electrodes 60 and the like are formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 4A to 5C, and the semiconductor device according to the present embodiment is completed (FIG. 5). 16 (c)).

  Thus, according to the present embodiment, it is possible to suppress an increase in contact resistance between the pad electrode 42 disposed on the first surface 12 side of the semiconductor substrate 10 and the through electrode 60. Further, the diffusion of metal from the conductive oxide layer 28 can be suppressed, and the characteristic deterioration of the semiconductor element 16 can be suppressed.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.
For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced is also an embodiment of the present invention.

  For example, the structure of the through electrode 60 and the manufacturing method thereof shown in the first embodiment may be applied to the third embodiment, and the structure of the through electrode 60 and the manufacturing method thereof shown in the third embodiment are the first. The present invention may be applied to the second, fourth to sixth embodiments. Moreover, you may further apply the barrier part 46 shown in 6th Embodiment to the semiconductor device by 1st thru | or 5th Embodiment.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof. In addition, each term in this specification is merely used for the purpose of describing the present invention, and may include equivalents thereof, and the present invention is not limited to the strict meaning of the term. .

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 12 ... 1st surface 14 ... 2nd surface 16 ... Semiconductor element 20, 32, 44 ... Interlayer insulation film 26, 30, 58 ... Barrier metal layer 28 ... Conductive oxide layer 38 ... Wiring layer 40 ... Electrode Layer 42 ... Pad electrode 46 ... Barrier portion 54 ... Via hole 60 ... Penetration electrode

Claims (19)

A semiconductor substrate;
An insulating film disposed on the semiconductor substrate;
A pad electrode disposed on the insulating film;
A conductive member provided in an opening that reaches the pad electrode through the semiconductor substrate and electrically connected to the pad electrode;
The pad electrode has at least a conductive oxide layer provided at a connection portion with the conductive member, and a metal layer electrically connected to the conductive oxide layer,
The semiconductor device further comprising a barrier metal layer provided between the conductive oxide layer and the insulating film. The semiconductor device according to claim 1, wherein a periphery of the conductive oxide layer excluding the connection portion is covered with the barrier metal layer. The semiconductor device according to claim 2, wherein the metal layer is electrically connected to the conductive oxide layer through the barrier metal layer. The semiconductor device according to claim 2, wherein the metal layer is electrically connected to the conductive oxide layer through a via plug. The semiconductor device according to claim 2, wherein a periphery of the conductive oxide layer excluding the connection portion is covered with the barrier metal layer and the metal layer. The semiconductor device according to claim 1, wherein the conductive oxide layer is disposed between the semiconductor substrate and the metal layer. The semiconductor device according to claim 1, wherein the metal layer is disposed between the semiconductor substrate and the conductive oxide layer. A second insulating film disposed between the side surface of the opening and the conductive member;
The semiconductor device according to claim 1, wherein the second insulating film is provided to be separated from the conductive oxide layer. Further comprising a semiconductor element provided on the semiconductor substrate,
The semiconductor device according to claim 1, wherein the pad electrode is electrically connected to the semiconductor element. The semiconductor device according to claim 1, wherein the barrier metal layer suppresses diffusion of a metal material constituting the conductive oxide layer into the insulating film. The semiconductor device according to claim 1, wherein the conductive oxide layer includes at least one conductive oxide material selected from the group including ITO, IZO, and IGZO. . The semiconductor device according to claim 1, wherein the barrier metal layer includes at least one conductive material selected from the group including Ti, Ta, TiN, and TaN. A semiconductor substrate;
An insulating film disposed on the semiconductor substrate;
A semiconductor element disposed on the semiconductor substrate;
A pad electrode electrically connected to the semiconductor element;
A conductive member provided in an opening that reaches the pad electrode through the semiconductor substrate and electrically connected to the pad electrode;
The pad electrode has at least a conductive oxide layer provided at a connection portion with the conductive member, and a metal layer electrically connected to the conductive oxide layer,
A semiconductor device further comprising a barrier portion made of a barrier metal material disposed between the semiconductor element and the conductive oxide layer. Forming an insulating film on the semiconductor substrate;
On the insulating film, a metal layer, a conductive oxide layer electrically connected to the metal layer, a barrier metal layer disposed between the insulating film and the conductive oxide layer, Forming a pad electrode comprising:
Forming an opening that penetrates the semiconductor substrate and the insulating film and reaches the conductive oxide layer;
Forming a conductive member electrically connected to the pad electrode in the opening. A method of manufacturing a semiconductor device, comprising: The step of forming the pad electrode includes:
Forming a first barrier metal layer;
Forming the conductive oxide layer on the first barrier metal layer;
Forming a second barrier metal layer so as to cover an upper surface and a side surface of the conductive oxide layer;
The method of manufacturing a semiconductor device according to claim 14, further comprising: forming the metal layer electrically connected to the conductive oxide layer on the conductive oxide layer. After the step of forming the second barrier metal layer, before the step of forming the metal layer, a step of removing the second barrier metal layer provided on the upper surface of the conductive oxide layer Have
The method of manufacturing a semiconductor device according to claim 15, wherein in the step of forming the metal layer, the metal layer is formed so as to cover an upper surface of the conductive oxide layer. After the step of forming the second barrier metal layer and before the step of forming the metal layer, further comprising a step of forming a via plug electrically connected to the conductive oxide layer;
The method of manufacturing a semiconductor device according to claim 15, wherein in the step of forming the metal layer, the metal layer electrically connected to the conductive oxide layer through the via plug is formed. The step of forming the pad electrode includes:
Forming the barrier metal layer;
Forming the conductive oxide layer on the barrier metal layer;
And forming the metal layer electrically connected to the conductive oxide layer so as to cover an upper surface and a side surface of the conductive oxide layer. Device manufacturing method. The step of forming the pad electrode includes:
Forming the metal layer;
Forming the conductive oxide layer on the metal layer;
Forming the barrier metal layer so as to cover at least the upper surface and the side surface of the conductive oxide layer,
The semiconductor device according to claim 14, wherein in the step of forming the opening, the opening reaching the conductive oxide layer through the semiconductor substrate, the insulating film, and the metal layer is formed. Manufacturing method.

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