JP7040858B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Semiconductor devices and methods for manufacturing semiconductor devices Download PDF

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JP7040858B2
JP7040858B2 JP2017182600A JP2017182600A JP7040858B2 JP 7040858 B2 JP7040858 B2 JP 7040858B2 JP 2017182600 A JP2017182600 A JP 2017182600A JP 2017182600 A JP2017182600 A JP 2017182600A JP 7040858 B2 JP7040858 B2 JP 7040858B2
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insulator layer
conductive film
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JP2019057688A (en
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美奈子 折津
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Lapis Semiconductor Co Ltd
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Description

本発明は、半導体装置及び半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

半導体基板に形成されたフォトダイオードに関する技術として、以下の技術が知られている。例えば、特許文献1には、基板上の受光素子領域上に、反射防止膜を形成する工程と、反射防止膜上に、後の工程にて発生するオーバーエッチングによる膜減り、プロセスダメージから反射防止膜を保護する保護膜を形成する工程とを含む受光素子内蔵型半導体装置の製造方法が記載されている。具体的には、保護膜としての多結晶シリコン膜を反射防止膜上に形成し、配線層間膜をドライエッチングで除去した後に、保護膜としての多結晶シリコン膜をウェットエッチングで除去する。 The following techniques are known as techniques related to photodiodes formed on semiconductor substrates. For example, Patent Document 1 describes a step of forming an antireflection film on a light receiving element region on a substrate, a film reduction on the antireflection film due to overetching that occurs in a later step, and antireflection from process damage. A method for manufacturing a semiconductor device with a built-in light receiving element, which includes a step of forming a protective film that protects the film, is described. Specifically, a polycrystalline silicon film as a protective film is formed on the antireflection film, the wiring interlayer film is removed by dry etching, and then the polycrystalline silicon film as a protective film is removed by wet etching.

特開2003-264310号公報Japanese Patent Application Laid-Open No. 2003-264310

フォトダイオードを備えた半導体装置の製造方法は、例えば、フォトダイオードが形成された半導体基板の表面の受光領域を覆う反射防止膜を形成する工程と、フォトダイオードに電気的に接続された配線を形成する工程と、配線に電気的に接続された外部接続端子を形成する工程と、外部接続端子を洗浄する工程と、を含み得る。 The method for manufacturing a semiconductor device provided with a photodiode is, for example, a step of forming an antireflection film covering a light receiving region on the surface of a semiconductor substrate on which a photodiode is formed, and forming a wiring electrically connected to the photodiode. A step of forming an external connection terminal electrically connected to the wiring, and a step of cleaning the external connection terminal may be included.

外部接続端子の材料として、Au等の重金属が使用される。このため、重金属汚染による半導体装置の特性変動を回避するために、外部接続端子を形成するまでの各処理をウエハ製造工程(前工程)において行い、外部接続端子の形成以降の各処理については、組み立て工程(後工程)において行う。 Heavy metals such as Au are used as the material for the external connection terminals. Therefore, in order to avoid fluctuations in the characteristics of semiconductor devices due to heavy metal contamination, each process up to the formation of the external connection terminal is performed in the wafer manufacturing process (pre-process), and each process after the formation of the external connection terminal is performed. Performed in the assembly process (post-process).

ここで、本発明者は、外部接続端子の洗浄工程において反射防止膜がエッチングされ、反射防止膜の膜厚が成膜時の膜厚から変化することを発見した。反射防止膜の反射率は、反射防止膜の膜厚に依存するため、反射防止膜の膜厚をコントロールすることが重要である。外部接続端子の洗浄工程において反射防止膜のエッチングが生じると、反射防止膜の反射率が変動し、フォトダイオードの受光感度にばらつきが生じる結果となる。 Here, the present inventor has discovered that the antireflection film is etched in the cleaning process of the external connection terminal, and the film thickness of the antireflection film changes from the film thickness at the time of film formation. Since the reflectance of the antireflection film depends on the film thickness of the antireflection film, it is important to control the film thickness of the antireflection film. When the antireflection film is etched in the cleaning step of the external connection terminal, the reflectance of the antireflection film fluctuates, resulting in a variation in the light receiving sensitivity of the photodiode.

この問題に対して特許文献1に記載の技術を適用し、保護膜としての多結晶シリコン膜を反射防止膜上に形成し、配線層間膜をドライエッチングで除去した後に、保護膜としての多結晶シリコン膜をウェットエッチングで除去する方法が考えられる。しかしながらこの場合、組み立て工程(後工程)で多結晶シリコン膜をエッチングする必要が生じるため、多結晶シリコン膜をエッチングする専用の高額な装置が必要となり、製造コストの上昇を招く結果となる。 To solve this problem, the technique described in Patent Document 1 is applied, a polycrystalline silicon film as a protective film is formed on the antireflection film, the wiring interlayer film is removed by dry etching, and then the polycrystal as a protective film is formed. A method of removing the silicon film by wet etching can be considered. However, in this case, since it is necessary to etch the polysilicon film in the assembly process (post-process), a high-priced device dedicated to etching the polysilicon film is required, which results in an increase in manufacturing cost.

本発明は、上記した点に鑑みてなされたものであり、低コストで反射防止膜の膜厚の変化を抑制することを目的とする。 The present invention has been made in view of the above points, and an object of the present invention is to suppress a change in the film thickness of the antireflection film at low cost.

本発明に係る半導体装置の製造方法は、フォトダイオードが形成された半導体基板を用意する工程と、前記半導体基板の表面の前記フォトダイオードの受光領域を覆い且つ前記半導体基板の屈折率よりも小さい屈折率を有する絶縁体層を形成する工程と、前記フォトダイオードに電気的に接続された第1の導電膜及び第2の導電膜を含む配線と、前記絶縁体層の前記受光領域に対応する部分を覆う前記第1の導電膜及び前記第2の導電膜を含むマスクと、を形成する工程と、前記配線の上面の少なくとも一部を露出させる第1の開口部及び前記マスクの上面及び側面を露出させる第2の開口部を有し且つ前記配線の側面を覆う保護膜を、前記絶縁体層上に形成する工程と、前記第1の開口部において前記配線に電気的に接続された端子を形成する工程と、前記端子の形成後に、前記第1の導電膜を溶解するエッチング液を用いて前記マスクを除去する工程と、を含む。 The method for manufacturing a semiconductor device according to the present invention includes a step of preparing a semiconductor substrate on which a photodiode is formed, and a refraction that covers the light receiving region of the photodiode on the surface of the semiconductor substrate and is smaller than the refractive index of the semiconductor substrate. A step of forming an insulator layer having a ratio, a wiring including a first conductive film and a second conductive film electrically connected to the photodiode, and a portion of the insulator layer corresponding to the light receiving region. The step of forming the first conductive film and the mask containing the second conductive film, the first opening for exposing at least a part of the upper surface of the wiring, and the upper surface and the side surface of the mask. A step of forming a protective film having a second opening to be exposed and covering the side surface of the wiring on the insulator layer, and a terminal electrically connected to the wiring in the first opening. It includes a step of forming the terminal and a step of removing the mask with an etching solution that dissolves the first conductive film after the formation of the terminal.

本発明に係る半導体装置は、フォトダイオードが形成された半導体基板と、前記半導体基板の表面の前記フォトダイオードの受光領域を覆う絶縁体層と、前記絶縁体層上に設けられ、前記受光領域を内包する領域に開口部を有する保護膜と、前記保護膜上に設けられ、前記フォトダイオードに電気的に接続された端子と、を含み、前記絶縁体層は、前記保護膜の前記開口部の端部に沿った凹部を有する。 The semiconductor device according to the present invention is provided with a semiconductor substrate on which a photodiode is formed, an insulator layer covering the light receiving region of the photodiode on the surface of the semiconductor substrate, and the light receiving region provided on the insulator layer. The insulating layer includes a protective film having an opening in a region to be included and a terminal provided on the protective film and electrically connected to the photodiode, and the insulator layer is the opening of the protective film. It has a recess along the end.

本発明によれば、低コストで反射防止膜として機能する絶縁体層の膜厚の変動を抑制することが可能となる。 According to the present invention, it is possible to suppress fluctuations in the film thickness of the insulator layer that functions as an antireflection film at low cost.

本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の構成を示す平面図である。It is a top view which shows the structure of the semiconductor device which concerns on embodiment of this invention. 比較例に係る半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on a comparative example. 本発明の他の実施形態に係る半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on other embodiment of this invention.

以下、本発明の実施形態について図面を参照しつつ説明する。尚、各図面において、実質的に同一又は等価な構成要素又は部分には同一の参照符号を付している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are designated by the same reference numerals.

図1A~1Sは、本発明の実施形態に係る半導体装置の製造方法の一例を示す断面図である。はじめに、シリコン単結晶で構成されるn型の基板層10a及びn型のエピタキシャル層10bを含む半導体基板10を用意する。次に、公知の熱酸化法を用いて、エピタキシャル層10bの表面に熱酸化膜11を形成する。次に、公知のフォトリソグラフィー技術を用いて、N型領域の形成予定位置に開口部100Aを有するレジストマスク100を半導体基板10上に形成する。 1A to 1S are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, a semiconductor substrate 10 including an n-type substrate layer 10a and an n-type epitaxial layer 10b composed of a silicon single crystal is prepared. Next, the thermal oxide film 11 is formed on the surface of the epitaxial layer 10b by using a known thermal oxidation method. Next, using a known photolithography technique, a resist mask 100 having an opening 100A at a position where an N-type region is to be formed is formed on the semiconductor substrate 10.

次に、公知のイオン注入技術を用いて、レジストマスク100の開口部100Aを介してエピタキシャル層10bにN型不純物を注入することで、エピタキシャル層10bの表層部にカソードとして機能するN型領域21を形成する。その後、レジストマスク100を除去する(図1B)。 Next, the N-type region 21 that functions as a cathode in the surface layer portion of the epitaxial layer 10b by injecting an N-type impurity into the epitaxial layer 10b through the opening 100A of the resist mask 100 using a known ion implantation technique. To form. After that, the resist mask 100 is removed (FIG. 1B).

次に、N型領域21の熱拡散処理を行う。すなわち、熱処理によって、N型領域21のN型不純物を、エピタキシャル層10bの深部にまで拡散させる。N型領域21は、エピタキシャル層10bと基板層10aとの界面近傍にまで達する(図1C)。 Next, the heat diffusion treatment of the N-type region 21 is performed. That is, the heat treatment diffuses the N-type impurities in the N-type region 21 deep into the epitaxial layer 10b. The N-type region 21 reaches the vicinity of the interface between the epitaxial layer 10b and the substrate layer 10a (FIG. 1C).

次に、公知のフォトリソグラフィー技術を用いて、P型領域の形成予定位置に開口部101Aを有するレジストマスク101を、半導体基板10上に形成する(図1D)。 Next, using a known photolithography technique, a resist mask 101 having an opening 101A at a position where a P-shaped region is to be formed is formed on the semiconductor substrate 10 (FIG. 1D).

次に、公知のイオン注入技術を用いて、レジストマスク101の開口部101Aを介してエピタキシャル層10bにP型不純物を注入することで、エピタキシャル層10bの表層部にアノードとして機能するP型領域22を形成する。その後、レジストマスク101を除去する(図1E)。 Next, a P-type region 22 that functions as an anode in the surface layer portion of the epitaxial layer 10b by injecting a P-type impurity into the epitaxial layer 10b through the opening 101A of the resist mask 101 using a known ion implantation technique. To form. After that, the resist mask 101 is removed (FIG. 1E).

次に、公知のフォトリソグラフィー技術を用いて、N型領域21に内包されるN領域の形成予定位置に開口部102Aを有するレジストマスク102を、半導体基板10上に形成する(図1F)。 Next, using a known photolithography technique, a resist mask 102 having an opening 102A at a position where an N + region contained in the N-type region 21 is to be formed is formed on the semiconductor substrate 10 (FIG. 1F).

次に、公知のイオン注入技術を用いて、レジストマスク102の開口部102Aを介してN型領域21に高濃度のN型不純物を注入することで、N型領域21の表層部にコンタクト領域として機能するN領域23を形成する。その後、レジストマスク102を除去する(図1G)。以上の工程を経ることで、半導体基板10にフォトダイオード200が形成される。 Next, by injecting a high concentration of N-type impurities into the N-type region 21 through the opening 102A of the resist mask 102 using a known ion implantation technique, the surface layer portion of the N-type region 21 is used as a contact region. Form a functioning N + region 23. After that, the resist mask 102 is removed (FIG. 1G). Through the above steps, the photodiode 200 is formed on the semiconductor substrate 10.

次に、半導体基板10の表面に反射防止膜として機能する絶縁体層30を形成する。具体的には、公知のCVD法(chemical vapor deposition)を用いて、半導体基板10の表面に第1の絶縁体層31を形成し、第1の絶縁体層31の表面に第2の絶縁体層32を形成する(図1H)。すなわち、絶縁体層30は、第1の絶縁体層31と、第2の絶縁体層32とを積層した積層膜によって構成される。第1の絶縁体層31及び第2の絶縁体層32を、それぞれ、半導体基板10の屈折率よりも小さい屈折率を有する材料で構成することで、絶縁体層30は反射防止膜として機能する。第1の絶縁体層31としてNSG(Nondoped Silicate Glass)を用いることができ、第2の絶縁体層32としてPSG(Phospho Silicate Glasses)を用いることができる。第1の絶縁体層31の膜厚と第2の絶縁体層32の膜厚との比率を制御することによって、反射防止膜として機能する絶縁体層30において所望の反射率を得ることができる。従って、第1の絶縁体層31及び第2の絶縁体層32の膜厚のばらつきを抑えることで、フォトダイオード200における受光感度のばらつきを抑えることができる。 Next, an insulator layer 30 that functions as an antireflection film is formed on the surface of the semiconductor substrate 10. Specifically, a first insulator layer 31 is formed on the surface of the semiconductor substrate 10 by using a known CVD method (chemical vapor deposition), and a second insulator is formed on the surface of the first insulator layer 31. The layer 32 is formed (FIG. 1H). That is, the insulator layer 30 is composed of a laminated film in which a first insulator layer 31 and a second insulator layer 32 are laminated. By forming the first insulator layer 31 and the second insulator layer 32 with a material having a refractive index smaller than that of the semiconductor substrate 10, the insulator layer 30 functions as an antireflection film. .. NSG (Non doped Silicate Glasses) can be used as the first insulator layer 31, and PSG (Phospho Silicate Glasses) can be used as the second insulator layer 32. By controlling the ratio of the film thickness of the first insulator layer 31 to the film thickness of the second insulator layer 32, a desired reflectance can be obtained in the insulator layer 30 functioning as an antireflection film. .. Therefore, by suppressing the variation in the film thickness of the first insulator layer 31 and the second insulator layer 32, it is possible to suppress the variation in the light receiving sensitivity of the photodiode 200.

次に、公知のフォトリソグラフィー技術及びエッチング技術を用いて、P型領域22に達するコンタクトホール及びN領域23に達するコンタクトホールを絶縁体層30に形成する。その後、公知のCVD法を用いて上記の各コンタクトホール内にバリアメタル41及び高融点金属42を順次埋め込むことで、P型領域22に接続されたプラグ40A及びN領域23に接続されたプラグ40Bを形成する。バリアメタル41として、例えばTiN(窒化チタン)を用いることができ、高融点金属42として、例えばW(タングステン)を用いることができる。絶縁体層30の表面に堆積したバリアメタル41及び高融点金属42は、エッチバックまたはCMP(Chemical Mechanical Polishing)により除去する(図1I)。 Next, using known photolithography techniques and etching techniques, a contact hole reaching the P-shaped region 22 and a contact hole reaching the N + region 23 are formed in the insulator layer 30. Then, by sequentially embedding the barrier metal 41 and the refractory metal 42 in each of the above contact holes using a known CVD method, the plugs 40A connected to the P-shaped region 22 and the plugs connected to the N + region 23 are connected. Form 40B. As the barrier metal 41, for example, TiN (titanium nitride) can be used, and as the refractory metal 42, for example, W (tungsten) can be used. The barrier metal 41 and the refractory metal 42 deposited on the surface of the insulator layer 30 are removed by etchback or CMP (Chemical Mechanical Polishing) (FIG. 1I).

次に、公知のスパッタ法を用いて、絶縁体層30の表面に、第1の導電膜51を形成し、第1の導電膜51上に第2の導電膜52を形成する。第1の導電膜51の材料として、例えばMo(モリブデン)を用いることができる。第2の導電膜52の材料として、例えばAlSiCuを用いることができる。次に、公知のフォトリソグラフィー技術を用いて、第1の導電膜51及び第2の導電膜52をパターニングするためのレジストマスク103を、第2の導電膜52上に形成する(図1J)。 Next, using a known sputtering method, the first conductive film 51 is formed on the surface of the insulator layer 30, and the second conductive film 52 is formed on the first conductive film 51. As the material of the first conductive film 51, for example, Mo (molybdenum) can be used. As the material of the second conductive film 52, for example, AlSiCu can be used. Next, using a known photolithography technique, a resist mask 103 for patterning the first conductive film 51 and the second conductive film 52 is formed on the second conductive film 52 (FIG. 1J).

次に、公知のエッチング技術を用いて、第1の導電膜51及び第2の導電膜52の、レジストマスク103から露出した部分をエッチングすることで、第1の導電膜51及び第2の導電膜52のパターニングを行う。これにより、プラグ40Aを介してP型領域22に電気的に接続された配線53及び、プラグ40Bを介してN型領域21に電気的に接続された配線54が、絶縁体層30上に形成される。更に、絶縁体層30上の、受光領域に対応する位置にメタルマスク55が形成される。絶縁体層30の受光領域に対応する領域の大部分は、メタルマスク55によって覆われる。その後、レジストマスク103を除去する(図1K)。 Next, by using a known etching technique to etch the portions of the first conductive film 51 and the second conductive film 52 exposed from the resist mask 103, the first conductive film 51 and the second conductive film 52 are conductive. The film 52 is patterned. As a result, the wiring 53 electrically connected to the P-type region 22 via the plug 40A and the wiring 54 electrically connected to the N-type region 21 via the plug 40B are formed on the insulator layer 30. Will be done. Further, a metal mask 55 is formed on the insulator layer 30 at a position corresponding to the light receiving region. Most of the region corresponding to the light receiving region of the insulator layer 30 is covered with the metal mask 55. After that, the resist mask 103 is removed (FIG. 1K).

次に、公知のCVD法を用いて、配線53、54およびメタルマスク55の上面及び側面を覆う保護膜(パッシベーション膜)60を、絶縁体層30の表面に形成する(図1L)。保護膜60の材料として、例えばSiN(シリコンナイトライド)等の絶縁体を用いることが可能である。 Next, using a known CVD method, a protective film (passivation film) 60 covering the upper surfaces and side surfaces of the wirings 53 and 54 and the metal mask 55 is formed on the surface of the insulator layer 30 (FIG. 1L). As the material of the protective film 60, for example, an insulator such as SiN (silicon nitride) can be used.

次に、公知のフォトリソグラフィー技術を用いて、保護膜60をパターニングするためのレジストマスク104を保護膜60上に形成する(図1M)。 Next, a resist mask 104 for patterning the protective film 60 is formed on the protective film 60 using a known photolithography technique (FIG. 1M).

次に、公知のエッチング技術を用いて、保護膜60の、レジストマスク104から露出した部分をエッチングすることで、保護膜60のパターニングを行う。これにより、配線53及び54の上面を露出させる開口部60A及び60Bが保護膜60に形成される。また、メタルマスク55の上面及び側面を露出させる開口部60Cが保護膜60に形成される。配線53及び54の上面の一部及び側面、絶縁体層30の表面の一部が保護膜60によって覆われる(図1N)。以上の各処理が、ウエハ製造工程(前工程)において実施される。引き続き、半導体装置をパッケージングする組み立て工程(後工程)が実施される。 Next, the protective film 60 is patterned by etching the portion of the protective film 60 exposed from the resist mask 104 using a known etching technique. As a result, openings 60A and 60B that expose the upper surfaces of the wirings 53 and 54 are formed in the protective film 60. Further, an opening 60C that exposes the upper surface and the side surface of the metal mask 55 is formed in the protective film 60. A part of the upper surface and the side surface of the wirings 53 and 54 and a part of the surface of the insulator layer 30 are covered with the protective film 60 (FIG. 1N). Each of the above processes is carried out in the wafer manufacturing process (preliminary process). Subsequently, an assembly process (post-process) for packaging the semiconductor device is carried out.

次に、公知のスパッタ法を用いて、半導体基板10の表面全体を覆うバリアメタル71を形成する。保護膜60の表面、配線53及び54の上面の、保護膜60から露出した部分、及びメタルマスク55の上面及び側面は、バリアメタル71によって覆われる。バリアメタル71の材料として、例えばTiN(窒化チタン)を用いることができる。その後、配線53及び54の形成位置に開口部105A及び105Bを有するレジストマスク105を半導体基板10上に形成する。すなわち、バリアメタル71で覆われた配線53及び54の上面は、それぞれ、レジストマスク105の開口部105A及び105Bにおいて露出し、それ以外の部分はレジストマスク105で覆われる(図1O)。 Next, a known sputtering method is used to form the barrier metal 71 that covers the entire surface of the semiconductor substrate 10. The surface of the protective film 60, the upper surface of the wirings 53 and 54, the portion exposed from the protective film 60, and the upper surface and the side surface of the metal mask 55 are covered with the barrier metal 71. As the material of the barrier metal 71, for example, TiN (titanium nitride) can be used. After that, a resist mask 105 having openings 105A and 105B at the forming positions of the wirings 53 and 54 is formed on the semiconductor substrate 10. That is, the upper surfaces of the wirings 53 and 54 covered with the barrier metal 71 are exposed at the openings 105A and 105B of the resist mask 105, respectively, and the other portions are covered with the resist mask 105 (FIG. 1O).

次に、公知の電解めっき法により、レジストマスク105の開口部105A及び105Bにおいて露出する配線53及び54にそれぞれ電気的に接続された外部接続端子81及び82を形成する(図1P)。外部接続端子81及び82の材料としてAu等の重金属を用いることが可能である。その後、レジストマスク105を除去する(図1Q)。 Next, by a known electrolytic plating method, external connection terminals 81 and 82 electrically connected to the wires 53 and 54 exposed in the openings 105A and 105B of the resist mask 105 are formed (FIG. 1P). Heavy metals such as Au can be used as the material for the external connection terminals 81 and 82. After that, the resist mask 105 is removed (FIG. 1Q).

次に、外部接続端子81及び82をマスクとして、バリアメタル71をエッチングにより除去する。その後、外部接続端子81及び82を洗浄する。外部接続端子81及び82の洗浄工程において、絶縁体層30の、受光領域に対応する部分は、メタルマスク55によって覆われているのでエッチングされず、絶縁体層30の、保護膜60またはメタルマスク55で覆われていない部分がエッチングされる。従って、絶縁体層30には、保護膜60の開口部60Cの端部に沿って凹部(溝)33が形成される。換言すれば、フォトダイオードの受光領域の外縁に沿った凹部(溝)33が、絶縁体層30に形成される(図1R)。 Next, the barrier metal 71 is removed by etching using the external connection terminals 81 and 82 as masks. After that, the external connection terminals 81 and 82 are washed. In the cleaning step of the external connection terminals 81 and 82, the portion of the insulator layer 30 corresponding to the light receiving region is not etched because it is covered with the metal mask 55, and the protective film 60 or the metal mask of the insulator layer 30 is not etched. The portion not covered by 55 is etched. Therefore, the insulator layer 30 is formed with a recess (groove) 33 along the end of the opening 60C of the protective film 60. In other words, a recess (groove) 33 along the outer edge of the light receiving region of the photodiode is formed in the insulator layer 30 (FIG. 1R).

次に、メタルマスク55をリフトオフ法によって除去する。具体的には、エッチング液として硝酸を用いて、Mo(モリブデン)を含むメタルマスク55の第1の導電膜51をエッチングする。これにより、メタルマスク55が絶縁体層30から剥離する(図1S)。 Next, the metal mask 55 is removed by the lift-off method. Specifically, nitric acid is used as the etching solution to etch the first conductive film 51 of the metal mask 55 containing Mo (molybdenum). As a result, the metal mask 55 is peeled off from the insulator layer 30 (FIG. 1S).

図2は、上記の各工程を経て製造された本発明の実施形態に係る半導体装置1の断面図、図3は、半導体装置1の平面図である。半導体装置1は、フォトダイオード200が形成された半導体基板10と、少なくとも半導体基板10の表面のフォトダイオード200の受光領域300を覆い且つ半導体基板10の屈折率よりも小さい屈折率を有する反射防止膜として機能する絶縁体層30と、フォトダイオード200に電気的に接続された配線53及び54と、絶縁体層30上に設けられ、フォトダイオード200の受光領域300を内包する領域に開口部60Cを有し且つ配線53及び54の側面を覆う保護膜(パッシベーション膜)60と、保護膜60上に設けられ、配線53及び54にそれぞれ電気的に接続された外部接続端子81及び82と、を含む。反射防止膜として機能する絶縁体層30は、保護膜60の開口部60Cの端部(または受光領域の外縁)に沿った凹部(溝)33を有する。 FIG. 2 is a cross-sectional view of the semiconductor device 1 according to the embodiment of the present invention manufactured through each of the above steps, and FIG. 3 is a plan view of the semiconductor device 1. The semiconductor device 1 covers the semiconductor substrate 10 on which the photodiode 200 is formed and the light receiving region 300 of the photodiode 200 on the surface of at least the semiconductor substrate 10, and has an antireflection film having a refractive index smaller than the refractive index of the semiconductor substrate 10. An opening 60C is provided in an insulator layer 30 that functions as a semiconductor, wirings 53 and 54 electrically connected to the photodiode 200, and an opening 60C provided on the insulator layer 30 and includes a light receiving region 300 of the photodiode 200. It includes a protective film (passion film) 60 that has and covers the side surfaces of the wirings 53 and 54, and external connection terminals 81 and 82 that are provided on the protective film 60 and are electrically connected to the wirings 53 and 54, respectively. .. The insulator layer 30 that functions as an antireflection film has a recess (groove) 33 along the end portion (or the outer edge of the light receiving region) of the opening 60C of the protective film 60.

図4は、本発明に対する比較例に係る半導体装置1Xの断面図である。比較例に係る半導体装置1Xは、絶縁体層30の表面を露出させた状態で外部接続端子81及び82の洗浄が行われた点が、本発明の実施形態に係る半導体装置1と異なる。場合絶縁体層30の表面を露出させた状態で外部接続端子81及び82の洗浄を行うと、絶縁体層30の露出部分がエッチングされる。反射防止膜として機能する絶縁体層30の反射率は、その膜厚に依存する。外部接続端子81及び82の洗浄工程において絶縁体層30のエッチングにより絶縁体層30の膜厚に変化を生じると、絶縁体層30の反射率が変動し、フォトダイオードの受光感度にばらつきが生じる結果となる。 FIG. 4 is a cross-sectional view of the semiconductor device 1X according to a comparative example with respect to the present invention. The semiconductor device 1X according to the comparative example is different from the semiconductor device 1 according to the embodiment of the present invention in that the external connection terminals 81 and 82 are cleaned with the surface of the insulator layer 30 exposed. Case When the external connection terminals 81 and 82 are washed with the surface of the insulator layer 30 exposed, the exposed portion of the insulator layer 30 is etched. The reflectance of the insulator layer 30 that functions as an antireflection film depends on its film thickness. When the film thickness of the insulator layer 30 is changed by etching the insulator layer 30 in the cleaning process of the external connection terminals 81 and 82, the reflectance of the insulator layer 30 fluctuates and the light receiving sensitivity of the photodiode varies. The result is.

一方、本実施形態に係る半導体装置1の製造方法によれば、反射防止膜として機能する絶縁体層30の、受光領域に対応する部分が、メタルマスク55によって覆われているので、外部接続端子81及び82の洗浄工程において、絶縁体層30の膜厚の変動を抑制できる。これにより、絶縁体層30の反射率の変動を抑制することができ、フォトダイオードの受光感度の装置間ばらつきを抑えることが可能となる。 On the other hand, according to the manufacturing method of the semiconductor device 1 according to the present embodiment, the portion of the insulator layer 30 that functions as the antireflection film corresponding to the light receiving region is covered with the metal mask 55, so that the external connection terminal is used. In the cleaning steps of 81 and 82, fluctuations in the film thickness of the insulator layer 30 can be suppressed. As a result, fluctuations in the reflectance of the insulator layer 30 can be suppressed, and variations in the light receiving sensitivity of the photodiode between devices can be suppressed.

また、本実施形態に係る半導体装置1の製造方法によれば、外部接続端子81及び82を形成する前の段階でメタルマスク55の形成及び保護膜60のパターニングが完了しているので、安価なウェットエッチング装置を使用してメタルマスク55の除去を行うことができる。すなわち、本実施形態に係る半導体装置1の製造方法によれば、低コストで反射防止膜として機能する絶縁体層30の膜厚の変動を抑制することが可能となる。 Further, according to the manufacturing method of the semiconductor device 1 according to the present embodiment, the formation of the metal mask 55 and the patterning of the protective film 60 are completed before the external connection terminals 81 and 82 are formed, so that the cost is low. The metal mask 55 can be removed using a wet etching apparatus. That is, according to the manufacturing method of the semiconductor device 1 according to the present embodiment, it is possible to suppress fluctuations in the film thickness of the insulator layer 30 that functions as an antireflection film at low cost.

また、絶縁体層30のエッチングを回避するためのメタルマスク55は、配線53及び54と同じ材料によって構成され、メタルマスク55の形成工程は、配線53及び54の形成工程と並行して行われる。従って、メタルマスク55を形成するための専用の設備及び工程が不要である。すなわち、本実施形態に係る半導体装置1の製造方法によれば、設備の追加及び工程数の増加を伴うことなく、反射防止膜として機能する絶縁体層30の膜厚の変動を抑制することが可能となる。 Further, the metal mask 55 for avoiding etching of the insulator layer 30 is made of the same material as the wirings 53 and 54, and the metal mask 55 forming step is performed in parallel with the wiring 53 and 54 forming steps. .. Therefore, no dedicated equipment or process for forming the metal mask 55 is required. That is, according to the manufacturing method of the semiconductor device 1 according to the present embodiment, it is possible to suppress fluctuations in the thickness of the insulator layer 30 that functions as an antireflection film without adding equipment or increasing the number of steps. It will be possible.

図5は、本発明の第2の実施形態に係る半導体装置1Aの構成を示す図である。上記した第1の実施形態に係る半導体装置1において配線53及び54は、それぞれ、Mo(モリブデン)を含む第1の導電膜51及びAlSiCuを含む第2の導電膜52により構成されていた。これに対し第2の実施形態に係る半導体装置1Aにおいて、配線53及び54は、Mo(モリブデン)を含む第1の導電膜51と、AlSiCuを含む第2の導電膜52との間に、Ti膜57及びTiN膜57が設けられている。このように、Mo膜と、AlSiCu膜との間に、Ti膜56及びTiN膜57を設けることで、AlSiCuの配線性が向上し、これによりエレクトロマイグレーションを抑制することができ、半導体装置の信頼性を高めることができる。外部接続端子81及び82の洗浄工程では、配線53及び54と同様の積層構造(Mo/Ti/TiN/AlSiCu)を有するメタルマスクによって絶縁体層30のエッチングが抑制される。 FIG. 5 is a diagram showing the configuration of the semiconductor device 1A according to the second embodiment of the present invention. In the semiconductor device 1 according to the first embodiment described above, the wirings 53 and 54 are composed of a first conductive film 51 containing Mo (molybdenum) and a second conductive film 52 containing AlSiCu, respectively. On the other hand, in the semiconductor device 1A according to the second embodiment, the wirings 53 and 54 are tied between the first conductive film 51 containing Mo (molybdenum) and the second conductive film 52 containing AlSiCu. A film 57 and a TiN film 57 are provided. By providing the Ti film 56 and the TiN film 57 between the Mo film and the AlSiCu film in this way, the wiring property of AlSiCu is improved, thereby suppressing electromigration, and the reliability of the semiconductor device can be suppressed. It can enhance the sex. In the cleaning step of the external connection terminals 81 and 82, the etching of the insulator layer 30 is suppressed by the metal mask having the same laminated structure (Mo / Ti / TiN / AlSiCu) as the wirings 53 and 54.

1、1A 半導体装置
10 半導体基板
30 絶縁体層
31 第1の絶縁体層
32 第2の絶縁体層
33 凹部(溝)
51 第1の導電膜
52 第2の導電膜
53、54 配線
55 メタルマスク
60 保護膜
60C 開口部
81、82 外部接続端子
200 フォトダイオード
300 受光領域
1, 1A Semiconductor device 10 Semiconductor substrate 30 Insulator layer 31 First insulator layer 32 Second insulator layer 33 Recess (groove)
51 First conductive film 52 Second conductive film 53, 54 Wiring 55 Metal mask 60 Protective film 60C Opening 81, 82 External connection terminal 200 Photodiode 300 Light receiving area

Claims (11)

フォトダイオードが形成された半導体基板を用意する工程と、
前記半導体基板の表面の前記フォトダイオードの受光領域を覆い且つ前記半導体基板の屈折率よりも小さい屈折率を有する絶縁体層を形成する工程と、
前記フォトダイオードに電気的に接続された第1の導電膜及び第2の導電膜を含む配線と、前記絶縁体層の前記受光領域に対応する部分を覆う前記第1の導電膜及び前記第2の導電膜を含むマスクと、を形成する工程と、
前記配線の上面の少なくとも一部を露出させる第1の開口部及び前記マスクの上面及び側面を露出させる第2の開口部を有し且つ前記配線の側面を覆う保護膜を、前記絶縁体層上に形成する工程と、
前記第1の開口部において前記配線に電気的に接続された端子を形成する工程と、
前記端子の形成後に、前記第1の導電膜を溶解するエッチング液を用いて前記マスクを除去する工程と、
を含む半導体装置の製造方法。
The process of preparing a semiconductor substrate on which a photodiode is formed, and
A step of forming an insulator layer that covers the light receiving region of the photodiode on the surface of the semiconductor substrate and has a refractive index smaller than that of the semiconductor substrate.
The first conductive film and the second conductive film covering the wiring including the first conductive film and the second conductive film electrically connected to the photodiode and the portion of the insulator layer corresponding to the light receiving region. And the process of forming the mask containing the conductive film of
A protective film having a first opening for exposing at least a part of the upper surface of the wiring and a second opening for exposing the upper surface and the side surface of the mask and covering the side surface of the wiring is provided on the insulator layer. And the process of forming
The step of forming a terminal electrically connected to the wiring in the first opening, and
A step of removing the mask with an etching solution that dissolves the first conductive film after the formation of the terminal.
A method for manufacturing a semiconductor device including.
前記配線を形成する工程及び前記マスクを形成する工程は、
前記絶縁体層上に、前記第1の導電膜及び前記第2の導電膜を積層する工程と、
前記第1の導電膜及び前記第2の導電膜をパターニングする工程と、
を含む請求項1に記載の製造方法。
The step of forming the wiring and the step of forming the mask are
The step of laminating the first conductive film and the second conductive film on the insulator layer, and
The step of patterning the first conductive film and the second conductive film,
The manufacturing method according to claim 1.
前記絶縁体層を形成する工程は、前記半導体基板上に第1の絶縁体層を形成する工程と、前記第1の絶縁体層上に前記第1の絶縁体層の材料とは異なる材料からなる第2の絶縁体層を形成する工程と、を含む
請求項1または請求項2に記載の製造方法。
The step of forming the insulator layer is from a material different from the step of forming the first insulator layer on the semiconductor substrate and the material of the first insulator layer on the first insulator layer. The manufacturing method according to claim 1 or 2, comprising the step of forming the second insulator layer.
前記マスクを除去する前に、前記端子を洗浄する工程を更に含む
請求項1から請求項3のいずれか1項に記載の製造方法。
The manufacturing method according to any one of claims 1 to 3, further comprising a step of cleaning the terminals before removing the mask.
前記第1の導電膜はMoを含み、前記第2の導電膜はAlSiCuを含む
請求項1から請求項4のいずれか1項に記載の製造方法。
The production method according to any one of claims 1 to 4, wherein the first conductive film contains Mo and the second conductive film contains AlSiCu.
前記第1の導電膜はMoを含み、前記第2の導電膜はTi、TiN及びAlSiCuを含む
請求項1から請求項4のいずれか1項に記載の製造方法。
The production method according to any one of claims 1 to 4, wherein the first conductive film contains Mo and the second conductive film contains Ti, TiN and AlSiCu.
フォトダイオードが形成された半導体基板と、
前記半導体基板の表面の前記フォトダイオードの受光領域を覆う絶縁体層と、
前記絶縁体層上に設けられ、前記受光領域を内包する領域に開口部を有する保護膜と、
前記保護膜上に設けられ、前記フォトダイオードに電気的に接続された端子と、
を含み、
前記絶縁体層は、前記保護膜の前記開口部の端部に沿った凹部を表面に有する
半導体装置。
A semiconductor substrate on which a photodiode is formed and
An insulator layer covering the light receiving region of the photodiode on the surface of the semiconductor substrate, and
A protective film provided on the insulator layer and having an opening in a region including the light receiving region,
A terminal provided on the protective film and electrically connected to the photodiode.
Including
The insulator layer is a semiconductor device having a recess on the surface along the end of the opening of the protective film.
前記絶縁体層は、前記半導体基板の屈折率より小さい屈折率を有する
請求項7に記載の半導体装置。
The semiconductor device according to claim 7, wherein the insulator layer has a refractive index smaller than that of the semiconductor substrate.
前記絶縁体層上に、前記フォトダイオードに電気的に接続された配線を更に備え、
前記保護膜は前記配線の側面を覆う
請求項7または請求項8に記載の半導体装置。
Further, on the insulator layer, wiring electrically connected to the photodiode is provided.
The semiconductor device according to claim 7 or 8, wherein the protective film covers the side surface of the wiring.
前記端子は、外部に露出している
請求項7から請求項9のいずれか1項に記載の半導体装置。
The semiconductor device according to any one of claims 7 to 9, wherein the terminal is exposed to the outside.
前記端子は、重金属によって構成されている
請求項7から請求項10のいずれか1項に記載の半導体装置。
The semiconductor device according to any one of claims 7 to 10, wherein the terminal is made of a heavy metal.
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JP2007067161A (en) 2005-08-31 2007-03-15 Fujitsu Ltd Semiconductor device and manufacturing method therefor
JP2010183032A (en) 2009-02-09 2010-08-19 Sony Corp Light-receiving element, semiconductor device and manufacturing method of the same, optical pickup device, and optical disk recording/reproducing apparatus
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US20160104729A1 (en) 2014-10-10 2016-04-14 Stmicroelectronics Sa Pinned photodiode with a low dark current

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JP2007067161A (en) 2005-08-31 2007-03-15 Fujitsu Ltd Semiconductor device and manufacturing method therefor
JP2010183032A (en) 2009-02-09 2010-08-19 Sony Corp Light-receiving element, semiconductor device and manufacturing method of the same, optical pickup device, and optical disk recording/reproducing apparatus
CN102903781A (en) 2012-08-28 2013-01-30 中国科学院半导体研究所 Silicon-based near infrared photoelectric detector structure and manufacturing method thereof
US20160104729A1 (en) 2014-10-10 2016-04-14 Stmicroelectronics Sa Pinned photodiode with a low dark current

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