KR940005709B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

No content.

Description

Semiconductor device and manufacturing method

1A to 1E are cross-sectional views sequentially showing a manufacturing process of a connecting electrode and a metal wiring used in a semiconductor device according to an embodiment of the present invention, respectively.

2 is a cross-sectional view showing the configuration of a connection electrode and a metal wiring used in a conventional semiconductor device.

FIG. 3 is a cross-sectional view for explaining a problem when there is no mask matching margin in FIG.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 diffusion layer

3, 12: interlayer insulating film 4, 7, 11: buffer layer

8: connection hole 9, 15: wiring layer

10 connection electrode 13 VIA connection hole

14 W film (tungsten film)

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor integrated circuit.

[Traditional Technology and Problems]

2 is a cross-sectional view showing the structure of a connection electrode and a metal wiring used in a conventional semiconductor device. Hereinafter, a conventional manufacturing method will be described with reference to this drawing.

After the impurity is introduced on the semiconductor substrate 21 to form the diffusion layer 22, the first interlayer insulating film 23 is formed. Subsequently, a hole 24 is formed in the interlayer insulating film 23 on the diffusion layer 22 by using a RIE method (reactive ion etching method) or the like to form a connection hole 24 with the diffusion layer 22. Thereafter, a first metal layer is formed on the interlayer insulating film 23 so as to cover the connection hole 24, and the first wiring layers 25 and 26 are formed by masking and patterning using a photolithography technique. A second interlayer insulating film 27 is formed on the wiring layers 25 and 26, and a hole is formed in the interlayer insulating film 27 on the wiring layer 26 to form a VIA connection hole 28 with the wiring layer 26. . Thereafter, the second wiring layer 29 is formed and patterned on the interlayer insulating film 27 so as to cover the connection hole 28.

In the above manufacturing method, a mask matching margin shown by a, b, c, and d in the drawing is taken. That is, a denotes a matching margin between the diffusion layer 22 and the connection hole 24, b denotes a matching margin between the wiring layer 25 and the connection hole 24, and c denotes a matching margin between the wiring layer 26 and the connection hole 28. Matching margin, d is a matching margin of the wiring layer 29 and the connection hole 28.

If the matching margins (a, b, c, d) are set to 0, when a misalignment occurs, for example, as shown in FIG. 3, when the mask is shifted in the direction of the arrow when forming the connection hole 24, etching is performed. Since the ratio (selectivity) is different, the substrate 21 in the portion deviating from the diffusion layer 22 is etched. The wiring layer 25 is a case where the mask is shifted in the direction of the arrow 32 at the time of processing. In the formation of the connection hole 28, if the mask is shifted in the direction of the arrow 31, the etching ratio (selection ratio) is reduced.

As described above, if there is no mask matching margin, there is a risk that various damages occur, such as an electrical short between the second wiring layer and the substrate, if a slight misalignment occurs.

Therefore, it is necessary to set positive values as large as, for example, about 0.5 to 1.0 mu m as the a, b, c, and d in order to guarantee an error frame of mask matching and processing between the wiring layers. However, such mask matching margins significantly hinder the miniaturization of wiring and connection size.

As described above, it is conventionally necessary to set a large positive value as the mask matching margin in order to guarantee mask matching and processing errors between the respective wiring layers. However, the miniaturization of the wiring and the connection size is significantly prevented.

[Purpose of invention]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly reliable semiconductor device miniaturized with a wiring structure that does not need to actively take a mask matching margin of a predetermined value and a method of manufacturing the same.

[Configuration of Invention]

A semiconductor device of the present invention for achieving the above object includes a first conductive semiconductor substrate, a first interlayer insulating film formed on the semiconductor substrate, a first buffer layer formed on the first interlayer insulating film, and the first interlayer insulating film. The opening width is narrowed by the first opening having a bottom portion in the middle, the second buffer layer formed on the side wall of the first opening, and the second buffer layer.

In addition, a method of manufacturing a semiconductor device according to the present invention includes forming a first interlayer insulating film on a first conductive semiconductor substrate, and forming a first buffer layer and a stopper insulating film on the first interlayer insulating film. Forming a step, selectively forming a first opening having a bottom portion in the first interlayer insulating film, forming a second buffer layer on the stopper insulating film and covering the first opening, an anisotropic etching method And leaving a second buffer layer on the sidewalls of the first openings, and performing anisotropic etching using the first and second buffer layers as masks to penetrate the bottom portion of the first openings and to surface the semiconductor substrate. Forming a second opening to expose the metal; and filling the second opening with the metal for wiring, and depositing the metal on the second buffer layer. Forming a connecting electrode to an extent having a line width of the first opening, and selectively forming a first wiring layer on the first buffer layer; and depositing a third buffer layer to perform anisotropic etching. A step of leaving the third buffer layer on each sidewall of the connecting electrode and the first wiring layer; forming a second interlayer insulating film and exposing the first wiring layer to the second interlayer insulating film;

(Action)

In the present invention configured as described above, the second buffer layer (Side Wall) formed on the side surface of the first opening is an effective matching margin when the second opening is formed. In addition, the third buffer layer (Side Wall) formed on the side of the first wiring layer becomes an effective matching margin for the first wiring layer when forming the third study.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 (a) to 1 (e) are cross-sectional views sequentially showing the manufacturing process of the connecting electrode and the metal wiring used in the semiconductor device according to the first embodiment method of the present invention.

After forming a well region on the semiconductor substrate 1, the device is separated (not shown), and impurities are selectively introduced into the device region to form the diffusion layer 2. Next, a SiO ₂ film is deposited using a CVD method (chemical vapor deposition method), and a BPSG film (boron phosphide glass) is subsequently deposited on the SiO ₂ film, and then a low temperature reflow process for flattening the surface The first interlayer insulating film 3 is formed through the process. Next, for example, a first buffer layer 4 made of polycrystalline silicon or a high melting point metal silicide is formed to a thickness of about 2000 microseconds by CVD, and then an oxide film 5 (stopper insulating film) of the first buffer layer 4 is formed. [FIG. 1 (a)].

Next, the first opening 6, 第 1 開孔 is drilled in the upper portion of the diffusion layer 2 using the RIE method (reactive ion etching method). The opening 6 is drilled for a predetermined etching time, so that the etching is stopped in the middle of the interlayer insulating film 3 (Fig. 1 (b)).

Next, for example, the second buffer layer 7 made of polysilicon or high melting point metal silicide is formed at about 3000 GPa, and then etched using RIE to leave the buffer layer 7 on the side of the first opening 6. Next, using these first and second buffer layers 4 and 7 as a mask, the connection hole 8 is formed so that a partial region of the diffusion layer 2 on the substrate surface may be exposed (FIG. 1 (c)).

Next, an Al-Si-Cu alloy is deposited by a sputtering method, and then heat-treated at 400 to 500 ° C to melt and fill the connection hole 8, and then deposit an Al-Si-Cu alloy. Thereafter, patterning is performed to form a connection electrode 10 that is the same layer as the first wiring layer 9 (FIG. 1 (d)).

Next, a third buffer layer 11 made of, for example, polycrystalline silicon or a high melting point metal silicide is deposited to be thicker than the second buffer layer 4 by using a low-temperature plasma CVD method (SiH ₄ ) method at 300 to 400 ° C. Etching is performed using the RIE method. As a result, the buffer layer 11 remains only on the side surfaces of the first wiring layer 9 and the connection electrode 10. Thereafter, the second interlayer insulating film 12 is formed by plasma CVD. Next, the second interlayer insulating film 12 is planarized using an etching method, and the VIA connection hole 13 through which the first wiring layer 9 is exposed is drilled. Thereafter, a W film 14 (tungsten film) is selectively deposited in the VIA connection hole 13 using the CVD method. Next, a second wiring layer 15 made of an Al-Si-Cu alloy is deposited and patterned to form a second wiring layer 15 on the W film 14.

According to the method of the above embodiment, the side wall (buffer layer 7) formed on the side surface of the connection hole 8 becomes an effective matching margin for the diffusion layer 2 and the connection electrode 10 at the time of opening the connection hole 8. In this case, although not shown, in the case where the gate electrode is formed on the substrate 1 with the diffusion layer 2 interposed therebetween, the diffusion layer can be formed small, thereby facilitating miniaturization of the device.

Moreover, the side wall (buffer layer 11) formed in the side surface of the said 1st wiring layer 9 becomes an effective matching margin with respect to the 1st wiring layer 9 at the time of opening of the VIA connection hole 13. As shown in FIG.

The wiring layer 9 and the connecting electrode 10 are shaped to have a forward taper by sidewalls (buffer layer 11) on the side. As a result, the planarization of the interlayer insulating film 12 is facilitated.

On the other hand, according to the above embodiment, although the inside of the connection hole 8 is filled by melting the Al alloy in Fig. 1 (d), even if a high melting point metal such as polycrystalline silicon or W (tungsten) is filled, Does not matter. In addition, when a barrier metal layer such as a TiN / Ti laminated structure is used as the support of the Al alloy melted and filled in the connection hole 8, it is possible to prevent Al from entering the substrate by heat treatment.

[Effects of the Invention]

As described above, according to the present invention, since a wiring structure can be formed in which sidewalls are formed on the sidewalls of the connection hole and the wiring, and this is used as an effective mask matching margin. do. As a result, a highly reliable semiconductor device and a manufacturing method thereof can be provided.

Claims (3)

A first conductive semiconductor substrate 1, a first interlayer insulating film 3 formed on the semiconductor substrate 1, a first buffer layer 4 formed on the first interlayer insulating film 3, and the first The first opening 6 having a bottom portion in the first interlayer insulating film 3, the second buffer layer 7 formed on the sidewall of the first opening 6, and the opening width of the second buffer layer 7 by the second buffer layer 7 Iii) the second opening 8, which is narrowed and penetrates the bottom of the first opening 6 to expose the surface of the semiconductor substrate 1, selectively on the first buffer layer 4; The first wiring layer 9 formed in the first wiring layer 9 and the second opening 8 filled in the connection electrode 10 and the first layer of the same layer as the first wiring layer 9 formed on the second buffer layer 7. A third buffer layer 11 formed as each sidewall of the first wiring layer 9 and the connecting electrode 10, the second interlayer lead film 12 covering the first wiring layer 9 and the connecting electrode 10, and The second interlayer insulating film 12 The third opening 13 formed to expose the first wiring layer 9, the high melting point gold curved film 14 formed on the first wiring layer 9 by filling the third opening 13, and And a second wiring layer (15) formed on the high melting point metal film (14). Forming a first interlayer insulating film 3 on the first conductive semiconductor substrate 1, and forming a first buffer layer 4 and a stopper insulating film 5 on the first interlayer insulating film 3 Selectively forming a first opening 6 having a bottom portion in the first interlayer insulating film 3, a second buffer layer covering the stopper insulating film 5 and covering the first opening 6 (7) forming a step; leaving a second buffer layer (7) on the sidewall of the first opening (6) by using an anisotropic etching method; masking the first and second buffer layers (4, 7) Anisotropic etching to form a second opening 8 through which the bottom of the first opening 6 is exposed and exposing the surface of the semiconductor substrate 1, wherein the wiring metal is Filling the second opening 8 and depositing it on the second buffer layer 7, and etching the metal to the wiring to form the first opening ( Forming the connecting electrode 10 to the extent having a line width of 6) and optionally forming the first wiring layer 9 on the first buffer layer 4, by depositing the third buffer layer 11, anisotropic etching The step of leaving the third buffer layer 11 on each side wall of the connecting electrode 10 and the first wiring layer 9 by forming a second interlayer insulating film 12 is performed. Forming a third opening 13 so that the first wiring layer 9 is always exposed to 12, and a high melting point metal on the first wiring layer 9 so as to fill the third opening 13. And forming a second double layer (15) on the solid solution metal film (14). The method of manufacturing a semiconductor device according to claim 2, wherein said first, second, and third buffer layers are formed of polycrystalline silicon or high melting point metal silicide.

Images