JP2019009348A - Quantum cascade semiconductor laser - Google Patents

Abstract

To suppress destruction of an insulation film in a quantum cascade semiconductor laser including the insulation film and metal film sequentially laminated on an end surface constituting a laser resonator.SOLUTION: A QCL 1 comprises: a semiconductor substrate 20 including a principal surface 20a, a rear surface 20b, and a substrate end surface 20c; a semiconductor laminate 30 including an upper surface 30a and a laminate end surface 30b and provided on the principal surface 20a; an upper electrode 50; a lower electrode 60; a metal film 72 provided on the laminate end surface 30b and the substrate end surface 20c, and extending over the upper electrode 50; and a semiconductor insulation part 75 having an upper surface 75c crossing a Z direction, provided between the upper electrode 50 and the metal film 72 in a Y direction, and including an undoped or a semi-insulating semiconductor. The metal film 72 is provided on the upper surface 75c from on the laminate end surface 30b, and the upper surface 75c is provided at a higher position than the upper surface 30a with reference to the principal surface 20a.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a quantum cascade laser.

A quantum cascade laser (QCL) disclosed in Non-Patent Document 1 has a configuration in which a lower electrode, a semiconductor substrate, a semiconductor stack, and an upper electrode are sequentially stacked. A metal film is provided on an end surface of the QCL laser resonator via an insulating film. SiO ₂ is used for the insulating film, and Au is used for the metal film. The QCL is mounted on the electronic component via solder.

S.R.Darvish, et al. “High-power, continuous-wave operation of distributed-feedback quantum-cascade lasers at λ〜7.8μm”, Applied Physics Letters 89, 251119, 2006.

  Some QCLs have a structure in which a lower electrode, a semiconductor substrate, a semiconductor stack, and an upper electrode are sequentially stacked. A metal film may be formed on the end face constituting such a QCL laser resonator as a reflection film in order to increase the reflectance of the laser beam at the end face. However, when the metal film is formed directly on the end face, the respective layers of the semiconductor element portion may be short-circuited (short-circuited) on the end face, which may cause a QCL malfunction. Therefore, it is desirable to provide an insulating film as a base layer between the end face and the metal film (see, for example, Non-Patent Document 1). The insulating film and the metal film are sequentially formed on the end surface from the side facing the end surface. At this time, the insulating film and the metal film may be formed on the upper electrode and the lower electrode by wrapping around the upper electrode and the lower electrode. When the QCL on which the insulating film and the metal film are formed in this way is mounted on an electronic component via, for example, solder, the metal film on the lower electrode comes into contact with the solder. When a voltage (for example, a high voltage of 10 V or more) is applied between the upper electrode and the lower electrode for laser oscillation in a state where the metal film is in contact with the solder as described above, the voltage applied to the lower electrode is reduced. And applied to the metal film via solder. As a result, an equivalent voltage is applied between the metal film on the upper electrode and the upper electrode via the insulating film.

  However, since the thickness of the insulating film on the upper electrode formed by wraparound tends to be extremely thin (for example, about a fraction of the thickness) of the insulating film on the end surface, such an extremely thin insulating film When a high voltage of, for example, 10 V or more is applied between the metal film on the upper electrode and the upper electrode through the insulating film, the insulating film between them may be destroyed. As a result, a large current (so-called rush current) flows near the end face via the broken portion of the insulating film, and there is a possibility that a failure such as end face breakage may occur in the QCL.

  In addition, when trying to increase the thickness of the insulating film on the upper electrode, it is necessary to further increase the thickness of the insulating film on the end face (for example, about several times). In this case, since the time for forming the insulating film on the end face increases (for example, several times), the QCL productivity decreases. In addition, when such an extremely thick insulating film is formed on the end face, the end face deteriorates due to an increase in stress generated in the insulating film, the crack of the insulating film, the end face of the insulating film There is a risk of peeling.

  The present invention has been made in view of such a problem, and suppresses the breakdown of the insulating film in the quantum cascade laser having the insulating film and the metal film sequentially stacked on the end face constituting the laser resonator. For the purpose.

  The quantum cascade laser according to the present invention includes a semiconductor substrate having a main surface and a back surface facing each other in the first direction, a substrate end surface intersecting with a second direction orthogonal to the first direction, and a main surface in the first direction. A first surface provided on the opposite side, a laminated end face included in a plane including the substrate end face, a core layer extending in the second direction from the laminated end face, and a clad layer provided on the core layer, on the main surface Crossing the first direction, the semiconductor stack provided on the substrate, the first electrode provided on the first surface, the second electrode provided on the back surface, the metal film provided on the stack end surface and the substrate end surface. And a semiconductor insulating portion including a semiconductor that is undoped or semi-insulating, and is provided between the first electrode and the metal film in the second direction. Provided over two surfaces , In the first direction, the second surface is provided in a position higher than the first surface principal surface as a reference.

  According to the present invention, in a quantum cascade laser having an insulating film and a metal film that are sequentially stacked on an end face constituting a laser resonator, the breakdown of the insulating film can be suppressed.

FIG. 1 is a perspective view showing a state in which a quantum cascade laser according to an embodiment is mounted. FIG. 2 is a perspective view of the quantum cascade laser of FIG. FIG. 3 is a cross-sectional view taken along line III-III in FIG. FIG. 4A to FIG. 4C are diagrams showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 5A to FIG. 5C are diagrams showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 6A to FIG. 6C are diagrams showing manufacturing steps of the quantum cascade laser shown in FIG. FIG. 7A and FIG. 7B are diagrams showing a manufacturing process of the quantum cascade laser shown in FIG. FIGS. 8A and 8B are diagrams showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 9 is a diagram showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 10 is a perspective view of a quantum cascade laser as a comparative example. 11 is a cross-sectional view taken along line XI-XI in FIG. FIG. 12 is a cross-sectional view of a quantum cascade laser according to a first modification. FIG. 13 is a cross-sectional view of a quantum cascade laser according to a second modification. FIG. 14 is a diagram showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 15 is a cross-sectional view of a quantum cascade laser according to another example of the second modification. FIG. 16 is a cross-sectional view of a quantum cascade laser according to a third modification. FIG. 17 is a cross-sectional view of a quantum cascade laser according to a third modification. FIG. 18A to FIG. 18C are diagrams showing a manufacturing process of the quantum cascade laser shown in FIGS. 16 and 17. FIG. 19A to FIG. 19C are diagrams showing manufacturing steps of the quantum cascade laser shown in FIG. 16 and FIG. FIG. 20 is a cross-sectional view of a quantum cascade laser according to a fourth modification. FIG. 21 is a cross-sectional view of a quantum cascade laser according to a fourth modification. FIG. 22A to FIG. 22C are diagrams showing manufacturing steps of the quantum cascade laser shown in FIG. 20 and FIG. FIG. 23A to FIG. 23C are diagrams showing manufacturing steps of the quantum cascade laser shown in FIG. 20 and FIG. FIG. 24A to FIG. 24C are diagrams showing manufacturing steps of the quantum cascade laser shown in FIG. 20 and FIG.

[Description of Embodiment of the Present Invention]
First, the contents of the embodiment of the present invention will be listed and described. A quantum cascade laser according to an embodiment of the present invention includes a semiconductor substrate having a main surface and a back surface that face each other in a first direction, a substrate end surface that intersects a second direction orthogonal to the first direction, and a first direction. A first surface provided on the opposite side of the main surface; a laminated end face included in a plane including the substrate end face; a core layer extending in the second direction from the laminated end face; and a clad layer provided on the core layer A semiconductor stack provided on the main surface, a first electrode provided on the first surface, a second electrode provided on the back surface, a metal film provided on the stack end surface and the substrate end surface, and a first direction A semiconductor insulating portion including an undoped or semi-insulating semiconductor provided in the second direction between the first electrode and the metal film, the metal film having a stacked end face From the top to the second surface Provided it, in the first direction, the second surface is provided in a position higher than the first surface principal surface as a reference.

  In the quantum cascade laser described above, the second electrode is mounted on the electronic component via, for example, solder, and a voltage (for example, a high voltage of 10 V or more) is applied between the first electrode and the second electrode. The laser beam oscillates. At this time, when the solder contacts the metal film and the voltage applied to the second electrode is applied to the metal film via the solder, the voltage is also applied between the metal film and the first electrode. . Since the insulating film provided between the metal film and the first electrode is easily formed thin, there is a possibility that the insulating film is destroyed by the voltage. However, in the quantum cascade laser described above, the semiconductor insulating part is provided between the first electrode and the metal film in the second direction, and the metal film is provided on the second surface of the semiconductor insulating part. And since the 2nd surface is provided in the position higher than the 1st surface, the insulating region (namely, area | region which consists of an insulating film and a semiconductor insulating part) between a 1st electrode and a metal film is fully ensured. can do. That is, the insulation resistance between the first electrode and the metal film can be increased. Therefore, according to the quantum cascade laser described above, even when the voltage is applied via the insulating film between the metal film on the second surface and the first electrode, the breakdown of the insulating film due to the voltage is suppressed. Can do. As a result, it is possible to suppress the above-described deterioration of the device characteristics of the quantum cascade laser due to end face breakdown caused by the breakdown of the insulating film.

  In the quantum cascade laser described above, the first surface includes a first region and a second region located between the stacked end face and the first region in the second direction, and the first electrode includes the first electrode The semiconductor insulating part may be provided on the second region.

  In the quantum cascade laser described above, the semiconductor insulating portion has a side surface facing the first electrode in the second direction, and the side surface faces the first surface side in the first direction with respect to the stacked end surface. It may be inclined. Thereby, for example, when the metal film is formed on the stacked end face from the second direction, the metal film can be made difficult to go around from the second surface to the side face. That is, the metal film can be hardly formed from the second surface to the side surface and the first electrode. Thereby, generation | occurrence | production of the short circuit by the contact with a metal film and a 1st electrode can be suppressed. As a result, the above-described malfunction of the quantum cascade laser due to the occurrence of the short circuit can be suppressed.

  Moreover, in the quantum cascade laser described above, the semiconductor insulating portion may extend on the stacked end face. Thereby, the electrical resistance in the vicinity of the laminated end face can be further increased, and the leakage current flowing in the vicinity of the laminated end face can be reduced. As a result, the device characteristics of the quantum cascade laser described above can be improved (for example, the threshold current can be reduced). In the quantum cascade laser described above, the semiconductor insulating part may be in contact with the metal film. As described above, by preventing an insulating film or the like made of a material that is not a semiconductor, for example, from interposing between the semiconductor insulating portion and the metal film, it is possible to improve heat dissipation at the end face of the stack. As a result, device characteristics and reliability of the quantum cascade laser described above can be improved. In addition, the semiconductor insulating portion can function as an insulating film that electrically insulates between the stacked end face and the metal film.

The quantum cascade laser described above may further include an insulating film provided between the stacked end face and the metal film. Thereby, generation | occurrence | production of the short circuit by contact with a lamination | stacking end surface and a metal film can be suppressed. As a result, the above-described malfunction of the quantum cascade laser due to the occurrence of the short circuit can be suppressed. In the quantum cascade laser described above, the insulating film may include at least one of SiO ₂ , SiON, SiN, alumina, BCB resin, and polyimide resin. These have excellent durability and insulating properties as protective films for the laminated end face and the substrate end face. Further, they are easily formed on the laminated end face and the substrate end face by using a general dielectric film forming method such as sputtering, CVD, or spin coating. That is, an insulating film forming process can be easily introduced into the above-described quantum cascade laser manufacturing process.

  The quantum cascade laser described above further includes two current block portions including an undoped or semi-insulating semiconductor, and the semiconductor stack is opposite to each other in the first direction and the third direction orthogonal to the second direction. The two current block portions may be formed of the same material as that of the semiconductor insulating portion, having a surface and exhibiting a mesa shape extending in the second direction. As a result, the semiconductor insulating portion and the two current block portions can be grown at the same time, and the manufacturing process of the quantum cascade laser described above can be simplified. That is, the quantum cascade laser described above can be easily manufactured. As a result, the productivity of the quantum cascade laser described above can be improved.

In the quantum cascade laser described above, the semiconductor insulating portion may include a semi-insulating semiconductor doped with at least one transition metal of Fe, Ti, Cr, and Co. A semiconductor doped with these transition metals has a sufficiently high electric resistance characteristic (for example, 10 ⁵ Ωcm or more) with respect to electrons, and thus is suitable as a material for a semiconductor insulating portion.

  In the quantum cascade laser described above, the metal film may contain Au. Thereby, the metal film can be effectively functioned as a reflective film having a high reflectance exceeding 90%, for example, on the laminated end face and the substrate end face.

  In the quantum cascade laser described above, the cladding layer may be an InP layer. Since InP is transparent to the oscillation light in the mid-infrared region (not showing light absorption), it is suitable as a material for the cladding layer. Further, since InP is a binary mixed crystal and lattice-matched to the InP substrate, the InP layer can be favorably grown on the InP substrate. Further, since the thermal conductivity of InP is good, heat from the core layer can be released well through the cladding layer. Thereby, the temperature characteristic of the quantum cascade laser described above can be improved.

  In the quantum cascade laser described above, the semiconductor substrate may be an InP substrate. The semiconductor stack constituting the quantum cascade laser in the mid-infrared region has a lattice constant close to InP. Therefore, when the semiconductor substrate is an InP substrate, the semiconductor stack can be grown on the semiconductor substrate with good crystal quality. Further, since InP is transparent to light in the mid-infrared region, the InP substrate can function as a cladding layer for the core layer.

[Details of the embodiment of the present invention]
A specific example of the quantum cascade laser according to the embodiment of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to the claim are included. In the following description, the same reference numerals are given to the same elements in the description of the drawings, and redundant descriptions are omitted.

(Embodiment)
FIG. 1 is a perspective view showing a state in which a quantum cascade laser (QCL) 1 according to an embodiment is mounted. In FIG. 1, an XYZ orthogonal coordinate system is shown for easy understanding. QCL1 is a distributed feedback (DFB) type element that oscillates single-mode light, and can oscillate in the mid-infrared region of 3 μm to 20 μm, for example. As shown in FIG. 1, the QCL 1 is mounted on the submount 3 mounted on the carrier 2 via the solder 4. Specifically, the QCL 1 is die-bonded on the submount 3 using the solder 4 in an epi-up form (a form in which the epitaxially grown side is placed on the upper surface). A lower electrode (described later) of the QCL 1 is electrically connected to the carrier 2 via the submount 3 and the solder 4. Further, one end of a wire 5 for supplying power to the QCL 1 is connected to an upper electrode (to be described later) of the QCL 1. The other end of the wire 5 is connected to a bonding pad (not shown). The upper electrode of the QCL 1 is electrically connected to the bonding pad via the wire 5. The carrier 2 and the bonding pad are electrically connected to an external power source (not shown). Then, by applying a predetermined voltage from the external power source to the upper electrode and the lower electrode of QCL1, QCL1 is turned on, current flows in QCL1, and QCL1 laser oscillates.

  The lengths W1 and L1 in the X direction and the Y direction of the carrier 2 are, for example, 4 mm to 8 mm, respectively, and the thickness H1 of the carrier 2 in the Z direction is, for example, 1 mm to 8 mm. The lengths W2 and L2 of the submount 3 in the X direction and the Y direction are, for example, 1 mm to 4 mm and 2 mm to 4 mm, respectively, and the thickness H2 of the submount 3 in the Z direction is, for example, 0.1 mm to 0.5 mm. is there. The submount 3 is made of, for example, AIN or CuW, and the carrier 2 is made of, for example, Cu or CuW. For example, AuSn, In, or silver paste is used for the solder 4, and Au wire or the like is used for the wire 5.

  FIG. 2 is a perspective view of the QCL 1 in FIG. 3 is a YZ sectional view taken along line III-III in FIG. As shown in FIGS. 2 and 3, the QCL 1 includes a semiconductor element part 10, an insulating film 71, a metal film 72, and a semiconductor insulating part 75. The semiconductor element unit 10 has a buried heterostructure (BH) current confinement structure. The semiconductor element portion 10 has a rectangular parallelepiped shape with the resonance direction (Y direction) as a longitudinal direction. The length L3 in the Y direction of the semiconductor element portion 10 is, for example, 1 mm to 3 mm, the length W3 in the X direction of the semiconductor element portion 10 is, for example, 400 μm to 800 μm, and the length in the Z direction of the semiconductor element portion 10 is The length (thickness) H3 is, for example, 100 μm to 200 μm. The semiconductor element portion 10 has a rear end face 10a and a front end face 10b that face each other in the Y direction. The semiconductor element unit 10 includes a semiconductor substrate 20, a semiconductor stack 30, two current block units 40, an upper electrode (first electrode) 50, and a lower electrode (second electrode) 60.

  As shown in FIG. 3, the semiconductor substrate 20 is mounted on the submount 3 via the solder 4. The semiconductor substrate 20 is, for example, an n-type InP substrate. The semiconductor substrate 20 has conductivity in order to apply a voltage to the upper electrode 50 and the lower electrode 60 to supply a current to the semiconductor stack 30. In QCL1, since electrons are used as carriers, the conductivity type of the semiconductor substrate 20 is usually n-type. The semiconductor substrate 20 functions as a lower cladding layer for the core layer 33. The semiconductor substrate 20 may not function as a lower cladding layer. In that case, a lower cladding layer is provided between the semiconductor substrate 20 and the core layer 33. The semiconductor substrate 20 includes a main surface 20a, a back surface 20b, and a substrate end surface 20c. The main surface 20a and the back surface 20b oppose each other in the thickness direction (Z direction which is the first direction). The back surface 20b is disposed on the submount 3 side in the Z direction of the semiconductor substrate 20 with respect to the main surface 20a. In one example, the distance between the main surface 20a and the back surface 20b in the Z direction (that is, the thickness of the semiconductor substrate 20 in the Z direction) is 100 nm. The substrate end surface 20c intersects the Y direction (second direction) and connects the main surface 20a and the back surface 20b. The substrate end surface 20c is included in the rear end surface 10a.

  The semiconductor stack 30 is provided on the main surface 20 a of the semiconductor substrate 20. The semiconductor stack 30 includes an upper surface (first surface) 30a that intersects the Z direction and a stack end face 30b that intersects the Y direction. The upper surface 30a is provided on the side opposite to the main surface 20a in the Z direction. The upper surface 30a includes a region 30c (first region) and a region 30d (second region) located between the stacked end surface 30b and the region 30c in the Y direction. The region 30c and the region 30d are arranged along the Y direction. The region 30c is a region excluding the region 30d on the upper surface 30a, and is connected to the front end surface 10b. The region 30d is a region provided at one end of the upper surface 30a in the Y direction, and is connected to the rear end surface 10a. The stacked end surface 30b is included in a plane including the substrate end surface 20c. That is, the laminated end surface 30b is included in the rear end surface 10a including the substrate end surface 20c. In addition, the semiconductor stack 30 has a mesa shape. That is, the semiconductor stack 30 has a stripe shape having a predetermined width WM in the X direction and extending along the Y direction, and is located at the center of the QCL 1 in the X direction. The semiconductor stack 30 includes both end faces facing each other in the Y direction and both side faces facing each other in the X direction. Both end faces of the semiconductor stack 30 are mirrors for constituting a QCL1 laser resonator. One end face of the both end faces is included in the laminated end face 30b. The semiconductor stack 30 includes a buffer layer 32, a core layer 33, a diffraction grating layer 34, an upper clad layer 35, and a contact layer 36, which are sequentially stacked on the semiconductor substrate 20.

  The buffer layer 32 and the upper cladding layer 35 are, for example, n-type InP layers. The buffer layer 32 functions as a lower clad layer for the core layer 33 together with the semiconductor substrate 20. The upper cladding layer 35 is provided on the core layer 33 via the diffraction grating layer 34. Note that the buffer layer 32 may not be provided in the semiconductor stack 30. In this case, the core layer 33 is provided on the main surface 20 a of the semiconductor substrate 20. The core layer 33 extends along the Y direction from the stacked end surface 30b. The core layer 33 has a plurality of unit structures. The plurality of unit structures are arranged side by side in the stacking direction (Z direction), and adjacent unit structures are in contact with each other. The number of unit structures is several tens, for example. Each unit structure forms a superlattice array in which quantum well layers (several nm thick) and barrier layers (several nm thick) are alternately stacked along the Z direction. GaInAs or GaInAsP is often used for the quantum well layer, and AlInAs is often used for the barrier layer. Each unit structure includes one active layer and one injection layer. The active layer is a light emitting region. The injection layer is provided to inject carriers into the active layer. In one example, the active layer and the injection layer are stacked together along the Z direction to form a GaInAs / AlInAs superlattice array.

  Here, the light emission principle of QCL1 will be briefly described. In QCL1, only electrons are used as carriers, and light emission occurs when electrons transition between subbands in the conduction band in the active layer. The light generated by the light emission is amplified in the laser resonator of QCL1, whereby QCL1 oscillates laser light in the mid-infrared region. Specifically, in QCL1, the following three-level laser operation is realized in the conduction band in the active layer. First, electrons are injected from the injection layer to the upper level of the active layer by tunneling. The electrons transit from the upper level to the lower level of the active layer. At this time, light having a wavelength corresponding to the transition energy (energy difference between subbands between the upper level and the lower level) is emitted according to the transition. The electrons that have transitioned to the lower level do not emit light to the ground level with a short relaxation time due to LO phonon scattering. The above-described electron behavior is caused by the fact that the energy difference between the lower level and the ground level is designed to be the LO phonon energy in order to resonantly generate LO phonon scattering. . In this way, the electrons do not emit light to the ground level with a short relaxation time, so that an inversion distribution is realized between the upper level and the lower level in the active layer. The electrons relaxed to the ground level move to the upper level of the next injection layer by a predetermined electric field. Thereafter, the same operation is repeated over several tens of cycles, for example, to obtain a gain necessary for laser oscillation of QCL1. Here, by appropriately selecting the material composition of the quantum well layer and the barrier layer, and the film thicknesses of these layers, and adjusting the energy difference between the upper level and the lower level as appropriate, for example, between 3 μm and 20 μm QCL1 capable of oscillation in the infrared region is realized.

  As shown in FIG. 3, the diffraction grating layer 34 is formed with a diffraction grating 34a composed of a concavo-convex pattern in which concave and convex portions are alternately and repeatedly arranged with a period Λ along the Y direction. The diffraction grating 34a is formed by patterning a resist on the diffraction grating layer 34 serving as a convex portion at intervals of a period Λ and then periodically etching a part of the diffraction grating layer 34 serving as a concave portion in the Z direction. Is done. The period Λ is set as appropriate, and only the light with the Bragg wavelength corresponding to the period Λ is selectively reflected by the diffraction grating and amplified in the laser resonator. As a result, the QCL 1 oscillates a single mode laser beam only with this Bragg wavelength. The performance of the diffraction grating layer 34 is expressed by a coupling coefficient indicating the magnitude of coupling between the forward guided light and the backward guided light in the laser resonator. In order for the QCL 1 to oscillate a single mode laser beam satisfactorily, it is desirable to use a diffraction grating 34a that provides a large coupling coefficient. Therefore, as the material of the diffraction grating layer 34, a high refractive index semiconductor that is advantageous for realizing a large coupling coefficient is used. In one example, the diffraction grating layer 34 is made of, for example, undoped or n-type GaInAs.

  The contact layer 36 realizes a good ohmic contact with the upper electrode 50. The contact layer 36 preferably includes a material having a small band gap and lattice-matching with the semiconductor substrate 20 in order to realize a good ohmic contact. The contact layer 36 is, for example, n-type GaInAs. Note that when a good ohmic contact can be realized between the upper cladding layer 35 and the upper electrode 50, the contact layer 36 may not be provided in the semiconductor stack 30.

The two current block portions 40 shown in FIG. 2 function as current confinement layers for confining current (carriers) in the semiconductor stack 30. The two current block portions 40 embed both side surfaces of the semiconductor stack 30. In other words, the two current block portions 40 are respectively disposed on both side surfaces of the semiconductor stack 30 on the main surface 20 a of the semiconductor substrate 20. For each current block 40, an undoped or semi-insulating semiconductor is used. Since these semiconductors have high electric resistance with respect to electrons as carriers, they are suitable as materials for the current block portion 40. Semi-insulating semiconductors are realized by adding (doping) transition metals such as Fe, Ti, Cr, and Co to III-V compound semiconductors to form deep levels in the forbidden band that trap electrons. Is done. The III-V compound semiconductor to which the transition metal is added has a sufficiently high electric resistance characteristic of 10 ⁵ Ωcm or more with respect to electrons. Fe is suitable as the transition metal. Note that when the undoped semiconductor has a sufficiently high electrical resistance to electrons, the undoped semiconductor may be applied to the current block unit 40. Examples of the undoped or semi-insulating III-V compound semiconductor include InP, GaInAs, AlInAs, GaInAsP, and AlGaInAs. These semiconductors are lattice-matched with the semiconductor substrate 20 and are grown using a general growth method such as molecular beam epitaxy (MBE) and metal organic vapor phase epitaxy (OMVPE).

  The upper electrode 50 and the lower electrode 60 are provided to supply current to the core layer 33. For the upper electrode 50 and the lower electrode 60, for example, Ti / Au, Ti / Pt / Au, or Au / Ge is used. The upper electrode 50 is, for example, a cathode electrode. The upper electrode 50 is provided on the upper surface 30 a (specifically, on the contact layer 36) and the current block unit 40 of the semiconductor stack 30. More specifically, the upper electrode 50 is provided on the region 30c of the upper surface 30a and is not provided on the region 30d. The lower electrode 60 is an anode electrode, for example. The lower electrode 60 is provided between the back surface 20 b of the semiconductor substrate 20 and the solder 4. The lower electrode 60 is at a positive potential with respect to the upper electrode 50.

  An optical confinement layer may be provided between the core layer 33 and the semiconductor substrate 20 and between the core layer 33 and the upper cladding layer 35. The band gap of the optical confinement layer is smaller than the band gap of the semiconductor substrate 20 and the upper cladding layer 35 and larger than the band gap of the core layer 33. Thereby, electrons injected from the buffer layer 32 are efficiently injected into the core layer 33 without being blocked by the optical confinement layer. When the above-described band gap magnitude relationship is satisfied, the refractive index of the optical confinement layer is larger than that of the semiconductor substrate 20 and the upper cladding layer 35 and smaller than that of the core layer 33. Therefore, the semiconductor substrate 20 and the upper cladding layer 35 function to confine light generated in the core layer 33 in the core layer 33 and the optical confinement layer, and as a result, confinement of light in the core layer 33 is enhanced. The optical confinement layer has a higher refractive index than the semiconductor substrate 20 and the upper cladding layer 35 and can be lattice-matched to the semiconductor substrate 20 in order to enhance the confinement of guided light in the core layer 33. It is desirable to consist of materials. For example, undoped or n-type GaInAs is used for the optical confinement layer.

The insulating film 71 is provided on the rear end face 10 a side in the Y direction of the semiconductor element unit 10, and is provided between the stacked end face 30 b and the substrate end face 20 c and the metal film 72. Specifically, the insulating film 71 is provided on the stacked end face 30 b and the substrate end face 20 c and extends over the region 30 d and the lower electrode 60. The insulating film 71 covers all of the stacked end surface 30 b and the substrate end surface 20 c, and covers all the end portions on the rear end surface 10 a side of the lower electrode 60. The thickness in the Y direction of the insulating film 71 on the rear end face 10 a is larger than the thickness in the Z direction of the insulating film 71 on the region 30 d and the thickness in the Z direction of the insulating film 71 on the lower electrode 60. In one example, the thickness in the Y direction of the insulating film 71 on the rear end face 10a is 100 nm to 200 nm, and the thickness in the Z direction of the insulating film 71 on the region 30d and the lower electrode 60 is 20 nm to 30 nm. . The insulating film 71 is a dielectric film including at least one of, for example, SiO ₂ , SiON, SiN, Al ₂ O ₃ (alumina), BCB resin, and polyimide resin. The metal film 72 is provided on the stacked end face 30 b and the substrate end face 20 c via the insulating film 71, and extends over the region 30 d and the lower electrode 60. The metal film 72 covers all the laminated end surface 30b and the substrate end surface 20c, and covers all the end portions on the rear end surface 10a side of the lower electrode 60. The metal film 72 does not extend on the region 30 c and is not in direct contact with the upper electrode 50. The metal film 72 includes, for example, Au, and has a high reflectance exceeding 90%, for example. The solder 4 is provided on the submount 3 in a range reaching the substrate end surface 10c. The metal film 72 extending over the lower electrode 60 is in contact with the solder 4. Alternatively, the metal film 72 may cover the substrate end surface 20c but may not extend over the lower electrode 60c. Even in this case, the lower part of the metal film 72 on the substrate end surface 20 c is in contact with the solder 4. The metal film 72 that does not extend over the lower electrode 60c is obtained when a long protective plate 90 that reaches the substrate end face 10c is used in the step of forming the metal film 72 described later.

  The semiconductor insulating portion 75 has a rectangular parallelepiped shape extending along the X direction. The semiconductor insulating portion 75 is provided on the region 30d, and is provided between the upper electrode 50 and the metal film 72 in the Y direction. Specifically, the semiconductor insulating portion 75 is provided between the upper electrode 50, the insulating film 71, and the metal film 72 in the Y direction, and between the region 30d, the insulating film 71, and the metal film 72 in the Z direction. Is provided. The semiconductor insulating portion 75 has a side surface 75a, a side surface 75b, an upper surface (second surface) 75c, and a lower surface 75d. The side surface 75a and the side surface 75b intersect the Y direction and are along a plane parallel to the rear end surface 10a. In one example, the side surface 75a and the side surface 75b are orthogonal to the Y direction. The side surface 75a faces the upper electrode 50 in the Y direction. The side surface 75b is provided on the side opposite to the side surface 75a in the Y direction. The side surface 75 b is entirely covered with the insulating film 71. The upper surface 75c and the lower surface 75d intersect with the Z direction. In one example, the side surface 75a and the side surface 75b are orthogonal to the Z direction. The upper surface 75c faces the insulating film 71 in the Z direction. The edges of the insulating film 71 and the metal film 72 are located on the upper surface 75c. That is, the insulating film 71 and the metal film 72 extend from the stacked end surface 30b to the upper surface 75c. The upper surface 75c is provided at a position higher than the region 30d of the upper surface 30a with respect to the main surface 20a of the semiconductor substrate 20 in the Z direction. In other words, the upper surface 75c is located on the opposite side of the region 30d with respect to the upper electrode 50 in the Z direction. The lower surface 75d is provided on the opposite side of the upper surface 75c in the Z direction and faces the region 30d.

  The thickness of the semiconductor insulating portion 75 in the Z direction (that is, the distance in the Z direction between the upper surface 75c and the lower surface 75d) is, for example, 1 μm to 2 μm, and more preferably, 1.5 to 2 μm. In addition, the width in the Y direction of the semiconductor insulating portion 75 (that is, the distance in the Y direction between the side surface 75a and the side surface 75b) is to avoid the occurrence of crystal deterioration such as abnormal crystals during crystal growth on the region 30d. For example, it is set to 10 μm or more. The width of the semiconductor insulating portion 75 in the Y direction is set to, for example, 70 μm or more for good flatness of the upper surface 75c of the semiconductor insulating portion 75. The same material as that which can be applied to the current block portion 37 can be applied to the semiconductor insulating portion 75. That is, the semiconductor insulating part 75 includes an undoped or semi-insulating semiconductor. The semi-insulating property of the semiconductor is that a transition metal such as Fe, Ti, Cr, and Co is added (doped) to the III-V compound semiconductor to form a deep level for trapping electrons in the forbidden band. It is realized by. Examples of undoped or semi-insulating III-V compound semiconductors include InP, GaInAs, AlInAs, GaInAsP, and AlGaInAs.

  An example of a method for manufacturing the QCL 1 having the above configuration will be described below. 4 (a) to 4 (c), 5 (a) to 5 (c), 6 (a) to 6 (c), 7 (a), 7 (b), and 8 (A), FIG. 8 (b), and FIG. 9 are diagrams showing a manufacturing process of the QCL 1 in FIG. 4A to FIG. 4C, FIG. 6A to FIG. 6C, and FIG. 7A and FIG. 7B are along the line III-III in FIG. The YZ cross section corresponding to the cross section is shown, and FIGS. 5A to 5C show the XZ cross section. First, a wafer to be the semiconductor substrate 20 is prepared. In the first crystal growth step, the buffer layer 32, the core layer 33, and the diffraction grating layer 34 are grown in this order on the main surface of the wafer by using a growth method such as MBE and OMVPE. Thereafter, a resist 80 is applied on the diffraction grating layer 34. Subsequently, as shown in FIG. 4A, a pattern for the diffraction grating 34a is formed on the resist 80 by a normal photolithography technique. At this time, the width of the pattern of the resist 80 in the X direction is Λ. Subsequently, by etching the diffraction grating layer 34 in the Z direction, a periodic structure for the diffraction grating 34a is formed on the diffraction grating layer 34, as shown in FIG.

Next, in the second crystal growth step, as shown in FIG. 4C, the upper cladding layer 35, the contact layer 36, and the semi-insulating material that becomes the semiconductor insulating portion 75 are formed on the diffraction grating layer 34. The semiconductor layer 76 is crystal-grown in this order. Next, as shown in FIG. 5A, a mask 81 is formed on the semiconductor layer 76 on the region to be the semiconductor stack 30 by a normal photolithography technique. The region to be the semiconductor stack 30 is a region having a predetermined width WM in the X direction and extending in the Y direction at the center in the X direction of QCL1. For the mask 81, for example, the same material as the material of the insulating film 71 is used. That is, the mask 81 is made of a dielectric material including at least one of SiN, SiON, alumina, and SiO ₂ .

  Thereafter, by using the mask 81, the semiconductor layer 76, the contact layer 36, the upper cladding layer 35, the diffraction grating layer 34, the core layer 33, the buffer layer 32, and the semiconductor substrate 20 are etched in the Z direction, As shown in FIG. 5B, a mesa-shaped semiconductor stack 30 is formed. Note that dry etching or wet etching can be applied as the etching of the semiconductor stack 30, but dry etching is preferably applied. The reason is that the predetermined width WM of the semiconductor stack 30 greatly affects the element characteristics of the QCL1, and therefore the predetermined width WM can be processed with high precision by dry etching having excellent vertical etching properties. For example, reactive ion etching (RIE) can be used as the dry etching. In reactive ion etching, a plasma etching gas is used.

  Next, in the third crystal growth step, a semi-insulating semiconductor layer such as InP to which Fe is added is grown with the mask 81 left on the semiconductor layer 76. At this time, as shown in FIG. 5C, the crystal is not grown on the mask 81, and is removed by etching in two regions on both side surfaces of the semiconductor stack 30 (that is, in FIG. 5B). The semiconductor layer is grown so as to embed each of the two regions corresponding to the portion. In this way, two current block portions 40 are formed. Next, after removing the mask 81, as shown in FIG. 6A, a mask 82 is formed on the semiconductor layer 76 provided on the region 30d by a normal photolithography technique. The mask 82 is made of the same material as the mask 81. Thereafter, the semiconductor layer 76 is etched in the Z direction using the mask 81, so that only the semiconductor layer 76 covered with the mask 82 remains. In this way, as shown in FIG. 6B, the semiconductor insulating portion 75 is formed.

  Next, as shown in FIG. 6C, a resist 83 is patterned on the semiconductor insulating portion 75 by a normal photolithography technique, and the metal film 51 to be the upper electrode 50 is formed on the resist 83 and the region 30c. Form. Thereafter, when the resist 83 is removed by lift-off, the resist 83 and the metal film 51 on the resist 83 are simultaneously removed from the semiconductor insulating portion 75. In this manner, as shown in FIG. 7A, the upper electrode 50 provided only on the region 30c is formed. Thereafter, the thickness of the wafer is reduced to a cleaving thickness (for example, 100 to 200 μm) by polishing or the like, and then the lower electrode 60 is formed on the back surface 20b of the semiconductor substrate 20 as shown in FIG. To do.

  After the above steps, as shown in FIG. 8A, a plurality of semiconductor element portions 10 formed with semiconductor insulating portions 75 are formed in an aligned state in the X direction and the Y direction on the entire surface of the wafer. Is done. FIG. 8A shows boundary lines B1 and B2 between the semiconductor element portions 10 when the plurality of semiconductor element portions 10 are individually divided. The boundary line B1 is along the X direction, and the boundary line B2 is along the Y direction. Then, by cleaving the plurality of semiconductor element portions 10 along the boundary line B1, a crack is generated in the wafer along the boundary line B1. As a result, the wafer is divided along the boundary line B1, and the chip bar 85 as shown in FIG. 8B is formed. The chip bar 85 includes a plurality of semiconductor element portions 10 arranged along the X direction and a semiconductor insulating portion 75 formed in the semiconductor element portion 10. The chip bar 85 has an end surface 85a including the rear end surface 10a of the QCL1 in the Y direction. The semiconductor insulating part 75 is provided on the end face 85 a side in the Y direction of the chip bar 85.

  Subsequently, a process of forming the insulating film 71 and the metal film 72 on the end face 85a will be described. First, as shown in FIG. 9, two protective plates 90 are prepared in order to form the insulating film 71 in a desired region of the chip bar 85. The desired region is a partial region including the end surface 85a of the chip bar 85. The region 30d includes the partial region. The protective plate 90 has a rectangular thin plate shape whose longitudinal direction is the X direction. As shown in FIG. 9, a single protective plate 90 is used to cover all the upper electrodes 50 included in other areas of the chip bar 85 except for the partial area. At this time, the protection plate 90 also covers a part of the side surface 75a (see FIG. 3) side of the semiconductor insulating portion 75 in the Y direction. Then, the lower electrode 60 included in the other region of the chip bar 85 is covered with another protective plate 90. Next, the insulating film 71 is formed on the end face 85a. Specifically, the constituent atoms of the insulating film 71 are deposited on the end face 85a from the side facing the end face 85a by using, for example, CVD or sputtering. The side facing the end surface 85a refers to a position facing the end surface 85a in the normal direction of the end surface 85a. At this time, the insulating film 71 is also formed on the upper surface 75 c and the lower electrode 60 by wrapping around the upper surface 75 c and the lower electrode 60 of the semiconductor insulating portion 75. In this way, the insulating film 71 is formed in the partial region of the chip bar 85.

  Subsequently, a metal film 72 is formed on the insulating film 71 on the end face 85a. Specifically, the constituent atoms of the metal film 72 are deposited on the end surface 85a from the side facing the end surface 85a by using, for example, electron beam evaporation. At this time, the metal film 72 is also formed on the insulating film 71 on the upper surface 75 c and the lower electrode 60 by wrapping around the upper surface 75 c and the lower electrode 60. In this way, the metal film 72 is formed in the partial region of the chip bar 85.

  The length in the Y direction of the protective plate 90 used when forming the metal film 72 is longer than the length in the Y direction of the protective plate 90 used when forming the insulating film 71. Thereby, the edge of the insulating film 71 on the upper surface 75c is located on the opposite side to the end surface 85a in the Y direction with respect to the edge of the metal film 72 on the upper surface 75c. Finally, the wafer is cracked along the boundary line B2 by cleaving the chip bar 85 along the boundary line B2 (see FIG. 8B) along the Y direction. Thus, the chip bars 85 are individually divided along the boundary line B2. Finally, QCL1 as shown in FIG. 1 is formed.

  The effects obtained by the QCL 1 of the present embodiment described above will be described together with the problems of the prior art. QCL is promising as a light source that can be used in technical fields where high growth is expected in the future, such as environmental gas analysis, medical diagnosis, and industrial processing. QCL can generate laser oscillation light in the mid-infrared region (for example, wavelength 3 μm to 30 μm). QCL is expected as a light source that realizes miniaturization and cost reduction, and is being actively developed. In particular, in the gas sensing field which is promising in the mid-infrared region, it is necessary to detect only the absorption line of a specific gas, so the development of DFB-type QCL capable of single mode operation in the mid-infrared region has become the mainstream. ing. In such a QCL, in principle, non-radiative recombination due to LO phonon scattering or the like occurs remarkably, so that the threshold current required for the laser oscillation of the QCL increases from several hundred mA to several A. The power consumption of QCL also increases. Such an increase in threshold current is one factor that hinders the practical use of QCL. Therefore, in order to suppress such an increase in threshold current, it is conceivable to provide a metal film on the end face constituting the QCL laser resonator.

  Here, a QCL structure in which a metal film is provided on the end face will be described as a comparative example. FIG. 10 is a perspective view of a QCL 100 as a comparative example. 11 is a cross-sectional view taken along line XI-XI in FIG. In each figure, an XYZ orthogonal coordinate system is shown for easy understanding. Since the QCL 100 is actually mounted on the submount via the solder 4, for example, FIG. 11 shows a state in which the solder 4 is attached under the QCL 100. The current confinement structure of the QCL 100 is a buried heterostructure similar to the structure of the QCL 1 of the present embodiment. As shown in FIG. 10, the QCL 100 includes a semiconductor element unit 10, an insulating film 71, and a metal film 72.

  The difference between the QCL 100 and the QCL 1 of the present embodiment is that the QCL 100 does not include the semiconductor insulating portion 75. Accordingly, the upper electrode 50 covers the entire upper surface 30a. The insulating film 71 and the metal film 72 extend over the upper electrode 50. When the QCL 100 is mounted on the submount via the solder 4, the metal film 72 on the lower electrode 60 comes into contact with the solder 4. When a voltage (for example, a high voltage of 10 V or more) is applied between the upper electrode 50 and the lower electrode 60 for laser oscillation of the QCL 100 with the metal film 72 in contact with the solder 4 as described above, the lower electrode The voltage applied to 60 is applied to the metal film 72 via the solder 4. As a result, the voltage is applied via the insulating film 71 between the metal film 72 on the upper electrode 50 and the upper electrode 50.

  However, since the thickness T2 of the insulating film 71 on the upper electrode 50 is likely to be extremely thinner than the thickness T1 of the insulating film 71 on the rear end face 10a as described above, such an extremely thin insulating film 71 is formed. When a high voltage of, for example, 10 V or more is applied between the metal film 72 on the upper electrode 50 and the upper electrode 50, the insulating film 71 in between may be broken. As a result, a large current (so-called inrush current) flows in the vicinity of the rear end face 10a via the destroyed portion of the insulating film 71, and there is a possibility that a failure such as an end face destruction may occur in the QCL 100. Note that if the thickness of the insulating film 71 on the upper electrode 50 is to be increased, it is necessary to further increase the thickness of the insulating film 71 on the rear end face 10a (for example, about several times). In this case, since the time for forming the insulating film 71 on the rear end face 10a increases (for example, several times), the productivity of the QCL 100 decreases. In addition, when such an extremely thick insulating film 71 is formed on the rear end face 10a, the rear end face 10a is deteriorated due to an increase in the stress generated in the insulating film 71, and the insulating film 71 is cracked or insulated. There is a possibility that peeling from the rear end face 10a of the film 71 may occur.

  On the other hand, in the QCL 1 of the present embodiment, as shown in FIG. 3, the semiconductor insulating portion 75 is provided between the region 30d and the metal film 72, and the upper surface 75c of the semiconductor insulating portion 75 is Since it is provided at a position higher than the upper surface 30 a of the semiconductor stack 30, a sufficient insulating region between the upper electrode 50 and the metal film 72 (that is, a region formed of the insulating film 71 and the semiconductor insulating portion 75) is ensured. be able to. That is, the insulation resistance between the upper electrode 50 and the metal film 72 can be increased. Therefore, according to the above-described QCL1, even when the voltage is applied via the insulating film 71 between the metal film 72 on the upper surface 75c and the upper electrode 50, the breakdown of the insulating film 71 due to the voltage can be suppressed. it can. As a result, it is possible to suppress the deterioration of the element characteristics of the QCL 1 due to end face destruction caused by the destruction of the insulating film 71. Further, since the semiconductor insulating portion 75 is interposed between the region 30 d and the metal film 72, the contact between the upper electrode 50 and the metal film 72 can be suppressed. Therefore, occurrence of a short circuit due to contact between the upper electrode 50 and the metal film 72 can be suppressed.

Further, as in the present embodiment, the insulating film 71 may be provided between the stacked end face 30b and the metal film 72 and may extend over the upper surface 75c. Thereby, generation | occurrence | production of the short circuit by the contact with the lamination | stacking end surface 30b and the metal film 72 can be suppressed. As a result, the occurrence of malfunction of QCL1 due to the occurrence of the short circuit can be suppressed. Further, as in the present embodiment, the insulating film 71 may include at least one of SiO ₂ , SiON, SiN, alumina, BCB resin, and polyimide resin. These have excellent durability and insulating properties as a protective film for the rear end face 10a. Further, they are easily formed on the rear end face 10a by using a general dielectric film forming method such as sputtering, CVD, or spin coating. That is, the film formation process of the insulating film 71 can be easily introduced into the manufacturing process of the QCL1.

Further, as in the present embodiment, the semiconductor insulating portion 75 may include a semi-insulating semiconductor doped with at least one transition metal among Fe, Ti, Cr, and Co. A semiconductor doped with these transition metals has a sufficiently high electric resistance characteristic (for example, 10 ⁵ Ωcm or more) with respect to electrons, and thus is suitable as a material for the semiconductor insulating portion 75.

  Further, as in the present embodiment, the metal film 72 may include Au. Thereby, in the rear end surface 10a, the metal film 72 can be effectively functioned as a high reflection film having a reflectance exceeding 90%, for example.

  Further, as in the present embodiment, the upper cladding layer 35 may be an InP layer. InP is suitable for the material of the upper cladding layer 35 because it is transparent to the oscillation light in the mid-infrared region (not showing light absorption). Further, since InP is a binary mixed crystal and lattice-matched to the InP semiconductor substrate 20, the InP layer can be satisfactorily grown on the InP substrate. Further, since the thermal conductivity of InP is good, the heat from the core layer 33 can be released well through the upper cladding layer 35. Thereby, the temperature characteristic of QCL1 can be improved.

  Further, as in the present embodiment, the semiconductor substrate 20 may be an InP substrate. The semiconductor stack 30 constituting the QCL1 has a lattice constant close to InP. Therefore, by using the semiconductor substrate 20 as the InP substrate, the semiconductor stack 30 can be grown on the semiconductor substrate 20 with good crystal quality. Further, since InP is transparent to light in the mid-infrared region, the InP substrate can function as a lower cladding layer for the core layer 33.

(First modification)
FIG. 12 is a cross-sectional view of the QCL 1A according to the first modification of the above embodiment. FIG. 12 shows a YZ cross section including the semiconductor stack 30 of QCL1A. The difference between this modification and the above embodiment is the inclination of the side surface of the semiconductor insulating portion. The side surface 75a of the semiconductor insulating portion 75 of the above embodiment is along a plane parallel to the rear end surface 10a. However, the side surface 75e of the semiconductor insulating portion 75A of this modification is inclined with respect to the plane parallel to the rear end surface 10a. (Ie, inclined with respect to a plane parallel to the laminated end face 30b), and formed in an inverted mesa shape. Specifically, as illustrated in FIG. 12, the side surface 75e is inclined with respect to a plane parallel to the stacked end surface 30b so as to face the upper surface 30a side in the Z direction. In other words, the normal vector of the side surface 75e is inclined so as to face the upper surface 30a side in the Z direction. Here, “toward the upper surface 30a side in the Z direction” means that the normal vector of the side surface 75e includes a component in the Z direction, and the component faces the upper surface 30a side. The inclination angle of the side surface 75e with respect to the stacked end surface 30b is, for example, in a range larger than 0 degree and smaller than 90 degrees.

  By inclining the side surface 75e in this way, the metal film 72 can be made difficult to travel from the upper surface 75c to the side surface 75e when the metal film 72 is formed on the rear end surface 10a from the Y direction. That is, the metal film 72 can be made difficult to be formed from the upper surface 75 c to the side surface 75 e and the upper electrode 50. Thereby, the occurrence of a short circuit due to the contact between the metal film 72 and the upper electrode 50 can be suppressed. As a result, it is possible to suppress the occurrence of malfunction of the QCL 1A due to the occurrence of the short circuit.

  Note that the difference between the manufacturing method of the QCL 1A of this modification and the manufacturing method of the QCL 1 of the above-described embodiment is a step of etching the semiconductor layer 76 in the Z direction (see FIG. 6B). That is, in this method of manufacturing QCL 1A, wet etching capable of anisotropic etching is applied as etching in this step. Then, by appropriately selecting the crystal plane orientation and the etchant of the side surface 75e, the side surface 75e inclined with respect to the stacked end surface 30b is formed. The other steps are the same as those in the above embodiment, and a description thereof will be omitted.

(Second modification)
FIG. 13 is a cross-sectional view of a QCL 1B according to a second modification of the above embodiment. FIG. 13 shows a YZ cross section including the semiconductor stack 30 of QCL1B. The difference between this modified example and the above embodiment is the shape of the semiconductor insulating portion. That is, the semiconductor insulating portion 75B of this modification has a shape extending on the stacked end face 30b. Specifically, the semiconductor insulating portion 75 </ b> B extends to the semiconductor substrate 20. The side surface 75a of the semiconductor insulating portion 75B faces the stacked end surface 30b and the semiconductor substrate 20 in the Y direction, and covers all the stacked end surface 30b. The lower surface 75d is located on the semiconductor substrate 20. As described above, the semiconductor insulating portion 75B extends on the stacked end face 30b, whereby the electrical resistance in the vicinity of the rear end face 10a can be increased, and the leakage current flowing in the vicinity of the rear end face 10a can be reduced. As a result, the element characteristics of the QCL 1B can be improved (for example, the threshold current can be reduced). Further, since the thickness in the Z direction of the semiconductor insulating portion 75B is larger than the thickness in the Z direction of the semiconductor insulating portion 75 of the above embodiment, the breakdown of the insulating film 71 near the rear end face 10a can be further suppressed.

  Next, an example of a method for manufacturing QCL 1B according to this modification will be described below. FIG. 14A to FIG. 14C are diagrams showing a manufacturing process of the QCL 1B of FIG. Since the manufacturing method of the QCL 1B according to the present modification is the same as that of the above-described embodiment up to the step of forming the two current block portions 40 (see FIG. 5C), the description up to that step is omitted. However, in this modification, in the second crystal growth step, the crystal is grown on the diffraction grating layer 34 up to the contact layer 36, and the semiconductor layer 76 (see FIG. 4C) is not grown on the contact layer 36. Therefore, after the process of forming the two current block portions 40, the semiconductor layer 76 is not formed on the contact layer 36, and the contact layer 36 is positioned in the uppermost layer.

  Thereafter, as shown in FIG. 14A, a mask 84 is formed on the region 30c by a normal photolithography technique. The mask 84 is made of the same material as the mask 81. Thereafter, the semiconductor stack 30 is etched in the Z direction. At this time, as illustrated in FIG. 14B, the region covered with the mask 84 of the semiconductor stack 30 remains, and the region not covered with the mask 84 of the semiconductor stack 30 extends from the contact layer 36 to the semiconductor. Etching is performed up to the substrate 20. At this time, the stacked end face 30b is formed at the boundary between the region covered with the mask 84 of the semiconductor stack 30 and the region where the semiconductor stack 30 is etched. Next, as shown in FIG. 14C, the semiconductor insulating portion 75B is grown on the stacked end face 30b in the fourth crystal growth step with the mask 84 remaining. Subsequent steps (steps for forming the upper electrode 50 on the upper surface 30a) and subsequent steps are the same as those in the above embodiment, and thus the description thereof is omitted.

  FIG. 15 is a cross-sectional view of a QCL 1C according to another example of the present modification. FIG. 15 shows a YZ cross section including the semiconductor stack 30 of QCL1C. In QCL1C, the semiconductor insulating portion 75B is in direct contact with the metal film 72. That is, in the QCL 1C, the insulating film 71 is not provided on the stacked end face 30b. The side surface 75b of the semiconductor insulating portion 75B is entirely covered with the metal film 72. As described above, the insulating film 71 is not provided on the stacked end face 30b, and the semiconductor insulating portion 75B having high thermal conductivity is provided, so that the heat dissipation at the stacked end face 30b can be improved. As a result, the element characteristics and reliability of the QCL 1C can be improved. Further, the semiconductor insulating portion 75B can function as an insulating film. Note that when manufacturing such a QCL1C, the same steps as those for manufacturing the QCL1B are performed. However, in the manufacturing method of the QCL 1C, the step of forming the insulating film 71 on the end face 85a is omitted.

(Third Modification)
16 and 17 are cross-sectional views of the QCL 1D according to the third modification of the above embodiment. FIG. 16 shows an XZ cross section including the region 30 c of the semiconductor stack 30. FIG. 17 shows an XZ cross section including the region 30 d of the semiconductor stack 30. The difference between this modification and the above embodiment is the configuration of two current block portions and a semiconductor insulating portion. That is, the semiconductor insulating portion 75 and the two current block portions 40 of the QCL 1D of the present modification are made of the same material. Then, the semiconductor insulating portion 75 and the two current block portions 40 are grown together. Since the semiconductor insulating portion 75 protrudes on the opposite side of the semiconductor substrate 20 with respect to the upper electrode 50 in the Z direction, the current block portion 40 that is grown together with the semiconductor insulating portion 75 also has the upper electrode 50 in the Z direction. On the other hand, it protrudes on the opposite side to the semiconductor substrate 20.

  An example of a method for manufacturing the QCL 1D will be described below. 18 (a) to 18 (c) and FIGS. 19 (a) to 19 (c) are diagrams showing steps of manufacturing the QCL 1D of FIGS. FIG. 18A to FIG. 18C show a cross section of the QCL 1D in the same process. FIG. 19A to FIG. 19C show a cross section of the QCL 1D in the same step after the steps of FIG. 18A to FIG. 18C. FIGS. 18A and 19A show YZ cross sections including the semiconductor stack 30 of QCL1D. 18B shows an XZ cross section along the line XVIIIb-XVIIIb in FIG. 18A, and FIG. 18C shows the XZ line along the line XVIIIc-XVIIIc in FIG. 18A. A cross section is shown. FIG. 19B shows an XZ cross section along the line XIXb-XIXb in FIG. 19A, and FIG. 19C shows the XZ line along the XIXc-XIXc line in FIG. A cross section is shown.

  The manufacturing method of the QCL 1D according to the present modification is the same as that of the above-described embodiment up to the step of forming the mesa-shaped semiconductor stack 30 (see FIG. 5B), and thus the description up to that step is omitted. However, in this modification, in the second crystal growth step, the crystal is grown up to the contact layer 36 on the diffraction grating layer 34, and the semiconductor layer 76 is not grown on the contact layer 36. Therefore, after the process of forming the mesa-shaped semiconductor stack 30, the semiconductor layer 76 is not formed on the contact layer 36, and the contact layer 36 is positioned at the uppermost layer.

  After the step of forming the mesa semiconductor stack 30, the mask 81 is removed, and the mask 86 is formed on the upper surface 30 a of the mesa semiconductor stack 30 as shown in FIGS. 18A and 18B. Form. As shown in FIGS. 18A to 18C, the mask 86 covers only the region 30c and does not cover the region 30d. The mask 86 is made of the same material as the mask 81 of the above embodiment. Next, as shown in FIGS. 19A to 19C, the two current block portions 40 are crystal-grown on both side surfaces of the semiconductor stack 30, and the semiconductor insulating portion 75 is crystal-grown on the region 30d. Let At this time, the two current block portions 40 and the semiconductor insulating portion 75 do not grow on the mask 86. In this way, the two current block portions 40 and the semiconductor insulating portion 75 are collectively formed. Thereafter, the mask 86 is removed. Subsequent steps (steps for forming the upper electrode 50 on the region 30c) and subsequent steps are the same as those in the above embodiment, and thus description thereof is omitted.

  In this way, the semiconductor insulating portion 75 and the two current block portions 40 are grown together, thereby simplifying the manufacturing process of the QCL 1D. That is, the QCL 1D can be easily manufactured. As a result, the productivity of QCL1D can be improved. Further, since the semiconductor insulating portion 75 and the current block portion 40 are single crystals that are collectively formed from the same material, defects are unlikely to occur at the interface between the semiconductor insulating portion 75 and the current block portion 40. Therefore, it is possible to suppress deterioration in the element characteristics and reliability of the QCL 1D due to this defect. Also in QCL1D, the same effects as in the above embodiment can be obtained.

(Fourth modification)
20 and 21 are cross-sectional views of the QCL 1E according to the fourth modification. 20 shows an XZ cross section including the semiconductor stack 30, and FIG. 21 shows an XZ cross section including the semiconductor insulating portion 75B. The difference between this modification and the above embodiment is the configuration of two current block portions and a semiconductor insulating portion. That is, the QCL 1E of the present modification includes the semiconductor insulating portion 75B of the second modified example, and the semiconductor insulating portion 75B and the two current block portions 40 are made of the same material. Then, the semiconductor insulating portion 75B and the two current block portions 40 are grown together. Since the semiconductor insulating portion 75B protrudes to the opposite side of the semiconductor substrate 20 with respect to the upper electrode 50 in the Z direction, the current block portion 40 that is grown together with the semiconductor insulating portion 75B also has the upper electrode 50 in the Z direction. On the other hand, it protrudes on the opposite side to the semiconductor substrate 20.

  An example of a method for manufacturing this QCL1E will be described below. 22 (a) to 22 (c), FIG. 23 (a) to FIG. 23 (c), and FIG. 24 (a) to FIG. 24 (c) show the manufacturing steps of the QCL1E of FIG. 20 and FIG. FIG. FIG. 22A to FIG. 22C show a cross section of the QCL 1E in the same process. FIG. 23A to FIG. 23C show a cross section of the QCL 1E in the same step after the steps of FIG. 22A to FIG. 22C. FIGS. 24A to 24C show a cross section of the QCL 1E in the same step after the steps of FIGS. 23A to 23C. FIG. 22A, FIG. 23A, and FIG. 24A show YZ cross sections including the semiconductor stack 30 of QCL1E. FIG. 22B shows an XZ cross section along the line XXIIb-XXIIb in FIG. 22A, and FIG. 22C shows the XZ line along the line XXIIc-XXIIc in FIG. A cross section is shown. FIG. 23B shows an XZ cross section along line XXIIIb-XXIIIb in FIG. 23A, and FIG. 23C shows XZ along line XXIIIc-XXIIIc in FIG. A cross section is shown. FIG. 24B shows an XZ cross section along the line XXIVb-XXIVb in FIG. 24A, and FIG. 24C shows the XZ line along the line XXIVc-XXIVc in FIG. A cross section is shown.

  Since the manufacturing method of QCL1E according to this modification is the same as that of the above-described embodiment up to the second crystal growth step (see FIG. 4C), the description up to that step is omitted. However, in this modification, in the second crystal growth step, the crystal is grown up to the contact layer 36 on the diffraction grating layer 34, and the semiconductor layer 76 is not grown on the contact layer 36. Therefore, after the second crystal growth step, the semiconductor layer 76 is not formed on the contact layer 36, and the contact layer 36 is positioned at the uppermost layer.

  Thereafter, as shown in FIGS. 22A to 22C, a mask 86 is formed on the upper surface 30a. The mask 86 covers only the region 30c and does not cover the region 30d. Next, as shown in FIGS. 23A to 23C, using this mask 86, the contact layer 36, the upper cladding layer 35, the diffraction grating layer 34, the core layer 33, the buffer layer 32, and Etching is performed on the semiconductor substrate 20 in the Z direction. As a result, as shown in FIG. 23B, a mesa-shaped semiconductor stack 30 is formed. At this time, as shown in FIG. 23A, the stacked end face 30 b is formed at the boundary between the region covered with the mask 86 of the semiconductor stack 30 and the region where the semiconductor stack 30 is etched. .

  Next, as shown in FIGS. 24A to 24C, the two current blocking portions 40 are crystal-grown on both side surfaces of the semiconductor stacked layer 30, and the semiconductor insulating portion 75B is crystallized on the stacked end surface 30b. Grow. At this time, the two current block portions 40 and the semiconductor insulating portion 75 </ b> B are not grown on the mask 86. In this way, the two current block portions 40 and the semiconductor insulating portion 75B are collectively formed. Thereafter, the mask 86 is removed. Subsequent steps (steps for forming the upper electrode 50 on the upper surface 30a) and subsequent steps are the same as those in the above embodiment, and thus the description thereof is omitted. Thus, also when growing the semiconductor insulation part 75B and the two current block parts 40 in a lump, the same effect as the QCL1D of the third modification can be obtained.

The quantum cascade laser of the present invention is not limited to the above-described embodiment, and various other modifications are possible. For example, the above-described embodiments and modifications may be combined with each other according to the necessary purpose and effect. In the above-described embodiments and modifications, the semiconductor insulating portion and the metal film are provided only on the rear end surface side in the Y direction of the semiconductor element portion. However, the semiconductor insulating portion and the metal film are It may be provided only on the front end face side, or may be provided on both the front end face and the rear end face of the semiconductor element portion. In the above-described embodiments and modifications, the QCL has a buried heterostructure. However, for example, a high mesa in which an insulating film (for example, a dielectric film such as SiO ₂ ) is formed on both side surfaces of the semiconductor stack 30. You may have other arbitrary structures, such as a structure. In the above-described embodiments and modifications, the DFB-type QCL having the diffraction grating layer 34 has been described. However, the present invention is not limited to this. That is, the above-described embodiment and each modification can be similarly applied to, for example, a Fabry-Perot (FP) type QCL that does not include the diffraction grating layer 34. This FP type QCL can provide the same improvement as the DFB type QCL. In the above-described embodiments and modifications, the upper electrode is a cathode electrode and the lower electrode is an anode electrode, but the upper electrode is an anode electrode and the lower electrode is a cathode electrode. In this case as well, the same effects as those of the above-described embodiment and each modification can be obtained.

  DESCRIPTION OF SYMBOLS 1,1A, 1B, 1C, 1D, 1E ... Quantum cascade semiconductor laser, 2 ... Carrier, 3 ... Submount, 4 ... Solder, 5 ... Wire, 10 ... Semiconductor element part, 10a ... Rear end surface, 10b ... Front end surface, DESCRIPTION OF SYMBOLS 20 ... Semiconductor substrate, 20a ... Main surface, 20b ... Back surface, 20c ... Substrate end surface, 30c, 30d ... Area, 30 ... Semiconductor laminated layer, 30a, 75c ... Upper surface, 30b ... Stacked end surface, 32 ... Buffer layer, 33 ... Core layer 34 ... Diffraction grating layer, 34a ... Diffraction grating, 35 ... Upper cladding layer, 36 ... Contact layer, 40 ... Current blocking part, 50 ... Upper electrode, 60 ... Lower electrode, 71 ... Insulating film, 72 ... Metal film, 75 75A, 75B... Semiconductor insulating portions, 75a, 75b... Side surfaces, 75d.

Claims (12)

A semiconductor substrate having a main surface and a back surface facing each other in a first direction, and a substrate end surface intersecting a second direction orthogonal to the first direction;
A first surface provided on a side opposite to the main surface in the first direction; a laminated end face included in a plane including the substrate end face; a core layer extending from the laminated end face along the second direction; and the core A semiconductor layer having a cladding layer provided on the layer and provided on the main surface;
A first electrode provided on the first surface;
A second electrode provided on the back surface;
A metal film provided on the laminated end face and the substrate end face;
A semiconductor insulating portion having a second surface intersecting the first direction, provided between the first electrode and the metal film in the second direction, and including an undoped or semi-insulating semiconductor;
With
The metal film is provided from the stacked end surface to the second surface,
The quantum cascade laser, wherein the second surface is provided at a position higher than the first surface with respect to the main surface in the first direction. The first surface includes a first region and a second region located between the stacked end surface and the first region in the second direction,
The first electrode is provided on the first region,
The quantum cascade laser according to claim 1, wherein the semiconductor insulating portion is provided on the second region. The semiconductor insulating portion has a side surface facing the first electrode in the second direction;
3. The quantum cascade laser according to claim 2, wherein the side surface is inclined with respect to the stacked end surface so as to face the first surface side in the first direction.   The quantum cascade laser according to claim 1, wherein the semiconductor insulating portion extends on the stacked end face.   The quantum cascade laser according to claim 4, wherein the semiconductor insulating portion is in contact with the metal film.   The quantum cascade laser according to claim 1, further comprising an insulating film provided between the stacked end face and the metal film. The quantum cascade laser according to claim 6, wherein the insulating film includes at least one of SiO ₂ , SiON, SiN, alumina, BCB resin, and polyimide resin. Further comprising two current blocking portions comprising an undoped or semi-insulating semiconductor;
The semiconductor laminate has both side surfaces facing each other in a third direction orthogonal to the first direction and the second direction, and has a mesa shape extending in the second direction;
8. The quantum cascade laser according to claim 1, wherein the two current blocking portions are embedded in both side surfaces, and are made of the same material as the semiconductor insulating portion.   The quantum cascade laser according to any one of claims 1 to 8, wherein the semiconductor insulating portion includes a semi-insulating semiconductor doped with at least one transition metal of Fe, Ti, Cr, and Co. .   The quantum cascade laser according to claim 1, wherein the metal film contains Au.   The quantum cascade laser according to claim 1, wherein the cladding layer is an InP layer.   The quantum cascade laser according to claim 1, wherein the semiconductor substrate is an InP substrate.

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