JP2019009347A - Quantum cascade semiconductor laser - Google Patents

Abstract

To suppress destruction of an insulation film in a quantum cascade semiconductor laser including the insulation film and metal film sequentially laminated on an end surface constituting a laser resonator.SOLUTION: A QCL 1 comprises: a semiconductor substrate 20 including a principal surface 20a, a rear surface 20b, and a substrate end surface 20c; a semiconductor laminate 30 including an upper surface 30a and a laminate end surface 30b and provided on the principal surface 20a; an upper electrode 50 provided on the upper surface 30a; an insulation film 71 provided on the laminate end surface 30b and the substrate end surface 20c, and extending over the upper electrode 50; a metal film 72 provided on the laminate end surface 30b and the substrate end surface 20c via the insulation film 71, and extending over the upper electrode 50; and an insulation film 75 including a portion provided between the upper electrode 50 and the metal film 72 in an X direction. The thickness in a Z direction of the insulation film 75 is thicker than the thickness in the Z direction of the insulation film 75 provided on the upper electrode 50.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a quantum cascade laser.

A quantum cascade laser (QCL) disclosed in Non-Patent Document 1 has a configuration in which a lower electrode, a semiconductor substrate, a semiconductor stack, and an upper electrode are sequentially stacked. A metal film is provided on an end surface of the QCL laser resonator via an insulating film. SiO ₂ is used for the insulating film, and Au is used for the metal film. The QCL is mounted on the electronic component via solder.

S.R.Darvish, et al. “High-power, continuous-wave operation of distributed-feedback quantum-cascade lasers at λ〜7.8μm”, Applied Physics Letters 89, 251119, 2006.

  Some QCLs have a structure in which a lower electrode, a semiconductor substrate, a semiconductor stack, and an upper electrode are sequentially stacked. A metal film may be formed on the end face constituting such a QCL laser resonator as a reflection film in order to increase the reflectance of the laser beam at the end face. However, when the metal film is formed directly on the end face, the respective layers of the semiconductor element portion may be short-circuited (short-circuited) on the end face, which may cause a QCL malfunction. Therefore, it is desirable to provide an insulating film as a base layer between the end face and the metal film (see, for example, Non-Patent Document 1). The insulating film and the metal film are sequentially formed on the end surface from the side facing the end surface. At this time, the insulating film and the metal film are often formed on the upper electrode and the lower electrode by wrapping around the upper electrode and the lower electrode. When the QCL on which the insulating film and the metal film are formed in this way is mounted on an electronic component via, for example, solder, the metal film on the lower electrode comes into contact with the solder. When a voltage (for example, a high voltage of 10 V or more) is applied between the upper electrode and the lower electrode for laser oscillation in a state where the metal film is in contact with the solder as described above, the voltage applied to the lower electrode is reduced. And applied to the metal film via solder. As a result, an equivalent voltage is applied between the metal film on the upper electrode and the upper electrode via the insulating film.

  However, since the thickness of the insulating film on the upper electrode formed by wraparound tends to be extremely thin (for example, about a fraction of the thickness) of the insulating film on the end surface, such an extremely thin insulating film When a high voltage of, for example, 10 V or more is applied between the metal film on the upper electrode and the upper electrode through the insulating film, the insulating film between them may be destroyed. As a result, a large current (so-called rush current) flows near the end face via the broken portion of the insulating film, and there is a possibility that a failure such as end face breakage may occur in the QCL.

  In addition, when it is going to increase the thickness of the insulating film on the upper electrode formed by wraparound, it is necessary to further increase the thickness of the insulating film on the end face (for example, about several times). In this case, since the time for forming the insulating film on the end face increases (for example, several times), the QCL productivity decreases. In addition, when such an extremely thick insulating film is formed on the end face, the end face deteriorates due to an increase in stress generated in the insulating film, the crack of the insulating film, the end face of the insulating film There is a risk of peeling.

  The present invention has been made in view of such a problem, and suppresses the breakdown of the insulating film in the quantum cascade laser having the insulating film and the metal film sequentially stacked on the end face constituting the laser resonator. For the purpose.

  The quantum cascade laser according to the present invention includes a semiconductor substrate having a main surface and a back surface facing each other in the first direction, a substrate end surface intersecting with a second direction orthogonal to the first direction, and a main surface in the first direction. Provided on the main surface having a surface provided on the opposite side, a laminated end face included in a plane including the substrate end face, a core layer extending from the laminated end face along the second direction, and a clad layer provided on the core layer A semiconductor stack, a first electrode provided on the front surface, a second electrode provided on the back surface, a first insulating film provided on the stack end face and the substrate end face, and extending over the first electrode; A metal film provided on the stacked end face and the substrate end face through the insulating film, extending over the first electrode, and provided on the first electrode, and provided between the first electrode and the metal film in the first direction. Including part Comprising a second insulating film, a thickness of the first direction of the second insulating film is thicker than the first direction of the thickness of the first insulating film provided on the first electrode.

  According to the present invention, in a quantum cascade laser having an insulating film and a metal film that are sequentially stacked on an end face constituting a laser resonator, the breakdown of the insulating film can be suppressed.

FIG. 1 is a perspective view showing a state in which a quantum cascade laser according to an embodiment is mounted. FIG. 2 is a perspective view of the quantum cascade laser of FIG. FIG. 3 is a cross-sectional view taken along line III-III in FIG. FIG. 4A to FIG. 4C are diagrams showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 5A to FIG. 5C are diagrams showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 6A to FIG. 6C are diagrams showing manufacturing steps of the quantum cascade laser shown in FIG. FIG. 7 is a diagram showing a manufacturing process of the quantum cascade laser shown in FIG. FIGS. 8A and 8B are diagrams showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 9 is a diagram showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 10 is a perspective view of a quantum cascade laser as a comparative example. 11 is a cross-sectional view taken along line XI-XI in FIG. FIG. 12 is a cross-sectional view of a quantum cascade laser according to a first modification. FIG. 13A and FIG. 13B are diagrams showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 14 is a cross-sectional view of a quantum cascade laser according to another example of the first modification. FIG. 15A and FIG. 15B are diagrams showing a manufacturing process of the quantum cascade laser shown in FIG. FIG. 16 is a cross-sectional view of a quantum cascade laser according to a second modification. FIG. 17A to FIG. 17C are diagrams showing a manufacturing process of the quantum cascade laser shown in FIG.

[Description of Embodiment of the Present Invention]
First, the contents of the embodiment of the present invention will be listed and described. A quantum cascade laser according to an embodiment of the present invention includes a semiconductor substrate having a main surface and a back surface that face each other in a first direction, a substrate end surface that intersects a second direction orthogonal to the first direction, and a first direction. A surface provided on the opposite side of the main surface, a laminated end surface included in a plane including the substrate end surface, a core layer extending from the laminated end surface along the second direction, and a clad layer provided on the core layer, A semiconductor stack provided on the surface, a first electrode provided on the front surface, a second electrode provided on the back surface, a first insulating film provided on the stack end surface and the substrate end surface and extending over the first electrode And a metal film provided on the stacked end face and the substrate end face via the first insulating film, extending over the first electrode, and provided on the first electrode, and the first electrode and the metal film in the first direction. Between And a second insulating film including a portion, the thickness of the first direction of the second insulating film is thicker than the first direction of the thickness of the first insulating film provided on the first electrode.

  In the quantum cascade laser described above, the second insulating film is provided between the first electrode and the metal film in the first direction. In addition, the thickness of the second insulating film is the thickness of the first insulating film. Therefore, it is possible to secure a sufficient insulating region between the first electrode and the metal film (that is, a region including the first insulating film and the second insulating film). That is, the insulation resistance between the first electrode and the metal film can be increased. Therefore, according to the quantum cascade laser described above, even if the voltage is applied between the metal film on the first electrode and the first electrode, the breakdown of the insulating film due to the voltage can be suppressed. As a result, it is possible to suppress the above-described deterioration of the device characteristics of the quantum cascade laser due to end face breakdown caused by the breakdown of the insulating film.

  In the quantum cascade laser described above, the surface includes a first region and a first region provided on the second region, including a second region located between the stacked end face and the first region in the second direction. The thickness of the electrode may be smaller than the thickness of the first electrode provided on the first region. Thus, by reducing the thickness of the laminated end face serving as a cleavage plane and the first electrode in the vicinity of the substrate end face, it is possible to easily cleave the laminated end face and the substrate end face. As a result, it is possible to increase the yield when manufacturing the quantum cascade laser. In addition, since the thickness of the first electrode provided on the second region is thinner than the thickness of the first electrode provided on the first region, the electrical resistance of the first electrode provided on the first region is smaller. The electric resistance of the first electrode provided on the second region is larger. Thereby, the leak current flowing in the vicinity of the laminated end face and the substrate end face can be reduced. As a result, the device characteristics of the quantum cascade laser described above can be improved (for example, the threshold current can be reduced). In the quantum cascade laser described above, the first electrode may be provided only on the first region. As described above, by preventing the first electrode from being provided in the vicinity of the laminated end surface and the substrate end surface serving as a cleavage plane, the above-described effect can be more remarkably exhibited.

  In the above-described quantum cascade laser, the back surface includes a third region and a fourth region located between the substrate end surface and the third region in the second direction, and is provided on the fourth region. The thickness of the electrode may be smaller than the thickness of the second electrode provided on the third region. Thus, by reducing the thickness of the laminated end face serving as a cleavage plane and the second electrode in the vicinity of the substrate end face, it is possible to easily cleave the laminated end face and the substrate end face. As a result, it is possible to increase the yield when manufacturing the above-described quantum cascade laser. Further, since the thickness of the second electrode in the fourth region is thinner than the thickness of the second electrode in the third region, the electric resistance of the second electrode in the fourth region is smaller than the electric resistance of the second electrode in the third region. Resistance is greater. Thereby, the leak current flowing in the vicinity of the laminated end face and the substrate end face can be reduced. As a result, the device characteristics of the quantum cascade laser described above can be improved (for example, the threshold current can be reduced). In the quantum cascade laser described above, the second electrode may be provided only on the third region. As described above, by preventing the second electrode from being provided in the vicinity of the laminated end surface and the substrate end surface serving as a cleavage plane, the above-described effect can be more remarkably exhibited.

  In the quantum cascade laser described above, the second insulating film includes a fifth region and a sixth region located between the fifth region and the plane including the stacked end surface in the second direction. The thickness of the region in the first direction may be greater than the thickness of the sixth region in the first direction. Thereby, a stepped portion that intersects the second direction is formed at the boundary between the fifth region and the sixth region. As a result, when the metal film is formed on the end face of the stack, the metal particles constituting the metal film are easily rebounded by the stepped portion. Therefore, it becomes difficult for the metal film to wrap around from the second insulating film onto the first electrode. Thereby, the short circuit by the contact with a metal film and a 1st electrode can be suppressed. As a result, the above-described malfunction of the quantum cascade laser due to the occurrence of the short circuit can be suppressed.

In the quantum cascade laser described above, at least one of the first insulating film and the second insulating film may include at least one of SiO ₂ , SiON, SiN, alumina, BCB resin, or polyimide resin. These have excellent durability and insulating properties as protective films for the laminated end face and the substrate end face. Further, they are easily formed on the laminated end face and the substrate end face by using a general dielectric film forming method such as sputtering, CVD, or spin coating. That is, an insulating film forming process can be easily introduced into the above-described quantum cascade laser manufacturing process.

  In the quantum cascade laser described above, the metal film may contain Au. Thereby, the metal film can be effectively functioned as a reflective film having a high reflectance exceeding 90%, for example, on the laminated end face and the substrate end face.

  In the quantum cascade laser described above, the cladding layer may be an InP layer. Since InP is transparent to the oscillation light in the mid-infrared region (not showing light absorption), it is suitable as a material for the cladding layer. Further, since InP is a binary mixed crystal and lattice-matched to the InP substrate, the InP layer can be favorably grown on the InP substrate. Further, since the thermal conductivity of InP is good, heat from the core layer can be released well through the cladding layer. Thereby, the temperature characteristic of the quantum cascade laser described above can be improved.

  In the quantum cascade laser described above, the core layer includes a plurality of active layers that are light emitting regions and a plurality of injection layers for injecting carriers into the active layer. They may be arranged alternately along the direction. By providing the injection layer between the active layers in this manner, electrons are continuously and smoothly delivered to the adjacent active layers, and light emission is efficiently achieved by the transition of electrons between subbands in the conduction band in the active layer. It can be generated well. As a result, the oscillation characteristics of the quantum cascade laser described above can be improved.

  In the quantum cascade laser described above, the active layer and the injection layer may include a GaInAs / AlInAs superlattice array. This superlattice array can provide transitions between subbands of electrons in the conduction band in the active layer, corresponding to wavelengths in the mid-infrared region (eg, 3-20 μm). Therefore, it is suitable as a material for the core layer of a quantum cascade laser capable of oscillating light in the mid-infrared region.

  In the quantum cascade laser described above, the semiconductor substrate may be an InP substrate. The semiconductor stack constituting the quantum cascade laser in the mid-infrared region has a lattice constant close to InP. Therefore, when the semiconductor substrate is an InP substrate, the semiconductor stack can be grown on the semiconductor substrate with good crystal quality. Further, since InP is transparent to light in the mid-infrared region, the InP substrate can function as a cladding layer for the core layer.

[Details of the embodiment of the present invention]
A specific example of the quantum cascade laser according to the embodiment of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to the claim are included. In the following description, the same reference numerals are given to the same elements in the description of the drawings, and redundant descriptions are omitted.

(Embodiment)
FIG. 1 is a perspective view showing a state in which a quantum cascade laser (QCL) 1 according to an embodiment is mounted. In FIG. 1, an XYZ orthogonal coordinate system is shown for easy understanding. QCL1 is a distributed feedback (DFB) type element that oscillates single-mode light, and can oscillate in the mid-infrared region of 3 μm to 20 μm, for example. As shown in FIG. 1, the QCL 1 is mounted on the submount 3 mounted on the carrier 2 via the solder 4. Specifically, the QCL 1 is die-bonded on the submount 3 using the solder 4 in an epi-up form (a form in which the epitaxially grown side is placed on the upper surface). A lower electrode (described later) of the QCL 1 is electrically connected to the carrier 2 via the submount 3 and the solder 4. Further, one end of a wire 5 for supplying power to the QCL 1 is connected to an upper electrode (to be described later) of the QCL 1. The other end of the wire 5 is connected to a bonding pad (not shown). The upper electrode of the QCL 1 is electrically connected to the bonding pad via the wire 5. The carrier 2 and the bonding pad are electrically connected to an external power source (not shown). Then, by applying a predetermined voltage from the external power source to the upper electrode and the lower electrode of QCL1, QCL1 is turned on, current flows in QCL1, and QCL1 laser oscillates.

  The lengths W1 and L1 in the X direction and the Y direction of the carrier 2 are, for example, 4 mm to 8 mm, respectively, and the thickness H1 of the carrier 2 in the Z direction is, for example, 1 mm to 8 mm. The lengths W2 and L2 of the submount 3 in the X direction and the Y direction are, for example, 1 mm to 4 mm and 2 mm to 4 mm, respectively, and the thickness H2 of the submount 3 in the Z direction is, for example, 0.1 mm to 0.5 mm. is there. The submount 3 is made of, for example, AIN or CuW, and the carrier 2 is made of, for example, Cu or CuW. For example, AuSn, In, or silver paste is used for the solder 4, and Au wire or the like is used for the wire 5.

  FIG. 2 is a perspective view of the QCL 1 in FIG. 3 is a YZ sectional view taken along line III-III in FIG. As shown in FIGS. 2 and 3, the QCL 1 includes a semiconductor element portion 10, an insulating film (first insulating film) 71, a metal film 72, and an insulating film 75 (second insulating film). The semiconductor element unit 10 has a buried heterostructure (BH) current confinement structure. The semiconductor element portion 10 has a rectangular parallelepiped shape with the resonance direction (Y direction) as a longitudinal direction. The length L3 in the Y direction of the semiconductor element portion 10 is, for example, 1 mm to 3 mm, the length W3 in the X direction of the semiconductor element portion 10 is, for example, 400 μm to 800 μm, and the length in the Z direction of the semiconductor element portion 10 is The length (thickness) H3 is, for example, 100 μm to 200 μm. The semiconductor element portion 10 has a rear end face 10a and a front end face 10b that face each other in the Y direction. The semiconductor element unit 10 includes a semiconductor substrate 20, a semiconductor stack 30, two current block units 40, an upper electrode (first electrode) 50, and a lower electrode (second electrode) 60.

  As shown in FIG. 3, the semiconductor substrate 20 is mounted on the submount 3 via the solder 4. The semiconductor substrate 20 is, for example, an n-type InP substrate. The semiconductor substrate 20 has conductivity in order to apply a voltage to the upper electrode 50 and the lower electrode 60 to supply a current to the semiconductor stack 30. In QCL1, since electrons are used as carriers, the conductivity type of the semiconductor substrate 20 is usually n-type. The semiconductor substrate 20 functions as a lower cladding layer for the core layer 33. The semiconductor substrate 20 may not function as a lower cladding layer. In that case, a lower cladding layer is provided between the semiconductor substrate 20 and the core layer 33. The semiconductor substrate 20 includes a main surface 20a, a back surface 20b, and a substrate end surface 20c. The main surface 20a and the back surface 20b oppose each other in the thickness direction (Z direction which is the first direction). The back surface 20b is disposed on the submount 3 side in the Z direction of the semiconductor substrate 20 with respect to the main surface 20a. In one example, the distance between the main surface 20a and the back surface 20b in the Z direction (that is, the thickness of the semiconductor substrate 20 in the Z direction) is 100 nm. The substrate end surface 20c intersects the Y direction (second direction) and connects the main surface 20a and the back surface 20b. The substrate end surface 20c is included in the rear end surface 10a.

  The semiconductor stack 30 is provided on the main surface 20 a of the semiconductor substrate 20. The semiconductor stacked layer 30 includes an upper surface (surface) 30a that intersects the Z direction and a stacked end surface 30b that intersects the Y direction. The upper surface 30a is provided on the side opposite to the main surface 20a in the Z direction. The stacked end surface 30b is included in a plane including the substrate end surface 20c. That is, the laminated end surface 30b is included in the rear end surface 10a including the substrate end surface 20c. In addition, the semiconductor stack 30 has a mesa shape. That is, the semiconductor stack 30 has a stripe shape having a predetermined width WM in the X direction and extending along the Y direction, and is located at the center of the QCL 1 in the X direction. The semiconductor stack 30 includes both end faces facing each other in the Y direction and both side faces facing each other in the X direction. Both end faces of the semiconductor stack 30 are mirrors for constituting a QCL1 laser resonator. One end face of the both end faces is included in the laminated end face 30b. The semiconductor stack 30 includes a buffer layer 32, a core layer 33, a diffraction grating layer 34, an upper clad layer 35, and a contact layer 36, which are sequentially stacked on the semiconductor substrate 20.

  The buffer layer 32 and the upper cladding layer 35 are, for example, n-type InP layers. The buffer layer 32 functions as a lower clad layer for the core layer 33 together with the semiconductor substrate 20. The upper cladding layer 35 is provided on the core layer 33 via the diffraction grating layer 34. Note that the buffer layer 32 may not be provided in the semiconductor stack 30. In this case, the core layer 33 is provided on the main surface 20 a of the semiconductor substrate 20. The core layer 33 extends along the Y direction from the stacked end surface 30b. The core layer 33 has a plurality of unit structures. The plurality of unit structures are arranged side by side in the stacking direction (Z direction), and adjacent unit structures are in contact with each other. The number of unit structures is several tens, for example. Each unit structure forms a superlattice array in which quantum well layers (several nm thick) and barrier layers (several nm thick) are alternately stacked along the Z direction. GaInAs or GaInAsP is often used for the quantum well layer, and AlInAs is often used for the barrier layer. Each unit structure includes one active layer and one injection layer. The active layer is a light emitting region. The injection layer is provided to inject carriers into the active layer. In one example, the active layer and the injection layer are stacked together along the Z direction to form a GaInAs / AlInAs superlattice array.

  Here, the light emission principle of QCL1 will be briefly described. In QCL1, only electrons are used as carriers, and light emission occurs when electrons transition between subbands in the conduction band in the active layer. The light generated by the light emission is amplified in the laser resonator of QCL1, whereby QCL1 oscillates laser light in the mid-infrared region. Specifically, in QCL1, the following three-level laser operation is realized in the conduction band in the active layer. First, electrons are injected from the injection layer to the upper level of the active layer by tunneling. The electrons transit from the upper level to the lower level of the active layer. At this time, light having a wavelength corresponding to the transition energy (energy difference between subbands between the upper level and the lower level) is emitted according to the transition. The electrons that have transitioned to the lower level do not emit light to the ground level with a short relaxation time due to LO phonon scattering. The above-described electron behavior is caused by the fact that the energy difference between the lower level and the ground level is designed to be the LO phonon energy in order to resonantly generate LO phonon scattering. . In this way, the electrons do not emit light to the ground level with a short relaxation time, so that an inversion distribution is realized between the upper level and the lower level in the active layer. The electrons relaxed to the ground level move to the upper level of the next injection layer by a predetermined electric field. Thereafter, the same operation is repeated over several tens of cycles, for example, to obtain a gain necessary for laser oscillation of QCL1. Here, by appropriately selecting the material composition of the quantum well layer and the barrier layer, and the film thicknesses of these layers, and adjusting the energy difference between the upper level and the lower level as appropriate, for example, between 3 μm and 20 μm QCL1 capable of oscillation in the infrared region is realized.

  As shown in FIG. 3, the diffraction grating layer 34 is formed with a diffraction grating 34a composed of a concavo-convex pattern in which concave and convex portions are alternately and repeatedly arranged with a period Λ along the Y direction. The diffraction grating 34a is formed by patterning a resist on the diffraction grating layer 34 serving as a convex portion at intervals of a period Λ and then periodically etching a part of the diffraction grating layer 34 serving as a concave portion in the Z direction. Is done. The period Λ is set as appropriate, and only the light with the Bragg wavelength corresponding to the period Λ is selectively reflected by the diffraction grating and amplified in the laser resonator. As a result, the QCL 1 oscillates a single mode laser beam only with this Bragg wavelength. The performance of the diffraction grating layer 34 is expressed by a coupling coefficient indicating the magnitude of coupling between the forward guided light and the backward guided light in the laser resonator. In order for the QCL 1 to oscillate a single mode laser beam satisfactorily, it is desirable to use a diffraction grating 34a that provides a large coupling coefficient. Therefore, as the material of the diffraction grating layer 34, a high refractive index semiconductor that is advantageous for realizing a large coupling coefficient is used. In one example, the diffraction grating layer 34 is made of, for example, undoped or n-type GaInAs.

  The contact layer 36 realizes a good ohmic contact with the upper electrode 50. The contact layer 36 preferably includes a material having a small band gap and lattice-matching with the semiconductor substrate 20 in order to realize a good ohmic contact. The contact layer 36 is, for example, n-type GaInAs. Note that when a good ohmic contact can be realized between the upper cladding layer 35 and the upper electrode 50, the contact layer 36 may not be provided in the semiconductor stack 30.

The two current block portions 40 shown in FIG. 2 function as current confinement layers for confining current (carriers) in the semiconductor stack 30. The two current block portions 40 embed both side surfaces of the semiconductor stack 30. In other words, the two current block portions 40 are respectively disposed on both side surfaces of the semiconductor stack 30 on the main surface 20 a of the semiconductor substrate 20. For each current block 40, an undoped or semi-insulating semiconductor is used. Since these semiconductors have high electric resistance with respect to electrons as carriers, they are suitable as materials for the current block portion 40. Semi-insulating semiconductors are realized by adding (doping) transition metals such as Fe, Ti, Cr, and Co to III-V compound semiconductors to form deep levels in the forbidden band that trap electrons. Is done. The III-V compound semiconductor to which the transition metal is added has a sufficiently high electric resistance characteristic of 10 ⁵ Ωcm or more with respect to electrons. Fe is suitable as the transition metal. Note that when the undoped semiconductor has a sufficiently high electrical resistance to electrons, the undoped semiconductor may be applied to the current block unit 40. Examples of the undoped or semi-insulating III-V compound semiconductor include InP, GaInAs, AlInAs, GaInAsP, and AlGaInAs. These semiconductors are lattice-matched with the semiconductor substrate 20 and are grown using a general growth method such as molecular beam epitaxy (MBE) and metal organic vapor phase epitaxy (OMVPE).

  The upper electrode 50 and the lower electrode 60 are provided to supply current to the core layer 33. For the upper electrode 50 and the lower electrode 60, for example, Ti / Au, Ti / Pt / Au, or Au / Ge is used. The upper electrode 50 is, for example, a cathode electrode. The upper electrode 50 is provided on the upper surface 30 a (specifically, on the contact layer 36) and the current block unit 40 of the semiconductor stack 30. The lower electrode 60 is an anode electrode, for example. The lower electrode 60 is provided between the back surface 20 b of the semiconductor substrate 20 and the solder 4. The lower electrode 60 is at a positive potential with respect to the upper electrode 50.

  An optical confinement layer may be provided between the core layer 33 and the semiconductor substrate 20 and between the core layer 33 and the upper cladding layer 35. The band gap of the optical confinement layer is smaller than the band gap of the semiconductor substrate 20 and the upper cladding layer 35 and larger than the band gap of the core layer 33. Thereby, electrons injected from the buffer layer 32 are efficiently injected into the core layer 33 without being blocked by the optical confinement layer. When the above-described band gap magnitude relationship is satisfied, the refractive index of the optical confinement layer is larger than that of the semiconductor substrate 20 and the upper cladding layer 35 and smaller than that of the core layer 33. Therefore, the semiconductor substrate 20 and the upper cladding layer 35 function to confine light generated in the core layer 33 in the core layer 33 and the optical confinement layer, and as a result, confinement of light in the core layer 33 is enhanced. The optical confinement layer has a higher refractive index than the semiconductor substrate 20 and the upper cladding layer 35 and can be lattice-matched to the semiconductor substrate 20 in order to enhance the confinement of guided light in the core layer 33. It is desirable to consist of materials. For example, undoped or n-type GaInAs is used for the optical confinement layer.

The insulating film 71 is provided on the rear end face 10 a side in the Y direction of the semiconductor element unit 10. Specifically, the insulating film 71 is provided on the stacked end face 30 b and the substrate end face 20 c and extends over the upper electrode 50 and the lower electrode 60. More specifically, the insulating film 71 covers all of the stacked end surface 30b and the substrate end surface 20c, and covers all the end portion on the rear end surface 10a side of the upper electrode 50 and the end portion on the rear end surface 10a side of the lower electrode 60. The thickness in the Y direction of the insulating film 71 on the rear end face 10 a is larger than the thickness in the Z direction of the insulating film 71 on the upper electrode 50 and the thickness in the Z direction of the insulating film 71 on the lower electrode 60. In one example, the thickness in the Y direction of the insulating film 71 on the rear end face 10a is 100 nm to 200 nm, and the thickness in the Z direction of the insulating film 71 on the upper electrode 50 and the lower electrode 60 is 20 nm to 30 nm. is there. The insulating film 71 is a dielectric film including at least one of, for example, SiO ₂ , SiON, SiN, Al ₂ O ₃ (alumina), BCB resin, and polyimide resin. The metal film 72 is provided on the stacked end face 30 b and the substrate end face 20 c via the insulating film 71 and extends over the upper electrode 50 and the lower electrode 60. Specifically, the metal film 72 covers all of the stacked end surface 30b and the substrate end surface 20c, and covers the end portion on the rear end surface 10a side of the upper electrode 50 and the end portion on the rear end surface 10a side of the lower electrode 60. The metal film 72 includes, for example, Au, and has a high reflectance exceeding 90%, for example. The solder 4 is provided on the submount 3 in a range reaching the substrate end surface 10c. The metal film 72 extending over the lower electrode 60 is in contact with the solder 4. Alternatively, the metal film 72 may cover the substrate end surface 20c but may not extend over the lower electrode 60c. Even in this case, the lower part of the metal film 72 on the substrate end surface 20 c is in contact with the solder 4. The metal film 72 that does not extend over the lower electrode 60c is obtained when a long protective plate 90 that reaches the substrate end face 10c is used in the step of forming the metal film 72 described later.

  The insulating film 75 includes a portion provided between the upper electrode 50 and the metal film 72 in the Z direction. Specifically, the insulating film 75 is sandwiched between the upper electrode 50 and the insulating film 71. One end of the insulating film 75 in the Y direction is included in a plane including the rear end face 10a, and the other end of the insulating film 75 is the front end with respect to the edge of the insulating film 71 on the upper electrode 50 in the Y direction. It extends to the surface 10b side. On the insulating film 75, the edge of the insulating film 71 on the upper electrode 50 and the edge of the metal film 72 are located. Note that, on the insulating film 75, the edge of the metal film 72 is located on the plane side with respect to the edge of the insulating film 71 in the Y direction.

The thickness of the insulating film 75 in the Z direction is larger than the thickness of the insulating film 71 on the upper electrode 50 in the Z direction. The thickness of the insulating film 75 in the Z direction is, for example, 100 nm to 300 nm, and more preferably, for example, 150 to 300 nm. The insulating film 75 may be a dielectric film made of the same material as the insulating film 71, or may be a dielectric film made of a material different from the insulating film 71. The insulating film 75 is a dielectric film including at least one of SiO ₂ , SiON, SiN, Al ₂ O ₃ (alumina), BCB resin, and polyimide resin, for example. Since SiO ₂ and SiON have good adhesion to the upper electrode 50, they are used as a material for the insulating film 75.

  An example of a method for manufacturing the QCL 1 having the above configuration will be described below. 4 (a) to 4 (c), 5 (a) to 5 (c), 6 (a) to 6 (c), 7, 8 (a) and 8 (b). FIG. 9 is a diagram showing a manufacturing process of the QCL 1 of FIG. 4 (a) to 4 (c) and FIGS. 6 (a) to 6 (c) show cross sections corresponding to the YZ cross section along the line III-III in FIG. (A)-FIG.5 (c) has shown XZ cross section. First, a wafer to be the semiconductor substrate 20 is prepared. In the first crystal growth step, the buffer layer 32, the core layer 33, and the diffraction grating layer 34 are grown in this order on the main surface of the wafer by using a growth method such as MBE and OMVPE. Thereafter, a resist 80 is applied on the diffraction grating layer 34. Subsequently, as shown in FIG. 4A, a pattern for the diffraction grating 34a is formed on the resist 80 by a normal photolithography technique. At this time, the width of the pattern of the resist 80 in the Y direction is Λ. Subsequently, by etching the diffraction grating layer 34 in the Z direction, a periodic structure for the diffraction grating 34a is formed on the diffraction grating layer 34, as shown in FIG.

Next, in the second crystal growth step, as shown in FIG. 4C, the upper clad layer 35 and the contact layer 36 are grown on the diffraction grating layer 34 in this order. Next, as shown in FIG. 5A, a mask 81 is formed in a region to be the semiconductor stack 30 by a normal photolithography technique. The region to be the semiconductor stack 30 is a region having a predetermined width WM in the X direction and extending in the Y direction at the center in the X direction of QCL1. For the mask 81, for example, the same material as the material of the insulating film 71 is used. That is, the mask 81 is made of a dielectric material including at least one of SiN, SiON, alumina, and SiO ₂ .

  Thereafter, the mask 81 is used to etch the semiconductor stack 30 in the Z direction, thereby forming the mesa-shaped semiconductor stack 30 as shown in FIG. Note that dry etching or wet etching can be applied as the etching of the semiconductor stack 30, but dry etching is preferably applied. The reason is that the predetermined width WM of the semiconductor stack 30 greatly affects the element characteristics of the QCL1, and therefore the predetermined width WM can be processed with high precision by dry etching having excellent vertical etching properties. For example, reactive ion etching (RIE) can be used as the dry etching. In reactive ion etching, a plasma etching gas is used.

  Next, in the third crystal growth step, a semi-insulating semiconductor layer such as InP to which Fe is added is grown with the mask 81 left on the semiconductor stack 30. At this time, as shown in FIG. 5C, the crystal is not grown on the mask 81, and is removed by etching in two regions on both side surfaces of the semiconductor stack 30 (that is, in FIG. 5B). The semiconductor layer is grown so as to embed each of the two regions corresponding to the portion. In this way, two current block portions 40 are formed. Next, after removing the mask 81, as shown in FIG. 6A, the upper electrode 50 is formed on the semiconductor stack 30 (that is, on the upper surface 30a). Thereafter, as shown in FIG. 6B, an insulating film 76 to be the insulating film 75 is formed on the upper electrode 50. Next, a resist 82 is patterned on the region of the upper electrode 50 where the insulating film 75 is to be formed. Next, when the insulating film 76 is etched in the Z direction, only the insulating film 76 protected by the resist 82 remains on the upper electrode 50. Thereafter, when the resist 82 is removed, an insulating film 75 is formed on the upper electrode 50 as shown in FIG. Thereafter, the thickness of the wafer is reduced to a thickness that can be cleaved (for example, 100 to 200 μm) by polishing or the like, and then the lower electrode 60 is formed on the back surface 20b of the semiconductor substrate 20 as shown in FIG.

  After the above steps, as shown in FIG. 8A, the plurality of semiconductor element portions 10 on which the insulating film 75 is formed are formed in an aligned state in the X direction and the Y direction on the entire surface of the wafer. The FIG. 8A shows boundary lines B1 and B2 between the semiconductor element portions 10 when the plurality of semiconductor element portions 10 are individually divided. The boundary line B1 is along the X direction, and the boundary line B2 is along the Y direction. Then, by cleaving the plurality of semiconductor element portions 10 along the boundary line B1, a crack is generated in the wafer along the boundary line B1. As a result, the wafer is divided along the boundary line B1, and the chip bar 85 as shown in FIG. 8B is formed. The chip bar 85 includes a plurality of semiconductor element portions 10 arranged along the X direction and an insulating film 75 formed on the semiconductor element portion 10. The chip bar 85 has an end surface 85a including the rear end surface 10a of the QCL1 in the Y direction. The insulating film 75 is provided on the end face 85 a side in the Y direction of the chip bar 85.

  Subsequently, a process of forming the insulating film 71 and the metal film 72 on the end face 85a will be described. First, as shown in FIG. 9, two protective plates 90 are prepared in order to form the insulating film 71 in a desired region of the chip bar 85. The desired region is a partial region including the end surface 85a of the chip bar 85. The protective plate 90 has a rectangular thin plate shape whose longitudinal direction is the X direction. As shown in FIG. 9, a single protective plate 90 is used to cover all the upper electrodes 50 included in other areas of the chip bar 85 except for the partial area. At this time, a part of the insulating film 75 on the front end face 10b side in the Y direction is also covered. Then, the lower electrode 60 included in the other region of the chip bar 85 is covered with another protective plate 90. Next, the insulating film 71 is formed on the end face 85a. Specifically, the constituent atoms of the insulating film 71 are deposited on the end face 85a from the side facing the end face 85a by using, for example, CVD or sputtering. The side facing the end surface 85a refers to a position facing the end surface 85a in the normal direction of the end surface 85a. At this time, the insulating film 71 is also formed on the insulating film 75 and the lower electrode 60 by wrapping around the insulating film 75 and the lower electrode 60. After film formation, the protective plate 90 is removed. In this way, the insulating film 71 is formed in the partial region of the chip bar 85.

  Subsequently, a metal film 72 is formed on the end face 85a. Specifically, the constituent atoms of the metal film 72 are deposited on the end surface 85a from the side facing the end surface 85a by using, for example, electron beam evaporation. At this time, the metal film 72 is also formed on the insulating film 75 by wrapping around the insulating film 75. In this way, the metal film 72 is formed in the partial region of the chip bar 85. After film formation, the protective plate 90 is removed.

  The length in the Y direction of the protective plate 90 used when forming the metal film 72 is longer than the length in the Y direction of the protective plate 90 used when forming the insulating film 71. As a result, the edge of the insulating film 71 on the insulating film 75 is located on the side opposite to the end face 85a in the Y direction with respect to the edge of the metal film 72 on the insulating film 75. Occurrence of a short circuit due to direct contact with can be prevented. Finally, the wafer is cracked along the boundary line B2 by cleaving the chip bar 85 along the boundary line B2 (see FIG. 8B) along the Y direction. Thus, the chip bars 85 are individually divided along the boundary line B2. Finally, QCL1 as shown in FIG. 1 is formed.

  The effects obtained by the QCL 1 of the present embodiment described above will be described together with the problems of the prior art. QCL is promising as a light source that can be used in technical fields where high growth is expected in the future, such as environmental gas analysis, medical diagnosis, and industrial processing. QCL can generate laser oscillation light in the mid-infrared region (for example, wavelength 3 μm to 30 μm). QCL is expected as a light source that realizes miniaturization and cost reduction, and is being actively developed. In particular, in the gas sensing field which is promising in the mid-infrared region, it is necessary to detect only the absorption line of a specific gas, so the development of DFB-type QCL capable of single mode operation in the mid-infrared region has become the mainstream. ing. In such a QCL, in principle, non-radiative recombination due to LO phonon scattering or the like occurs remarkably, so that the threshold current required for the laser oscillation of the QCL increases from several hundred mA to several A. The power consumption of QCL also increases. Such an increase in threshold current is one factor that hinders the practical use of QCL. Therefore, in order to suppress such an increase in threshold current, it is conceivable to provide a metal film on the end face constituting the QCL laser resonator.

  Here, a QCL structure in which a metal film is provided on the end face will be described as a comparative example. FIG. 10 is a perspective view of a QCL 100 as a comparative example. 11 is a cross-sectional YZ view along the line XI-XI in FIG. In each figure, an XYZ orthogonal coordinate system is shown for easy understanding. Since the QCL 100 is actually mounted on the submount via the solder 4, for example, FIG. 11 shows a state in which the solder 4 is attached under the QCL 100. The current confinement structure of the QCL 100 is a buried heterostructure similar to the structure of the QCL 1 of the present embodiment. As shown in FIG. 10, the QCL 100 includes a semiconductor element unit 10, an insulating film 71, and a metal film 72.

  The difference between the QCL 100 and the QCL 1 of the present embodiment is that the QCL 100 does not include the insulating film 75. When the QCL 100 is mounted on the submount via the solder 4, the metal film 72 on the lower electrode 60 comes into contact with the solder 4. When a voltage (for example, a high voltage of 10 V or more) is applied between the upper electrode 50 and the lower electrode 60 for laser oscillation of the QCL 100 with the metal film 72 in contact with the solder 4 as described above, the lower electrode The voltage applied to 60 is applied to the metal film 72 via the solder 4. As a result, the voltage is applied via the insulating film 71 between the metal film 72 on the upper electrode 50 and the upper electrode 50.

  However, since the thickness T2 of the insulating film 71 on the upper electrode 50 is likely to be extremely thinner than the thickness T1 of the insulating film 71 on the rear end face 10a as described above, such an extremely thin insulating film 71 is formed. When a high voltage of, for example, 10 V or more is applied between the metal film 72 on the upper electrode 50 and the upper electrode 50, the insulating film 71 in between may be broken. As a result, a large current (so-called inrush current) flows in the vicinity of the rear end face 10a via the destroyed portion of the insulating film 71, and there is a possibility that a failure such as an end face destruction may occur in the QCL 100. Note that if the thickness of the insulating film 71 on the upper electrode 50 is to be increased, it is necessary to further increase the thickness of the insulating film 71 on the rear end face 10a (for example, about several times). In this case, since the time for forming the insulating film 71 on the rear end face 10a increases (for example, several times), the productivity of the QCL 100 decreases. In addition, when such an extremely thick insulating film 71 is formed on the rear end face 10a, the rear end face 10a is deteriorated due to an increase in the stress generated in the insulating film 71, and the insulating film 71 is cracked or insulated. There is a possibility that peeling from the rear end face 10a of the film 71 may occur.

  On the other hand, in the QCL 1 of the present embodiment, as shown in FIG. 3, an insulating film 75 is provided between the upper electrode 50 and the metal film 72 in the Z direction. Since the thickness is larger than the thickness of the insulating film 71, a sufficient insulating region between the upper electrode 50 and the metal film 72 (that is, a region including the insulating film 71 and the insulating film 75) can be secured sufficiently. That is, the insulation resistance between the upper electrode 50 and the metal film 72 can be increased. Therefore, according to QCL1, even when the voltage is applied between the metal film 72 on the upper electrode 50 and the upper electrode 50, the breakdown of the insulating films 71 and 75 due to the voltage can be suppressed. As a result, it is possible to suppress the deterioration of the element characteristics of the QCL 1 due to end face destruction caused by the destruction of the insulating films 71 and 75.

Further, as in the present embodiment, at least one of the insulating film 71 and the insulating film 75 may include at least one of SiO ₂ , SiON, SiN, alumina, BCB resin, and polyimide resin. These have excellent durability and insulating properties as a protective film for the rear end face 10a. Further, they are easily formed on the rear end face 10a by using a general dielectric film forming method such as sputtering, CVD, or spin coating. That is, the film formation process of the insulating films 71 and 75 can be easily introduced into the QCL1 manufacturing process described above.

  Further, as in the present embodiment, the metal film 72 may include Au. Thereby, in the rear end surface 10a, the metal film 72 can be effectively functioned as a high reflection film having a reflectance exceeding 90%, for example.

  Further, as in the present embodiment, the upper cladding layer 35 may be an InP layer. InP is suitable for the material of the upper cladding layer 35 because it is transparent to the oscillation light in the mid-infrared region (not showing light absorption). Further, since InP is a binary mixed crystal and lattice-matched to the InP semiconductor substrate 20, the InP layer can be satisfactorily grown on the InP substrate. Further, since the thermal conductivity of InP is good, the heat from the core layer 33 can be released well through the upper cladding layer 35. Thereby, the temperature characteristic of QCL1 can be improved.

  In addition, as in the present embodiment, the core layer 33 includes a plurality of active layers that are light emitting regions and a plurality of injection layers for injecting carriers into the active layer, and the active layers and the injection layers are in the Z direction. May be arranged alternately. By providing the injection layer between the active layers in this way, electrons are continuously and smoothly delivered to the adjacent active layers, and light emission due to transition of electrons between subbands in the conduction band in the active layer is efficient. It can be generated well. As a result, the oscillation characteristics of QCL1 can be improved.

  Further, as in the present embodiment, the active layer and the injection layer may each include a GaInAs / AlInAs superlattice array. This superlattice array can provide transitions between subbands of electrons in the conduction band in the active layer, corresponding to wavelengths in the mid-infrared region (eg, 3-20 μm). Therefore, it is suitable as a material for the core layer 33 of QCL1 capable of oscillating light in the mid-infrared region.

  Further, as in the present embodiment, the semiconductor substrate 20 may be an InP substrate. The semiconductor stack 30 constituting the QCL1 has a lattice constant close to InP. Therefore, by using the semiconductor substrate 20 as the InP substrate, the semiconductor stack 30 can be grown on the semiconductor substrate 20 with good crystal quality. Further, since InP is transparent to light in the mid-infrared region, the InP substrate can function as a lower cladding layer for the core layer 33.

(First modification)
FIG. 12 is a cross-sectional view of a QCL 1A according to a third modification of the above embodiment. FIG. 12 shows a YZ cross section including the semiconductor stack 30 of QCL1A. The difference between this modification and the above embodiment is the thickness of the upper electrode and the lower electrode. That is, a part of the upper electrode 50A and the lower electrode 60A of this modification is thinned. As illustrated in FIG. 12, the upper surface 30a includes a region 30c (first region) and a region 30d (second region) located between the stacked end surface 30b and the region 30c in the Y direction. The region 30c and the region 30d are arranged along the Y direction. The region 30c is a region excluding the region 30d on the upper surface 30a, and is connected to the front end surface 10b. The region 30d is a region provided at one end of the upper surface 30a in the Y direction, and is connected to the rear end surface 10a. The upper electrode 50A is provided on the region 30c and the region 30d. The thickness of the upper electrode 50A provided on the region 30d is thinner than the thickness of the upper electrode 50A provided on the region 30c.

  The back surface 20b includes a region 20f (third region) and a region 20g (fourth region) located between the substrate end surface 20c and the region 30c in the Y direction. The region 20f and the region 20g are arranged along the Y direction. The region 20f is a region excluding the region 20g on the back surface 20b, and is connected to the front end surface 10b. The region 20g is a region provided at one end portion in the Y direction of the back surface 20b, and is connected to the rear end surface 10a. The lower electrode 60A is provided on the region 20f and the region 20g. The thickness of the lower electrode 60A provided on the region 20g is thinner than the thickness of the lower electrode 60A provided on the region 20f.

  The thickness in the Z direction of the upper electrode 50A provided on the region 30c and the thickness in the Z direction of the lower electrode 60A provided on the region 20f are, for example, 5 μm to 10 μm in order to suppress a decrease in heat dissipation of the QCL 1A. Set to the thickness of On the other hand, the thickness in the Z direction of the upper electrode 50A provided on the region 30d and the thickness in the Z direction of the lower electrode 60A provided on the region 20g are, for example, 0.5 to 1.0 μm. Further, the length in the Y direction of the upper electrode 50A provided on the region 30d (ie, the length in the Y direction of the region 30d) and the length in the Y direction of the lower electrode 60A provided on the region 20g (ie, the region 20g). The length in the Y direction) is, for example, 10 to 100 μm.

  The insulating film 71, the insulating film 75, and the metal film 72 extend from the region 30d to the region 30c. The insulating film 71 and the metal film 72 further extend from the region 20g to the region 20f. In the insulating film 71, a stepped portion 71a is formed near the boundary between the upper electrode 50A provided on the region 30c and the upper electrode 50A provided on the region 30d. In the insulating film 71, a step portion 71b is formed in the vicinity of the boundary between the lower electrode 60A provided on the region 20f and the lower electrode 60A provided on the region 20g. In one example, the stepped portion 71a and the stepped portion 71b are orthogonal to the Y direction.

  Thus, the rear end face 10a can be easily cleaved by reducing the thickness of the upper electrode 50A and the lower electrode 60A in the vicinity of the rear end face 10a (that is, the laminated end face 30b and the substrate end face 20c) to be a cleavage plane. . As a result, the yield when manufacturing QCL 1A can be increased. In addition, since the thickness of the upper electrode 50A provided on the region 30d is thinner than the thickness of the upper electrode 50A provided on the region 30c, the region has an electric resistance higher than that of the upper electrode 50A provided on the region 30c. The electric resistance of the upper electrode 50A provided on 30d is larger. In addition, since the thickness of the lower electrode 60A provided on the region 20g is thinner than the thickness of the lower electrode 60A provided on the region 20f, the electric resistance of the lower electrode 60A provided on the region 20f is smaller than the electric resistance of the lower electrode 60A provided on the region 20f. The electric resistance of the lower electrode 60A provided on 20g is larger. Thereby, the leak current flowing in the vicinity of the rear end face 10a can be reduced. As a result, the element characteristics of the QCL 1A can be improved (for example, the threshold current can be reduced). In addition, even when the thickness of the upper electrode 50A provided on the region 30d and the thickness of the lower electrode 60A provided on the region 20g are reduced as described above, the same effect as that of the above embodiment is obtained. It can play suitably.

  Subsequently, an example of a manufacturing method of the QCL 1A according to this modification will be described below. The manufacturing method of the QCL 1A according to this modification is the same as that of the above embodiment until the third crystal growth step (see FIG. 5C) for forming the two current block portions 40. Therefore, the description up to that step is omitted, and the steps after the step of forming the upper electrode 50A on the semiconductor stack 30 will be described. FIG. 13A to FIG. 13C are diagrams showing a manufacturing process of the QCL 1A of FIG. FIGS. 13A to 13C show YZ cross sections including the semiconductor stack 30 of QCL 1A. First, as shown in FIG. 13A, a metal film 51 to be the upper electrode 50A is thinly formed on the entire upper surface 30a of the semiconductor stack 30. Thereafter, the resist 86 is patterned so as to cover the metal film 51 provided on the region 30d.

  Next, as illustrated in FIG. 13B, a metal film 51 is further formed on the thin metal film 51. At this time, since the metal film 51 is not formed on the resist 86, the metal film 51 is further formed only on the metal film 51 provided on the region 30c. As a result, the thickness of the metal film 51 provided on the region 30d is smaller than the thickness of the metal film 51 provided on the region 30c. In this way, the upper electrode 50A is formed on the upper surface 30a. Next, as shown in FIG. 13C, the resist 86 is removed. Thereafter, an insulating film 75 is formed on the upper electrode 50A in the same manner as in the above embodiment (see FIGS. 6B and 6C). Subsequently, the lower electrode 60A is formed on the back surface 20b of the semiconductor substrate 20 in the same manner as the step of forming the upper electrode 50A. Subsequent steps are the same as those in the above embodiment, and a description thereof will be omitted.

  Here, when the metal film 72 is formed on the end surface 85a from the side facing the end surface 85a, the metal particles constituting the metal film 72 are rebounded by the stepped portion 71a, so that the metal film 72 is on the region 30c. It becomes difficult to wrap around the upper electrode 50A provided on the upper electrode 50A. This makes it difficult for the metal film 72 to be formed on the upper electrode 50A provided on the region 30c, so that electrical insulation between the metal film 72 and the upper electrode 50A can be made more reliable. At this time, since the metal particles constituting the metal film 72 are bounced back to the stepped portion 71b, the metal film 72 is unlikely to wrap around the lower electrode 60A provided on the region 20f. This makes it difficult for the metal film 72 to be formed on the lower electrode 60A provided on the region 20f, so that the electrical insulation between the metal film 72 and the lower electrode 60A can be further ensured. That is, according to the QCL 1A of the present modification, the insulating property in the vicinity of the rear end face 10a can be improved, and the breakdown of the insulating film 71 in the vicinity of the rear end face 10a can be suppressed. In this modification, the thicknesses of both the upper electrode 50A provided on the region 30d and the lower electrode 60A provided on the region 20g are provided on the upper electrode 50A and the region 20f provided on the region 30c. However, only the upper electrode 50A provided on the region 30d may be thinner than the upper electrode 50A provided on the region 30c, or provided on the region 20g. Only the lower electrode 60A may be thinner than the lower electrode 60A provided on the region 20f. Even in such a case, the above-described effects can be suitably achieved.

  FIG. 14 is a cross-sectional view of a QCL 1B according to another example of the present modification. As shown in FIG. 14, the upper electrode 50A may be provided only on the region 30c, and the lower electrode 60A may be provided only on the region 20f. That is, the upper electrode 50A is not provided on the region 30d, and the lower electrode 60A is not provided on the region 20g. The insulating film 71, the insulating film 75, and the metal film 72 extend from the region 30d to the region 30c. The insulating film 71 and the metal film 72 further extend from the region 20g to the region 20f. Thus, by preventing the upper electrode 50A and the lower electrode 60A from being provided in the vicinity of the rear end face 10a, the above-described effect can be more remarkably exhibited. That is, according to the QCL 1B, the rear end face 10a can be cleaved more easily. As a result, it is possible to further increase the yield when manufacturing the QCL 1B. Further, since the upper electrode 50A and the lower electrode 60A are not provided in the vicinity of the rear end face 10a, the electrical resistance in the vicinity of the rear end face 10a can be further increased. Thereby, the leakage current flowing in the vicinity of the rear end face 10a can be further reduced. As a result, the device characteristics of the QCL 1B can be further improved (for example, the threshold current can be reduced).

  In addition, when manufacturing QCL1B, the following processes are passed after the third crystal growth process (refer FIG.5 (c)) which forms the two current block parts 40 of the said embodiment. FIG. 15A to FIG. 15C are diagrams showing a manufacturing process of the QCL 1B of FIG. 15A to 15C show YZ cross sections including the semiconductor stack 30 of QCL1B. First, as shown in FIG. 15A, the resist 87 is patterned so as to cover the region 30d. Next, as shown in FIG. 15B, a metal film 52 to be the upper electrode 50A is formed on the region 30c and the resist 87 by vapor deposition or the like. Next, as shown in FIG. 15C, the resist 87 is removed by lift-off. Thereby, the resist 87 and the metal film 52 formed on the resist 87 are simultaneously removed. In this way, the upper electrode 50A is formed on the upper surface 30a. Thereafter, an insulating film 75 is formed on the upper electrode 50A in the same manner as in the above embodiment (see FIGS. 6B and 6C).

  Subsequently, the lower electrode 60A is formed on the back surface 20b of the semiconductor substrate 20 in the same manner as the step of forming the upper electrode 50A. In this way, the semiconductor element portion 10A of the QCL 1B according to this modification is completed. Subsequent steps are the same as those in the above embodiment, and a description thereof will be omitted. In the QCL 1B, the case where both the upper electrode 50A and the lower electrode 60A are provided only on the region 30c and the region 20f is illustrated, but the configuration in which the upper electrode 50A is provided only on the region 30c, Only one of the configurations in which the electrode 60A is provided only on the region 20f may be employed. Even in such a case, the above-described effects can be suitably achieved.

(Second modification)
FIG. 16 is a cross-sectional view of a QCL 1C according to the second modification of the above embodiment. FIG. 16 shows a YZ cross section including the semiconductor stack 30 of QCL1C. The difference between this modification and the above embodiment is the thickness of the second insulating film. That is, in this modification, a part of the insulating film 75A is thick. The insulating film 75A has a region 75a (fifth region) and a region 75b (sixth region) located between the plane including the rear end surface 10a in the Y direction and the region 75a. The region 75a extends toward the front end face 10b side with respect to the edge of the insulating film 71 on the upper electrode 50 in the Y direction. The thickness of the region 75a in the Z direction is larger than the thickness of the region 75b in the Z direction. In one example, the thickness of the region 75a is 200 to 400 nm, more preferably 300 to 400 nm. The region 75a is provided at a position higher than the metal film 72 with respect to the main surface 20a in the Z direction. In other words, the region 75a protrudes on the side opposite to the upper electrode 50 with respect to the metal film 72 in the Z direction.

  The region 75b is sandwiched between the upper electrode 50 and the insulating film 71 in the Z direction. The thickness of the region 75b in the Z direction is the same as the thickness of the insulating film 75 in the above embodiment in the Z direction. The edges of the insulating film 71 and the metal film 72 on the upper electrode 50 are located on the region 75b. That is, the insulating film 71 and the metal film 72 on the upper electrode 50 are provided on the region 75b and are not provided on the region 75a.

  At the boundary between the region 75a and the region 75b, a stepped portion 75c that intersects the Y direction is formed. In one example, the stepped portion 75c is orthogonal to the Y direction. The step portion 75 c faces the edge of the insulating film 71 and the edge of the metal film 72 on the region 75 b in the Y direction. Since the insulating film 75A has such a stepped portion 75c, when forming the metal film 72 on the rear end face 10a, the metal particles constituting the metal film 72 are likely to be rebounded at the stepped portion 75c. It becomes difficult to wrap around the upper electrode 50. That is, the metal film 72 can be made difficult to be formed from the insulating film 75A to the upper electrode 50. Thereby, the short circuit by the contact with the metal film 72 and the upper electrode 50 can be suppressed. As a result, it is possible to suppress the occurrence of malfunction of the QCL 1C due to the occurrence of the short circuit.

  Next, an example of a method for manufacturing the QCL 1C according to this modification will be described below. The manufacturing method of the QCL 1C according to this modification is the same as that of the above embodiment until the step of forming the insulating film 76 on the upper electrode 50 (see FIG. 6C). Therefore, in the following, the description up to the step is omitted, and after the step, the steps after the step of forming the insulating film 75A will be described. However, in the step of forming the insulating film 76 on the upper electrode 50, the thickness of the insulating film 76 in the Z direction is the same as the thickness of the region 75a in the Z direction. FIG. 17A to FIG. 17C are diagrams showing a manufacturing process of the QCL 1C of FIG. First, as shown in FIG. 17A, a resist 88 is patterned on the upper electrode 50. At this time, the resist 88 is patterned on the upper electrode 50 except for the region to be the region 75 b in the insulating film 76. Next, when the insulating film 76 not covered with the resist 88 is etched in the Z direction, an insulating film 75A is formed on the upper electrode 50 as shown in FIG. Thereafter, as shown in FIG. 17C, the resist 88 is removed. Subsequent steps are the same as those in the above embodiment, and a description thereof will be omitted.

The quantum cascade laser of the present invention is not limited to the above-described embodiment, and various other modifications are possible. For example, the above-described embodiments and modifications may be combined with each other according to the necessary purpose and effect. In the above-described embodiment and each modification, the insulating film and the metal film are provided only on the rear end surface side in the Y direction of the semiconductor element portion. However, the insulating film and the metal film are provided on the front end surface of the semiconductor element portion. It may be provided only on the side, or may be provided on both the front end face and the rear end face of the semiconductor element portion. In the above-described embodiments and modifications, the QCL has a buried heterostructure. However, for example, a high mesa in which an insulating film (for example, a dielectric film such as SiO ₂ ) is formed on both side surfaces of the semiconductor stack 30. You may have other arbitrary structures, such as a structure. In the above-described embodiments and modifications, the DFB-type QCL having the diffraction grating layer 34 has been described. However, the present invention is not limited to this. That is, the above-described embodiment and each modification can be similarly applied to, for example, a Fabry-Perot (FP) type QCL that does not include the diffraction grating layer 34. This FP type QCL can provide the same improvement as the DFB type QCL. In the above-described embodiments and modifications, the upper electrode is a cathode electrode and the lower electrode is an anode electrode, but the upper electrode is an anode electrode and the lower electrode is a cathode electrode. In this case as well, the same effects as those of the above-described embodiment and each modification can be obtained.

  DESCRIPTION OF SYMBOLS 1,1A, 1B, 1C ... Quantum cascade semiconductor laser, 2 ... Carrier, 3 ... Submount, 4 ... Solder, 5 ... Wire, 10 ... Semiconductor element part, 10a ... Rear end surface, 10b ... Front end surface, 20 ... Semiconductor substrate 20a ... main surface, 20b ... back surface, 20c ... substrate end surface, 30c, 30d, 20f, 20g, 75a, 75b ... region, 30 ... semiconductor stack, 30a ... top surface, 30b ... stack end surface, 32 ... buffer layer, 33 ... Core layer 34 ... Diffraction grating layer 34a ... Diffraction grating 35 ... Upper cladding layer 36 ... Contact layer 40 ... Current blocking part 50, 50A ... Upper electrode 60,60A ... Lower electrode 71,75,75A ... insulating film, 72 ... metal film.

Claims (12)

A semiconductor substrate having a main surface and a back surface facing each other in a first direction, and a substrate end surface intersecting a second direction orthogonal to the first direction;
A surface provided on a side opposite to the main surface in the first direction, a laminated end surface included in a plane including the substrate end surface, a core layer extending from the laminated end surface along the second direction, and the core layer A semiconductor layer provided on the main surface;
A first electrode provided on the surface;
A second electrode provided on the back surface;
A first insulating film provided on the stacked end surface and the substrate end surface and extending over the first electrode;
A metal film provided on the stacked end face and the substrate end face via the first insulating film and extending over the first electrode;
A second insulating film provided on the first electrode and including a portion provided between the first electrode and the metal film in the first direction;
With
The quantum cascade laser, wherein a thickness of the second insulating film in the first direction is thicker than a thickness of the first insulating film provided on the first electrode in the first direction. The surface includes a first region and a second region located between the stacked end surface and the first region in the second direction,
2. The quantum cascade laser according to claim 1, wherein a thickness of the first electrode provided on the second region is thinner than a thickness of the first electrode provided on the first region. The surface includes a first region and a second region located between the stacked end surface and the first region in the second direction,
The quantum cascade laser according to claim 1, wherein the first electrode is provided only on the first region. The back surface includes a third region and a fourth region located between the substrate end surface and the third region in the second direction,
4. The quantum cascade according to claim 1, wherein a thickness of the second electrode provided on the fourth region is thinner than a thickness of the second electrode provided on the third region. 5. Semiconductor laser. The back surface includes a third region and a fourth region located between the substrate end surface and the third region in the second direction,
4. The quantum cascade laser according to claim 1, wherein the second electrode is provided only on the third region. 5. The second insulating film has a fifth region, and a sixth region located between the plane including the stacked end surface and the fifth region in the second direction,
6. The quantum cascade laser according to claim 1, wherein a thickness of the fifth region in the first direction is larger than a thickness of the sixth region in the first direction. 7. The device according to claim 1, wherein at least one of the first insulating film and the second insulating film includes at least one of SiO ₂ , SiON, SiN, alumina, BCB resin, and polyimide resin. A quantum cascade laser as described in 1.   The quantum cascade laser according to claim 1, wherein the metal film contains Au.   The quantum cascade laser according to claim 1, wherein the cladding layer is an InP layer. The core layer includes a plurality of active layers that are light emitting regions, and a plurality of injection layers for injecting carriers into the active layer,
10. The quantum cascade laser according to claim 1, wherein the active layer and the injection layer are alternately arranged along the first direction. 11.   11. The quantum cascade laser according to claim 10, wherein the active layer and the injection layer include a GaInAs / AlInAs superlattice array.   The quantum cascade laser according to claim 1, wherein the semiconductor substrate is an InP substrate.

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