JP2018533137A - ピクセルタイルレベルグラニュラリティをもつグラフィックス処理ユニットプリエンプション - Google Patents

ピクセルタイルレベルグラニュラリティをもつグラフィックス処理ユニットプリエンプション Download PDF

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Publication number
JP2018533137A
JP2018533137A JP2018515930A JP2018515930A JP2018533137A JP 2018533137 A JP2018533137 A JP 2018533137A JP 2018515930 A JP2018515930 A JP 2018515930A JP 2018515930 A JP2018515930 A JP 2018515930A JP 2018533137 A JP2018533137 A JP 2018533137A
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Prior art keywords
gpu
commands
primitives
stage
pixel
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Pending
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JP2018515930A
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English (en)
Japanese (ja)
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JP2018533137A5 (enExample
Inventor
アチャリヤ、アニルド・ラジェンドラ
ジョン、ガン
ゴエル、ビネート
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Qualcomm Inc
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Qualcomm Inc
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Publication of JP2018533137A publication Critical patent/JP2018533137A/ja
Publication of JP2018533137A5 publication Critical patent/JP2018533137A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/50—Lighting effects
    • G06T15/80—Shading
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Image Generation (AREA)
  • Image Processing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • User Interface Of Digital Computer (AREA)
JP2018515930A 2015-09-29 2016-07-08 ピクセルタイルレベルグラニュラリティをもつグラフィックス処理ユニットプリエンプション Pending JP2018533137A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562234355P 2015-09-29 2015-09-29
US62/234,355 2015-09-29
US15/013,714 2016-02-02
US15/013,714 US9842376B2 (en) 2015-09-29 2016-02-02 Graphics processing unit preemption with pixel tile level granularity
PCT/US2016/041525 WO2017058331A1 (en) 2015-09-29 2016-07-08 Graphics processing unit preemption with pixel tile level granularity

Publications (2)

Publication Number Publication Date
JP2018533137A true JP2018533137A (ja) 2018-11-08
JP2018533137A5 JP2018533137A5 (enExample) 2019-07-25

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JP2018515930A Pending JP2018533137A (ja) 2015-09-29 2016-07-08 ピクセルタイルレベルグラニュラリティをもつグラフィックス処理ユニットプリエンプション

Country Status (7)

Country Link
US (1) US9842376B2 (enExample)
EP (1) EP3357034B1 (enExample)
JP (1) JP2018533137A (enExample)
KR (1) KR20180059892A (enExample)
CN (1) CN108140233B (enExample)
BR (1) BR112018006349A2 (enExample)
WO (1) WO2017058331A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10338953B2 (en) * 2016-03-18 2019-07-02 Intel Corporation Facilitating execution-aware hybrid preemption for execution of tasks in computing environments
US10460513B2 (en) * 2016-09-22 2019-10-29 Advanced Micro Devices, Inc. Combined world-space pipeline shader stages
US11609791B2 (en) 2017-11-30 2023-03-21 Advanced Micro Devices, Inc. Precise suspend and resume of workloads in a processing unit
CN108121566A (zh) * 2017-12-06 2018-06-05 中国航空工业集团公司西安航空计算技术研究所 一种图形指令解析设计方法
CN109683966A (zh) * 2018-12-12 2019-04-26 中国航空工业集团公司西安航空计算技术研究所 一种面向设备优化的OpenGL驱动实现方法
US10748239B1 (en) 2019-03-01 2020-08-18 Qualcomm Incorporated Methods and apparatus for GPU context register management
US12026799B2 (en) 2021-03-19 2024-07-02 Samsung Electronics Co., Ltd. Method and apparatus for software based preemption using two-level binning to improve forward progress of preempted workloads
US20230205602A1 (en) * 2021-12-28 2023-06-29 Advanced Micro Devices, Inc. Priority inversion mitigation
US12406425B2 (en) 2022-08-24 2025-09-02 Advanced Micro Devices, Inc. Vertex index routing for two level primitive batch binning

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013025823A (ja) * 2011-07-18 2013-02-04 Apple Inc 仮想ｇｐｕ

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8139070B1 (en) * 2007-10-03 2012-03-20 Matrox Graphics, Inc. Systems for and methods of context switching in a graphics processing system
US9652282B2 (en) * 2011-11-08 2017-05-16 Nvidia Corporation Software-assisted instruction level execution preemption
US8572573B2 (en) * 2012-03-09 2013-10-29 Nvidia Corporation Methods and apparatus for interactive debugging on a non-preemptible graphics processing unit
US10535185B2 (en) * 2012-04-04 2020-01-14 Qualcomm Incorporated Patched shading in graphics processing
US10002021B2 (en) * 2012-07-20 2018-06-19 Qualcomm Incorporated Deferred preemption techniques for scheduling graphics processing unit command streams
US8963933B2 (en) * 2012-07-23 2015-02-24 Advanced Micro Devices, Inc. Method for urgency-based preemption of a process
US10095526B2 (en) 2012-10-12 2018-10-09 Nvidia Corporation Technique for improving performance in multi-threaded processing units
US9710874B2 (en) 2012-12-27 2017-07-18 Nvidia Corporation Mid-primitive graphics execution preemption
US9230518B2 (en) 2013-09-10 2016-01-05 Qualcomm Incorporated Fault-tolerant preemption mechanism at arbitrary control points for graphics processing
US9280845B2 (en) 2013-12-27 2016-03-08 Qualcomm Incorporated Optimized multi-pass rendering on tiled base architectures
US9396032B2 (en) * 2014-03-27 2016-07-19 Intel Corporation Priority based context preemption

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013025823A (ja) * 2011-07-18 2013-02-04 Apple Inc 仮想ｇｐｕ

Also Published As

Publication number Publication date
US20170091895A1 (en) 2017-03-30
WO2017058331A1 (en) 2017-04-06
US9842376B2 (en) 2017-12-12
KR20180059892A (ko) 2018-06-05
BR112018006349A2 (pt) 2018-10-16
EP3357034A1 (en) 2018-08-08
CN108140233A (zh) 2018-06-08
CN108140233B (zh) 2021-06-25
EP3357034B1 (en) 2019-04-10

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