JP2018515985A - 巡回冗長検査でのアルゴリズムの構成方法 - Google Patents
巡回冗長検査でのアルゴリズムの構成方法 Download PDFInfo
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- JP2018515985A JP2018515985A JP2017557210A JP2017557210A JP2018515985A JP 2018515985 A JP2018515985 A JP 2018515985A JP 2017557210 A JP2017557210 A JP 2017557210A JP 2017557210 A JP2017557210 A JP 2017557210A JP 2018515985 A JP2018515985 A JP 2018515985A
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- JP
- Japan
- Prior art keywords
- algorithm
- polynomial generator
- polynomial
- crc
- data stream
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/17—Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/617—Polynomial operations, e.g. operations related to generator polynomials or parity-check polynomials
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
Abstract
Description
m(x)=mL−1xL−1+mL−2xL−2+mL−2xL−2+・・・+m0
式中、Lはデータパケットの長さである。
g(x)=gk−1xk−1+gk−2xk−2+gk−2xk−2+・・・+g0
式中、kは多項式ジェネレータの長さである。本発明では、計算されるCRCチェックサムを次式で表すことができる。
c(x)=ck−2xk−2+ck−3xk−3+ck−4xk−4+・・・+c0
f(x)=m(x)xk−1+c(x)
m(x)xk−1=g(x)q(x)+c(x)
この場合、次式から解が得られる。
c(x)=剰余{(m(x)xk−1)/g(x)}
fn−1=A、fn−1=A+B、fn−1=A+B+C、・・・、f2=E+F+G、f1=F+G、f0=G
したがって、
ck−2=fk−2,ck−2=fk−2、・・・、c1=f1,c0=f0
である。
Claims (5)
- 並列巡回冗長検査(CRC)を行うためのアルゴリズムの構成方法であって、(i)多項式ジェネレータg(x)=gk−1xk−1+gk−2xk−2+gk−2xk−2+・・・+g0、およびf(x)=m(x)xk−1+c(x)について考慮するステップであって、m(x)=mL−1xL−1+mL−2xL−2+mL−2xL−2+・・・+m0であるステップと、(ii)前記f(x)および前記g(x)を互いの関数としてテーブルに変換するステップと、(iii)k=7およびL=7の代表的な場合を考慮すると、fn−1=A、fn−1=A+B、fn−1=A+B+C、・・・、f2=E+F+G、f1=F+G、f0=Gを得るステップであって、A、B、C、・・・、Gが除数係数であるステップと、(iv)ck−2=fk−2、ck−2=fk−2、・・・、c1=f1、c0=f0を得るステップとを備えるアルゴリズムの構成方法。
- 前記ステップ(iii)で、前記多項式ジェネレータの前記g(x)の前記係数がすべて1に等しいわけではない場合、前記導出には前記多項式ジェネレータの前記除数係数に基づく余分な乗算因数が必要である、請求項1に記載のアルゴリズムの構成方法。
- 請求項1に記載の前記ステップ(iii)で具体化することができる数学的定式化を利用することにより、前記多項式ジェネレータのシーケンスによりデータストリームからCRCチェックサムを得るために、前記除数係数A、B、・・・、F、Gが使用される、請求項1に記載のアルゴリズムの構成方法。
- 前記アルゴリズムが、前記多項式ジェネレータの長さおよび前記データストリームの長さとは無関係である、請求項1に記載のアルゴリズムの構成方法。
- デジタル論理回路実装で具体化される前記アルゴリズムが、典型的な1システム・クロック・サイクルの遅延を伴う最も遅い合成組合せ論理経路の伝播遅延だけにより速度が制限される、請求項1に記載のアルゴリズムの構成方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/SG2015/050119 WO2016186571A1 (en) | 2015-05-20 | 2015-05-20 | A method of arrangement of an algorithm in cyclic redundancy check |
Publications (1)
Publication Number | Publication Date |
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JP2018515985A true JP2018515985A (ja) | 2018-06-14 |
Family
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Family Applications (1)
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JP2017557210A Pending JP2018515985A (ja) | 2015-05-20 | 2015-05-20 | 巡回冗長検査でのアルゴリズムの構成方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US10623018B2 (ja) |
JP (1) | JP2018515985A (ja) |
KR (1) | KR102353983B1 (ja) |
CN (1) | CN107667475A (ja) |
DE (1) | DE112015006550T5 (ja) |
IL (1) | IL255381B (ja) |
MY (1) | MY185222A (ja) |
WO (1) | WO2016186571A1 (ja) |
Families Citing this family (1)
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CN116861493B (zh) * | 2023-08-31 | 2024-03-29 | 上海芯联芯智能科技有限公司 | 一种校验码生成方法、处理器及电子设备 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0840462B1 (en) * | 1996-10-29 | 2004-12-15 | International Business Machines Corporation | A method and apparatus for a two-step calculation of CRC-32 |
EP1260023A2 (en) * | 2000-02-17 | 2002-11-27 | Analog Devices, Inc. | Method, apparatus, and product for use in generating crc and other remainder based codes |
CN1193294C (zh) * | 2003-01-27 | 2005-03-16 | 西安电子科技大学 | 一种多通道多位并行计算crc码的方法 |
US7257257B2 (en) * | 2003-08-19 | 2007-08-14 | Intel Corporation | Method and apparatus for differential, bandwidth-efficient and storage-efficient backups |
US7181671B2 (en) * | 2003-09-23 | 2007-02-20 | Macronix International Co., Ltd. | Parallelized CRC calculation method and system |
US7219293B2 (en) | 2003-12-17 | 2007-05-15 | Macronix International Co., Ltd. | High performance CRC calculation method and system with a matrix transformation strategy |
US8341510B2 (en) | 2007-06-22 | 2012-12-25 | Sony Corporation | CRC generator polynomial select method, CRC coding method and CRC coding circuit |
US8185811B2 (en) * | 2007-08-17 | 2012-05-22 | Kan Ling Capital, L.L.C. | Robust joint erasure marking viterbi algorithm decoder |
JP4831018B2 (ja) | 2007-08-28 | 2011-12-07 | 日本電気株式会社 | 並列巡回符号生成装置および並列巡回符号検査装置 |
US9311185B2 (en) * | 2009-10-30 | 2016-04-12 | Cleversafe, Inc. | Dispersed storage unit solicitation method and apparatus |
CN101783688B (zh) * | 2010-03-05 | 2013-08-14 | 苏州和迈微电子技术有限公司 | 一种64位并行多模式crc码生成电路的设计方法 |
US8782227B2 (en) * | 2010-06-22 | 2014-07-15 | Cleversafe, Inc. | Identifying and correcting an undesired condition of a dispersed storage network access request |
-
2015
- 2015-05-20 MY MYPI2017704239A patent/MY185222A/en unknown
- 2015-05-20 WO PCT/SG2015/050119 patent/WO2016186571A1/en active Application Filing
- 2015-05-20 JP JP2017557210A patent/JP2018515985A/ja active Pending
- 2015-05-20 DE DE112015006550.4T patent/DE112015006550T5/de active Pending
- 2015-05-20 KR KR1020177033017A patent/KR102353983B1/ko active IP Right Grant
- 2015-05-20 CN CN201580080126.7A patent/CN107667475A/zh active Pending
- 2015-05-20 US US15/573,674 patent/US10623018B2/en active Active
-
2017
- 2017-11-01 IL IL255381A patent/IL255381B/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
CN107667475A (zh) | 2018-02-06 |
KR102353983B1 (ko) | 2022-01-20 |
US10623018B2 (en) | 2020-04-14 |
WO2016186571A1 (en) | 2016-11-24 |
US20180131388A1 (en) | 2018-05-10 |
MY185222A (en) | 2021-04-30 |
DE112015006550T5 (de) | 2018-02-15 |
KR20180008484A (ko) | 2018-01-24 |
IL255381B (en) | 2021-06-30 |
IL255381A0 (en) | 2017-12-31 |
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