WO2013189274A1 - 一种用于并行bch编码的电路、编码器及方法 - Google Patents

一种用于并行bch编码的电路、编码器及方法 Download PDF

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WO2013189274A1
WO2013189274A1 PCT/CN2013/077379 CN2013077379W WO2013189274A1 WO 2013189274 A1 WO2013189274 A1 WO 2013189274A1 CN 2013077379 W CN2013077379 W CN 2013077379W WO 2013189274 A1 WO2013189274 A1 WO 2013189274A1
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output
register
input
mod
circuit
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French (fr)
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朱丽娟
莫海锋
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记忆科技(深圳)有限公司
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Priority to US14/409,982 priority Critical patent/US9614550B2/en
Publication of WO2013189274A1 publication Critical patent/WO2013189274A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3961—Arrangements of methods for branch or transition metric calculation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/159—Remainder calculation, e.g. for encoding and syndrome calculation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/159—Remainder calculation, e.g. for encoding and syndrome calculation
    • H03M13/1595—Parallel or block-wise remainder calculation

Definitions

  • the present invention relates to the field of error correction coding, and more particularly to a circuit, an encoder and a method for parallel BCH coding. Background technique
  • BCH code As an important error correction coding method, BCH code has been widely used in the field of communication and consumer electronics.
  • the BCH code is taken from the abbreviation of Bose, Ray-Chaudhuri and Hocquenghem. It is a cyclic code that corrects multiple random errors and can be described by the root of the generator polynomial g ( X ).
  • g X
  • serial coding is often used where speed is not critical, as serial coding is the most economical. In the case of high speed requirements, parallel coding is required.
  • Patent Application No. 200810065971.9 discloses "circuits, encoders and methods for parallel BCH encoding" using a parallel iterative encoding circuit comprising a number of constant vector multipliers, a constant matrix multiplier and some XOR gates, although The fanout of the circuit is controlled compared to the LFSR structure, but the area of the multiplier is still too large.
  • an object of the present invention is to provide a circuit, an encoder and a method for parallel BCH coding, which can effectively shorten a path, thereby making the timing performance of the circuit better, and avoiding the LFSR when the clock frequency is increased.
  • the structure can not meet the timing requirements because the path is too long, and the area is saved.
  • the present invention provides a circuit for parallel BCH encoding, comprising P input branches, registers, and adders of Galois fields connected to the P branches and the registers,
  • each input branch includes a selector and an exclusive OR gate
  • the output of the exclusive OR gate is used as a selection signal of the selector
  • the output of the selector is the output of each input branch ;
  • the input sequence of the current cycle ⁇ m(pl), m(p-2), m(0) ⁇ is input to the P exclusive OR gates in order corresponding to the output high bits of the previous cycle of the register, and the XOR gate operation result is output.
  • P constant polynomials ⁇ (x r «0) mod g(x), (x r «l) mod g(x), .... , (x r «(pl)) mod g( x) ⁇ in order to input to P selectors in sequence, respectively, to select the result as the first output;
  • the first output and the second output perform a Galois field summation output to the register as an output of the current period of the register;
  • the P branches, adders, and the registers are subjected to a certain number of operations to obtain a final encoded output.
  • the specific number is determined by the length K of the input information data and the degree of parallelism P, and the specific number is the smallest integer not less than K/P.
  • the present invention accordingly provides an encoder employing the above circuit.
  • the present invention accordingly provides a method for parallel BCH coding, including:
  • the input sequence of the current cycle ⁇ m(pl), m(p-2), m(0) ⁇ is XORed in order with the output high bit of the previous cycle of the register, and the operation result is output as a selection signal to the selector.
  • P constant polynomials ⁇ (x r «0) mod g(x), (x r «l) mod g(x), .... , (x r «(pl)) mod g(x) ⁇ Selecting in sequence with 0, and selecting the result as the first output;
  • the first output and the second output perform a Galois field summation output to the register as an output of the current period of the register;
  • the specific number is determined by the length K of the input information data and the degree of parallelism P, and the specific number is the smallest integer not less than K/P.
  • the present invention also provides a circuit for parallel BCH encoding, comprising a residual module, a register, and an adder of a Galois field connected to the remainder module and the register; the input of the circuit in one clock cycle For the information bit of the P bit, the information bit is input to the remainder module as the first output, and The output of one cycle of the register is shifted to the high-bit P bit as a second output; the first output and the second output are summed by Galois field, output to a register, and the result is stored in the register In the middle, after a certain number of iterations, the final coded output is obtained.
  • the specific number is determined by the length K of the input information data and the degree of parallelism P, and the specific number is the smallest integer not less than K/P.
  • the present invention also provides an encoder employing the above circuit.
  • the present invention also provides a method for parallel BCH coding, including:
  • the input of the circuit is the information bit of the P bit, and the information bit is input to the spare module as the first output; the output of the previous cycle of the register is shifted to the high bit P bit as the second output; The first output and the second output are summed by a Galois field, output to a register, and the result is stored in the register; after a certain number of iterations, the final encoding output is obtained.
  • the specific number is determined by the length K of the input information data and the degree of parallelism P, and the specific number is the smallest integer not less than K/P.
  • the circuit, the encoder and the method for parallel BCH coding provided by the invention adopt an iterative algorithm, and use a look-up table to select a constant polynomial.
  • the working level is high, it can be compared with the traditional LFSR structure. Effectively shortening the path, so that the timing performance of the circuit is better, avoiding the situation that the LFSR structure cannot meet the timing requirement when t is too large when the clock frequency increases.
  • the circuit since the circuit is very simple, there are only a few selectors and some XOR gates, which greatly saves the area.
  • the present invention can effectively shorten the path, thereby making the timing performance of the circuit better, and avoiding the situation that the LFSR structure cannot meet the timing requirement due to the path being too long when the clock frequency is increased, and the area is saved.
  • FIG. 1 is a circuit diagram of a BCH encoder of a conventional serial LFSR structure
  • FIG. 2 is a schematic structural diagram of a circuit for parallel BCH encoding according to the present invention.
  • FIG. 3 is a structural block diagram of a specific embodiment of a circuit for parallel BCH encoding according to the present invention
  • FIG. 4 is a logic diagram of a circuit for parallel BCH encoding according to the present invention
  • FIG. 5 is a block diagram showing the structure of an input residual module in a circuit for parallel BCH encoding according to the present invention
  • FIG. 6 is a flow chart of a method for parallel BCH encoding according to the present invention.
  • each input branch includes a selector 30 and an exclusive OR gate 40.
  • the output of the exclusive OR gate 40 serves as a selection signal for the selector 30, and the output of the selector 30 is controlled by a selection signal.
  • the output of 30 is the output of each input branch.
  • the input sequence ⁇ m(pl), m(p-2), m(0) ⁇ of the current cycle is input to the P exclusive OR gates 40 correspondingly to the output high bits of the previous cycle of the register 10, respectively, and the XOR gate 40 is The operation result is output to the selector 30, and P constant polynomials ⁇ (xr«0) mod g(x), (xr «l) mod g(x), ....
  • the invention adopts an iterative algorithm, and uses a table lookup method to select a constant polynomial.
  • the path can be effectively shortened compared with the conventional LFSR structure, so that the timing performance of the circuit is better. It is avoided that when the clock frequency increases, the LFSR structure cannot satisfy the timing requirement because t is too large.
  • the circuit since the circuit is very simple, there are only a few selectors and some XOR gates, which greatly saves the area. Thereby, the invention can effectively shorten the path, thereby making the timing performance of the circuit better, and avoiding the situation that the LFSR structure cannot meet the timing requirement due to the path being too long when the clock frequency is increased, and the area is saved.
  • the information bit input with the weight length n and k bit is:
  • m(x)*x r b*g(x)+d(x) ( Al )
  • b is the quotient after m(x)*x r is divisible by g(x)
  • d(x) ( ((m(kl) x r x pl + m(k-2) x r x p " 2 + ... + m(kp) x r ) * x p + m(kpl) x r x pl + m(kp-2) x r x p " 2 + ... + m(kpp) x r ) * x p + + m(pl) x r x pl + m(p-2) x r x p " 2 + ...
  • Equation (A6 ) can be converted into a circuit as shown in FIG. 4 .
  • t(x) is the value in the register.
  • the input of the circuit is the information bit of p bit, and the information bit is input to the remainder module 50 as the first output; meanwhile, the register is The output of the previous cycle is shifted to the high bit p bit and the result of the generator polynomial is used as the second output; the two outputs are summed together by the Galois field, output to the register, and the result is stored in the register, so After iterating a certain number of times, all the k bit information bits are input into the register output, that is, the parity bit, that is, the BCH encoder result.
  • the circuit inputs p bits in one clock cycle, respectively ⁇ m(pl), m(p-2), m(0) ⁇ , which serve as selection signals for each selector; one input for each selector is The same, 0, the other input is different, respectively (x r «0) mod g (x), (x r «l) mod g (x), ...., (x r «( Pl))
  • the p polynomials of mod g(x) are obvious. These p polynomials are constant polynomials after the error correction capability is determined. And, in Figure 4, (dout «p) mod g(x) can be calculated using the previous p constant polynomials:
  • the high p bit of the register output value is extracted together with the input of the next cycle as the selection signal of the p constant polynomials, and at the same time, the output value of the register is arithmetically shifted left by p bits (to the high shift bit), and left shifted out.
  • the result is combined with the output of each selector in the Galois field addition input register to obtain the final encoded result.
  • the whole BCH encoder can be constructed by combining Figure 4 and Figure 5. If the information is of length k and the degree of parallelism of the circuit is p, then after iterating k/p times, the output value of the register is the check digit output. , As shown in Figure 3. If k cannot be divisible by p, then the lower bit of the p bit input of the last clock cycle can be filled with 0.
  • the specific implementation is:
  • the input sequence ⁇ m(pl), m(p-2), m(0) ⁇ is input to each selector in the encoder in sequence as one of the selection signals, and the other selection signal of the selector is the previous cycle.
  • Register output is high Bit.
  • Cycle the 2 and 3 processes continuously, update the value in the register every cycle, and participate in the operation of the next cycle until all the information bits are input, so that the value in the serial output register is added to the input information. After the sequence, the BCH encoded codeword is obtained.
  • Table 1 shows the performance comparison between the present invention and the conventional parallel LFSR structure when the information bit length is 2 KB and the error correction capability is 80.
  • the operating frequency is 100MHz
  • the area of the present invention is only slightly better than the LFSR structure, but if the operating frequency is increased to 400MHz, the conventional parallel 16-channel LFSR structure cannot pass the timing verification at all, and the present invention However, it can be easily verified, and when the frequency is increased by 4 times, the area is only equivalent to 100MHz, and the advantage is quite obvious.
  • the present invention correspondingly provides a method for parallel BCH coding, which is illustrated by
  • Encoder implementation shown in 2 including:
  • Step S601 the input sequence ⁇ m(pl), m(p-2), m(0) ⁇ of the current cycle is respectively subjected to an exclusive OR operation corresponding to the output high bit of the previous cycle of the register, and the operation result is output as a selection signal.
  • P constant polynomials ⁇ (x r «0) mod g(x), (x r «l) mod g(x), .... , (xr «(pl)) mod g(x ) ⁇ Select in order with 0, and select the result as the first output.
  • This step is implemented by selector 30, XOR gate 40, and register 10.
  • Step S602 the output of the previous cycle of the register is shifted to the high-order bit P bit as the second output. This step is implemented by register 10.
  • Step S603 the first output and the second output perform a Galois field summation output to the register as an output of the current period of the register. This step is implemented by the register 10 and the adder 20.
  • step S604 the above steps are subjected to a specific number of operations to obtain a final encoded output.
  • the present invention also provides another circuit for parallel BCH encoding, the circuit comprising a residual module, a register, and an adder of a Galois field connected to the remainder module and the register; in one clock cycle, The input of the circuit is a P bit information bit, and the information bit is input to the spare module as a first output, and the output of the previous cycle of the register is shifted to the high bit P bit as a second output; the first output is And the second output is summed with the Galois field, output to the register, and the result is stored in the register, and after a certain number of iterations, the final encoded output is obtained.
  • the specific number is determined by the length K of the input information data and the degree of parallelism P, and the specific number is the smallest integer not less than K/P.
  • the specific principle of the circuit for parallel BCH coding has been described in detail above, and therefore will not be described herein.
  • the present invention also provides another method for parallel BCH encoding, comprising: in one clock cycle, the input of the circuit is a P-bit information bit, and the information bit is input to the spare module as a first output; The output of one cycle is followed by the P bit of the high bit shift as a second output; the first output and the second output are summed by Galois field, output to a register, and the result is stored in the register; After a certain number of iterations, the final encoded output is obtained.
  • the specific principle of the method for parallel BCH coding has been described in detail above, and therefore will not be described herein.
  • the circuit, the encoder and the method for parallel BCH coding adopt an iterative algorithm, and use a table lookup method to select a constant polynomial, when the working level is high, compared with the conventional
  • the LFSR structure can effectively shorten the path, so that the timing performance of the circuit is better, and the LFSR structure can not meet the timing requirement because the t is too large when the clock frequency is increased.
  • the circuit is very simple, there are only a few selectors and some XOR gates, which greatly saves the area.
  • the invention can effectively shorten the path, thereby making the timing performance of the circuit better, and avoiding the situation that the LFSR structure can not meet the timing requirement due to the path being too long when the clock frequency is increased, and the area is saved.

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Abstract

本发明适用于纠错编码领域，提供了一种用于并行BCH编码的电路、编码器及方法，该方法包括：当前周期的输入序列{m(p-1)，m(p-2)，....，m(0)}按顺序分别与寄存器上一周期的输出高位对应进行异或运算，将运算结果作为选择信号输出至选择器，将P个常数多项式{(xr<<0) mod g(x)，(xr<<1) mod g(x)，....，(xr<<(p-1)) mod g(x)}按顺序分别与0进行选择，将选择结果与寄存器上一周期的输出向高位移位P位后输出进行求和输出至寄存器，作为寄存器当前周期的输出；经过特定数量次运算得到最终编码输出。借此，本发明可以有效缩短路径，使电路时序性能更好，节约面积。

Description

一种用于并行 BCH编码的电路、 编码器及方法 技术领域
本发明涉及纠错编码领域， 尤其涉及一种用于并行 BCH编码的电路、 编码 器及方法。 背景技术
BCH码作为一种重要的纠错编码方式， 在通信领域和消费电子领域得到了 广泛的应用。 BCH码取自 Bose、 Ray-Chaudhuri与 Hocquenghem的缩写， 是纠 正多个随机错误的循环码， 可以用生成多项式 g ( X ) 的根描述。 随着技术的发 展， 人们对 BCH的纠错能力的要求越来越高， 而这也使得人们对 BCH编解码 器的性能越来越敏感。 BCH的编码方式主要有两种， 一种是串行编码， 一种是 并行编码。 在对速度要求不高的场合通常使用串行编码， 因为串行编码的面积 最省。 而在速度要求很高的场合， 就需要采用并行编码方式了。
目前常用的并行编码方式是采用线性反馈移位寄存器（ LFSR )法进行 BCH 编码， 如图 1所示。 然而， 随着纠错能力的不断增强， 数据带宽不断增大， BCH 编码器所使用的并行 LFSR结构往往因为路径过长，会出现难以满足时钟频率的 情况。 专利申请 200810065971.9公开了 "用于并行 BCH编码的电路、 编码器及 方法" ， 采用一种并行迭代编码电路， 该电路包含若干个常数向量乘法器、 一 个常数矩阵乘法器以及一些异或门， 虽然较之 LFSR结构控制了电路的扇出，但 乘法器的面积仍然过大。
综上可知， 现有 BCH编码的电路在实际使用上， 显然存在不便与缺陷， 所以 有必要加以改进。 发明内容
针对上述的缺陷， 本发明的目的在于提供一种用于并行 BCH编码的电路、 编码器及方法， 能够有效的缩短路径， 从而使电路的时序性能更好， 避免了当 时钟频率增加时， LFSR结构由于路径太长而满足不了时序要求的情况， 同时节 约了面积。 为了实现上述目的， 本发明提供一种用于并行 BCH编码的电路， 包括 P个 输入支路、 寄存器以及与所述 P个支路和所述寄存器连接的伽罗华域的加法器，
P为并行度， 所述每个输入支路包括一选择器以及一异或门， 所述异或门的输出 作为选择器的选择信号， 所述选择器的输出为每个输入支路的输出；
当前周期的输入序列 {m(p-l), m(p-2), m(0)}按顺序分别与寄存器上一 周期的输出高位对应输入至 P个异或门，将异或门运算结果输出至选择器，将 P 个常数多项式 { (xr«0) mod g(x), (xr«l) mod g(x), .... , (xr«(p-l)) mod g(x)} 按顺序分别与 0输入至 P个选择器进行选择， 将选择结果作为第一输出；
将所述寄存器上一周期的输出向高位移位 P位后作为第二输出；
第一输出和第二输出进行伽罗华域求和输出至寄存器， 作为寄存器当前周 期的输出；
所述 P个支路、 加法器以及所述寄存器经过特定数量次运算， 得到最终编 码输出。
根据本发明的电路，特定数量由输入信息数据的长度 K和并行度 P来决定， 特定数量为不小于 K/P的最小整数。
本发明相应提供一种采用上述电路的编码器。
本发明相应提供一种用于并行 BCH编码的方法， 包括：
当前周期的输入序列 {m(p-l), m(p-2), m(0)}按顺序分别与寄存器上一 周期的输出高位对应进行异或运算， 将运算结果作为选择信号输出至选择器， 将 P个常数多项式 { (xr«0) mod g(x), (xr«l) mod g(x), .... , (xr«(p-l)) mod g(x)} 按顺序分别与 0进行选择， 将选择结果作为第一输出；
将所述寄存器上一周期的输出向高位移位 P位后作为第二输出；
第一输出和第二输出进行伽罗华域求和输出至寄存器， 作为寄存器当前周 期的输出；
上述步骤经过特定数量次运算， 得到最终编码输出。
根据本发明的方法，特定数量由输入信息数据的长度 K和并行度 P来决定， 特定数量为不小于 K/P的最小整数。
本发明还提供一种用于并行 BCH编码的电路， 包括求余模块、 寄存器以及 与所述求余模块和所述寄存器连接的伽罗华域的加法器； 在一个时钟周期内， 电路的输入为 P位的信息位， 信息位输入所述求余模块后作为第一输出， 同时 将寄存器上一周期的输出向高位移位 P位后作为第二输出； 将所述第一输出和 第二输出进行伽罗华域求和， 输出至寄存器中， 并将结果存入所述寄存器中， 经过特定数量次迭代后， 得到最终编码输出。
根据本发明的电路，特定数量由输入信息数据的长度 K和并行度 P来决定， 特定数量为不小于 K/P的最小整数。
本发明还相应提供一种采用上述电路的编码器。
本发明还相应提供一种用于并行 BCH编码的方法， 包括：
在一个时钟周期内， 电路的输入为 P位的信息位， 信息位输入所述求余模 块后作为第一输出； 将寄存器上一周期的输出向高位移位 P位后作为第二输出； 将所述第一输出和第二输出进行伽罗华域求和， 输出至寄存器中， 并将结果存 入所述寄存器中； 上述步骤经过特定数量次迭代后， 得到最终编码输出。
根据本发明的方法，特定数量由输入信息数据的长度 K和并行度 P来决定， 特定数量为不小于 K/P的最小整数。
本发明提供的用于并行 BCH编码的电路、 编码器及方法采用了迭代算法， 利用查表的方式来对常数多项式进行选择， 当工作平频率很高时， 较之于传统 的 LFSR结构， 可以有效的缩短路径， 从而使电路的时序性能更好， 避免了当时 钟频率增加时， LFSR结构由于 t太大而满足不了时序要求的情况。 同时由于电 路非常筒单， 只有几个选择器和一些异或门， 从而大大节约了面积。 借此， 本 发明可以有效的缩短路径， 从而使电路的时序性能更好， 避免了当时钟频率增 加时， LFSR结构由于路径太长而满足不了时序要求的情况， 同时节约了面积。 附图说明
图 1是传统串行 LFSR结构的 BCH编码器的电路图；
图 2是本发明一种用于并行 BCH编码的电路的原理结构图；
图 3是本发明一种用于并行 BCH编码的电路一种具体实施例的结构框图； 图 4是本发明一种用于并行 BCH编码的电路的逻辑图；
图 5是本发明一种用于并行 BCH编码的电路中输入求余模块的结构框图； 图 6是本发明一种用于并行 BCH编码的方法的流程图。 具体实施方式 为了使本发明的目的、 技术方案及优点更加清楚明白， 以下结合附图及实 施例， 对本发明进行进一步详细说明。 应当理解， 此处所描述的具体实施例仅 仅用以解释本发明， 并不用于限定本发明。
如图 2和图 3所示， 本发明一种用于并行 BCH编码的电路， 用于编码器， 其包括 P个输入支路、 寄存器 10以及与 P个输入支路和寄存器 10连接的伽罗 华域的加法器 20。 其中， P为并行度， 每个输入支路包括一选择器 30以及一异 或门 40, 异或门 40的输出作为选择器 30的选择信号， 通过选择信号控制选择 器 30的输出， 选择器 30的输出为每个输入支路的输出。
当前周期的输入序列 {m(p-l), m(p-2), m(0)}按顺序分别与寄存器 10 上一周期的输出高位对应输入至 P个异或门 40,将异或门 40运算结果输出至选 择器 30,将 P个常数多项式 { (xr«0) mod g(x), (xr«l) mod g(x), .... , (xr«(p-l)) mod g(x)}按顺序分别与 0输入至 P个选择器 30进行选择，将选择结果作为第一 输出； 将寄存器 10上一周期的输出向高位移位 P位后作为第二输出； 第一输出 和第二输出进行伽罗华域求和输出至寄存器 10 ,作为寄存器 10当前周期的输出； P个支路、 加法器 20以及寄存器 10经过特定数量次运算， 得到最终编码输出。 特定数量由输入信息数据的长度 κ和并行度 P来决定， 特定数量为不小于 K/P 的最小整数。
本发明采用了迭代算法， 利用查表的方式来对常数多项式进行选择， 当工 作平频率很高时， 较之于传统的 LFSR结构， 可以有效的缩短路径， 从而使电路 的时序性能更好， 避免了当时钟频率增加时， LFSR结构由于 t太大而满足不了 时序要求的情况。 同时由于电路非常筒单， 只有几个选择器和一些异或门， 从 而大大节约了面积。 借此， 本发明可以有效的缩短路径， 从而使电路的时序性 能更好， 避免了当时钟频率增加时， LFSR结构由于路径太长而满足不了时序要 求的情况， 同时节约了面积。
本发明的具体设计原理如下：
殳码长为 n, k bit的信息位输入为：
m(x)=m(k- l)xk l+m(k-2)xk 2+ +m(l)x+m(0), 生成多项式为 g(x), 输出的 r=n-k bit校验位为 d(x), 那么根据 BCH的编码原理， 有：
m(x)*xr = b*g(x)+d(x) ( Al ) 其中， b为 m(x)*xr被 g(x)整除之后的商 , d(x)为余。 将 m(x)代入, 得： (m(k-l)xk l+m(k-2)xk 2+ +m(l)x+m(0)) * xr = b*g(x)+d(x)
m(k-l) xr xk l+m(k-2) xr xk"2+ +m(l) xr x+m(0) xr = b*g(x)+d(x) ( A2 ) 求校验位的过程也就是对上式 (A2)左端对 g(x)求余的过程。 因此，校验位可 由下式求得：
d(x) = (m(k-l) xr xk l + m(k-2) xr xk"2 + + m(l) xr x + m(0) xr) mod g(x)
( A3 ) 假设并行系数为 p, 上式 (A3)转换为：
d(x) = ( ((m(k-l) xr xp l + m(k-2) xr xp"2 + ... + m(k-p) xr ) * xp + m(k-p-l) xr xp l + m(k-p-2) xr xp"2 + ... + m(k-p-p) xr) * xp + + m(p-l) xr xp l + m(p-2) xr xp"2 + ... + m(0) xr) mod g(x) ( A4 ) 假设 s(a) = m(k-a-l) xr xp + m(k-a-2) xr xp"2 + ... + m(k-a-p) xr, 则上式 ( A4 ) 可写为：
d(x) = ( ...... (s(0) * xp + s(p)) * xp + + s(k-p)) mod g(x)
= ( ((s(0) * xp ) mod g(x) + s(p) mod g(x)) * xp ) mod g(x) + + s(k-p) mod g(x)) mod g(x)
=( ((s(0) mod g(x) * xp ) mod g(x) + s(p) mod g(x)) * xp ) mod g(x) + + s(k-p) mod g(x)) mod g(x) ( A5 ) 又假设 t(a) = s(a) mod g(x), 则上式可写成：
d(x) = ((....(( ((t(0) « p) mod g(x)) + t(p) ) « p) mod g(x) + ..... ) mod g(x) ) + t(k-p) ( A6 ) 该式（A6 )可以转换为如图 4所示的电路。 式（A6 )中， t(x)为寄存器中的 值， 在一个时钟周期内， 电路的输入为 p bit的信息位， 信息位通过输入求余模 块 50后作为第一输出； 同时，将寄存器上一周期的输出向高位移位 p bit之后并 对生成多项式求余的结果作为第二输出； 两个输出一起做伽罗华域求和， 输出 至寄存器中， 将结果存入寄存器中， 如此迭代一定次数后， 将所有的 k bit信息 位输入后的寄存器输出即校验位， 也就是 BCH编码器结果。 由此， 编码的过程 就转换为对多项式求余的过程， 即 t(a) = s(a) mod g(x), 也就是设计输入求余模 块 50, 将 s(a)多项式代入 t(a)中得：
t(a) = s(a) mod g(x)
= (m(k-a-l) xr xp— 1 + m(k-a-2) xr xp— 2 + ... + m(k-a-p) xr) mod g(x)
= ((m(k-a-l) xr xp— 1 ) mod g(x) + (m(k-a-2) xrxp"2) mod g(x) + ... + (m(k-a-p) xr ) mod g(x)) mod g(x)
= (m(k-a-l) * ((xr « (p-1)) mod g(x)) + m(k-a-2) * ((xr « (p-2)) mod g(x)) + ... + m(k-a-p) * xr) ( A7 ) 公式的推算过程用到了求余运算的运算法则， 同时结合了伽罗华域中的运 算法则。 这样， 将上述多项式（A7 )运算转化为电路， 如图 5所示。 该电路在 一个时钟周期内输入 p个 bit, 分别为 {m(p-l), m(p-2), m(0)}， 它们作为 各个选择器的选择信号； 各个选择器的有一个输入是相同的， 为 0, 另一个输入 则各不相同， 分别是（xr«0) mod g(x), (xr«l) mod g(x), .... , (xr«(p-l)) mod g(x)这 p个多项式 艮明显，这 p个多项式在纠错能力确定之后都是常数多项式。 并且， 在图 4中， （dout«p) mod g(x)可以利用前面的这 p个常数多项式来进行 计算：
(dout«p) mod g(x) = (dout[r-l]&( (xr«(p-l)) mod g(x) )) +
(dout[r-2]&( (xr«(p-2)) mod g(x) )) + +(dout[r-p]&( (xr«0) mod g(x) ))
+ {dout[r-p-l:0] , p'bO}
也就是将寄存器输出值的高 p位拎出来与下个周期的输入一起作为 p个常 数多项式的选择信号， 同时，寄存器的输出值进行算术左移 p位（向高位移位）， 左移出来的结果与各个选择器的输出结果一起进行伽罗华域相加输入寄存器 中， 从而得到最终的编码结果。
综上， 将图 4和图 5相结合即可构成整个 BCH编码器， 假设信息为长度为 k, 电路并行度为 p, 那么迭代 k/p次后， 寄存器的输出值即为校验位输出， 如 图 3所示。 若 k不能被 p整除， 那么最后一个时钟周期的 p bit的输入中， 低位 填 0即可， 具体实施方案为：
1、 外部发出复位信号， 将寄存器清零。
2、 输入序列 {m(p-l), m(p-2), m(0)}按顺序作为选择信号之一输入编 码器中的各个选择器中， 选择器的另一个选择信号为上一周期寄存器的输出高 位。
3、将寄存器上一周期的输出向高位移位 p bit之后的结果作为第二输出； 两 个输出一起做伽罗华域求和， 输出至寄存器中。
4、 将 2、 3 过程不断循环， 每个周期都会更新寄存器中的值， 并参与下一 个周期的运算， 直到所有的信息位输入完成， 这样串行输出寄存器中的值， 添 加到输入的信息序列之后就得到了 BCH编码后的码字。
经过实验证明，本发明可以在 400MHz的频率下并行 16路进行工作。同时， 因为机理与原来的 LFSR不一样， 工作频率越高，相对于 LFSR结构的优势越明 显， 如表 1所示。 表 1示意出了当信息位长为 2KB, 纠错能力为 80时本发明与 传统并行 LFSR结构的性能比较。 在同样的条件下分析， 工作频率为 100MHz, 本发明的面积只是稍优于 LFSR结构， 但若将工作频率增大到 400MHz, 传统的 并行 16路的 LFSR结构根本无法通过时序验证， 而本发明却能轻松通过验证， 并且在频率增大了 4倍的情况下， 面积仅与 100MHz时相当， 优势相当明显。
表 1
Figure imgf000009_0001
如图 6所示， 本发明相应提供一种用于并行 BCH编码的方法， 其通过如图
2所示的编码器实现， 包括：
步骤 S601 , 当前周期的输入序列 {m(p-l), m(p-2), m(0)}按顺序分别 与寄存器上一周期的输出高位对应进行异或运算， 将运算结果作为选择信号输 出至选择器， 将 P个常数多项式 { (xr«0) mod g(x), (xr«l) mod g(x), .... , (xr«(p-l)) mod g(x)}按顺序分别与 0进行选择， 将选择结果作为第一输出。 本 步骤通过选择器 30、 异或门 40以及寄存器 10实现。
步骤 S602, 将寄存器上一周期的输出向高位移位 P位后作为第二输出。 本 步骤通过寄存器 10实现。
步骤 S603, 第一输出和第二输出进行伽罗华域求和输出至寄存器， 作为寄 存器当前周期的输出。 本步骤通过寄存器 10以及加法器 20实现。
步骤 S604, 上述步骤经过特定数量次运算， 得到最终编码输出。 本发明还提供另一种用于并行 BCH编码的电路， 该电路包括求余模块、 寄 存器以及与所述求余模块和所述寄存器连接的伽罗华域的加法器； 在一个时钟 周期内， 电路的输入为 P位的信息位， 信息位输入所述求余模块后作为第一输 出， 同时将寄存器上一周期的输出向高位移位 P位后作为第二输出； 将所述第 一输出和第二输出进行伽罗华域求和， 输出至寄存器中， 并将结果存入所述寄 存器中， 经过特定数量次迭代后， 得到最终编码输出。 特定数量由输入信息数 据的长度 K和并行度 P来决定， 特定数量为不小于 K/P的最小整数。 该用于并 行 BCH编码的电路的具体原理已在前文做详细描述， 故在此不再赘述。
本发明还提供另一种用于并行 BCH编码的方法，包括：在一个时钟周期内， 电路的输入为 P位的信息位， 信息位输入所述求余模块后作为第一输出； 将寄 存器上一周期的输出向高位移位 P位后作为第二输出； 将所述第一输出和第二 输出进行伽罗华域求和， 输出至寄存器中， 并将结果存入所述寄存器中； 上述 步骤经过特定数量次迭代后， 得到最终编码输出。 该用于并行 BCH编码的方法 的具体原理已在前文做详细描述， 故在此不再赘述。
综上所述， 本发明提供的用于并行 BCH编码的电路、 编码器及方法采用了 迭代算法， 利用查表的方式来对常数多项式进行选择， 当工作平频率很高时， 较之于传统的 LFSR结构， 可以有效的缩短路径， 从而使电路的时序性能更好， 避免了当时钟频率增加时， LFSR结构由于 t太大而满足不了时序要求的情况。 同时由于电路非常筒单， 只有几个选择器和一些异或门， 从而大大节约了面积。 借此， 本发明可以有效的缩短路径， 从而使电路的时序性能更好， 避免了当时 钟频率增加时， LFSR结构由于路径太长而满足不了时序要求的情况， 同时节约 了面积。
当然， 本发明还可有其它多种实施例， 在不背离本发明精神及其实质的情况 些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims

权利要求书
1、 一种用于并行 BCH编码的电路， 其特征在于， 包括 P个输入支路、 寄 存器以及与所述 P个支路和所述寄存器连接的伽罗华域的加法器， P为并行度， 所述每个输入支路包括一选择器以及一异或门， 所述异或门的输出作为选择器 的选择信号， 所述选择器的输出为每个输入支路的输出；
当前周期的输入序列 {m(p-l), m(p-2), m(0)}按顺序分别与寄存器上一 周期的输出高位对应输入至 P个异或门，将异或门运算结果输出至选择器，将 P 个常数多项式 { (xr«0) mod g(x), (xr«l) mod g(x), .... , (xr«(p-l)) mod g(x)} 按顺序分别与 0输入至 P个选择器进行选择， 将选择结果作为第一输出；
将所述寄存器上一周期的输出向高位移位 P位后作为第二输出；
第一输出和第二输出进行伽罗华域求和输出至所述寄存器， 作为所述寄存 器当前周期的输出；
所述 P个支路、 加法器以及所述寄存器经过特定数量次运算， 得到最终编 码输出。
2、根据权利要求 1所述的电路， 所述特定数量由输入信息数据的长度 K和 并行度 P来决定， 特定数量为不小于 K/P的最小整数。
3、 一种采用如权利要求 1或 2所述电路的编码器。
4、 一种用于并行 BCH编码的方法， 其特征在于， 包括：
当前周期的输入序列 {m(p-l), m(p-2), m(0)}按顺序分别与寄存器上一 周期的输出高位对应进行异或运算， 将运算结果作为选择信号输出至选择器， 将 P个常数多项式 { (xr«0) mod g(x), (xr«l) mod g(x), .... , (xr«(p-l)) mod g(x)} 按顺序分别与 0进行选择， 将选择结果作为第一输出；
将所述寄存器上一周期的输出向高位移位 P位后作为第二输出；
第一输出和第二输出进行伽罗华域求和输出至所述寄存器， 作为所述寄存 器当前周期的输出；
上述步骤经过特定数量次运算， 得到最终编码输出。
5、根据权利要求 4所述的方法， 所述特定数量由输入信息数据的长度 K和 并行度 P来决定， 特定数量为不小于 K/P的最小整数。
6、 一种用于并行 BCH编码的电路， 其特征在于， 包括输入求余模块、 寄 存器以及与所述求余模块和所述寄存器连接的伽罗华域的加法器； 在一个时钟周期内， 电路的输入为 P位的信息位， 信息位输入所述求余模 块后作为第一输出， 同时将所述寄存器上一周期的输出向高位移位 P位后作为 第二输出；
将所述第一输出和第二输出进行伽罗华域求和， 输出至所述寄存器中， 并 将结果存入所述寄存器中， 经过特定数量次迭代后， 得到最终编码输出。
7、根据权利要求 6所述的电路， 所述特定数量由输入信息数据的长度 K和 并行度 P来决定， 特定数量为不小于 K/P的最小整数。
8、 一种采用如权利要求 6或 7所述电路的编码器。
9、 一种用于并行 BCH编码的方法， 其特征在于， 包括：
在一个时钟周期内， 电路的输入为 P位的信息位， 信息位输入所述求余模 块后作为第一输出；
将寄存器上一周期的输出向高位移位 P位后作为第二输出；
将所述第一输出和第二输出进行伽罗华域求和， 输出至寄存器中， 并将结 果存入所述寄存器中；
上述步骤经过特定数量次迭代后， 得到最终编码输出。
10、 根据权利要求 9所述的方法， 特定数量由输入信息数据的长度 K和并 行度 P来决定， 特定数量为不小于 K/P的最小整数。
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CN104320145A (zh) * 2014-10-29 2015-01-28 中国科学院微电子研究所 (15,7)bch码的编码电路设计方法
RU2601827C1 (ru) * 2015-06-10 2016-11-10 Открытое акционерное общество Научно-производственный центр "Электронные вычислительно-информационные системы" Реконфигурируемый кодер бчх кодов
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CN111446974A (zh) * 2019-01-16 2020-07-24 南京大学 一种低复杂度低延迟的gii-bch编码器硬件架构
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