JP2018500770A5 - - Google Patents
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- JP2018500770A5 JP2018500770A5 JP2017533823A JP2017533823A JP2018500770A5 JP 2018500770 A5 JP2018500770 A5 JP 2018500770A5 JP 2017533823 A JP2017533823 A JP 2017533823A JP 2017533823 A JP2017533823 A JP 2017533823A JP 2018500770 A5 JP2018500770 A5 JP 2018500770A5
- Authority
- JP
- Japan
- Prior art keywords
- hole
- dielectric layer
- laminate structure
- conductive foil
- less
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000011888 foil Substances 0.000 claims 14
- 239000000463 material Substances 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 2
- 230000000149 penetrating Effects 0.000 claims 2
- 238000007747 plating Methods 0.000 claims 2
- 238000005553 drilling Methods 0.000 claims 1
- 238000001035 drying Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 239000011148 porous material Substances 0.000 claims 1
Claims (15)
少なくとも1つの誘電体層と前記誘電体層の第1側部上の第1導電箔とを具える積層体構造を形成するステップと;
前記誘電体層の第2側部から前記第1導電箔に向けて延在し、前記誘電体層を少なくとも部分的に通る貫通していない孔または止まり孔を、前記積層体構造内に形成するステップであって、前記孔の深さと直径のアスペクト比が、20対1未満であり、前記孔が、125度より大きい孔下部先端角を有する、ステップと;
前記孔内にビアフィルインクを堆積させるステップと;
前記ビアフィルインクを乾燥および/または硬化させてホールプラグを形成するステップと;
を具えることを特徴とする方法。 In the method of forming a hole plug:
Forming a laminate structure comprising at least one dielectric layer and a first conductive foil on a first side of the dielectric layer;
A non-penetrating hole or blind hole extending from the second side of the dielectric layer toward the first conductive foil and passing at least partially through the dielectric layer is formed in the laminate structure. a step, the aspect ratio of depth to diameter of the hole is 20: 1 than der is, the hole has a larger hole lower tip angle than 125 degrees, the steps;
Depositing via fill ink in the holes;
Drying and / or curing the viafill ink to form a hole plug;
A method characterized by comprising.
前記誘電体層の第2側部上に第2導電箔をさらに具えるように前記積層体構造を形成するステップを具え、前記第2導電箔が前記孔によって貫通していることを特徴とする方法。 The method of claim 1 further comprises:
Forming the laminate structure to further comprise a second conductive foil on the second side of the dielectric layer, wherein the second conductive foil is penetrated by the hole; Method.
前記第2誘電箔上に使い捨ての層をさらに具えるように前記積層体構造を形成するステップを具えることを特徴とする方法。 The method of claim 1 further comprises:
Forming said laminate structure to further comprise a disposable layer on said second dielectric foil.
ホールプラグ材料を通るめっきしたスルーホールを形成するステップを具えていることを特徴とする方法。 The method of claim 1 further comprises:
Forming a plated through hole through the hole plug material.
(a)10:1未満、
(b)5:1未満、
(c)3:1未満、または
(d)1:1未満
であることを特徴とする方法。 The method of claim 1, wherein the aspect ratio of the holes is:
(A) less than 10: 1,
(B) less than 5: 1,
(C) less than 3: 1 or (d) less than 1: 1.
少なくとも誘電体層と、前記誘電体層の第1側部上に第1導電箔とを具える積層体構造と;
前記積層体構造内に前記誘電体層の第2側部から前記第1導電箔に向けて延在する貫通していない孔、または止まり孔であって、深さ対直径のアスペクト比が20:1未満であり、125度より大きい孔下部先端角を有する貫通していない孔または止まり孔と;
前記孔内に堆積させてホールプラグを形成するビアフィルインクと;
を具えることを特徴とする積層体構造。 In a laminate structure with hole plugs:
A laminate structure comprising at least a dielectric layer and a first conductive foil on a first side of the dielectric layer;
A non-penetrating hole or blind hole extending from the second side of the dielectric layer to the first conductive foil in the laminate structure, wherein the aspect ratio of depth to diameter is 20 : 1 less der is, a hole or blind hole does not penetrate having pores greater lower tip angle than 125 degrees;
Via fill ink deposited in the hole to form a hole plug;
A laminate structure characterized by comprising:
第2導電箔が前記孔によって貫通していることを特徴とする積層体構造。 The laminate structure according to claim 12 further comprises:
A laminated structure characterized in that the second conductive foil penetrates through the hole.
前記ホールプラグ材料を通るめっきしたスルーホールを具えることを特徴とする積層体構造。 The laminate structure according to claim 12 further comprises:
A laminate structure comprising a plated through hole through the hole plug material.
誘電体層と、前記誘電体層の第1側部上の第1導電箔と、前記誘電体層の第2側部上の第2導電箔と、を具える積層体構造を形成するステップと;
前記第2導電箔を部分的に除去して前記第2導電箔上に開口部を形成し、前記誘電体層の一部を曝露するステップと;
レーザー穿孔を前記積層体構造の曝露部分を通して行い、前記第1導電箔に向けて延在し、前記誘電体層を少なくとも部分的に通る貫通していない孔または止まり孔を形成するステップであって、前記孔の深さと直径のアスペクト比が、20対1未満であるステップと;
前記孔内にビアフィルインクを堆積させるステップと;
前記ビアフィルインクを硬化させてホールプラグを形成するステップと;
を具えていることを特徴とする方法。 In the method of forming a hole plug:
Forming a laminate structure comprising: a dielectric layer; a first conductive foil on a first side of the dielectric layer; and a second conductive foil on a second side of the dielectric layer; ;
Partially removing the second conductive foil to form an opening on the second conductive foil and exposing a portion of the dielectric layer;
Performing laser drilling through an exposed portion of the laminate structure to form a non-through hole or blind hole extending toward the first conductive foil and at least partially through the dielectric layer, The aspect ratio of the depth and diameter of the holes is less than 20 to 1;
Depositing via fill ink in the holes;
Curing the via fill ink to form a hole plug;
A method characterized by comprising:
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201462096011P | 2014-12-23 | 2014-12-23 | |
US62/096,011 | 2014-12-23 | ||
US201462096817P | 2014-12-24 | 2014-12-24 | |
US62/096,817 | 2014-12-24 | ||
PCT/US2015/067736 WO2016106428A1 (en) | 2014-12-23 | 2015-12-28 | Hole plug for thin laminate |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018500770A JP2018500770A (en) | 2018-01-11 |
JP2018500770A5 true JP2018500770A5 (en) | 2019-02-14 |
Family
ID=56151554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017533823A Pending JP2018500770A (en) | 2014-12-23 | 2015-12-28 | Hole plug for thin laminate |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP3238512A4 (en) |
JP (1) | JP2018500770A (en) |
KR (1) | KR102594179B1 (en) |
CN (1) | CN107211539A (en) |
WO (1) | WO2016106428A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113964613B (en) * | 2021-12-16 | 2022-04-22 | 苏州浪潮智能科技有限公司 | Method, device and equipment for reducing stub of high-speed connector and readable medium |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02198193A (en) * | 1989-01-27 | 1990-08-06 | Hitachi Seiko Ltd | Method of holing printed board |
JPH03228396A (en) * | 1990-02-01 | 1991-10-09 | Toshiba Corp | Manufacture of multilayer printed circuit board |
JP2001274204A (en) * | 2000-03-24 | 2001-10-05 | Hitachi Cable Ltd | Bimetal substrate and bga structure |
JP2002344144A (en) * | 2001-03-14 | 2002-11-29 | Toppan Printing Co Ltd | Wiring board, method of multilayer the same and surface protective film |
JP2002319763A (en) * | 2001-04-24 | 2002-10-31 | Matsushita Electric Ind Co Ltd | Multilayer wiring board and its producing method |
JP2008103548A (en) * | 2006-10-19 | 2008-05-01 | Sumitomo Electric Ind Ltd | Multilayer printed wiring board, and its manufacturing method |
JP2012195389A (en) * | 2011-03-15 | 2012-10-11 | Fujitsu Ltd | Wiring board, wiring board unit, electronic equipment and wiring board manufacturing method |
CN103687342B (en) * | 2013-12-02 | 2016-08-31 | 广州美维电子有限公司 | A kind of printed circuit board with disconnected hole and preparation method thereof |
-
2015
- 2015-12-28 JP JP2017533823A patent/JP2018500770A/en active Pending
- 2015-12-28 EP EP15874375.7A patent/EP3238512A4/en active Pending
- 2015-12-28 WO PCT/US2015/067736 patent/WO2016106428A1/en active Application Filing
- 2015-12-28 CN CN201580075279.2A patent/CN107211539A/en active Pending
- 2015-12-28 KR KR1020177018501A patent/KR102594179B1/en active IP Right Grant
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