JP2018198273A - Circuit board, electronic device, and manufacturing method of circuit board - Google Patents

Abstract

To reduce the possibility of cracks that may occur around the opening of an interlayer connection via in an insulating layer in a circuit board having the interlayer connection via.SOLUTION: A circuit board includes a plurality of insulating layers laminated in a first direction, and at least one of the plurality of insulating layers includes an interlayer connection via in which a metal layer is formed on an inner peripheral wall of a hole penetrating in the first direction, and a slit extending from the opening side of the interlayer connection via to the inside of the hole in the first direction is formed in the metal layer.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a circuit board, an electronic device, and a method for manufacturing a circuit board.

  In order to increase the bonding strength between the via land and the via hole conductor, a technique for forming a slit or the like in the via land provided immediately above the via hole is known.

JP 2002-26520 A

  However, in the conventional technology as described above, in a circuit board including an interlayer connection via in which a metal layer is formed on the inner peripheral wall of a hole penetrating the insulating layer, it may occur around the opening of the interlayer connection via in the insulating layer. It is difficult to reduce the possibility of cracking. In the vicinity of the opening of the interlayer connection via in the insulating layer, stress is likely to concentrate due to the force received from the metal layer during pressurization and heating in the lamination process.

  Accordingly, in one aspect, an object of the present invention is to reduce the possibility of a crack that may occur around an opening of an interlayer connection via in an insulating layer in a circuit board including the interlayer connection via.

One aspect includes a plurality of insulating layers stacked in a first direction,
At least one of the plurality of insulating layers has an interlayer connection via in which a metal layer is formed on an inner peripheral wall of a hole penetrating in the first direction,
A circuit board is provided in which the metal layer is formed with a slit extending from the opening side of the interlayer connection via to the hole in the first direction.

  In one aspect, according to the present invention, in a circuit board having an interlayer connection via, it is possible to reduce the possibility of a crack that may occur around the opening of the interlayer connection via in the insulating layer.

It is explanatory drawing of the circuit board by one Example. It is a perspective view which shows a metal layer roughly. It is explanatory drawing of the stress relaxation function by a slit. It is explanatory drawing of the problem by a comparative example. FIG. 10 is an explanatory diagram of a process (No. 1) in the method for manufacturing the circuit board 10. FIG. 10 is an explanatory diagram of a process (No. 2) in the method for manufacturing the circuit board 10. FIG. 10 is an explanatory diagram of a process (No. 3) in the method for manufacturing the circuit board 10. FIG. 10 is an explanatory diagram of a process (No. 4) in the method for manufacturing the circuit board 10. FIG. 10 is an explanatory diagram of a process (No. 5) in the method for manufacturing the circuit board 10. FIG. 11 is an explanatory diagram of a process (No. 6) in the method for manufacturing the circuit board 10. FIG. 11 is an explanatory diagram of a process (No. 7) in the method for manufacturing the circuit board 10. FIG. 10 is an explanatory diagram of a process (No. 8) in the method for manufacturing the circuit board 10. FIG. 10 is an explanatory diagram of a process (No. 9) in the method for manufacturing the circuit board 10. FIG. 10 is an explanatory diagram of a process (No. 10) in the method for manufacturing the circuit board 10. FIG. 11 is an explanatory diagram of a process (No. 11) in the method for manufacturing the circuit board 10. It is explanatory drawing of the state of the site | part regarding the interlayer connection via | veer in the process of FIG. 5C. It is explanatory drawing of the state of the site | part regarding the interlayer connection via | veer in the process of FIG. 5D. It is explanatory drawing of the state of the site | part regarding the interlayer connection via | veer in the process of FIG. 5E. It is explanatory drawing of the state of the site | part regarding the interlayer connection via | veer in the process of FIG. 5F.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

  FIG. 1 is an explanatory diagram of a circuit board 10 according to an embodiment, and is a cross-sectional view schematically showing a structure of the circuit board 10 at the time of pressurization and heating in a lamination process. FIG. 1 shows a Z direction (an example of a first direction) representing a stacking direction, and hereinafter, the Z1 side is an upper side for the sake of explanation.

  The circuit board 10 is a multilayer circuit board that is manufactured by employing a batch lamination method. The circuit board 10 is provided in an electronic device, for example, and can be applied to a multilayer printed wiring board on which electronic components are mounted. The electronic devices are arbitrary, but are diverse, for example, smart phones, mobile phones, tablet terminals, desktop PCs (Personal Computers), notebook PCs, and the like.

  In the batch lamination method, an interlayer connection via is provided in an insulating layer, and the interlayer connection via is filled with a conductive paste to produce a single layer plate. Then, in the laminating step, a single-layer board having a desired number of layers is laminated, and pressurization / heating is performed, so that a multilayer circuit board connected between layers by a conductive paste is produced. FIG. 1 schematically shows an external force R related to the pressure applied to the circuit board 10 during pressurization / heating (vacuum heat press) in the lamination process. The pressure generated in the circuit board 10 during pressurization and heating is generated by an external force R applied in the stacking direction.

  As shown in FIG. 1, the circuit board 10 includes an insulating layer 1, a conductor portion 2, a resin layer 3, and an interlayer connection via 4.

  The insulating layer 1 is made of, for example, glass (glass plate). The insulating layer 1 may be formed of a brittle material such as a silicon wafer, a sapphire substrate, or a ceramic substrate in addition to glass. In the example shown in FIG. 1, the circuit board 10 includes three insulating layers 1, but the number of insulating layers 1 is arbitrary.

  The conductor part 2 forms wiring. In addition, the formation method and formation aspect of the conductor part 2 are arbitrary. For example, the conductor portion 2 may be formed around the opening of the interlayer connection via 4 as a via land.

  The resin layer 3 is formed between the insulating layers 1 in the stacking direction and functions as an adhesive layer. The resin layer 3 may be formed of a thermosetting resin such as epoxy or a thermoplastic resin such as polyimide.

  The interlayer connection via 4 is provided for each insulating layer 1. In the interlayer connection via 4, a metal layer 40 is formed on the inner peripheral wall of the hole 11 that penetrates the insulating layer 1 in the Z direction. The metal layer 40 is formed, for example, by plating copper. Details of the metal layer 40 will be described later. In addition, although the hole 11 is formed in circular equal cross section seeing to a Z direction, in the modification, the hole 11 may be formed in truncated cone shape by cross sectional view. In this case, the hole 11 has an opening diameter on one side of the upper and lower sides larger than the opening diameter on the other side. Further, the metal layer 40 may have a constant thickness in the Z direction, or the thickness may vary depending on the position in the Z direction.

  The hole 11 of the interlayer connection via 4 is filled with a conductor material that is the same as the metal of the metal layer 40 (copper in this embodiment) or has a lower elastic modulus than the metal of the metal layer 40. For example, the hole 11 of the interlayer connection via 4 is filled with a conductive paste. The material of the conductive paste is made of Sn, Ag, Cu, Bi or a metal compound containing at least one of these metals and a resin.

  FIG. 2 is a perspective view schematically showing the metal layer 40. In FIG. 2, as an example, the metal layer 40 is related to the portion X in FIG. 1.

  In the metal layer 40, a slit 42 extending from the opening side of the interlayer connection via 4 to the inside of the hole 11 is formed. That is, the slit 42 extends from the surface of the insulating layer 1 to the inner side (inner side in the Z direction). The slit 42 is in the form of a notch in which the opening side of the interlayer connection via 4 is opened. The slit 42 does not extend over the entire Z direction of the interlayer connection via 4, and may extend only to a portion of the opening side of the interlayer connection via 4 in the Z direction, or the interlayer connection via 4. May extend over the entire Z direction.

  The slits 42 may be respectively formed in openings on both sides of the interlayer connection via 4 in the Z direction. For example, in the example shown in FIG. 1, the insulating layer 1 of the intermediate layer has slits on the bonding side with the lowermost insulating layer 1 and the uppermost insulating layer 1, that is, on both the upper and lower openings. 42 may be formed. In addition, although the resin which concerns on the resin layer 3 is filled in the space of the slit 42, it replaces with this resin and the conductive paste and other resin may be filled in the space of the slit 42.

  As will be described later, the slit 42 has a stress relaxation function for reducing stress generated around the opening of the interlayer connection via 4 in the insulating layer 1 (edge of the opening). The slits 42 are preferably formed at a plurality of locations along the circumferential direction of the inner peripheral wall of the hole 11 in order to enhance the stress relaxation function. For example, in the example shown in FIG. 2, four slits 42 are provided for one opening. When a plurality of slits 42 are formed, they may be formed at equal intervals along the circumferential direction of the inner peripheral wall of the hole 11. In this case, the slits 42 are formed at diagonal positions in the opening of the interlayer connection via 4. Further, the slit 42 preferably has a curved outer shape when viewed in the radial direction of the inner peripheral wall of the hole 11 as shown in FIG. That is, the slit 42 preferably has a structure without an acute angle portion.

  FIG. 3 is an explanatory diagram of the stress relaxation function by the slit 42. FIG. 4 is an explanatory diagram of a problem caused by the comparative example, and is a cross-sectional view schematically showing the structure of the circuit board 10A at the time of pressurization and heating in the lamination process.

  The circuit board 10A according to the comparative example is different from the circuit board 10 according to the present embodiment in that the interlayer connection via 4 is replaced with the interlayer connection via 4A. The interlayer connection via 4A according to the comparative example is different from the interlayer connection via 4 according to the present embodiment in that the metal layer 40 is replaced with a metal layer 40A. The metal layer 40A has a slit 42 with respect to the metal layer 40. There is no difference.

By the way, as shown in FIG. 1, pressure is applied to the circuit board 10 in the vertical direction at the time of pressurization and heating (vacuum heat pressing) in the laminating process. For example, the vacuum hot press is performed at a temperature of 200 ° C. and a pressure of 30 kg / cm ² . At this time, force (force in the compression direction) is applied to the metal layer 40 from both sides in the Z direction.

  In this regard, in the comparative example, the stress generated around the opening of the interlayer connection via 4A in the insulating layer 1 (the edge of the opening) is relatively large, and the crack C1 is likely to occur as schematically shown in FIG. Specifically, when the metal layer 40A receives a force from both sides in the Z direction, the metal layer 40A tends to be deformed in a radially expanding direction, but the radially outer side is surrounded by the insulating layer 1 (glass). However, stress concentration occurs at the edge of the opening of the interlayer connection via 4 </ b> A in the insulating layer 1. As a result, the crack C1 is likely to occur.

  On the other hand, according to the present embodiment, since the metal layer 40 of the interlayer connection via 4 has the slit 42, the possibility that a crack such as the crack C1 generated in the comparative example is generated can be reduced. Specifically, when the metal layer 40 receives a force from both sides in the Z direction, the metal layer 40 tends to deform in a direction spreading in the radial direction. At this time, since the metal layer 40 has the slit 42, the deformation in the radial direction is suppressed by the deformation in the circumferential direction as schematically shown by the arrow R2 in FIG. As a result, the stress at the portion where the interlayer connection via 4 and the insulating layer 1 are in contact is reduced, and the possibility of the occurrence of a crack such as the crack C1 generated in the comparative example can be reduced.

  Next, with reference to FIG. 5A thru | or FIG. 6D, the manufacturing method (manufacturing process) of the circuit board 10 is demonstrated.

  5A to 5K are explanatory diagrams of each step in the method for manufacturing the circuit board 10, and the direction from FIG. 5A to FIG. 5K corresponds to the direction approaching the product. 5A to 5K schematically show a cross-sectional view through a portion where the interlayer connection via 4 is formed. FIGS. 6A to 6D are diagrams showing states of portions related to the interlayer connection via 4 according to some processes, in which the left side is a top view and the right side is a perspective view. 6A to 6D correspond to FIGS. 5C to 5F, respectively.

First, as shown in FIG. 5A, in order to form the hole 11 of the interlayer connection via 4, the glass 500 is drilled with a CO ₂ laser. The drilling is not limited to the CO ₂ laser, but may be realized by excimer laser, processing by etching, sand blasting, or the like.

  Next, as shown in FIG. 5B, a seed 501 is formed using electroless plating. Sputtering or the like may be used instead of electroless plating.

  Next, as illustrated in FIG. 5C, the dry film resist 502 is melted by, for example, vacuum lamination, and the dry film resist 502 is brought into close contact with the wall surface of the hole 11 related to the interlayer connection via 4. Instead of the dry film resist 502, a similar resist may be formed by coating a liquid resist by spin coating. As a result, as shown in FIG. 6A, the dry film resist 502 is formed so as to adhere to the wall surface on the inlet side of the hole 11 and cover the hole 11.

  Next, as shown in FIG. 5D, a pattern to be a slit 42 is formed in the dry film resist 502 attached to the wall surface of the hole 11 related to the interlayer connection via 4, and exposure and development are performed. The dry film resist 502 is formed in the shape of the slit 42. Thereby, as shown in FIG. 6B, a dry film resist 502 corresponding to the shape of the slit 42 is formed on the wall surface of the hole 11.

  Next, as shown in FIG. 5E, the metal layer 40 is formed on the wall surface of the hole 11 related to the interlayer connection via 4 and the conductor portion 2 to be a wiring is formed by electrolytic plating. As a result, as shown in FIG. 6C, a plating layer (metal layer 40) is formed in a region excluding the dry film resist 502 related to the slit 42 on the wall surface of the hole 11.

  Next, as shown in FIG. 5F, the seed layer is removed. Thereby, as shown to FIG. 6D, the metal layer 40 provided with the slit 42 is completed.

  Next, as shown in FIG. 5G, resin lamination is performed to form a resin layer 503 to be the resin layer 3. At this time, the space of the slit 42 is filled with resin.

  Next, as shown in FIG. 5H, a hole 504 is formed in the resin layer 503 in order to form the hole 11 related to the interlayer connection via 4.

  Next, as shown in FIG. 5I, paste printing is performed. That is, the conductive paste is filled in the holes 504 of the resin layer 503. Hereinafter, the glass 500 in which the conductive paste 505 is filled in the hole 504 of the resin layer is referred to as a “single layer plate 520”.

  Next, as shown in FIG. 5J, a plurality of single-layer plates 520 are prepared and laminated. As shown in FIG. 5J, the resin layer 503 is not formed on the upper side of the uppermost single-layer plate 520, and the resin layer 503 is formed on the lower side of the lowermost single-layer plate 520. It has not been.

  Next, the laminated single-layer plate 520 is pressed by a vacuum hot press (for example, 200 ° C., 90 minutes, 3 MPa). When the conductive paste 505 and the resin layer 503 are cured, a circuit board is completed.

  Thus, according to the present embodiment, the metal layer 40 including the slit 42 can be easily formed by forming the dry film resist 502 corresponding to the shape of the slit 42 on the wall surface of the hole 11.

  Although each embodiment has been described in detail above, it is not limited to a specific embodiment, and various modifications and changes can be made within the scope described in the claims. It is also possible to combine all or a plurality of the components of the above-described embodiments.

  For example, in the embodiment described above, all the interlayer connection vias 4 of the insulating layer 1 have the metal layer 40 having the slits 42, but this is not limitative. Only the interlayer connection vias 4 of some insulating layers 1 may have the metal layer 40 having the slits 42.

In addition, the following additional remarks are disclosed regarding the above Example.
[Appendix 1]
Including a plurality of insulating layers stacked in a first direction;
At least one of the plurality of insulating layers has an interlayer connection via in which a metal layer is formed on an inner peripheral wall of a hole penetrating in the first direction,
The circuit board, wherein the metal layer is formed with a slit extending from the opening side of the interlayer connection via to the hole in the first direction.
[Appendix 2]
The circuit board according to appendix 1, wherein the plurality of insulating layers are formed of glass.
[Appendix 3]
The circuit board according to appendix 1 or 2, wherein the slit is formed at a plurality of locations along the circumferential direction of the inner peripheral wall.
[Appendix 4]
The circuit board according to any one of appendices 1 to 3, wherein the hole of the interlayer connection via is filled with a conductive material having a lower elastic modulus than the metal of the metal layer.
[Appendix 5]
The circuit board according to any one of appendices 1 to 4, wherein the slit has a curved outer shape when viewed in a radial direction of the inner peripheral wall.
[Appendix 6]
An electronic device comprising a circuit board,
The circuit board includes a plurality of insulating layers stacked in a first direction,
At least one of the plurality of insulating layers has an interlayer connection via in which a metal layer is formed on an inner peripheral wall of a hole penetrating in the first direction,
The electronic device, wherein the metal layer is formed with a slit extending from the opening side of the interlayer connection via to the hole in the first direction.
[Appendix 7]
Forming a hole penetrating the insulating layer in the first direction;
Attaching a resist to a region extending over the whole circumferential direction of the inner peripheral wall of the hole and into the hole;
Exposing and developing a portion of the resist along the circumferential direction of the inner peripheral wall of the hole; and
Plating the inner peripheral wall of the developed hole with metal;
Filling the hole with a conductive paste to form a single layer plate; and
Preparing a plurality of the single-layer plates filled with the conductive paste and laminating them.

DESCRIPTION OF SYMBOLS 1 Insulating layer 2 Conductor part 3 Resin layer 4 Interlayer connection via 10 Circuit board 11 Hole 40 Metal layer 42 Slit 500 Glass 501 Seed 502 Dry film resist 503 Resin layer 504 Hole 505 Conductive paste 520 Single layer board

Claims (5)

Including a plurality of insulating layers stacked in a first direction;
At least one of the plurality of insulating layers has an interlayer connection via in which a metal layer is formed on an inner peripheral wall of a hole penetrating in the first direction,
The circuit board, wherein the metal layer is formed with a slit extending from the opening side of the interlayer connection via to the hole in the first direction.   The circuit board according to claim 1, wherein the plurality of insulating layers are formed of glass.   The circuit board according to claim 1, wherein the slit is formed at a plurality of locations along a circumferential direction of the inner peripheral wall. An electronic device comprising a circuit board,
The circuit board includes a plurality of insulating layers stacked in a first direction,
At least one of the plurality of insulating layers has an interlayer connection via in which a metal layer is formed on an inner peripheral wall of a hole penetrating in the first direction,
The electronic device, wherein the metal layer is formed with a slit extending from the opening side of the interlayer connection via to the hole in the first direction. Forming a hole penetrating the insulating layer in the first direction;
Attaching a resist to a region extending over the whole circumferential direction of the inner peripheral wall of the hole and into the hole;
Exposing and developing a portion of the resist along the circumferential direction of the inner peripheral wall of the hole; and
Plating the inner peripheral wall of the developed hole with metal;
Filling the hole with a conductive paste to form a single layer plate; and
Preparing a plurality of the single-layer plates filled with the conductive paste and laminating them.

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