JP2018190483A5 - - Google Patents

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Publication number
JP2018190483A5
JP2018190483A5 JP2018089264A JP2018089264A JP2018190483A5 JP 2018190483 A5 JP2018190483 A5 JP 2018190483A5 JP 2018089264 A JP2018089264 A JP 2018089264A JP 2018089264 A JP2018089264 A JP 2018089264A JP 2018190483 A5 JP2018190483 A5 JP 2018190483A5
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JP
Japan
Prior art keywords
page
sequence
integrated circuit
pages
main memory
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2018089264A
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English (en)
Japanese (ja)
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JP2018190483A (ja
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Publication date
Priority claimed from US15/585,429 external-priority patent/US9905294B1/en
Application filed filed Critical
Publication of JP2018190483A publication Critical patent/JP2018190483A/ja
Publication of JP2018190483A5 publication Critical patent/JP2018190483A5/ja
Pending legal-status Critical Current

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JP2018089264A 2017-05-03 2018-05-07 低キュー深度環境における、ｎレベルのｎａｎｄ型フラッシュセルのプログラミング Pending JP2018190483A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/585,429 US9905294B1 (en) 2017-05-03 2017-05-03 Writing logically offset pages of data to N-level memory cells coupled to a common word line
US15/585,429 2017-05-03

Publications (2)

Publication Number Publication Date
JP2018190483A JP2018190483A (ja) 2018-11-29
JP2018190483A5 true JP2018190483A5 (enExample) 2019-02-28

Family

ID=61225806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018089264A Pending JP2018190483A (ja) 2017-05-03 2018-05-07 低キュー深度環境における、ｎレベルのｎａｎｄ型フラッシュセルのプログラミング

Country Status (5)

Country Link
US (1) US9905294B1 (enExample)
JP (1) JP2018190483A (enExample)
KR (1) KR20180122565A (enExample)
CN (1) CN108806754B (enExample)
TW (1) TWI689926B (enExample)

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US10896002B2 (en) 2018-06-29 2021-01-19 Seagate Technology Llc Reverse directory structure in a garbage collection unit (GCU)
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US11403228B2 (en) * 2020-02-18 2022-08-02 Micron Technology, Inc. Memory device page program sequence
US11275687B2 (en) * 2020-07-07 2022-03-15 Micron Technology, Inc. Memory cache management based on storage capacity for parallel independent threads
US11783893B2 (en) * 2020-12-23 2023-10-10 Intel Corporation Utilizing NAND buffer for DRAM-less multilevel cell programming

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