JP2018182694A - Full differential amplifier circuit, and optical receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a full differential amplifier circuit which increases a gain, widens a band, and suppresses a circuit scale while suppressing an increase in power consumption; and an optical receiving circuit.SOLUTION: A full differential amplifier circuit is one which amplifies a pair of differential input signals input to a first differential input terminal 106a and a second differential input terminal 106b, and outputs the resultant signals from a first differential output terminal 107a and a second differential output terminal 107b. The full differential amplifier circuit comprises: a differential amplifying unit 101 for amplifying the pair of differential input signals to output the resultant signals to a pair of output nodes; a first inverter 102a and a first inductor 105a connected in series between one output node of the pair of output nodes, and the first differential output terminal, and having a first feedback circuit 104a; and a second inverter 102b and a second inductor 105b connected in series between the other output node of the pair of output node, and the second differential output terminal 107b, and having a second feedback circuit 104b.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a fully differential amplifier circuit and an optical receiver circuit, and more particularly to a fully differential amplifier circuit composed of a semiconductor integrated circuit and a light receiver circuit.

  BACKGROUND ART In recent years, with the increase in capacity of multimedia content due to the spread of the Internet, etc., technology development for large-capacity high-speed communication is in progress. The transmission of electrical signals exchanged between information communication devices such as servers and routers has also been proposed to apply an optical transmission technology using an optical fiber cable that is fast and has small transmission loss and reflection. In optical fiber transmission, although the transmission medium is light, a large number of integrated circuits are used in a transmitter / receiver that performs signal processing such as signal identification.

  FIG. 10 is a block diagram for explaining an optical receiving circuit that receives an optical signal and generates a pair of differential signals for signal processing. The light receiving circuit 29 of FIG. 10 is realized by a semiconductor integrated circuit, and is connected to a light receiving element 18 which receives an optical signal and generates a current signal according to the received intensity. The light receiving circuit 29 includes an input terminal 27 to which a current signal from the light receiving element 18 is input, and a light receiving circuit 29 having output terminals 28a and 28b for outputting a pair of differential signals. The light receiving circuit 29 further generates a reference voltage formed of a pre-amplifier 21 composed of an inverting amplifier 19 and a feedback resistor 20 for amplifying and converting a current signal from the light receiving element 18 into a voltage signal, a resistor 22 and a capacitor 23. A fully differential amplifier circuit 25 for comparing and amplifying the electric signal from the preamplifier 21 and the reference voltage of the reference voltage generator 24, and a limit amplifier 26 in which the fully differential amplifier circuits are connected in multiple stages. Configured

  In the optical receiver circuit 29 as shown in FIG. 10, integration technology by bipolar transistors has been mainly used so far, but high speed operation comparable to bipolar transistors can be realized by advances in MOS transistor technology. It became possible. As an example of the full differential amplification circuit required for the light receiving circuit, there is a full differential amplification circuit using an N channel MOS transistor shown in FIG.

  The fully differential amplifier circuit of FIG. 11 has sources connected in common, gates connected to input terminals 204a and 204b respectively, and N channel MOS transistors 201a and 201b forming a differential pair, and drains of N channel MOS transistors 201a and 201b. Are connected between load resistances 216a and 216b whose other ends are connected to the positive power supply terminal 211, and between the connection point of both sources of N channel MOS transistors 201a and 201b and the negative power supply terminal 212. The constant current source 203 includes signal output terminals 210a and 210b connected to the drains of the N channel MOS transistors 201a and 201b.

Looking at only one side of the differential pair of the fully differential amplification circuit of FIG. 11, it is a source ground circuit. Small signal voltage gain A _v of the source-grounded circuit when the load resistance and R _d can be expressed by the following equation (1).

The mutual conductance g _m of the MOS transistor is expressed by the following equation (2).

Here, μ represents the average electron mobility of the channel of the MOS transistor, C _ox represents the gate oxide film capacitance of the MOS transistor, L represents the channel length of the MOS transistor, and W represents the channel width of the MOS transistor. I _d represents the drain current of the MOS transistor, V _gs represents the gate-source voltage of the MOS transistor, and V _th represents the threshold voltage of the MOS transistor.

  On the other hand, optical fibers in optical fiber transmission are roughly classified into single mode fibers having a core diameter of 10 μm or less, and multimode fibers having a large core diameter of 50 μm or 62.5 μm. Since the multimode fiber has a large core diameter, it is easy to couple light with a light emitting element or a light receiving element, and has the feature of being able to be assembled at low cost.

  However, since the core diameter is large, a difference occurs in the light propagation path, and at the receiving end, it becomes a synthesized signal of the light having the delay difference, resulting in mode dispersion in which the signal waveform is blunt. As a method of compensating for this mode dispersion characteristic by an electronic circuit, a method of compensating for attenuation in a high frequency region of frequency characteristic has been proposed.

  In the attenuation compensation circuit that compensates for attenuation in the high frequency region, the fully differential amplifier circuit shown in FIG. 12 further includes a pair of load inductors 217a and 217b in addition to the elements of the fully differential amplifier circuit in FIG. In the fully differential amplification circuit shown in FIG. 12, a pair of load inductors 217a and 217b are inserted in series to the load resistors 216a and 216b, and peaking at high frequencies is used to expand the gain band. In the fully differential amplifier circuit of FIG. 12, the increase in impedance of the load inductors 17a and 17b at high frequencies is used to raise the load impedance to suppress the decrease in the gain of the fully differential amplifier circuit.

  In forming the inductor on the semiconductor integrated circuit, for example, as shown in FIG. 13, the wiring between Port 1 and Port 2 is formed into a spiral shape. FIG. 13 (a) shows the case where it is configured in a planar shape, and FIG. 13 (b) shows the case where a spiral is formed between upper and lower wiring layers using upper layer wiring, lower layer wiring and through holes. The inductance of the inductor is proportional to the area of the wiring.

  Patent Document 1 relates to a fully differential amplifier circuit, and a fully differential amplifier circuit using MOS transistors has been proposed. Patent Document 2 relates to a light receiving circuit, and a light receiving circuit has been proposed which receives a current signal converted from an optical signal by a light receiving element and outputs a differential voltage signal subjected to voltage conversion to a signal processing circuit in a subsequent stage. .

JP, 2005-72974, A JP, 2015-76652, A

  By the way, the fully differential amplification circuit 25 and the limit amplifier 26 used in the optical reception circuit 29 as shown in FIG. 10 require an input amplitude of about several hundreds of mV in the data identification circuit connected in the subsequent stage. You need to raise it.

  In order to increase the gain, there are a method of increasing the gain of all differential amplifier circuits alone and a method of connecting all differential amplifier circuits in multiple stages.

To increase the gain of the fully differential amplifier circuit alone, the total differential amplifier shown in FIG. 11, a method of increasing the resistance value of the load resistor is to increase the mutual conductance g _m. When the resistance value is increased, the area of the resistance is increased, the parasitic capacitance of the resistance is also increased, and the band is limited. In the method of increasing the transconductance g _m, it is necessary to increase the channel width W as shown in equation (2), limits the bandwidth increases parasitic capacitance of the transistor. In addition, when the voltage gain is increased, an increase in the gate-drain capacitance C _gd appears at the gate due to the Miller effect, and the band is limited.

Furthermore, as the fully differential amplifier circuit shown in FIG. 12, the load inductors 217a, when increasing the gain of the fully differential amplifier circuit to expand bandwidth 217b, an increase in the transconductance g _m parasitic capacitance of the transistor It becomes large and the bandwidth is limited. On the other hand, in the method of increasing the drain current I _d, the inductor shown in FIG. 13 (a) should increase the wiring width, the parasitic capacitance of the wiring is increased and the band is limited. For this reason, in the multistage connection of the fully differential amplifier circuit whose gain band is expanded by peaking with the load inductor shown in FIG. 12, the band can not be expanded sufficiently. On the other hand, since the multistage connection is made to increase the gain, the power consumption increases and the circuit scale becomes large.

  An object of the present invention is to provide an all-differential amplification circuit that increases gain, widens a band, and reduces the circuit size while suppressing an increase in power consumption, and an optical reception circuit.

In order to achieve the above object, a fully differential amplifier circuit according to the present invention amplifies a pair of differential input signals input to a first differential input terminal and a second differential input terminal to produce a first differential output. A fully differential amplifier circuit that outputs from the terminal and the second differential output terminal,
A differential amplification unit that amplifies the pair of differential output signals and outputs the amplified output to the pair of output nodes;
A first inverter and a first inductor serially connected between one of the pair of output nodes and the first differential output terminal;
A second inverter and a second inductor connected in series between another output node of the pair of output nodes and the second differential output terminal,
The first inverter has a first feedback path for feeding back the output to the input, and the second inverter has a second feedback path for feeding back the output to the input.

An optical receiver circuit according to the present invention includes the above-mentioned fully differential amplifier circuit,
A current signal converted from an optical signal is input, voltage converted, and a differential voltage signal is output.

  According to the present invention, it is possible to increase the gain, expand the band, and suppress the circuit scale while suppressing the increase in power consumption.

FIG. 2 is a circuit diagram for illustrating a fully differential amplifier circuit according to a high-level embodiment of the present invention. FIG. 1 is a circuit diagram for illustrating a fully differential amplifier circuit according to a first embodiment of the present invention. It is a basic composition figure of a negative feedback amplification circuit. It is a characteristic view which shows the frequency characteristic of the negative feedback amplifier circuit of FIG. It is a characteristic view showing the frequency characteristic of LC filter circuit. It is a characteristic view showing the frequency characteristic of the fully differential amplification circuit of an embodiment of the present invention. It is a circuit diagram for demonstrating the fully differential amplifier circuit by 2nd Embodiment of this invention. Is a fully differential amplification circuit. It is a circuit diagram for demonstrating the fully differential amplifier circuit by 3rd Embodiment of this invention. Is a fully differential amplification circuit. It is a circuit diagram for demonstrating the fully-differential amplifier circuit by 4th Embodiment of this invention. Is a fully differential amplification circuit. It is a block diagram for demonstrating an optical receiver circuit. FIG. 2 is a circuit diagram showing a general fully differential amplifier circuit. FIG. 5 is a circuit diagram illustrating a fully differential amplifier circuit having a load inductance. (A) And (b) is a shape figure of the spiral inductor on a semiconductor integrated circuit.

  Preferred embodiments of the present invention will be described in detail with reference to the drawings. Before describing specific embodiments of the present invention, embodiments according to the high-level concept of the present invention will be described. FIG. 1 is a circuit diagram for explaining a fully differential amplifier circuit according to a high-level embodiment of the present invention.

  The fully differential amplification circuit of FIG. 1 amplifies a pair of differential input signals input to the first differential input terminal 106 a and the second differential input terminal 106 b to generate a first differential output terminal 107 a and a second difference. This is a full differential amplifier circuit that outputs from the dynamic output terminal 107b. The first differential input terminal 106 a and the second differential input terminal 106 b are a pair of differential input terminals 106. The first differential output terminal 107 a and the second differential output terminal 107 b are a pair of differential output terminals 107.

  The fully differential amplifier circuit of FIG. 1 includes a differential amplifier unit 101 which amplifies the pair of differential output signals and outputs the amplified signal to the pair of output nodes. Furthermore, in the fully differential amplifier circuit of FIG. 1, the first inverter 102a and the first inductor 105a connected in series between the output node of one of the pair of output nodes and the first differential output terminal 107a. including. Furthermore, the fully differential amplification circuit of FIG. 1 includes a second inverter and a second inductor connected in series between the other output node of the pair of output nodes and the second differential output terminal 107b. ,including. The first inverter 102 a of FIG. 1 includes an inverter 103 a and a first feedback path 104 a that feeds back the output of the inverter 103 a to the input. The second inverter 102b of FIG. 1 includes an inverter 103b and a second feedback path 104b that feeds back the output of the inverter 103b to the input.

  According to the fully differential amplification circuit of the present embodiment, the first inverter 102a and the second inverter 102b connected to the output node of the differential amplification unit 101 have the first feedback path 104a that feeds back the output to the input. ing. This can realize high voltage gain. Further, it is possible to give peaking to the frequency characteristic and expand the band by the first inductor 105a at the rear stage of the first inverter 102a and the second inductor 105b at the rear stage of the second inverter 102b. Hereinafter, more specific embodiments of the present invention will be described.

First Embodiment
First, a fully differential amplifier circuit according to a first embodiment of the present invention will be described. FIG. 2 is a circuit diagram for explaining a fully differential amplifier circuit according to a first embodiment of the present invention. FIG. 3 is a basic configuration diagram of the negative feedback amplifier circuit. FIG. 4 is a characteristic diagram showing frequency characteristics of the negative feedback amplifier circuit of FIG. FIG. 5 is a characteristic diagram showing frequency characteristics of the LC filter circuit. FIG. 6 is a characteristic diagram showing frequency characteristics of the fully differential amplifier circuit according to the embodiment of the present invention.

[Description of configuration]
The present embodiment relates to an example in which the differential amplification unit of the full differential amplification circuit is configured to include an N channel MOS (Metal Oxide Semiconductor) transistor forming a differential pair. Referring to FIG. 2, in the fully differential amplification circuit according to the first embodiment, a pair of differential signals input to signal input terminals 4 a and 4 b as an example of a first differential input terminal and a second differential input terminal. This is a fully differential amplifier circuit that amplifies an input signal and outputs it from the signal output terminals 10a and 10b as an example of a first differential output terminal and a second differential output terminal.

  The fully differential amplifier circuit of FIG. 2 amplifies a pair of differential output signals and outputs the amplified signal to a pair of output nodes, an output node of one of the pair of output nodes, and a signal output terminal 10a. And a first inverter and a first inductor connected in series with each other. Furthermore, the fully differential amplifier circuit of FIG. 2 includes a second inverter and a second inductor connected in series between the other output node of the pair of output nodes and the signal output terminal 10b.

  The differential amplification unit 14 has sources connected in common, gates connected to the signal input terminals 4a and 4b, respectively, to form differential pairs of N channel MOS transistors 1a and 1b, and sources of a pair of N channel MOS transistors 1a and 1b. It includes a constant current source 3 connected between the common connection point and the negative power supply terminal 12, a pair of P-channel MOS transistors 2a and 2b whose gates are commonly connected, and a bias unit 13. Bias unit 13 includes a P-channel MOS transistor 2 c whose source is connected to positive power supply terminal 11 and whose gate and drain are commonly connected, and constant current source 5 whose one end is connected to negative power supply terminal 12.

  In the present embodiment, as an example of the first inverter and the second inverter, a pair of inverters 15a and 15b with feedback resistors are provided. In this embodiment, a pair of inductors 9a and 9b is provided as an example of the first inductor and the second inductor.

  Inverter 15a with a feedback resistor includes a P-channel MOS transistor 6a, an N-channel MOS transistor 7a, and a resistor 8a. In the inverter 15a with feedback resistance, the gate of the P channel MOS transistor 6a and the gate of the N channel MOS transistor 7a are connected and used as an input, and the drain of the P channel MOS transistor 6a and the drain of the N channel MOS transistor 7a are connected. It is an inverter which is used as an output, and a resistor 8a is connected as a feedback resistor between input and output. The inverter 15a with a feedback resistor may be hereinafter referred to as the inverter 15a.

  Inverter 15b with a feedback resistor includes a P channel MOS transistor 6b, an N channel MOS transistor 7b, and a resistor 8b. The gate of P channel MOS transistor 6b is connected to the gate of N channel MOS transistor 7b to be an input, and the drain of P channel MOS transistor 6b is connected to the drain of N channel MOS transistor 7b to be an output. The resistor 8 b is an inverter connected as a feedback resistor. The inverter 15b with a feedback resistor may be hereinafter referred to as the inverter 15b.

  One end of the pair of inductors 9a and 9b is connected to the output of the inverter with feedback resistor 15a and 15b, and the other end is connected to the signal output terminals 10a and 10b, respectively.

[Description of operation]
The operation of the fully differential amplifier of FIG. 2 will be described. In FIG. 2, P channel MOS transistors 2a and 2b of differential amplifier 14 constitute a pair of load transistors. The bias unit 13 of the differential amplification unit 14 applies a bias voltage to the gates of the P channel MOS transistors 2a and 2b. The P channel MOS transistor 2c of the bias unit 13 constitutes a current mirror circuit with the P channel MOS transistors 2a and 2b. In other words, in FIG. 2, the differential amplification unit 14 constitutes a differential pair of current mirror type current source loads composed of the bias unit 13 and the P channel MOS transistors 2 a and 2 b. If only one side of the differential pair is seen, it becomes a source ground circuit of the current source load.

Differential small signal gain _{A v} of the amplifier 14, the mutual conductance _{g mn} of N-channel MOS transistors 1a and N-channel MOS transistor 1b which constitute the differential pair, the on-resistance _{R on,} P-channel MOS current source load Assuming that the on resistance of the transistors 2a and 2b is R _op , it is expressed by the following equation (3).

Here, when the mutual conductance g _mn of the N channel MOS transistor forming the differential pair is determined, the process of channel length L of 28 nm is used, the power supply voltage is 0.9 V, the drain current I _d is 2 mA, and the threshold of the transistor _Assuming that the voltage V _th is 0.2 V and the gate-source voltage is 0.4 V, the following equation is obtained from the equation (2), and a large value can not be obtained.

Also, in the case of a power supply voltage of 0.9 V, the output amplitude can not be large. Assuming that the output amplitude is 0.3 V _pp , R _on // R _op is 150 Ω when the drain current I _d is 2 mA.

Therefore, the absolute value of the small signal gain A _V of the differential amplifier section, by the equation (3) is as follows, not take a large value.

Next, the operation of the inverter with feedback resistor 15a, 15b of this embodiment will be described. FIG. 3 shows the basic configuration of the negative feedback amplifier circuit. The negative feedback amplifier circuit of FIG. 3 includes one inverting amplifier circuit and a feedback path β. A is an amplification circuit configured using an active element, and β is usually composed of a passive element such as a resistor. The closed loop gain G _close of the negative feedback amplifier circuit is expressed by the following equation.

  Since the gain A of the amplification circuit has frequency characteristics, the frequency characteristics A (ω) is expressed by the following equation (5).

From the equations (4) and (5), the closed loop gain G _close becomes the following equation.

Therefore, the closed loop gain G _close is 1 / (1 + βA ₀ ) times the open loop gain A ₀ and the band is (1 + βA ₀ ) times. FIG. 4 shows the frequency characteristics of the negative feedback amplifier circuit. Here, a represents the frequency characteristic in the open loop and b represents the frequency characteristic in the closed loop.

  Next, a peaking circuit based on the inductors 9a and 9b at the rear stage of the inverters 15a and 15b with feedback resistors will be described.

When the fully differential amplification circuits shown in FIG. 2 are connected in multiple stages, an N channel MOS transistor forming a differential pair of the fully differential amplification circuits in the subsequent stages is provided downstream of the inductors 9a and 9b of one fully differential amplification circuit. 1a and 1b are further connected to each other. The parasitic capacitance of the gate-source capacitance C _{gs of} the transistor, the gate-drain capacitance C _gd , and the gate-substrate capacitance C _gb can be seen to construct an LC filter circuit.

  In general, the frequency characteristic of the LC filter circuit is expressed by the following equation (7).

  The gain decreases in the region where ω is sufficiently large, but the gain increases in the vicinity of ω = 1 / √ (LC). Here, when L is 100 pH and C is 100 fF, the peaking characteristic is obtained at about 50 GHz. FIG. 5 shows an example of the frequency characteristic of the LC filter circuit.

  From the above, the fully differential amplification circuit shown in FIG. 2 has a peaking circuit configuration including the differential amplification unit 14, the inverters 15a and 15b with feedback resistors, and the inductors 9a and 9b.

  The gain of the fully differential amplification circuit shown in FIG. 2 is determined by the resistors 8a and 8b connected between the input and the output of the inverters 15a and 15b with feedback resistors. The input voltages of the inverters 15a and 15b with feedback resistors are the constant current source 3 connected to the differential pair of the differential amplifier unit 14 and the constant current source of the bias unit 13 for the current source load of the differential amplifier unit 14 Adjusted at 5 and optimized.

  In the fully differential amplification circuit shown in FIG. 2, the inductance can be optimized in consideration of the parasitic capacitance of the post-stage circuit, and the frequency characteristics can be expanded flat.

[Description of effect]
FIG. 6 shows the frequency characteristics of the fully differential amplification circuit shown in FIG. Here, A is the frequency characteristic at the output point of the differential amplifier unit 14 of the full differential amplifier circuit of FIG. 2, B is the frequency characteristic at the output point of the inverter 15a with feedback resistor of FIG. The frequency characteristic in the output point (signal output terminal 10a) of a subsequent full differential amplifier circuit is shown. Further, in the fully differential amplification circuit shown in FIG. 2, the differential amplification unit 14 does not have to increase the gain, and therefore the current consumption can be reduced. Furthermore, when the inverters 15a and 15b with feedback resistors are configured to include MOS transistors as in the present embodiment, no steady current flows, so that the full differential amplifier circuit shown in FIG. 2 can realize low power consumption.

Second Embodiment
Next, a fully differential amplifier circuit according to a second embodiment of the present invention will be described. FIG. 7 is a circuit diagram for explaining a fully differential amplifier circuit according to a second embodiment of the present invention.

[Description of configuration]
The present embodiment relates to an example in which the differential amplification unit of the full differential amplification circuit is configured to include a P channel MOS transistor forming a differential pair. Referring to FIG. 7, the fully differential amplification circuit according to the second embodiment has signal input terminals 4 a and 4 b as an example of the first differential input terminal and the second differential input terminal as in the first embodiment. It is a fully differential amplifier circuit which amplifies a pair of differential input signals to be input and outputs the amplified signal from the signal output terminals 10a and 10b as an example of a first differential output terminal and a second differential output terminal.

  Similar to the first embodiment, the fully differential amplification circuit of FIG. 7 includes a differential amplification unit 14 that amplifies a pair of differential output signals and outputs the amplified signal to the pair of output nodes. Furthermore, the fully differential amplifier circuit of FIG. 7 includes a first inverter and a first inductor connected in series between the signal output terminal 10a and one of the pair of output nodes. Furthermore, the fully differential amplifier circuit of FIG. 7 includes a second inverter and a second inductor connected in series between the other output node of the pair of output nodes and the signal output terminal 10b.

  In this embodiment, in the differential amplification unit 14, the sources are commonly connected, the gates are respectively connected to the signal input terminals 4a and 4b, and the P channel MOS transistors 2a and 2b forming a differential pair, and a pair of P channel MOS transistors It includes a constant current source 3 connected between a source common connection point 2a and 2b and a positive power supply terminal 11, a pair of N channel MOS transistors 1a and 1b whose gates are commonly connected, and a bias unit 13. Bias unit 13 includes an N-channel MOS transistor 1 c whose source is connected to negative power supply terminal 12 and whose gate and drain are commonly connected, and constant current source 5 whose one end is connected to positive power supply terminal 11.

  The differential amplifier 14 shown in FIG. 7 is a differential pair of P channel MOS transistors 2a and 2b, as opposed to the differential pair of N channel MOS transistors 1a and 1b of the differential amplifier 14 shown in FIG.

  In the present embodiment, as in the first embodiment, a pair of inverters 15a and 15b with feedback resistors are provided as an example of the first inverter and the second inverter. In the present embodiment, as in the first embodiment, a pair of inductors 9a and 9b is provided as an example of the first inductor and the second inductor. The pair of inverters 15a and 15b with feedback resistors and the pair of inductors 9a and 9b have the same configurations as those in the first embodiment, and thus detailed description will be omitted. Also in this embodiment, the inverter 15a with feedback resistance and the inductor 9a, and the inverter 15b with feedback resistance and the inductor 9b are connected in series between the output node of the differential amplifier 14 and the signal output terminals 10a and 10b. It is done.

  In FIG. 7, the differential amplifier unit 14 forms a differential pair of current mirror type current source loads composed of the bias unit 13 and the N channel MOS transistors 1a and 1b. The source grounding circuit of the current source load is the same as the differential amplification unit 14 of FIG.

[Description of effect]
According to the fully differential amplifier circuit of this embodiment, the gain of the fully differential amplifier circuit shown in FIG. 7 is determined by the feedback resistors connected to the inverters 15a and 15b with feedback resistors, and the gain of the inverters 15a and 15b with feedback resistors is The input voltage is adjusted and optimized by the constant current source 3 of the differential pair and the constant current source 5 of the current source load. Further, in the fully differential amplification circuit shown in FIG. 7, the inductance can be optimized in consideration of the parasitic capacitance of the post-stage circuit, and the frequency characteristics can be expanded flat.

  Furthermore, according to the fully differential amplification circuit of the present embodiment, as in the first embodiment, the differential amplification unit 14 does not need to increase the gain, and therefore the current consumption can be reduced. Furthermore, since no steady-state current flows through the inverters 15a and 15b with feedback resistors, the full differential amplification circuit shown in FIG. 2 can realize low power consumption. As in the present embodiment, the differential amplification unit 14 of the full differential amplification circuit can be configured to include a differential pair of P-channel MOS transistors 2a and 2b.

Third Embodiment
Next, a fully differential amplifier circuit according to a third embodiment of the present invention will be described. FIG. 8 is a circuit diagram for explaining a fully differential amplifier circuit according to a third embodiment of the present invention. Similar to the first embodiment, this embodiment relates to an example in which the differential amplifier of the fully differential amplifier circuit is configured to include an N channel MOS transistor forming a differential pair. Furthermore, in the present embodiment, the differential amplification unit 14 of the fully differential amplification circuit of the first embodiment is shown in a more specific circuit configuration. The same reference numerals are assigned to components similar to those of the fully differential amplifier circuit of the first embodiment, and the detailed description thereof is omitted.

[Description of configuration]
The fully differential amplifier of FIG. 8 includes a differential amplification unit 14, a pair of inverters 15a and 15b with a feedback resistor, and a pair of inductors 9a and 9b, as in the first embodiment. The differential amplifier unit 14 of FIG. 8 has sources connected in common, gates connected to the signal input terminals 4a and 4b, respectively, to form a differential pair of N channel MOS transistors 1a and 1b, and a pair of N channel MOS transistors 1a, It includes a current mirror circuit 32 connected between the common source connection point 1 b and the negative power supply terminal 12, a pair of P channel MOS transistors 2 a and 2 b whose gates are commonly connected, and a bias unit 13.

  In the current mirror circuit 32 of FIG. 8, an N channel MOS transistor 31a provided instead of the constant current source 3 of FIG. 2 and a P channel having a source connected to the positive power supply terminal 11 and a gate and a drain connected in common. It includes an MOS transistor 2d and an N-channel MOS transistor 31b whose source is connected to the negative power supply terminal 12 and whose gate and drain are commonly connected. The reference bias from the bias unit 13 is applied to the P-channel MOS transistor 2d, and the N-channel MOS transistors 31b and 31a constitute a current mirror circuit.

  The current generated by bias unit 13 is folded back at the channel width ratio of P channel MOS transistor 2c and P channel MOS transistor 2d to become a current source load of the differential pair, and N channel MOS transistor 31a and N channel MOS transistor 31b. The channel width ratio of the current of the differential pair.

[Description of effect]
According to the fully differential amplifier circuit of this embodiment, the gain of the fully differential amplifier circuit shown in FIG. 8 is determined by the feedback resistors connected to the inverters 15a and 15b with feedback resistors, and the gain of the inverters 15a and 15b with feedback resistors is The input voltage is adjusted and optimized by the constant current source 3 of the differential pair and the constant current source 5 of the current source load. Further, in the fully differential amplifier circuit shown in FIG. 8, the inductance can be optimized in consideration of the parasitic capacitance of the subsequent stage circuit, and the frequency characteristics can be expanded flat.

  Furthermore, according to the fully differential amplification circuit of the present embodiment, as in the first embodiment, the differential amplification unit 14 does not need to increase the gain, and therefore the current consumption can be reduced. Furthermore, since no steady-state current flows through the inverters 15a and 15b with feedback resistors, the full differential amplification circuit shown in FIG. 2 can realize low power consumption.

Fourth Embodiment
Next, a fully differential amplifier circuit according to a fourth embodiment of the present invention will be described. FIG. 9 is a circuit diagram for explaining a fully differential amplifier circuit according to a fourth embodiment of the present invention. Similar to the first and third embodiments, this embodiment relates to an example in which the differential amplifier of the fully differential amplifier circuit is configured to include an N channel MOS transistor forming a differential pair. Furthermore, in the present embodiment, the differential amplification unit 14 of the fully differential amplification circuit of the first embodiment is shown in a more specific circuit configuration. The same reference numerals are assigned to components similar to those of the fully differential amplifier circuit according to the first embodiment or the third embodiment, and the detailed description thereof is omitted.

[Description of configuration]
The fully differential amplifier of FIG. 9 includes a differential amplification unit 14, a pair of inverters 15a and 15b with feedback resistors, and a pair of inductors 9a and 9b, as in the first embodiment. In the differential amplification unit 14 of FIG. 9, the sources are commonly connected, the gates are respectively connected to the signal input terminals 4a and 4b, and the differential pair N channel MOS transistors 1a and 1b and a pair of N channel MOS transistors 1a, It includes an N channel MOS transistor 31 a connected between the common source connection point 1 b and the negative power supply terminal 12, and a bias unit 13.

  The bias unit 13 of the present embodiment includes N channel MOS transistors 31 c and 31 b and a resistor 30 in place of the constant current source 5 of FIG. 2. In the bias unit 13 of this embodiment, the drain and the gate of the N channel MOS transistor 31c are connected in common, the source is connected to the negative power supply terminal 12, and the resistor 30 is the drain and the gate of the N channel MOS transistor 31c connected in common. N channel MOS transistor 31b is connected to negative power supply terminal 12, the gate is connected to the gate of N channel MOS transistor 31c, and the drain is to the gate and drain of P channel MOS transistor 2c. It is connected.

  The output of the bias unit 13 of the present embodiment is given to the gate of the N channel MOS transistor 31a. The bias unit 13 of this embodiment forms a current mirror circuit with N channel MOS transistors 31c and 31b, and the N channel MOS transistors 31c and 31b form a current mirror circuit with the N channel MOS transistor 31a.

  In the bias section 13 of this embodiment, the current generated by the resistor 30 and the N channel MOS transistor 31c is folded back at the channel width ratio of the N channel MOS transistors 31c and 31b, and the P channel MOS transistor 2c and the P channel MOS transistor 2a, It becomes a current source load of the differential pair at a channel width ratio of 2b, and becomes a current of the differential pair at a channel width ratio of the N channel MOS transistor 31a and the N channel MOS transistor 31c.

[Description of effect]
According to the fully differential amplifier circuit of this embodiment, the gain of the fully differential amplifier circuit shown in FIG. 9 is determined by the feedback resistors connected to the inverters 15a and 15b with feedback resistors, and the gain of the inverters 15a and 15b with feedback resistors is The input voltage is adjusted and optimized by the constant current source 3 of the differential pair and the constant current source 5 of the current source load. Further, in the fully differential amplifier circuit shown in FIG. 9, the inductance can be optimized in consideration of the parasitic capacitance of the post-stage circuit, and the frequency characteristics can be expanded flat.

  Furthermore, according to the fully differential amplification circuit of the present embodiment, as in the first embodiment, the differential amplification unit 14 does not need to increase the gain, and therefore the current consumption can be reduced. Furthermore, since no steady-state current flows through the inverters 15a and 15b with feedback resistors, the full differential amplification circuit shown in FIG. 2 can realize low power consumption.

Other Embodiments
By applying the fully-differential amplifier circuit according to the first to fourth embodiments described above, an optical receiver circuit is configured to input a current signal converted from an optical signal, convert the voltage, and output a differential voltage signal. be able to. For example, the fully differential amplification circuits of the first to fourth embodiments having the above-described configuration in the fully differential amplification circuit 25 of the light reception circuit 29 of FIG. 10 or the limit amplifier 26 in which the fully differential amplification circuits are connected in multiple stages. Can be applied to configure the light receiving circuit of the embodiment of the present invention.

  The light receiving circuit thus obtained can realize low power consumption.

  As mentioned above, although the preferable embodiment of this invention was described, this invention is not limited to this. It is needless to say that various modifications are possible within the scope of the invention described in the claims, and they are also included in the scope of the present invention.

  The fully differential amplifier circuit according to an embodiment of the present invention is particularly useful for a semiconductor integrated circuit applied to an optical receiver module with a data communication speed of 25 Gb / s or more, and is not limited thereto, and high gain and wide band The present invention is widely applicable to all differential amplifier circuits required.

Some or all of the above embodiments may be described as in the following appendices, but is not limited to the following.
(Supplementary Note 1) A fully differential output in which a pair of differential input signals input to the first differential input terminal and the second differential input terminal are amplified and output from the first differential output terminal and the second differential output terminal An amplification circuit,
A differential amplification unit that amplifies the pair of differential output signals and outputs the amplified output to the pair of output nodes;
A first inverter and a first inductor connected in series between an output node of the pair of output nodes and the first differential output terminal;
A second inverter and a second inductor connected in series between another output node of the pair of output nodes and the second differential output terminal,
A fully differential amplifier circuit, wherein the first inverter has a first feedback path that feeds back the output to the input, and the second inverter has a second feedback path that feeds back the output to the input.
(Supplementary note 2) The fully differential amplifier circuit according to supplementary note 1, wherein the first feedback path of the first inverter and the second feedback path of the second inverter each include a feedback resistor.
(Supplementary note 3) The fully differential amplification circuit according to supplementary note 1 or 2, wherein the differential amplification part includes a bias part for the pair of load transistors.
(Supplementary note 4) The fully differential amplification circuit according to supplementary note 3, wherein the bias unit includes a transistor that forms a current mirror circuit with the pair of load transistors.
(Supplementary Note 5) The differential amplification unit constitutes a pair of load transistors of the first conductivity type, a differential pair, and a current common to the differential pair transistor of the second conductivity type and the differential pair transistors. The full differential amplifier circuit according to Appendix 3 or 4, wherein the source is connected in series.
(Supplementary note 6) The fully differential amplification circuit according to supplementary note 5, wherein the current source includes a transistor, and the bias unit biases the transistor of the current source.
(Supplementary note 7) The fully differential amplifier circuit according to supplementary note 6, wherein the bias unit includes a transistor that forms a current mirror circuit with the transistor of the current source.
(Supplementary Note 8) The fully differential amplifier circuit according to Supplementary note 5, wherein the pair of load transistors of the first conductivity type is a P-channel MOS transistor, and the differential pair transistor of the second conductivity type is an N-channel MOS transistor. .
(Supplementary note 9) The fully differential amplification circuit according to supplementary note 5, wherein the pair of load transistors of the first conductivity type is an N channel MOS transistor, and the differential pair transistor of the second conductivity type is a P channel MOS transistor. .
(Supplementary note 10) The all-difference amplifying circuit according to any one of supplementary notes 1 to 9, wherein a band of frequency characteristics is controlled by the inductances of the first inductor and the second inductor.
(Supplementary note 11) The full difference amplification amplifier circuit according to any one of supplementary notes 2 to 9, wherein a voltage gain and an output voltage are controlled by resistance values of the feedback resistors of the first inverter and the second inverter.
(Supplementary note 12) The full differential amplification circuit according to any one of supplementary notes 1 to 11, including:
An optical receiver circuit that inputs a current signal converted from an optical signal, converts the voltage, and outputs a differential voltage signal.
(Supplementary note 13) The light receiving circuit according to supplementary note 12, wherein the fully differential amplification circuits are connected in multiple stages.

1a, 1b N channel MOS transistor 2a, 2b P channel MOS transistor 3 constant current source 4a, 4b signal input terminal 5 constant current source 6a, 6b P channel MOS transistor 7a, 7b N channel MOS transistor 8a, 8b resistance 9a, 9b Inductor 10a, 10b Signal output terminal 11 Positive power supply terminal 12 Negative power supply terminal 13 Bias section 14 Differential amplifier section 15a, 15b Inverter with feedback resistance 18 Light receiving element 19 Inversion amplifier 20 Feedback resistance 21 Preamplifier 22 Resistance 23 Capacity 24 Reference voltage generation 25 full differential amplifier circuit 26 limit amplifier 27 input terminal 28a, 28b output terminal 29 light receiving circuit 30 resistance 31a, 31b, 31c N channel MOS transistor 32 current mirror circuit

Claims (10)

A fully differential amplifier circuit that amplifies a pair of differential input signals input to a first differential input terminal and a second differential input terminal and outputs the amplified signals from the first differential output terminal and the second differential output terminal. ,
A differential amplification unit that amplifies the pair of differential output signals and outputs the amplified output to the pair of output nodes;
A first inverter and a first inductor connected in series between an output node of the pair of output nodes and the first differential output terminal;
A second inverter and a second inductor connected in series between another output node of the pair of output nodes and the second differential output terminal,
A fully differential amplifier circuit, wherein the first inverter has a first feedback path that feeds back the output to the input, and the second inverter has a second feedback path that feeds back the output to the input.   The fully differential amplifier circuit according to claim 1, wherein the first feedback path of the first inverter and the second feedback path of the second inverter each include a feedback resistor. The differential amplifier unit may include a bias unit for the pair of load transistors.
The fully differential amplifier circuit according to claim 2 or 3.   The fully differential amplifier circuit according to claim 3, wherein the bias unit includes a transistor forming a current mirror circuit with the pair of load transistors.   The differential amplifier unit includes a pair of load transistors of a first conductivity type, a differential pair, and a differential pair transistor of a second conductivity type and a current source common to the differential pair transistors in series. The fully differential amplifier circuit according to claim 3 or 4 connected to   The fully differential amplifier circuit according to claim 5, wherein the current source includes a transistor, and the bias unit biases the transistor of the current source.   The fully differential amplifier circuit according to claim 6, wherein the bias unit includes a transistor forming a current mirror circuit with the transistor of the current source.   6. The fully differential amplifier circuit according to claim 5, wherein the pair of load transistors of the first conductivity type is a P-channel MOS transistor, and the differential pair transistor of the second conductivity type is an N-channel MOS transistor.   6. The fully differential amplifier circuit according to claim 5, wherein the pair of load transistors of the first conductivity type is an N-channel MOS transistor, and the differential pair transistor of the second conductivity type is a P-channel MOS transistor. A fully differential amplifier circuit according to any one of claims 1 to 9, including:
An optical receiver circuit that inputs a current signal converted from an optical signal, converts the voltage, and outputs a differential voltage signal.

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