JP2005072974A - Low voltage amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure stable signal amplitude against a variation in power supply voltage and a variation, etc., in a MOS transistor threshold based on environmental temperature, operating temperature or a manufacturing condition or the like in all differential amplifier circuits that operate by low voltage. <P>SOLUTION: In all differential amplifier circuits wherein a pair of active loads, a differential pair and a common constant current source are connected in series and which has a bias circuit for the active loads, a design condition of a MOS transistor (gate length: L1, and gate width: W1) for forming the active loads that operate with the current ratio of 1: n, and of a MOS transistor (gate length: Lr, and gate width: Wr) for forming the bias circuit, is (1/2) (Wr/Lr) (L1/W1)<n for the purpose of making the MOS transistors for forming the active loads operate within a linear area. This forms all differential amplifier circuits which obtain a stable output against variations in power supply voltage, and a threshold or the like. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a fully differential amplifier circuit using MOS transistors. For example, the present invention relates to a fully differential amplifier circuit that is preferably used in a linear amplifier circuit integrated circuit, can use a low-voltage power source such as a battery, and can operate at high speed.

  In recent years, the use of a battery as an operating power source has become common in portable electronic devices, home appliances, and the like. In addition, in semiconductor integrated circuits used in these electronic devices, the size of transistors used for high capacity and high integration has been reduced. Along with this, a further reduction in the applied voltage has been demanded. Conventionally, the power supply voltage of the low-voltage analog circuit has been designed to operate at about 1.2 to 1.8 V, but there is a demand for a circuit that is further reduced in voltage and operates stably even at 1 V or less.

  Conventionally, a fully differential amplifier circuit is used as a transistor amplifier circuit used in an audio signal processing device, a video signal processing device such as an optical disk, and the like. In the fully differential amplifier circuit, the difference between the first input signal supplied to one transistor of the two transistors constituting the differential pair and the second input signal supplied to the other transistor is amplified and output. . Examples of a conventional fully-differential amplifier circuit using MOS transistors are shown in FIGS. For example, see Behzad Razavi, Design of Analog CMOS Integrated Circuits McGRAW-HILL page 190 Figure 6.29 (a), page 124 4.32, page 134 Figure 4.45.

  The fully differential amplifier circuit shown in FIG. 1A uses a current source composed of a transistor as a load, and the fully differential amplifier circuit shown in FIG. 1B uses a diode composed of a transistor as a load. The fully differential amplifier circuit shown in FIG. 1C uses a resistor composed of a transistor as a load.

(I) About the fully-differential amplifier circuit of the current source load shown in FIG. 1 (a) This differential amplifier circuit operates a load composed of transistors as a current source. For this reason, in such a conventional differential amplifier circuit, a saturation region (portion greater than V _eff ) in the static characteristics of a normal transistor as shown in FIG. 2 has been used. As described above, when the transistor is used in the saturation region, there is a non-saturation region by V _eff , and therefore, the amplitude of the output voltage V _out can only be used up to VDD−V _eff . Therefore, the maximum signal amplitude is suppressed by V _eff . Under normal conditions using a low power supply of about 1 V, V _eff is about 100 to 300 mV.

In addition, the current source load fully differential amplifier circuit shown in FIG. 1A has a problem that the common mode bias becomes unstable. For this reason, as shown in FIG. 3, for example, a fully differential amplifier circuit has been developed to which a common mode feedback (CMMON: COMMON-MODE Feed Back) circuit is added in order to determine the operating point of the output voltage. However, the addition of such a CMFB circuit not only complicates the circuit but also connects a plurality of extra elements to the output node _Vout , so that the signal bandwidth is degraded by the parasitic capacitance of these elements. There is a problem.

(Ii) About the fully differential amplifier circuit of the diode load shown in FIG. 1 (b) In the fully differential amplifier circuit of the diode load as shown in FIG. 1 (b), the load is diode-connected. There is a problem that a gain cannot be expected, and a signal band is deteriorated because a gate capacitance of a MOS transistor used as a load diode with respect to the output node _Vout exists. Further, since the drain-source voltage V _DS of the load transistor acting as a diode is dependent on the change in the threshold V _T, it is required to have a design margin in consideration of V _T variation.

(Iii) Resistive load fully differential amplifier circuit shown in FIG. 1 (c) In a fully differential amplifier circuit having a resistive load as shown in FIG. 1 (c), the gate of a MOS transistor used as a resistive load voltage V _P, to objection to the common-mode bias signal input to the gate of the input stage transistor, there is a problem that the load resistor fluctuates. The drain of the load transistor - since the source voltage V _DS is dependent on variations of the power supply voltage V _DD, it is necessary to have a design margin. In addition, since the drain-source voltage V _{DS of} the load transistor further depends on the variation of the threshold value V _T , it is necessary to have a design margin as well.

Further, problems relating to characteristics inherent to the MOS transistor in the low voltage analog circuit will be described by taking a fully differential amplifier circuit having a current source load as shown in FIG. 1A as an example. FIG. 4 shows the concept of the configuration of this fully differential amplifier circuit and the relationship between the applied voltage and the signal region in each component. In FIG. 4, A (Veff_load) is a voltage applied to the current source load, B (Signal) is a voltage related to signal amplification, and C (Veff_input and Veff_cc) is a voltage required to operate the differential input circuit. It is. That is, V _{eff input} is a voltage related to the transistor in the input stage, and V _{eff cc} is a voltage related to the current source of the current mirror circuit.

FIG. 5 shows a schematic voltage distribution when the voltage of the power source of the fully differential amplifier circuit of such a current source load is lowered. Note _k p _{V eff} corresponds to region A of FIG. _4, k _{n V eff} corresponds to region C in FIG. In an actual fully-differential amplifier circuit, noise inevitably occurs, so this portion is shown as a Noise region.

In order to operate a load composed of MOS transistors as a current source, a so-called saturation region in the static characteristics of a normal transistor as shown in FIG. 2 has been used in such a fully differential amplifier circuit. As described above, when the MOS transistor is used in the saturation region, there is a non-saturation region corresponding to V _eff as shown in FIG. 2, and therefore the amplitude of the output voltage V _out can only be used up to VDD−V _eff . Therefore, the maximum signal amplitude is suppressed by V _eff (and the noise part).

Even when the low-voltage power supply, _normally, since there is never k _p V eff, Noise, and _k n _{V eff} decreases in accordance with the low voltage of the power supply, as shown in FIG. 5, the signal area only Results in a decrease. For this reason, the signal / noise ratio (S / N ratio) decreases. Therefore, in order to reduce the voltage of the fully differential amplifier circuit, it is necessary to make V _eff smaller in terms of circuit design.
Design of Analog CMOS Integrated Circuits McGRAW-HILL by Behzad Razavi page 190 Figure 6.29 (a), page 124 4.32, page 134 Figure 4.45

  For example, in a fully differential amplifier circuit that operates at a low voltage of 1 V or less, for example, variations in power supply voltage, such as battery voltage, variations in threshold voltage of MOS transistors based on environmental temperature, operating temperature, manufacturing conditions, etc. It is important to ensure a stable signal amplitude. In the present invention, since the active load that has been used in the saturation region is used in the linear region, the design conditions of the MOS transistor that forms the active load and the MOS transistor that forms the bias circuit are determined. An object of the present invention is to form a fully-differential amplifier circuit capable of obtaining a stable output with respect to fluctuations in the above.

An example of a fully differential amplifier circuit of the present invention is shown in FIG. The circuit configuration of FIG. 6 includes a differential amplification unit in which a pair of load transistors, a differential pair transistor, and a first constant current source common to the differential pair transistors are connected in series, and a parallel connection with the differential amplification unit. A bias circuit connected to each other and having a gate and a drain connected to each other and a second constant current source connected in series;
Fully differential amplification in which the gates of the pair of load transistors are connected to the gates of the bias transistors, and the ratio of the currents flowing through the first constant current source and the second constant current source is 2: n. A circuit,
The gate length and gate width of the pair of load transistors (each gate length: Ll, each gate width: Wl) and the bias transistor (gate length: Lr, gate width: Wr) are (1/2) (Wr / Lr) ( Ll / Wl) <n.

Further, as an example of the present invention, the fully differential amplifier circuit shown in FIG. 8 includes a differential in which a pair of load transistors, a differential pair transistor, and a first constant current source common to the differential pair transistor are connected in series. An amplification unit;
A bias circuit that is connected in parallel to the differential amplifier, and in which a bias transistor and a second constant current source are connected in series;
A reference circuit that is connected in parallel with the differential amplifier and the bias circuit, and in which a third constant current source and a reference transistor are connected in series;
The gates of the pair of load transistors are connected to the gates of the bias transistors, and the current flowing through the first constant current source and the second constant current source operates at a current ratio of 2: n. A fully-differential amplifier circuit in which a constant current source, the second constant current source, and the reference transistor form a current mirror circuit;
The gate length and gate width of the pair of load transistors (each gate length: Ll, each gate width: Wl) and the bias transistor (gate length: Lr, gate width: Wr) are (1/2) (Wr / Lr) ( Ll / Wl) <n.

As an example of the present invention, the fully differential amplifier circuit shown in FIG. 11 includes a pair of constant current sources including first and second constant current sources, and first outputs connected to respective outputs of these constant current sources. A first stage differential amplifying unit in which a differential pair transistor and a third constant current source common to the first differential pair transistor are connected in series;
A pair of constant current sources connected in parallel to the first-stage differential amplifier and composed of fourth and fifth constant current sources, and a second differential pair connected to the output pairs of these constant current sources, respectively. A second stage differential amplifying unit in which a transistor and a pair of load transistors are connected in series;
Here, the output of the first constant current source and the output of the fourth constant current source are connected, and the output of the second constant current source and the output of the fifth constant current source are connected. ,
A bias circuit connected in parallel with the first stage and second stage differential amplifying sections, and having a sixth constant current source and a bias transistor connected to the gate and drain connected in series;
The gates of the pair of load transistors are connected to the gates of the bias transistors, and the ratio of the current flowing through the second differential pair transistor to the current flowing through the sixth constant current source is a current ratio of 1: n. A fully differential amplifier circuit operating in
The gate length and the gate width of the load transistor (gate length: Ll, gate width: Wl) and the bias transistor (gate length: Lr, gate width: Wr) are (1/2) (Wr / Lr) (Ll / Wl) <N is a fully differential amplifier circuit.

The fully differential amplifier circuit according to the present invention does not require a CMFB circuit for determining the operating point of the output voltage at the output of the differential amplifier circuit, so that no extra parasitic capacitance is added, which is suitable for speeding up. Further, since the gate capacitance cannot be seen as the parasitic capacitance of the load transistor, it is suitable for speeding up. As described later, by satisfying the condition of (1/2) (W _r / L _r ) (L _l / W _l ) <n, the load transistor operates as a resistive load that operates in the linear region, The maximum output amplitude up to the power supply voltage can be obtained. The voltage V _DSl applied to the load transistor is
V _DSl = (1 / 2n) (W _r / L _r ) (L _l / W _l ) V _effr = (1/2) (W _r / L _r ) (L _l / W _l ) {2I _Dr / (μ _p C _ox (W _r / L _r ))} ^1/2
The maximum amplitude of the output signal is not affected by the V _DD fluctuation and is not affected by the threshold voltage V _T fluctuation.

In the above two equations, W _r and W _l are gate widths of the bias transistor M _r and the load transistor M _l , L _r and L _l are substantial gate lengths of the transistors M _r and M _l , and n is a constant current source. current _{ratio, V DSL} drain-source voltage of the load transistor _{M l,} the difference between V _Effr the V _GSR and V _T, i.e. (V _GSr -V _T), the drain current of _{I Dr} bias transistor _{M r,} mu _p is the mobility of the transistors M _r and M _l , and C _ox is the gate oxide film capacitance of the transistors M _r and M _l .

  The present invention is particularly effective in reducing the power supply voltage and speeding up the fully differential amplifier circuit. That is, by realizing an analog circuit with a standard CMOS, high-speed characteristics realized with a logic CMOS transistor can be utilized. In order to take advantage of this merit, a circuit configuration to which no parasitic capacitance is added as in the present invention is important. In addition, in a conventional fully differential amplifier circuit, it is difficult to ensure a stable signal amplitude at a low power supply voltage, but it is possible to ensure a signal amplitude without depending on power supply fluctuations or threshold fluctuations. It becomes important. The present invention makes it possible to use a low power supply voltage, and to achieve higher speed of a circuit to be applied.

[Example 1]
FIG. 6 shows a first embodiment relating to a fully differential amplifier circuit as an example of the present invention. The sources of a pair of first and second PMOS transistors 2 and 3 operating as load resistors are connected to a first power supply VDD1, and the gates of these transistors are connected to a common node 4. The first and second PMOS transistors 2 and 3 are collectively referred to as a transistor Ml. The drains of the first and second PMOS transistors 2 and 3 are connected to the output terminals Vout-5 and Vout + 6 of the differential amplifier circuit, respectively.

  Output terminals 5 and 6 are connected to the drains of a pair of first and second nMOS transistors 7 and 8 constituting a differential amplifier circuit. The drains of the first and second nMOS transistors 7 and 8 are connected to a common node 9, respectively. The first and second nMOS transistors 7 and 8 are collectively referred to as a transistor Min. The common node 9 is connected to one terminal of the first constant current source 10.

  The constant current source 10 is normally used in a semiconductor integrated circuit, and is not particularly limited, but can be formed by, for example, a PMOS transistor or an nMOS transistor. The other terminal of the constant current source 10 is connected to a second potential VSS11 that is at, for example, the ground potential. The input signal enters the input terminal Vout + 12 and the input terminal Vout-13 connected to the gates of the first and second nMOS transistors 7 and 8, respectively.

  In the present invention, as shown in FIG. 1, a third PMOS transistor 14 and a second constant current source 15 connected in series are further controlled in order to control the gate voltage of the PMOS transistors 2 and 3 operating as load resistors. Is provided. The source of the third PMOS transistor 14 is connected to the first power supply VDD1, and the gate and drain thereof are connected to each other and to the common node 4. The gate and drain of the third PMOS transistor 14 are further connected to one terminal of the second constant current source 15. Note that when the third PMOS transistor 14 is described in correspondence with the transistors Ml and Min, it is described as the transistor Mr. The other terminal of the constant current source 15 is connected to the second potential VSS11. This constant current source 15 is also commonly used in a semiconductor integrated circuit, and can be formed by, for example, a PMOS transistor or an nMOS transistor.

  In the circuit of the first embodiment of the present invention shown in FIG. 6, the current ratio of the constant current source is n, that is, the ratio of the current flowing through the constant current source 10 of the differential pair and the constant current source 15 of the bias transistor is 2: n.

  In the circuit configuration of FIG. 6, in order to operate the transistor Ml in the linear region, the shape (gate length L, gate width W) of each of the transistors Ml and Mr is set to be in the range of the expression (1). . Here, the current ratio n of the constant current source can be determined, for example, by setting the W / L ratio of the transistor configured by the current mirror circuit shown in FIG. 8 according to the second embodiment of the present invention. The current mirror circuit of FIG. 8 is a circuit that can obtain a current value having a current ratio similar to this ratio by setting the transistor size W / L ratio of the reference transistor M1 and M2 and M3.

  When the condition of the following expression (1) is satisfied, the transistor Mr operates in the saturation region and the transistor Ml operates in the linear region. When the transistor Ml operates in the linear region, the output signal amplitude can be used up to the drain-source voltage VDSl of the transistor Ml. Since the drain-source voltage VDSl of the transistor Ml is not affected at all by the power supply voltage and the threshold fluctuation as defined by the following equation (2), the maximum value of the signal amplitude that operates stably. Can be set easily.

  6, 7, and 8, the case where the input stage transistor is an nMOS is described. However, the same effect can be obtained when these circuits are configured by replacing the nMOS and the pMOS.

(1/2) (W _r / L _r ) (L _l / W _l ) <n
(1)
V _DSl = (1 / 2n) (W _r / L _r ) (L _l / W _l ) V _effr = (1/2) (W _r / L _r ) (L _l / W _l ) {2I _Dr / (μ _p C _ox (W _r / L _r ))} ^1/2 > (V _out amplitude)
(2)
The _V effr is an effective voltage of M _r.

  Hereinafter, the process of deriving the above equations (1) and (2) will be described.

FIG. 9 shows a general structure of an nMOS transistor. A case where a positive voltage V _G is applied to the gate and a positive voltage V _D is applied to the drain will be described. Channel voltage changes from zero potential of the source to the drain voltage V _D, Therefore, the voltage between the gate and the channel is changed from V _G by location until V _G -V _D. Therefore, the charge density Qd (x) at the channel position x is expressed as follows: the channel width is W, the gate capacitance per unit area is C _OX , the gate-source potential V _GS , the channel potential at the position n is V (x), and n-type When the gate voltage when inverted to V _TH is
Qd (x) = WC _OX [V _GS −V (x) −V _TH ].

On the other hand, the relationship between the channel current I and the charge Qd in the channel region is generally given as I = Qd × v where the charge velocity is vm / second. Therefore, the drain current _ID is
I _D = −WC _OX [V _GS −V (x) −V _TH ] × v.

In general, when the carrier mobility in the channel region is μ and the electric field strength is E, v = μE and E = −dv / dx,
I _D = −WC _OX [V _GS −V (x) −V _TH ] × μ _n dv (x) / dx.

Multiplying both sides by dx, integrating the above equation with the boundary conditions v (0) = 0, V (L) = V _DS ,
∫ ^L _x = a ^{_{0 I D dx = ∫ vDS v}} = 0 WC OX μ n [V GS -V (x) -VTH] dv.

Since the value of _ID is the same everywhere in the position x of channel n,
_{I D = (W / L)} C OX μ n [(V GS -V TH) V DS - (1/2) V DS 2]
(3)
It becomes.

When the above equation is calculated by changing V _GS , a quadratic curve (parabola) shown in FIG. 10 is obtained. The hatched portion is a so-called triode region.

Since the vertex of each parabola is V _DS = V _GS −V _TH , the current value at the vertex is
_{ID, max} = (1/2) μn Cox (W / L) (V _GS −V _TH ) ² (4)
It becomes.

At the voltage on the right side of the apex shown in FIG. 10 where V _DS has increased, the channel is pinched off, so that it deviates from the characteristic of equation (3), and exhibits a saturation characteristic in which _ID becomes substantially constant as shown by the alternate long and short dash line. Equation (4) generally gives the current value in the saturation region.

On the other hand, in the region where V _DS is small, that is, when V _DS <2 (V _GS −V _TH ), Equation (3) omits the term of (1/2) V _DS ² ,
I _D = (W / L) C _OX μ _n (V _GS −V _TH ) V _DS (5)
Can be written. The drain current is a linear function of VDS, and this formula generally gives voltage-current characteristics in the linear region. Although the above is calculated by taking the nMOS transistor shown in FIG. 9 as an example, the same applies to the case of a pMOS transistor.

Thus, M _r is the saturation region in the circuit configuration of FIG. 6, when the M _l is operating in the linear region, the current flowing through each transistor is expressed as follows.

I _Dr = nI = (1/2) μ _p C _ox (W _r / L _r ) (V _GSr -V _T ) ² (6)
I _Dl = I = μ _p C _ox (W _l / L _l ) (V _GSl -V _T ) ² V _DSl (7)
Here, I _Dr and I _Dl are the drain currents of the transistors M _r and M _l ,
μ _p is the mobility of the transistors M _r and M _l ,
C _ox is the gate oxide capacitance of the transistors M _r and M _l ,
W _r and W _l are the gate widths of the transistors M _r and M _l ,
L _r and L _l are the substantial gate lengths of the transistors M _r and M _l ,
V _GSr and V _GSl are the gate-source voltages of the transistors M _r and M _l ,
V _T is the threshold voltage of transistors M _r and M _l ,
V _DSl the drain-to-source voltage of the transistor _{M l,}
n is the current ratio of the constant current source.

  In the circuit configuration of FIG. 6, the expressions (6) and (7) are applied to the first constant current source 10 and the second constant current source 15, and the current I of the expressions (6) and (7) is applied. Are equal, the following equation is obtained.

(1 / 2n) μ _p C _ox (W _r / L _r ) (V _GSr −V _T ) ² = μ _p C _ox (W _l / L _l ) (V _GSl −V _T ) V _DSl (8)
In the circuit configuration of FIG. 6, since the gates of the transistors M _r and M _l are short-circuited and the sources are common, the gate-source voltages V _GSr and V _GSl of the respective transistors are equal, so (V _GSr −V _T ) = (V _GS1 -V _T ). Therefore, equation (8) is as follows.

(1 / 2n) μ _p C _ox (W _r / L _r ) (V _GSr −V _T ) = μ _p C _ox (W _l / L _l ) V _DSl (9)
When formula (6) is transformed
(V _GSr -V _T ) = {2I _Dr / (μ _p C _ox (W _r / L _r ))} ^1/2
So that
When the expression (9) is expanded for V _DSl and the above (V _GSr −V _T ) is substituted, the following is obtained.

V _DSl = (1 / 2n) (W _r / L _r ) (L _l / W _l ) (V _GSr -V _T ) = (1 / 2n) (W _r / L _r ) (L _l / W _l ) { 2I _Dr / (μ _p C _ox (W _r / L _r ))} ^1/2
(10)
From equation (10), V _DSl corresponding to the maximum amplitude of the signal output from the fully differential amplifier circuit having the circuit configuration of FIG. 6 is always a constant value even if the power supply voltage and the threshold voltage V _T vary. Can be obtained.

Next, conditions for M _l to operate in the linear region in the circuit configuration of FIG. 6 are obtained.

As it is apparent from general Figure 2 shows the static characteristics of the transistor, when the drain-source voltage V _DSL transistor M _l is of the following conditions, the transistor M _l is operated in the linear region.

V _DSl <V _effl
Where V _effr = (V _GSl -V _T )
V _DSl <(V _GSl -V _T ) (11)
Next, when the equation (10) is substituted into the equation (11), the following equation is obtained.

(1 / 2n) (W _r / L _r ) (L _l / W _l ) (V _GSr −V _T ) <(V _GSl −V _T ) (12)
Since V _GSr = V _GSl ,
(1/2) (W _r / L _r ) (L _l / W _l ) <n
(1)
Is obtained.

By defining the constants (Wr / Lr), (Ll / Wl), and n of the fully differential amplifier circuit of FIG. 6 so as to satisfy the condition of the expression (1), V _OUT appearing at the output of the differential amplifier circuit Can obtain the maximum output amplitude given by equation (7). Equation (1) is a function of only Wr, Lr, Ll, Wl, and n, and the operating condition n of the constant current source and the structure of the load transistor and the bias transistor (gate width and gate length) are predetermined in the design stage. It can be seen that by setting the range, the load transistor of the fully differential amplifier circuit can be operated in the linear region.

  FIG. 7 is a diagram showing an example in which the constant current sources 10 and 15 are configured by using MOS transistors M1 and M2 in the circuit of the first embodiment related to the full operation amplifier circuit according to the present invention shown in FIG. The sizes of the MOS transistors M2 and M1 are designed so that a current ratio of n: 2 is obtained.

[Example 2]
FIG. 8 shows a second embodiment in which the constant current source is configured by a current mirror circuit as a specific circuit for realizing the current ratio of n times in the first embodiment. The current mirror circuit includes M1, M2, and M3 as MOS transistors that constitute a current mirror unit, and the gate of a reference transistor M3 having a gate and a drain connected to each of the transistors M1 and M2 each having a gate connected thereto. It is configured.

  8 showing the second embodiment is different from the circuit of FIG. 6 in that the third nMOS transistor 16 (the transistor M1) is replaced with the node 9 and the second potential in place of the first constant current source 10 of FIG. The fourth nMOS transistor 17 (the transistor M2) is connected to the third pMOS transistor 14 and the second potential VSS11 in place of the second constant current source 15 in FIG. Is connected between. Further, the constant current source 18 has one terminal connected to the first power supply VDD1, and the other terminal of the constant current source 18 is connected to the drain of the fifth nMOS transistor 19 (the transistor M3). The source of the fifth nMOS transistor 19 is connected to the second potential VSS11, and the drain and gate of the fifth nMOS transistor 19 are connected to each other. The gates of the third, fourth and fifth nMOS transistors 16, 17 and 19 are connected to each other.

In the second embodiment, the ratio of the gate sizes W / L of M1, M2, and M3 (W and L are the gate width and gate length of the transistor, respectively) is set arbitrarily, so that the current ratio is similar to this ratio. The current value can be obtained. In the circuit according to the second embodiment illustrated in FIG. 8, the size (W / L) of M2 is set to n × (W ₀ / L ₀ ) and the size of M1 (W ₀ / L ₀ ) with respect to the size (W ₀ / L ₀ ) of M3. / L) is set to 2 × (W ₀ / L ₀ ), and each shows a case where a current ratio of 1: n: 2 is obtained. Note that the same effect can be obtained with respect to the circuit of the seventh embodiment when the nMOS and the pMOS are interchanged.

[Example 3]
Compared to the first embodiment, not only a single-stage fully-differential amplifier circuit but also a fully-differential amplifier circuit that can obtain the same effects as those described above by applying the present invention to the load of a folded cascode circuit Example 3 of this is shown in FIG.

  In FIG. 11, the circuit indicated by the dotted line on the left side is the first-stage fully differential amplifier circuit 20, the circuit indicated by the dotted line on the right side is the second stage amplifier circuit 21 in the folded cascode circuit, The load circuit 22 (common to part 22) set so that the circuit shown by the dotted line frame operates in the linear region described in the first embodiment is shown.

  The first-stage fully-differential amplifier circuit 20 includes a pair of differential amplification nMOS transistors 35 and 36 (Min) and constant current sources 31 and 32 respectively located between the drains of the nMOS transistors 35 and 36 and VDD. (CC4, CC5) and a constant current source 39 arranged between the sources of the nMOS transistors 35 and 36 and VSS.

The configuration of the folded cascode circuit is as follows. The outputs 23 and 24 of the first-stage fully differential amplifier circuit 20 are connected to the sources of the pMOS transistors 25 and 26 (M1 and M2) of the second-stage amplifier circuit 21. A pair of nMOS transistors 27 and 28 (collectively referred to as Ml), which are loads in the second stage amplifier circuit, are connected to the drains of the pMOS transistors 25 and 26. Further, constant current sources 29 and 30 (CC2 and CC3) are connected to sources of the pMOS transistors 25 and 26, and a bias current is supplied to the pMOS transistors 25 and 26. In the embodiment of FIG. 11, since the bias currents of the pMOS transistors 25 and 26 can be supplied from the constant current sources 31 and 32 (CC4 and CC5), the constant current sources 29 and 30 (CC2 and CC3) It is not always necessary. In other words, the constant current source 31 and the constant current source 29 may be configured as one common constant current source, and the constant current source 32 and the constant current source may be configured as one common constant current source (not illustrated). ). The gates of the pMOS transistors 25 and 26 are connected to a voltage _Vbias that operates the transistors in the saturation region.

  The circuit shown in FIG. 11 further includes a bias circuit for the load transistors 27 and 28 of the folded cascode circuit, which includes a bias nMOS transistor 37 (Mr) connected in series with the constant current source CC1 between VDD and VSS.

  In the folded cascode circuit shown in FIG. 11, constant current sources CC2, CC3, CC4, and CC5 configured by a current mirror circuit or the like are selected so that the value of the current flowing through the pMOS transistors 25 and 26 becomes I, and the bias The current flowing through the nMOS transistor 37 (Mr) is set to nI. In such a case, the gate length L and the gate width W of the transistor Mr and the transistor Ml are set so as to satisfy the condition of the expression (1).

At this time, as described in the first embodiment, the drain-source voltage V _DSl of the load transistor Ml indicated by reference numerals 27 and 28 affects the fluctuation of the power supply voltage and the threshold value as represented by the equation (2). Without doing so, it is possible to obtain the maximum output amplitude and to operate in the linear region. The same effect can be obtained with respect to the circuit of the third embodiment even when the nMOS and the pMOS are interchanged.

  FIG. 12 shows the simulation results of the input / output characteristics of the fully differential amplifier circuit, constant current source load differential amplifier circuit, and diode load differential amplifier circuit according to the present invention. It can be seen that the input / output characteristic i of the fully-differential amplifier circuit according to the present invention can have a larger output amplitude than the other circuits and has a good linearity.

All differential amplifier circuit according to the present invention as well in FIG. 13, shows the results of a constant-current source load differential amplifier circuit and the diode temperature dependence of the simulation of the V _DS of the load differential amplifier circuit. It can be seen that the temperature dependency i of _VDS of the fully differential amplifier circuit according to the present invention is smaller than that of other circuits.

It is a figure which shows the example of the fully differential amplifier circuit of the current load in the prior art, a diode load, and a resistance load. It is a figure which shows the voltage current (Vds-Id) characteristic of a MOS transistor. It is a figure which shows the conventional fully differential amplifier circuit which has a common mode feedback circuit. It is a figure which shows the concept of the relationship between the applied voltage in a general fully differential amplifier circuit, the voltage concerning a circuit element, and the voltage applied to a signal area | region. It is a figure which shows the outline voltage distribution at the time of reducing the voltage of the power supply of a fully differential amplifier circuit, especially the change of a signal / noise (S / N). It is a figure which shows the circuit of Example 1 which concerns on all the operation | movement amplifier circuits by this invention. In the circuit of Example 1 which concerns on the full operation | movement amplifier circuit by this invention, it is a figure which shows the circuit which comprised especially the constant current source with the MOS transistor. FIG. 5 is a diagram showing a circuit of a second embodiment that constitutes a current mirror circuit in the full operation amplifier circuit according to the present invention. It is a figure which shows the general structure of a MOS transistor. It is a figure which shows the voltage-current characteristic of the nMOS transistor based on (3) Formula described in this-application specification. It is a figure which shows the circuit of Example 3 of this invention which applied this invention to the load of the folded cascode circuit. It is a comparison figure which shows the result of the simulation of the input-output characteristic of the fully differential amplifier circuit which concerns on this invention, and the conventional constant current source load differential amplifier circuit and the diode load differential amplifier circuit. It is a comparison figure which shows the result of the simulation of the temperature characteristic of VDS of the fully differential amplifier circuit which concerns on this invention, and the conventional constant current source load differential amplifier circuit and the diode load differential amplifier circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... 1st power supply, 2 ... 1st PMOS transistor, 3 ... 2nd PMOS transistor, 4 ... Node, 5 ... Output terminal Vout-, 6 ... Output terminal Vout +, 7 ... 1st nMOS transistor, 8 ... 2nd nMOS transistor, 9... Node, 10... First constant current source, 11... Second potential, 12... Input terminal Vout +, 13 ... Input terminal Vout-, 14. 2 constant current sources, 16 ... third nMOS transistor, 17 ... fourth nMOS transistor, 18 ... constant current source, 19 ... fifth nMOS transistor, 20 ... differential amplifier circuit, 21 ... folded cascode circuit, 22: Load circuit that operates in a linear region, 23, 24: Differential amplification circuit 25 ... pMOS transistor M1, 26 ... pMOS transistor M2, 25 ... nMOS transistor, 28 ... nMOS transistor, 29 ... constant current source CC2, 30 ... constant current source CC3, 31 ... constant current source CC4, 32 ... constant current Sources CC5, 33 ... Control MOS transistor Mr, 34 ... Constant current source CC1, 35 ... nMOS transistor, 36 ... nMOS transistor, 37 ... nMOS transistor, 38 ... Constant current source CC1, ... Constant current source

Claims (13)

A differential amplification section in which a pair of load transistors, a differential pair transistor, and a first constant current source common to the differential pair transistor are connected in series;
A bias circuit connected in parallel with the differential amplifying unit and having a gate and a drain connected to each other and a second constant current source connected in series;
The gates of the pair of load transistors are connected to the gates of the bias transistors, and operate at a current ratio of 2: n through the first constant current source and the second constant current source. A fully differential amplifier circuit,
The gate length and gate width of the pair of load transistors (each gate length: Ll, each gate width: Wl) and the bias transistor (gate length: Lr, gate width: Wr),
(1/2) (Wr / Lr) (Ll / Wl) <n
Fully differential amplifier circuit.   The fully differential amplifier circuit according to claim 1, wherein the pair of load transistors and the bias transistor are nMOS transistors, and the differential pair transistor is a pMOS transistor.   The fully differential amplifier circuit according to claim 1, wherein the pair of load transistors and the bias transistor are pMOS transistors, and the differential pair transistor is an nMOS transistor.   4. The fully differential amplifier circuit according to claim 1, wherein each of the first and second constant current sources includes a MOS transistor. 5. A differential amplification section in which a pair of load transistors, a differential pair transistor, and a first constant current source common to the differential pair transistor are connected in series;
A bias circuit that is connected in parallel with the differential amplifier, and in which a bias transistor and a second constant current source are connected in series;
A reference circuit connected in parallel with the differential amplifier and the bias circuit, and a third constant current source and a reference transistor connected in series;
The gates of the pair of load transistors are connected to the gates of the bias transistors, and the ratio of currents flowing through the first constant current source and the second constant current source is 2: n. The first constant current source, the second constant current source, and the reference transistor are fully differential amplifier circuits forming a current mirror circuit,
The gate length and gate width of the pair of load transistors (each gate length: Ll, each gate width: Wl) and the bias transistor (gate length: Lr, gate width: Wr),
(1/2) (Wr / Lr) (Ll / Wl) <n
Fully differential amplifier circuit.   Each of the first and second constant current sources is composed of a MOS transistor, and each gate width of each gate length in the MOS transistor constituting the first constant current source and the MOS transistor constituting the second constant current source The fully-differential amplifier circuit according to claim 5, wherein a ratio (L / W) to is set to 2: n.   6. The fully differential amplifier circuit according to claim 5, wherein each of the first and second constant current sources is composed of a MOS transistor, and each gate of the MOS transistor is connected to a gate of the reference transistor.   The fully differential amplifier circuit according to claim 5, wherein the pair of load transistors and bias transistors are nMOS transistors, and the differential pair transistors are pMOS transistors.   8. The fully differential amplifier circuit according to claim 5, wherein the pair of load transistors and bias transistors are pMOS transistors, and the differential pair transistors are nMOS transistors. A pair of constant current sources composed of first and second constant current sources, a first differential pair transistor connected to respective outputs of these constant current sources, and the first differential pair transistor A first stage differential amplifier connected in series with a third constant current source common to
A pair of constant current sources connected in parallel to the first-stage differential amplifier and composed of fourth and fifth constant current sources, and a second differential connected to an output pair of these constant current sources, respectively. A second stage differential amplifying unit in which a pair of transistors and a pair of load transistors are connected in series;
Here, the output of the first constant current source and the output of the fourth constant current source are connected, and the output of the second constant current source and the output of the fifth constant current source are Connected,
A bias circuit connected in parallel with the first stage and second stage differential amplifying sections and having a sixth constant current source and a bias transistor having a gate and a drain connected in series;
The gates of the pair of load transistors are connected to the gate of the bias transistor, and the ratio of the current flowing through the second differential pair transistor to the current flowing through the sixth constant current source is 1: a fully differential amplifier circuit operating at a current ratio of n,
A gate length and a gate width of the load transistor (gate length: Ll, gate width: Wl) and the bias transistor (gate length: Lr, gate width: Wr),
(1/2) (Wr / Lr) (Ll / Wl) <n
Fully differential amplifier circuit.   The fully differential amplifier circuit according to claim 10, wherein the pair of load transistors and the bias transistor are nMOS transistors, and the differential pair transistor is a pMOS transistor.   11. The fully differential amplifier circuit according to claim 10, wherein the pair of load transistors and the bias transistor are pMOS transistors, and the differential pair transistor is an nMOS transistor.   The first and fourth constant current sources are formed as one common constant current source, and the second and fifth constant current sources are formed as another common constant current source. 13. The fully differential amplifier circuit according to any one of 10 to 12.

Images