WO2021084809A1 - Operational amplifier - Google Patents

Operational amplifier Download PDF

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Publication number
WO2021084809A1
WO2021084809A1 PCT/JP2020/027316 JP2020027316W WO2021084809A1 WO 2021084809 A1 WO2021084809 A1 WO 2021084809A1 JP 2020027316 W JP2020027316 W JP 2020027316W WO 2021084809 A1 WO2021084809 A1 WO 2021084809A1
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amplifier
amplifier circuit
circuit
current
transconductance
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PCT/JP2020/027316
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French (fr)
Japanese (ja)
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宮崎　大輔
信久 小澤
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ソニーセミコンダクタソリューションズ株式会社
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Priority to JP2021554074A priority Critical patent/JPWO2021084809A1/ja
Publication of WO2021084809A1 publication Critical patent/WO2021084809A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics

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  • This technology relates to operational amplifiers. More specifically, the present invention relates to an operational amplifier that amplifies and outputs an input voltage.
  • the phase of the output signals of the amplifier circuits connected in parallel is made in phase, so that the signal band is widened without lowering the DC gain.
  • a capacitance for removing the DC component is required.
  • a common feedback circuit is required to determine the common mode voltage.
  • This technology was created in view of this situation, and aims to omit the circuit required to control the voltage level in the operational amplifier.
  • the present technology has been made to solve the above-mentioned problems, and the first aspect thereof is a first amplifier circuit that outputs a current corresponding to an input voltage, and a current corresponding to the input voltage.
  • This is an operational amplifier including a second amplifier circuit that outputs a current obtained by adding a current output from the first amplifier circuit. This has the effect of adding current to the outputs of the two amplifier circuits and outputting them.
  • each of the first and second amplifier circuits may be provided with a transconductance amplifier that generates a current corresponding to the input voltage.
  • each of the first and second amplifier circuits includes an active load that serves as a load for the transconductance amplifier, and the active load generates a current corresponding to the voltage with respect to the output current of the transconductance amplifier.
  • An internal transconductance amplifier may be provided, and a positive feedback circuit that positively feeds back the output of the internal transconductance amplifier to its input side may be provided.
  • the first amplifier circuit further includes another transconductance amplifier that generates a current corresponding to the voltage with respect to the output current of the transconductance amplifier of the first amplifier circuit.
  • the active load of the second amplifier circuit may generate a current obtained by adding the output current of the other transconductance amplifier and the output current of the transconductance amplifier of the second amplifier circuit. This brings about the effect of performing current addition in the active load of the second amplifier circuit.
  • the gain of the first amplifier circuit is higher than the gain of the second amplifier circuit, and the speed of the first amplifier circuit is higher than the speed of the second amplifier circuit. Assuming that it is slow, a high-gain and high-speed operational amplifier can be obtained as a whole.
  • each of the first and second amplifier circuits may be a differential amplifier circuit. Even in this case, the common feedback circuit becomes unnecessary by assuming the current addition.
  • a third amplifier circuit that amplifies and outputs the voltage with respect to the output current of the second amplifier circuit may be further provided.
  • the third amplifier circuit may be a push-pull circuit or a class AB amplifier. That is, an amplifier suitable for the application can be used as an output stage.
  • FIG. 1 is a block diagram showing an example of an operational amplifier according to the first embodiment of the present technology.
  • This operational amplifier includes a first amplifier circuit 100 and a second amplifier circuit 200.
  • the first amplifier circuit 100 and the second amplifier circuit 200 are differential amplifier circuits, and input signals from the input terminals 11 and 12 of the operational amplifier are similarly input to both of them. Further, the output signal of the second amplifier circuit 200 is output to the output terminals 91 and 92 of the operational amplifier.
  • the input signal and output signal of this operational amplifier are differential signals.
  • the first amplifier circuit 100 includes a transconductance amplifier 110, an active load 120, and a transconductance amplifier 130.
  • the second amplifier circuit 200 includes a transconductance amplifier 210 and an active load 220.
  • the transconductance amplifiers 110, 130 and 210 are current-voltage conversion circuits that convert the input voltage into a current.
  • the transconductance amplifier 110 generates a current corresponding to the voltage of the input signal from the input terminals 11 and 12.
  • the active load 120 is an active load (transistor load) of the transconductance amplifier 110.
  • the transconductance amplifier 130 generates a current corresponding to the voltage with respect to the current generated by the transconductance amplifier 110.
  • the current generated by the transconductance amplifier 110 becomes a voltage corresponding to the current due to the capacitance 129, and is input to the transconductance amplifier 130 as a voltage.
  • the transconductance amplifier 210 generates a current corresponding to the voltage of the input signal from the input terminals 11 and 12.
  • the active load 220 is the active load of the transconductance amplifiers 210 and 130.
  • the active load 220 is shared by the transconductance amplifiers 210 and 130.
  • the active load 220 has a function of adding the current generated by the transconductance amplifier 210 and the current generated by the transconductance amplifier 130.
  • the current added in the active load 220 becomes a voltage corresponding to the current due to the capacitance 229, and is output to the output terminals 91 and 92.
  • FIG. 2 is a circuit diagram showing an example of an operational amplifier according to the first embodiment of the present technology.
  • this operational amplifier includes a first amplifier circuit 100 and a second amplifier circuit 200.
  • the circuits inside the first amplifier circuit 100 and the second amplifier circuit 200 are the transconductance amplifiers 110, 130 and 210 and the active load as described above, except that the current sources 113, 133 and 213 are specified. It includes 120 and 220. Current sources 113, 133 and 213 generate current from the power supply potential VDD.
  • the transconductance amplifier 110 includes P-type MOS (Metal-Oxide-Semiconductor) transistors 111 and 112 in which one of the differential input signals is input to the gate.
  • the sources of the MOS transistors 111 and 112 are connected to the current source 113.
  • the drains of the MOS transistors 111 and 112 are connected to the inputs of the active load 120 and the transconductance amplifier 130.
  • the active load 120 includes N-type MOS transistors 121 to 124 and resistors 125 and 126.
  • the source of the MOS transistors 121 to 124 is connected to the ground potential VSS.
  • MOS transistors 121 and 122 constitute a transconductance amplifier (internal transconductance amplifier of active load 120).
  • the output of the transconductance amplifier 110 is connected to the gates of the MOS transistors 121 and 122 via resistors 125 and 126. That is, the resistors 125 and 126 generate a voltage corresponding to the output current of the transconductance amplifier 110, and this voltage is applied between the gate and drain of the MOS transistors 121 and 122.
  • the MOS transistors 123 and 124 cross-connect the gate and drain to each other. As a result, the transconductance amplifier composed of the MOS transistors 121 and 122 is positively fed back. That is, the MOS transistors 123 and 124 are positive feedback circuits that positively feed back the output of the transconductance amplifier composed of the MOS transistors 121 and 122 to the input side thereof.
  • the transconductance amplifier 130 includes P-type MOS transistors 131 and 132 in which one of the differential signals, which is the output signal of the transconductance amplifier 110, is input to the gate.
  • the sources of the MOS transistors 131 and 132 are connected to the current source 133.
  • the drains of the MOS transistors 131 and 132 are connected to the input of the active load 220.
  • the transconductance amplifier 210 includes P-type MOS transistors 211 and 212 in which one of the differential input signals is input to the gate.
  • the sources of the MOS transistors 211 and 212 are connected to the current source 213.
  • the drains of the MOS transistors 211 and 212 are connected to the input of the active load 220.
  • the active load 220 includes N-type MOS transistors 221 to 224 and resistors 225 and 226.
  • the sources of the MOS transistors 221 to 224 are connected to the ground potential VSS.
  • MOS transistors 221 and 222 constitute a transconductance amplifier (internal transconductance amplifier of active load 220).
  • the output of the transconductance amplifier 210 and the output of the transconductance amplifier 130 are connected to the gates of the MOS transistors 221 and 222 via resistors 225 and 226. That is, the resistors 125 and 126 generate a voltage corresponding to the sum of the output current of the transconductance amplifier 110 and the output current of the transconductance amplifier 130, and this voltage is applied between the gate and drain of the MOS transistors 221 and 222. Will be done.
  • the MOS transistors 223 and 224 cross-connect the gate and drain to each other.
  • the transconductance amplifier composed of the MOS transistors 221 and 222 is positively fed back. That is, the MOS transistors 223 and 224 are positive feedback circuits that positively feed back the output of the transconductance amplifier composed of the MOS transistors 221 and 222 to the input side thereof.
  • the output signal of the transconductance amplifier 210 with the active load 220 as the load is output as the differential output signal of the second amplifier circuit 200.
  • FIG. 3 is a diagram showing an example of an active load equivalent circuit according to an embodiment of the present technology.
  • Each of the active loads 120 and 220 in this embodiment is represented as a load 20 in which the transconductance amplifier 10 is positively fed back.
  • a load 20 in which the transconductance amplifier 10 is positively fed back.
  • the impedances Z of the active loads 120 and 220 are expressed by the following equations.
  • FIG. 4 is a diagram showing an example of an equivalent circuit of an operational amplifier according to the first embodiment of the present technology.
  • the input resistance Rin and the feedback resistance Rf are connected, and the relationship between the off voltage Voff, the input voltage Vin, and the output voltage Vout is examined.
  • the mutual conductances of the transconductance amplifiers 110, 130, and 210 are gm1, gm1a, and gm2, respectively. Further, the resistance values of the active loads 120 and 220 are both set to R0.
  • the open loop gain (gain) Av1 of the first amplifier circuit 100 is expressed by the following equation.
  • Av1 gm1, R0, gm1a, R0
  • Av2 gm2 ⁇ R0
  • the operational amplifier according to the first embodiment if the gain Av1 of the first amplifier circuit 100 is made sufficiently higher than the gain Av2 of the second amplifier circuit 200, the flicker noise of the second amplifier circuit 200 and the like It is possible to avoid the influence of the offset due to.
  • the combination of the first amplifier circuit 100 and the second amplifier circuit 200 does not affect the DC level transfer function.
  • a plurality of amplifier circuits can be used by adding the output signals of the first amplifier circuit 100 and the second amplifier circuit 200 by the current. It can. That is, the circuit for controlling the voltage level required in the conventional voltage addition can be omitted.
  • a high gain and low speed amplifier circuit is adopted as the first amplifier circuit 100 and a low gain and high speed amplifier circuit is adopted as the second amplifier circuit 200, a high gain and high speed operational amplifier can be obtained as a whole. Be done.
  • Second Embodiment> an example in which the operational amplifier of the first embodiment described above is applied to a class AB output amplifier will be described.
  • FIG. 5 is a block diagram showing an example of an operational amplifier according to a second embodiment of the present technology.
  • the operational amplifier in the second embodiment includes a third amplifier circuit 300 as an output stage in addition to the first amplifier circuit 100 and the second amplifier circuit 200. As a result, signal amplification can be performed according to the application.
  • first amplifier circuit 100 and the second amplifier circuit 200 are the same as those in the first embodiment described above, detailed description thereof will be omitted.
  • FIG. 6 is a circuit diagram showing an example of an operational amplifier according to a second embodiment of the present technology.
  • the class AB output stage is configured as the third amplifier circuit 300. That is, the third amplifier circuit 300 is a class AB amplifier that amplifies the voltage with respect to the output current of the second amplifier circuit 200.
  • the third amplifier circuit 300 includes N-type MOS transistors 311 and 312 and P-type MOS transistors 321 and 322, and constitutes a minimum selector push-pull circuit which is a kind of differential amplifier circuit.
  • the present technology can have the following configurations.
  • a first amplifier circuit that outputs a current according to the input voltage
  • An operational amplifier including a second amplifier circuit that outputs a current obtained by adding a current corresponding to the input voltage and a current output from the first amplifier circuit.
  • Each of the first and second amplifier circuits has an active load that serves as a load for the transconductance amplifier.
  • the active load includes an internal transconductance amplifier that generates a current corresponding to a voltage with respect to the output current of the transconductance amplifier, and a positive feedback circuit that positively feeds back the output of the internal transconductance amplifier to its input side.
  • the first amplifier circuit further includes another transconductance amplifier that generates a current corresponding to a voltage with respect to the output current of the transconductance amplifier of the first amplifier circuit.
  • the active load of the second amplifier circuit is described in (3) above, which generates a current obtained by adding the output current of the other transconductance amplifier and the output current of the transconductance amplifier of the second amplifier circuit. Operational amplifier.
  • Transconductance amplifier 20 Load 100 First amplifier circuit 110 Transconductance amplifier 111, 112 MOS transistor 113 Current source 120 Active load 121 to 124 MOS transistor 125, 126 Resistance 129 Capacity 130 Transconductance amplifier 131, 132 MOS transistor 133 Current source 200 Second amplifier circuit 210 Transconductance amplifier 211, 212 MOS transistor 213 Current source 220 Active load 221 to 224 MOS transistor 225, 226 Resistance 229 Capacity 300 Third amplifier circuit 311, 312, 321, 322 MOS transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The present invention eliminates complicated control of voltage levels in an operational amplifier. This operational amplifier comprises a first amplifier circuit and a second amplifier circuit. The first amplifier circuit outputs a current corresponding to an input voltage. The second amplifier circuit generates a current corresponding to the input voltage. The second amplifier circuit outputs a current that is the sum of the self-generated current and the current output from the first amplifier circuit. For example, an overall high-gain, high-speed operational amplifier can be obtained without requiring a circuit for voltage level control by adopting a high-gain, low-speed amplifier circuit as the first amplifier circuit and adopting a low-gain, high-speed amplifier circuit as the second amplifier circuit.

Description

演算増幅器Op amp
　本技術は、演算増幅器に関する。詳しくは、入力電圧を増幅して出力する演算増幅器に関する。 This technology relates to operational amplifiers. More specifically, the present invention relates to an operational amplifier that amplifies and outputs an input voltage.
　従来、演算増幅器の利得を向上させるために、複数の増幅回路の出力信号を足し合わせる技術が知られている。例えば、２段増幅回路の出力と並列に１段増幅回路を接続して、両者の出力信号を重畳する増幅回路が提案されている（例えば、特許文献１参照。）。 Conventionally, a technique of adding output signals of a plurality of amplifier circuits has been known in order to improve the gain of an operational amplifier. For example, an amplifier circuit has been proposed in which a one-stage amplifier circuit is connected in parallel with the output of the two-stage amplifier circuit and the output signals of both are superimposed (see, for example, Patent Document 1).
特開２０１７－０７９３９７号公報Japanese Unexamined Patent Publication No. 2017-07939
　上述の従来技術では、並列に接続される増幅回路の出力信号の位相を同位相にすることにより、直流利得を低下させることなく信号帯域の広域化を図っている。しかしながら、従来技術では増幅回路の出力信号を電圧レベルで加算しているため、直流成分を除去するための容量が必要になる。また、差動信号を扱う場合には、コモンモード電圧を決定するためにコモンフィードバック回路が必要になる。 In the above-mentioned conventional technique, the phase of the output signals of the amplifier circuits connected in parallel is made in phase, so that the signal band is widened without lowering the DC gain. However, in the prior art, since the output signal of the amplifier circuit is added at the voltage level, a capacitance for removing the DC component is required. Further, when handling a differential signal, a common feedback circuit is required to determine the common mode voltage.
　本技術はこのような状況に鑑みて生み出されたものであり、演算増幅器において電圧レベルの制御に必要な回路を省くことを目的とする。 This technology was created in view of this situation, and aims to omit the circuit required to control the voltage level in the operational amplifier.
　本技術は、上述の問題点を解消するためになされたものであり、その第１の側面は、入力電圧に応じた電流を出力する第１の増幅回路と、上記入力電圧に応じた電流と上記第１の増幅回路から出力された電流とを加えた電流を出力する第２の増幅回路とを具備する演算増幅器である。これにより、２つの増幅回路の出力を電流加算して出力するという作用をもたらす。 The present technology has been made to solve the above-mentioned problems, and the first aspect thereof is a first amplifier circuit that outputs a current corresponding to an input voltage, and a current corresponding to the input voltage. This is an operational amplifier including a second amplifier circuit that outputs a current obtained by adding a current output from the first amplifier circuit. This has the effect of adding current to the outputs of the two amplifier circuits and outputting them.
　また、この第１の側面において、上記第１および第２の増幅回路の各々は、上記入力電圧に応じた電流を生成するトランスコンダクタンスアンプを備えるようにしてもよい。この場合において、上記第１および第２の増幅回路の各々は、上記トランスコンダクタンスアンプの負荷となるアクティブロードを備え、上記アクティブロードは、上記トランスコンダクタンスアンプの出力電流に対する電圧に応じた電流を生成する内部トランスコンダクタンスアンプと、上記内部トランスコンダクタンスアンプの出力をその入力側に正帰還させる正帰還回路とを備えてもよい。正帰還をかけたアクティブロードを利用することにより、増幅回路として高ゲイン化を図るという作用をもたらす。 Further, in this first aspect, each of the first and second amplifier circuits may be provided with a transconductance amplifier that generates a current corresponding to the input voltage. In this case, each of the first and second amplifier circuits includes an active load that serves as a load for the transconductance amplifier, and the active load generates a current corresponding to the voltage with respect to the output current of the transconductance amplifier. An internal transconductance amplifier may be provided, and a positive feedback circuit that positively feeds back the output of the internal transconductance amplifier to its input side may be provided. By using the active load with positive feedback, it has the effect of increasing the gain as an amplifier circuit.
　また、この第１の側面において、上記第１の増幅回路は、上記第１の増幅回路の上記トランスコンダクタンスアンプの出力電流に対する電圧に応じた電流を生成する他のトランスコンダクタンスアンプをさらに備え、上記第２の増幅回路の上記アクティブロードは、上記他のトランスコンダクタンスアンプの出力電流と上記第２の増幅回路の上記トランスコンダクタンスアンプの出力電流とを加算した電流を生成するようにしてもよい。これにより、第２の増幅回路のアクティブロードにおいて電流加算を行うという作用をもたらす。 Further, in the first aspect, the first amplifier circuit further includes another transconductance amplifier that generates a current corresponding to the voltage with respect to the output current of the transconductance amplifier of the first amplifier circuit. The active load of the second amplifier circuit may generate a current obtained by adding the output current of the other transconductance amplifier and the output current of the transconductance amplifier of the second amplifier circuit. This brings about the effect of performing current addition in the active load of the second amplifier circuit.
　また、この第１の側面において、上記第１の増幅回路のゲインは上記第２の増幅回路のゲインよりも高く、また、上記第１の増幅回路の速度は上記第２の増幅回路の速度よりも遅い場合を想定すると、全体として高ゲインで高速な演算増幅器が得られる。 Further, in this first aspect, the gain of the first amplifier circuit is higher than the gain of the second amplifier circuit, and the speed of the first amplifier circuit is higher than the speed of the second amplifier circuit. Assuming that it is slow, a high-gain and high-speed operational amplifier can be obtained as a whole.
　また、この第１の側面において、上記第１および第２の増幅回路の各々は、差動増幅回路であってもよい。この場合であっても、電流加算を前提とすることにより、コモンフィードバック回路は不要となる。 Further, in this first aspect, each of the first and second amplifier circuits may be a differential amplifier circuit. Even in this case, the common feedback circuit becomes unnecessary by assuming the current addition.
　また、この第１の側面において、上記第２の増幅回路の出力電流に対する電圧を増幅して出力する第３の増幅回路をさらに具備してもよい。この場合において、上記第３の増幅回路は、プッシュプル回路であってもよく、また、ＡＢ級アンプであってもよい。すなわち、用途に応じたアンプを出力段として利用可能である。 Further, in the first aspect, a third amplifier circuit that amplifies and outputs the voltage with respect to the output current of the second amplifier circuit may be further provided. In this case, the third amplifier circuit may be a push-pull circuit or a class AB amplifier. That is, an amplifier suitable for the application can be used as an output stage.
本技術の第１の実施の形態における演算増幅器の一例を示すブロック図である。It is a block diagram which shows an example of the operational amplifier in 1st Embodiment of this technique. 本技術の第１の実施の形態における演算増幅器の一例を示す回路図である。It is a circuit diagram which shows an example of the operational amplifier in 1st Embodiment of this technique. 本技術の実施の形態におけるアクティブロードの等価回路の例を示す図である。It is a figure which shows the example of the equivalent circuit of the active load in embodiment of this technique. 本技術の第１の実施の形態における演算増幅器の等価回路の例を示す図である。It is a figure which shows the example of the equivalent circuit of the operational amplifier in the 1st Embodiment of this technique. 本技術の第２の実施の形態における演算増幅器の一例を示すブロック図である。It is a block diagram which shows an example of the operational amplifier in the 2nd Embodiment of this technique. 本技術の第２の実施の形態における演算増幅器の一例を示す回路図である。It is a circuit diagram which shows an example of the operational amplifier in the 2nd Embodiment of this technique.
　以下、本技術を実施するための形態（以下、実施の形態と称する）について説明する。説明は以下の順序により行う。
　１．第１の実施の形態（２つの増幅回路の出力を電流加算した例）
　２．第２の実施の形態（ＡＢ級出力アンプに適用した例） Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First Embodiment (Example of adding current to the outputs of two amplifier circuits)
2. Second embodiment (example applied to class AB output amplifier)
　＜１．第１の実施の形態＞
　［演算増幅器］
　図１は、本技術の第１の実施の形態における演算増幅器の一例を示すブロック図である。 <1. First Embodiment>
[Operational amplifier]
FIG. 1 is a block diagram showing an example of an operational amplifier according to the first embodiment of the present technology.
　この演算増幅器は、第１の増幅回路１００と、第２の増幅回路２００とを備える。第１の増幅回路１００および第２の増幅回路２００は差動増幅回路であり、何れにも演算増幅器の入力端子１１および１２からの入力信号が同様に入力される。また、第２の増幅回路２００の出力信号が演算増幅器の出力端子９１および９２に出力される。この演算増幅器の入力信号および出力信号は、差動信号である。 This operational amplifier includes a first amplifier circuit 100 and a second amplifier circuit 200. The first amplifier circuit 100 and the second amplifier circuit 200 are differential amplifier circuits, and input signals from the input terminals 11 and 12 of the operational amplifier are similarly input to both of them. Further, the output signal of the second amplifier circuit 200 is output to the output terminals 91 and 92 of the operational amplifier. The input signal and output signal of this operational amplifier are differential signals.
　第１の増幅回路１００は、トランスコンダクタンスアンプ１１０と、アクティブロード１２０と、トランスコンダクタンスアンプ１３０とを備える。また、第２の増幅回路２００は、トランスコンダクタンスアンプ２１０と、アクティブロード２２０とを備える。 The first amplifier circuit 100 includes a transconductance amplifier 110, an active load 120, and a transconductance amplifier 130. The second amplifier circuit 200 includes a transconductance amplifier 210 and an active load 220.
　トランスコンダクタンスアンプ１１０、１３０および２１０は、入力された電圧を電流に変換する電流電圧変換回路である。 The transconductance amplifiers 110, 130 and 210 are current-voltage conversion circuits that convert the input voltage into a current.
　トランスコンダクタンスアンプ１１０は、入力端子１１および１２からの入力信号の電圧に応じた電流を生成する。アクティブロード１２０は、トランスコンダクタンスアンプ１１０の能動負荷（トランジスタ負荷）である。 The transconductance amplifier 110 generates a current corresponding to the voltage of the input signal from the input terminals 11 and 12. The active load 120 is an active load (transistor load) of the transconductance amplifier 110.
　トランスコンダクタンスアンプ１３０は、トランスコンダクタンスアンプ１１０によって生成された電流に対する電圧に応じた電流を生成する。なお、トランスコンダクタンスアンプ１１０によって生成された電流は、容量１２９によってその電流に応じた電圧となり、電圧としてトランスコンダクタンスアンプ１３０に入力される。 The transconductance amplifier 130 generates a current corresponding to the voltage with respect to the current generated by the transconductance amplifier 110. The current generated by the transconductance amplifier 110 becomes a voltage corresponding to the current due to the capacitance 129, and is input to the transconductance amplifier 130 as a voltage.
　トランスコンダクタンスアンプ２１０は、入力端子１１および１２からの入力信号の電圧に応じた電流を生成する。アクティブロード２２０は、トランスコンダクタンスアンプ２１０および１３０の能動負荷である。 The transconductance amplifier 210 generates a current corresponding to the voltage of the input signal from the input terminals 11 and 12. The active load 220 is the active load of the transconductance amplifiers 210 and 130.
　このように、このアクティブロード２２０は、トランスコンダクタンスアンプ２１０および１３０に共有される。これにより、このアクティブロード２２０は、トランスコンダクタンスアンプ２１０によって生成された電流と、トランスコンダクタンスアンプ１３０によって生成された電流とを加算する機能を有する。このアクティブロード２２０において加算された電流は、容量２２９によってその電流に応じた電圧となり、出力端子９１および９２に出力される。 In this way, the active load 220 is shared by the transconductance amplifiers 210 and 130. As a result, the active load 220 has a function of adding the current generated by the transconductance amplifier 210 and the current generated by the transconductance amplifier 130. The current added in the active load 220 becomes a voltage corresponding to the current due to the capacitance 229, and is output to the output terminals 91 and 92.
　［回路］
　図２は、本技術の第１の実施の形態における演算増幅器の一例を示す回路図である。 [circuit]
FIG. 2 is a circuit diagram showing an example of an operational amplifier according to the first embodiment of the present technology.
　上述のブロック図について説明したように、この演算増幅器は、第１の増幅回路１００と、第２の増幅回路２００とを備える。第１の増幅回路１００および第２の増幅回路２００の内部の回路は、電流源１１３、１３３および２１３を明示した点を除き、上述のように、トランスコンダクタンスアンプ１１０、１３０および２１０と、アクティブロード１２０および２２０を備える。電流源１１３、１３３および２１３は、電源電位ＶＤＤから電流を生成するものである。 As described with respect to the block diagram described above, this operational amplifier includes a first amplifier circuit 100 and a second amplifier circuit 200. The circuits inside the first amplifier circuit 100 and the second amplifier circuit 200 are the transconductance amplifiers 110, 130 and 210 and the active load as described above, except that the current sources 113, 133 and 213 are specified. It includes 120 and 220. Current sources 113, 133 and 213 generate current from the power supply potential VDD.
　トランスコンダクタンスアンプ１１０は、差動入力信号の一方がゲートに入力されるＰ型のＭＯＳ（Metal-Oxide-Semiconductor）トランジスタ１１１および１１２を備える。ＭＯＳトランジスタ１１１および１１２のソースは、電流源１１３に接続される。ＭＯＳトランジスタ１１１および１１２のドレインは、アクティブロード１２０およびトランスコンダクタンスアンプ１３０の入力に接続される。 The transconductance amplifier 110 includes P-type MOS (Metal-Oxide-Semiconductor) transistors 111 and 112 in which one of the differential input signals is input to the gate. The sources of the MOS transistors 111 and 112 are connected to the current source 113. The drains of the MOS transistors 111 and 112 are connected to the inputs of the active load 120 and the transconductance amplifier 130.
　アクティブロード１２０は、Ｎ型のＭＯＳトランジスタ１２１乃至１２４と、抵抗１２５および１２６とを備える。ＭＯＳトランジスタ１２１乃至１２４のソースは、接地電位ＶＳＳに接続される。 The active load 120 includes N-type MOS transistors 121 to 124 and resistors 125 and 126. The source of the MOS transistors 121 to 124 is connected to the ground potential VSS.
　ＭＯＳトランジスタ１２１および１２２は、トランスコンダクタンスアンプ（アクティブロード１２０の内部トランスコンダクタンスアンプ）を構成する。ＭＯＳトランジスタ１２１および１２２のゲートには、抵抗１２５および１２６を介してトランスコンダクタンスアンプ１１０の出力が接続される。すなわち、抵抗１２５および１２６はトランスコンダクタンスアンプ１１０の出力電流に応じた電圧を生成し、この電圧がＭＯＳトランジスタ１２１および１２２のゲート・ドレイン間に印加される。 MOS transistors 121 and 122 constitute a transconductance amplifier (internal transconductance amplifier of active load 120). The output of the transconductance amplifier 110 is connected to the gates of the MOS transistors 121 and 122 via resistors 125 and 126. That is, the resistors 125 and 126 generate a voltage corresponding to the output current of the transconductance amplifier 110, and this voltage is applied between the gate and drain of the MOS transistors 121 and 122.
　また、ＭＯＳトランジスタ１２３および１２４は、ゲート・ドレインを互いにクロス接続する。これにより、ＭＯＳトランジスタ１２１および１２２により構成されるトランスコンダクタンスアンプに正帰還をかけた構造となる。すなわち、ＭＯＳトランジスタ１２３および１２４は、ＭＯＳトランジスタ１２１および１２２により構成されるトランスコンダクタンスアンプの出力をその入力側に正帰還させる正帰還回路である。 Further, the MOS transistors 123 and 124 cross-connect the gate and drain to each other. As a result, the transconductance amplifier composed of the MOS transistors 121 and 122 is positively fed back. That is, the MOS transistors 123 and 124 are positive feedback circuits that positively feed back the output of the transconductance amplifier composed of the MOS transistors 121 and 122 to the input side thereof.
　トランスコンダクタンスアンプ１３０は、トランスコンダクタンスアンプ１１０の出力信号である差動信号の一方がゲートに入力されるＰ型のＭＯＳトランジスタ１３１および１３２を備える。ＭＯＳトランジスタ１３１および１３２のソースは、電流源１３３に接続される。ＭＯＳトランジスタ１３１および１３２のドレインは、アクティブロード２２０の入力に接続される。 The transconductance amplifier 130 includes P- type MOS transistors 131 and 132 in which one of the differential signals, which is the output signal of the transconductance amplifier 110, is input to the gate. The sources of the MOS transistors 131 and 132 are connected to the current source 133. The drains of the MOS transistors 131 and 132 are connected to the input of the active load 220.
　トランスコンダクタンスアンプ２１０は、差動入力信号の一方がゲートに入力されるＰ型のＭＯＳトランジスタ２１１および２１２を備える。ＭＯＳトランジスタ２１１および２１２のソースは、電流源２１３に接続される。ＭＯＳトランジスタ２１１および２１２のドレインは、アクティブロード２２０の入力に接続される。 The transconductance amplifier 210 includes P- type MOS transistors 211 and 212 in which one of the differential input signals is input to the gate. The sources of the MOS transistors 211 and 212 are connected to the current source 213. The drains of the MOS transistors 211 and 212 are connected to the input of the active load 220.
　アクティブロード２２０は、Ｎ型のＭＯＳトランジスタ２２１乃至２２４と、抵抗２２５および２２６とを備える。ＭＯＳトランジスタ２２１乃至２２４のソースは、接地電位ＶＳＳに接続される。 The active load 220 includes N-type MOS transistors 221 to 224 and resistors 225 and 226. The sources of the MOS transistors 221 to 224 are connected to the ground potential VSS.
　ＭＯＳトランジスタ２２１および２２２は、トランスコンダクタンスアンプ（アクティブロード２２０の内部トランスコンダクタンスアンプ）を構成する。ＭＯＳトランジスタ２２１および２２２のゲートには、抵抗２２５および２２６を介してトランスコンダクタンスアンプ２１０の出力およびトランスコンダクタンスアンプ１３０の出力が接続される。すなわち、抵抗１２５および１２６はトランスコンダクタンスアンプ１１０の出力電流とトランスコンダクタンスアンプ１３０の出力電流とを加算した電流に応じた電圧を生成し、この電圧がＭＯＳトランジスタ２２１および２２２のゲート・ドレイン間に印加される。 MOS transistors 221 and 222 constitute a transconductance amplifier (internal transconductance amplifier of active load 220). The output of the transconductance amplifier 210 and the output of the transconductance amplifier 130 are connected to the gates of the MOS transistors 221 and 222 via resistors 225 and 226. That is, the resistors 125 and 126 generate a voltage corresponding to the sum of the output current of the transconductance amplifier 110 and the output current of the transconductance amplifier 130, and this voltage is applied between the gate and drain of the MOS transistors 221 and 222. Will be done.
　また、ＭＯＳトランジスタ２２３および２２４は、ゲート・ドレインを互いにクロス接続する。これにより、ＭＯＳトランジスタ２２１および２２２により構成されるトランスコンダクタンスアンプに正帰還をかけた構造となる。すなわち、ＭＯＳトランジスタ２２３および２２４は、ＭＯＳトランジスタ２２１および２２２により構成されるトランスコンダクタンスアンプの出力をその入力側に正帰還させる正帰還回路である。 Further, the MOS transistors 223 and 224 cross-connect the gate and drain to each other. As a result, the transconductance amplifier composed of the MOS transistors 221 and 222 is positively fed back. That is, the MOS transistors 223 and 224 are positive feedback circuits that positively feed back the output of the transconductance amplifier composed of the MOS transistors 221 and 222 to the input side thereof.
　アクティブロード２２０を負荷とするトランスコンダクタンスアンプ２１０の出力信号は、第２の増幅回路２００の差動出力信号として出力される。 The output signal of the transconductance amplifier 210 with the active load 220 as the load is output as the differential output signal of the second amplifier circuit 200.
　［アクティブロード］
　図３は、本技術の実施の形態におけるアクティブロードの等価回路の例を示す図である。 [Active load]
FIG. 3 is a diagram showing an example of an active load equivalent circuit according to an embodiment of the present technology.
　この実施の形態におけるアクティブロード１２０および２２０の各々は、トランスコンダクタンスアンプ１０に正帰還をかけた負荷２０として表される。正帰還をかけたアクティブロードを利用することにより、増幅回路として高ゲイン化を図ることができる。また、正帰還をかけたアクティブロードは、自動的にコモン電圧（平均電圧）が決定されるため、コモンフィードバック回路は不要になる。 Each of the active loads 120 and 220 in this embodiment is represented as a load 20 in which the transconductance amplifier 10 is positively fed back. By using an active load with positive feedback, it is possible to increase the gain as an amplifier circuit. Further, since the common voltage (average voltage) is automatically determined for the active load with positive feedback, the common feedback circuit becomes unnecessary.
　ここで、トランスコンダクタンスアンプ１０の相互コンダクタンスをｇｍ０、負荷２０の抵抗値をＲ０とすると、アクティブロード１２０および２２０のインピーダンスＺは次式により表される。
　　Ｚ＝－（Ｒ０／ｇｍ０）／（Ｒ０－（１／ｇｍ０））
　　　＝Ｒ０／（ｇｍ０・Ｒ０－１）
したがって、このインピーダンスＺは、ｇｍ０が「１／Ｒ０」である場合を境として、その極性が反転することがわかる。 Here, assuming that the transconductance of the transconductance amplifier 10 is gm0 and the resistance value of the load 20 is R0, the impedances Z of the active loads 120 and 220 are expressed by the following equations.
Z =-(R0 / gm0) / (R0- (1 / gm0))
= R0 / (gm0 ・ R0-1)
Therefore, it can be seen that the polarity of this impedance Z is reversed when gm0 is "1 / R0".
　［伝達特性］
　図４は、本技術の第１の実施の形態における演算増幅器の等価回路の例を示す図である。 [Transmission characteristics]
FIG. 4 is a diagram showing an example of an equivalent circuit of an operational amplifier according to the first embodiment of the present technology.
　ここでは、演算増幅器の伝達特性を解析するために、入力抵抗Ｒｉｎ、帰還抵抗Ｒｆを接続して、オフ電圧Ｖｏｆｆ、入力電圧Ｖｉｎおよび出力電圧Ｖｏｕｔの関係について検討する。 Here, in order to analyze the transmission characteristics of the operational amplifier, the input resistance Rin and the feedback resistance Rf are connected, and the relationship between the off voltage Voff, the input voltage Vin, and the output voltage Vout is examined.
　トランスコンダクタンスアンプ１１０、１３０、２１０の相互コンダクタンスを、それぞれｇｍ１、ｇｍ１ａ、ｇｍ２とする。また、アクティブロード１２０および２２０の抵抗値を、ともにＲ０とする。 The mutual conductances of the transconductance amplifiers 110, 130, and 210 are gm1, gm1a, and gm2, respectively. Further, the resistance values of the active loads 120 and 220 are both set to R0.
　このとき、第１の増幅回路１００のオープンループ利得（ゲイン）Ａｖ１は、次式により表される。
　　Ａｖ１＝ｇｍ１・Ｒ０・ｇｍ１ａ・Ｒ０ At this time, the open loop gain (gain) Av1 of the first amplifier circuit 100 is expressed by the following equation.
Av1 = gm1, R0, gm1a, R0
　また、第２の増幅回路２００のオープンループ利得（ゲイン）Ａｖ２は、次式により表される。
　　Ａｖ２＝ｇｍ２・Ｒ０ Further, the open loop gain (gain) Av2 of the second amplifier circuit 200 is expressed by the following equation.
Av2 = gm2 ・ R0
　まず、オフ電圧Ｖｏｆｆと出力電圧Ｖｏｕｔの関係を次式に示す。
Figure JPOXMLDOC01-appb-M000001
 上式において、Ａｖ１＞＞Ａｖ２を満たす場合には、
Figure JPOXMLDOC01-appb-M000002
 となる。すなわち、この場合は、第２の増幅回路２００のオフセットは出力電圧に表れなくなる。 First, the relationship between the off voltage Voff and the output voltage Vout is shown by the following equation.
Figure JPOXMLDOC01-appb-M000001
 In the above equation, when Av1 >> Av2 is satisfied,
Figure JPOXMLDOC01-appb-M000002
 Will be. That is, in this case, the offset of the second amplifier circuit 200 does not appear in the output voltage.
　一方、Ａｖ１＜＜Ａｖ２となる場合には、
Figure JPOXMLDOC01-appb-M000003
 となる。すなわち、この場合は、第２の増幅回路２００のオフセットが出力電圧に表れることになる。 On the other hand, when Av1 << Av2,
Figure JPOXMLDOC01-appb-M000003
 Will be. That is, in this case, the offset of the second amplifier circuit 200 appears in the output voltage.
　したがって、この第１の実施の形態における演算増幅器においては、第１の増幅回路１００のゲインＡｖ１を第２の増幅回路２００のゲインＡｖ２よりも十分高くすると、第２の増幅回路２００のフリッカーノイズ等によるオフセットの影響を回避することができる。 Therefore, in the operational amplifier according to the first embodiment, if the gain Av1 of the first amplifier circuit 100 is made sufficiently higher than the gain Av2 of the second amplifier circuit 200, the flicker noise of the second amplifier circuit 200 and the like It is possible to avoid the influence of the offset due to.
　次に、入力電圧Ｖｉｎと出力電圧Ｖｏｕｔの関係を次式に示す。
Figure JPOXMLDOC01-appb-M000004
 上式を変形すると、次式が得られる。
Figure JPOXMLDOC01-appb-M000005
 Next, the relationship between the input voltage Vin and the output voltage Vout is shown in the following equation.
Figure JPOXMLDOC01-appb-M000004
 By transforming the above equation, the following equation is obtained.
Figure JPOXMLDOC01-appb-M000005
　したがって、第１の増幅回路１００および第２の増幅回路２００を組み合わせても、直流レベルの伝達関数には影響を与えないことが分かる。 Therefore, it can be seen that the combination of the first amplifier circuit 100 and the second amplifier circuit 200 does not affect the DC level transfer function.
　このように、本技術の第１の実施の形態によれば、第１の増幅回路１００および第２の増幅回路２００の出力信号を電流により加算することにより、複数の増幅回路を利用することができる。すなわち、従来の電圧加算において必要とされた電圧レベルの制御のための回路を省くことができる。特に、第１の増幅回路１００として高ゲインで低速な増幅回路を採用し、第２の増幅回路２００として低ゲインで高速な増幅回路を採用すれば、全体として高ゲインで高速な演算増幅器が得られる。 As described above, according to the first embodiment of the present technology, a plurality of amplifier circuits can be used by adding the output signals of the first amplifier circuit 100 and the second amplifier circuit 200 by the current. it can. That is, the circuit for controlling the voltage level required in the conventional voltage addition can be omitted. In particular, if a high gain and low speed amplifier circuit is adopted as the first amplifier circuit 100 and a low gain and high speed amplifier circuit is adopted as the second amplifier circuit 200, a high gain and high speed operational amplifier can be obtained as a whole. Be done.
　＜２．第２の実施の形態＞
　この第２の実施の形態では、上述の第１の実施の形態の演算増幅器をＡＢ級出力アンプに適用した例について説明する。 <2. Second Embodiment>
In this second embodiment, an example in which the operational amplifier of the first embodiment described above is applied to a class AB output amplifier will be described.
　［演算増幅器］
　図５は、本技術の第２の実施の形態における演算増幅器の一例を示すブロック図である。 [Operational amplifier]
FIG. 5 is a block diagram showing an example of an operational amplifier according to a second embodiment of the present technology.
　この第２の実施の形態における演算増幅器は、第１の増幅回路１００および第２の増幅回路２００に加えて、出力段として第３の増幅回路３００を備える。これにより、用途に応じた信号増幅を行うことができる。 The operational amplifier in the second embodiment includes a third amplifier circuit 300 as an output stage in addition to the first amplifier circuit 100 and the second amplifier circuit 200. As a result, signal amplification can be performed according to the application.
　なお、第１の増幅回路１００および第２の増幅回路２００については、上述の第１の実施の形態と同様であるため、詳細な説明は省略する。 Since the first amplifier circuit 100 and the second amplifier circuit 200 are the same as those in the first embodiment described above, detailed description thereof will be omitted.
　［回路］
　図６は、本技術の第２の実施の形態における演算増幅器の一例を示す回路図である。 [circuit]
FIG. 6 is a circuit diagram showing an example of an operational amplifier according to a second embodiment of the present technology.
　この例では、オーディオアンプを想定して、第３の増幅回路３００として、ＡＢ級出力段を構成している。すなわち、この第３の増幅回路３００は、第２の増幅回路２００の出力電流に対する電圧を増幅するＡＢ級アンプである。 In this example, assuming an audio amplifier, the class AB output stage is configured as the third amplifier circuit 300. That is, the third amplifier circuit 300 is a class AB amplifier that amplifies the voltage with respect to the output current of the second amplifier circuit 200.
　この第３の増幅回路３００は、Ｎ型のＭＯＳトランジスタ３１１および３１２と、Ｐ型のＭＯＳトランジスタ３２１および３２２を備え、差動増幅回路の一種であるミニマムセレクタ・プッシュプル回路を構成する。 The third amplifier circuit 300 includes N- type MOS transistors 311 and 312 and P- type MOS transistors 321 and 322, and constitutes a minimum selector push-pull circuit which is a kind of differential amplifier circuit.
　このように、本技術の第２の実施の形態によれば、用途に応じた出力段を備える演算増幅器を構成することができる。 As described above, according to the second embodiment of the present technology, it is possible to configure an operational amplifier having an output stage according to the application.
　なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。 Note that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a corresponding relationship with each other. Similarly, the matters specifying the invention within the scope of claims and the matters in the embodiment of the present technology having the same name have a corresponding relationship with each other. However, the present technology is not limited to the embodiment, and can be embodied by applying various modifications to the embodiment without departing from the gist thereof.
　なお、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。 It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.
　なお、本技術は以下のような構成もとることができる。
（１）入力電圧に応じた電流を出力する第１の増幅回路と、
　前記入力電圧に応じた電流と前記第１の増幅回路から出力された電流とを加えた電流を出力する第２の増幅回路と
を具備する演算増幅器。
（２）前記第１および第２の増幅回路の各々は、前記入力電圧に応じた電流を生成するトランスコンダクタンスアンプを備える
前記（１）に記載の演算増幅器。
（３）前記第１および第２の増幅回路の各々は、前記トランスコンダクタンスアンプの負荷となるアクティブロードを備え、
　前記アクティブロードは、前記トランスコンダクタンスアンプの出力電流に対する電圧に応じた電流を生成する内部トランスコンダクタンスアンプと、前記内部トランスコンダクタンスアンプの出力をその入力側に正帰還させる正帰還回路とを備える
前記（２）に記載の演算増幅器。
（４）前記第１の増幅回路は、前記第１の増幅回路の前記トランスコンダクタンスアンプの出力電流に対する電圧に応じた電流を生成する他のトランスコンダクタンスアンプをさらに備え、
　前記第２の増幅回路の前記アクティブロードは、前記他のトランスコンダクタンスアンプの出力電流と前記第２の増幅回路の前記トランスコンダクタンスアンプの出力電流とを加算した電流を生成する
前記（３）に記載の演算増幅器。
（５）前記第１の増幅回路のゲインは前記第２の増幅回路のゲインよりも高い
前記（１）から（４）のいずれかに記載の演算増幅器。
（６）前記第１の増幅回路の速度は前記第２の増幅回路の速度よりも遅い
前記（１）から（５）のいずれかに記載の演算増幅器。
（７）前記第１および第２の増幅回路の各々は、差動増幅回路である
前記（１）から（６）のいずれかに記載の演算増幅器。
（８）前記第２の増幅回路の出力電流に対する電圧を増幅して出力する第３の増幅回路をさらに具備する前記（１）から（７）のいずれかに記載の演算増幅器。
（９）前記第３の増幅回路は、プッシュプル回路である
前記（８）に記載の演算増幅器。
（１０）前記第３の増幅回路は、ＡＢ級アンプである
前記（８）または（９）に記載の演算増幅器。 The present technology can have the following configurations.
(1) A first amplifier circuit that outputs a current according to the input voltage, and
An operational amplifier including a second amplifier circuit that outputs a current obtained by adding a current corresponding to the input voltage and a current output from the first amplifier circuit.
(2) The operational amplifier according to (1), wherein each of the first and second amplifier circuits includes a transconductance amplifier that generates a current corresponding to the input voltage.
(3) Each of the first and second amplifier circuits has an active load that serves as a load for the transconductance amplifier.
The active load includes an internal transconductance amplifier that generates a current corresponding to a voltage with respect to the output current of the transconductance amplifier, and a positive feedback circuit that positively feeds back the output of the internal transconductance amplifier to its input side. The operational amplifier according to 2).
(4) The first amplifier circuit further includes another transconductance amplifier that generates a current corresponding to a voltage with respect to the output current of the transconductance amplifier of the first amplifier circuit.
The active load of the second amplifier circuit is described in (3) above, which generates a current obtained by adding the output current of the other transconductance amplifier and the output current of the transconductance amplifier of the second amplifier circuit. Operational amplifier.
(5) The operational amplifier according to any one of (1) to (4), wherein the gain of the first amplifier circuit is higher than the gain of the second amplifier circuit.
(6) The operational amplifier according to any one of (1) to (5), wherein the speed of the first amplifier circuit is slower than the speed of the second amplifier circuit.
(7) The operational amplifier according to any one of (1) to (6) above, wherein each of the first and second amplifier circuits is a differential amplifier circuit.
(8) The operational amplifier according to any one of (1) to (7) above, further comprising a third amplifier circuit that amplifies and outputs a voltage with respect to the output current of the second amplifier circuit.
(9) The operational amplifier according to (8) above, wherein the third amplifier circuit is a push-pull circuit.
(10) The operational amplifier according to (8) or (9) above, wherein the third amplifier circuit is a class AB amplifier.
　１０　トランスコンダクタンスアンプ
　２０　負荷
　１００　第１の増幅回路
　１１０　トランスコンダクタンスアンプ
　１１１、１１２　ＭＯＳトランジスタ
　１１３　電流源
　１２０　アクティブロード
　１２１～１２４　ＭＯＳトランジスタ
　１２５、１２６　抵抗
　１２９　容量
　１３０　トランスコンダクタンスアンプ
　１３１、１３２　ＭＯＳトランジスタ
　１３３　電流源
　２００　第２の増幅回路
　２１０　トランスコンダクタンスアンプ
　２１１、２１２　ＭＯＳトランジスタ
　２１３　電流源
　２２０　アクティブロード
　２２１～２２４　ＭＯＳトランジスタ
　２２５、２２６　抵抗
　２２９　容量
　３００　第３の増幅回路
　３１１、３１２、３２１、３２２　ＭＯＳトランジスタ 10 Transconductance amplifier 20 Load 100 First amplifier circuit 110 Transconductance amplifier 111, 112 MOS transistor 113 Current source 120 Active load 121 to 124 MOS transistor 125, 126 Resistance 129 Capacity 130 Transconductance amplifier 131, 132 MOS transistor 133 Current source 200 Second amplifier circuit 210 Transconductance amplifier 211, 212 MOS transistor 213 Current source 220 Active load 221 to 224 MOS transistor 225, 226 Resistance 229 Capacity 300 Third amplifier circuit 311, 312, 321, 322 MOS transistor

Claims (10)

  1. 　入力電圧に応じた電流を出力する第１の増幅回路と、
    　前記入力電圧に応じた電流と前記第１の増幅回路から出力された電流とを加えた電流を出力する第２の増幅回路と
    を具備する演算増幅器。     The first amplifier circuit that outputs the current according to the input voltage and
    An operational amplifier including a second amplifier circuit that outputs a current obtained by adding a current corresponding to the input voltage and a current output from the first amplifier circuit.
  2. 　前記第１および第２の増幅回路の各々は、前記入力電圧に応じた電流を生成するトランスコンダクタンスアンプを備える
    請求項１記載の演算増幅器。     The operational amplifier according to claim 1, wherein each of the first and second amplifier circuits includes a transconductance amplifier that generates a current corresponding to the input voltage.
  3. 　前記第１および第２の増幅回路の各々は、前記トランスコンダクタンスアンプの負荷となるアクティブロードを備え、
    　前記アクティブロードは、前記トランスコンダクタンスアンプの出力電流に対する電圧に応じた電流を生成する内部トランスコンダクタンスアンプと、前記内部トランスコンダクタンスアンプの出力をその入力側に正帰還させる正帰還回路とを備える
    請求項２記載の演算増幅器。     Each of the first and second amplifier circuits has an active load that serves as a load for the transconductance amplifier.
    A claim that the active load includes an internal transconductance amplifier that generates a current corresponding to a voltage with respect to the output current of the transconductance amplifier, and a positive feedback circuit that positively feeds back the output of the internal transconductance amplifier to its input side. 2. The operational amplifier according to 2.
  4. 　前記第１の増幅回路は、前記第１の増幅回路の前記トランスコンダクタンスアンプの出力電流に対する電圧に応じた電流を生成する他のトランスコンダクタンスアンプをさらに備え、
    　前記第２の増幅回路の前記アクティブロードは、前記他のトランスコンダクタンスアンプの出力電流と前記第２の増幅回路の前記トランスコンダクタンスアンプの出力電流とを加算した電流を生成する
    請求項３記載の演算増幅器。     The first amplifier circuit further includes another transconductance amplifier that generates a current corresponding to a voltage with respect to the output current of the transconductance amplifier of the first amplifier circuit.
    The operation according to claim 3, wherein the active load of the second amplifier circuit generates a current obtained by adding the output current of the other transconductance amplifier and the output current of the transconductance amplifier of the second amplifier circuit. amplifier.
  5. 　前記第１の増幅回路のゲインは前記第２の増幅回路のゲインよりも高い
    請求項１記載の演算増幅器。     The operational amplifier according to claim 1, wherein the gain of the first amplifier circuit is higher than the gain of the second amplifier circuit.
  6. 　前記第１の増幅回路の速度は前記第２の増幅回路の速度よりも遅い
    請求項１記載の演算増幅器。     The operational amplifier according to claim 1, wherein the speed of the first amplifier circuit is slower than the speed of the second amplifier circuit.
  7. 　前記第１および第２の増幅回路の各々は、差動増幅回路である
    請求項１記載の演算増幅器。     The operational amplifier according to claim 1, wherein each of the first and second amplifier circuits is a differential amplifier circuit.
  8. 　前記第２の増幅回路の出力電流に対する電圧を増幅して出力する第３の増幅回路をさらに具備する請求項１記載の演算増幅器。 The operational amplifier according to claim 1, further comprising a third amplifier circuit that amplifies and outputs a voltage with respect to the output current of the second amplifier circuit.
  9. 　前記第３の増幅回路は、プッシュプル回路である
    請求項８記載の演算増幅器。     The operational amplifier according to claim 8, wherein the third amplifier circuit is a push-pull circuit.
  10. 　前記第３の増幅回路は、ＡＢ級アンプである
    請求項８記載の演算増幅器。     The operational amplifier according to claim 8, wherein the third amplifier circuit is a class AB amplifier.
PCT/JP2020/027316 2019-10-29 2020-07-14 Operational amplifier WO2021084809A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122624A1 (en) * 2001-12-21 2003-07-03 Stmicroelectronics S.R.L Analog input circuit with common mode compatibility to both supply nodes
JP2017079397A (en) * 2015-10-20 2017-04-27 株式会社東芝 Amplifier circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122624A1 (en) * 2001-12-21 2003-07-03 Stmicroelectronics S.R.L Analog input circuit with common mode compatibility to both supply nodes
JP2017079397A (en) * 2015-10-20 2017-04-27 株式会社東芝 Amplifier circuit

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