JP2018181162A - Information processor, information processing method, and information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor capable of recording and analyzing a pattern of memory access made by a user circuit.SOLUTION: A tracking unit is arranged between a user circuit and a system memory in an FPGA which executes part of application processing, a header information extraction unit of the tracking unit extracts access information in memory access from the user circuit to the memory access, a registration control unit of the tracking unit registers, for each application, a pattern of the memory access based on the extracted access information, and in a case where the memory access from the user circuit has been detected, a detection control unit of the tracking unit determines whether or not the pattern of the memory access based on the extracted access information and a registered pattern of memory access corresponding to the application agree with each other, thereby making it possible to record and analyze the pattern of the memory access by the user circuit.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an information processing apparatus, an information processing method, and an information processing system.

  It has CPU (Central Processing Unit) and FPGA (Field Programmable Gate Array) that can change the configuration of programmable logic circuit based on circuit information, and offloads part of processing performed by CPU to FPGA There is a system that speeds up processing. In such a system, the system memory is shared by the CPU and the FPGA, and data communication between the CPU and the FPGA is performed via the system memory.

JP 2001-325150 A JP, 2006-11692, A

  The FPGA has user circuits that process applications, and the area of system memory to which each user circuit can access is managed. When an attempt is made to access another area of the system memory due to a malfunction or malicious access (illegal access) of the user circuit, the access is suppressed.

  However, in the conventional method, within the area of the system memory to which the user circuit can access, even if the pattern of the memory access by the user circuit is different from the normal pattern, it can not be detected as an abnormal operation. . In one aspect, it is an object of the present invention to provide an information processing apparatus capable of recording and analyzing a memory access pattern by a user circuit.

  One aspect of the information processing apparatus is disposed between a processing circuit that executes a part of processing of an application and a memory, and an information extraction unit that extracts access information in memory access from the processing circuit to the memory; A registration unit for registering a memory access pattern based on access information extracted by the processing circuit from the first memory access to the memory, and a second memory access from the processing circuit to the memory; And a determination unit that determines whether or not the memory access pattern based on the access information extracted by the memory access according to and the registered memory access pattern corresponding to the application that performs the second memory access match.

  In one aspect of the present invention, it is possible to provide an information processing apparatus capable of recording and analyzing a memory access pattern by a processing circuit that executes part of application processing.

FIG. 1 is a diagram showing an exemplary configuration of an information processing system according to an embodiment of the present invention. FIG. 2 is a view showing a configuration example of the tracking unit in the present embodiment. FIG. 3 is a view showing an example of the format of a memory access packet in the present embodiment. FIG. 4 is a diagram for explaining a pattern table in the present embodiment. FIG. 5 is a diagram showing an operation example of the information processing system in the present embodiment. FIG. 6 is a diagram showing an operation example of the information processing system in the present embodiment. FIG. 7 is a diagram showing another configuration example of the information processing system in the present embodiment.

Hereinafter, embodiments of the present invention will be described based on the drawings.
FIG. 1 is a block diagram showing an exemplary configuration of an information processing system according to an embodiment of the present invention. The information processing system in the present embodiment includes a central processing unit (CPU) 10, a system memory 20, and a field programmable gate array (FPGA) 30.

  The CPU 10 includes CPU cores 11A and 11B, a memory management unit (MMU) 12, and an IO memory management unit (IOMMU) 13. The CPU 10 is an example of an arithmetic processing unit. The CPU cores 11A and 11B execute processing according to a program (application or the like) read from the system memory 20 or the like. Although the example shown in FIG. 1 shows an example having two CPU cores 11A and 11B, the present invention is not limited to this, and the number of CPU cores 11 that the CPU 10 has is arbitrary.

  The memory management unit (MMU) 12 controls access to the system memory 20 and the like, and performs, for example, conversion from a logical address of a virtual memory space to a physical address and data communication between the CPU 10 and the system memory 20. The IO memory management unit (IOMMU) 13 manages a memory space for IO (for input / output devices), and converts, for example, a logical address of a virtual memory space to an address assigned to an IO device, the CPU 10 and the FPGA 30 Perform data communication with each other.

  The system memory 20 is a memory that stores programs such as an operating system (OS) and applications, data, and the like. The system memory 20 is provided with, for example, a kernel area 21 in which a kernel or the like is stored, and shared memory areas 22A and 22B shared and used by the CPU 10 and the FPGA 30.

  The FPGA 30 is a reconfigurable device capable of changing the configuration of programmable logic circuits based on circuit information. The FPGA 30 has a user circuit (user logic) 31 and a tracking 32. The user circuit 31 is an example of a processing circuit. In the present embodiment, part of the processing performed by the CPU 10 is offloaded to the user circuit 31 of the FPGA 30 to perform processing.

  For example, in the FPGA 30, the user circuit A31A performs part of the processing of the application AppA executed by the CPU core 11A of the CPU 10, and the user circuit A31B performs part of the processing of the application AppB executed by the CPU core 11B of the CPU 10. . At this time, for example, the application AppA communicates with the user circuit A31A via the shared memory area A22A, and the application AppB communicates with the user circuit B31B via the shared memory area B22B.

  The tracking unit 32 is disposed between the user circuit 31 of the FPGA 30 and the IO memory management unit (IOMMU) 13 of the CPU 10, and records and analyzes a memory access pattern by the user circuit 31. The tracking unit 32 performs memory access registration from the user circuit 31 to the system memory 20 and abnormality detection. The tracking unit 32 may be disposed between the user circuit 31 of the FPGA 30 and the IO memory management unit (IOMMU) 13 of the CPU 10. The tracking unit 32 may be disposed not only in the FPGA 30, but also in the CPU 10. The CPU 10 and the FPGA 30 may be arranged as separate devices (ICs).

  The tracking unit 32 registers a memory access pattern from the user circuit 31 when operating in the registration mode, and performs abnormality detection of memory access from the user circuit 31 when operating in the detection mode. As described above, the pattern detection independent of the user circuit 31 and the application can be performed by separating the registration mode in which the memory access pattern is registered and the detection mode in which the memory access abnormality is detected.

  In the registration mode, the tracking unit 32 learns a memory access pattern for each application (process ID) executed by the user circuit 31 and for each access type (read or write). As the memory access pattern, the maximum address and the minimum address of <1> memory access, <2> memory access granularity (maximum burst length), and <3> the area to be subjected to the sequential access are specified and registered.

  Also, in the detection mode, whether or not the registered memory access pattern corresponding to the process ID and the access type (read or write) in the current memory access matches the current memory access pattern in the detection mode Determine If it is determined that the registered memory access pattern and the current memory access pattern do not match, the tracking unit 32 generates, for example, an interrupt to the CPU 10. At this time, the memory access may be blocked or operated continuously.

  FIG. 2 is a block diagram showing a configuration example of the tracking unit 32 in the present embodiment. The tracking unit 32 includes a header information extraction unit 201, a registration control unit 202, a detection control unit 203, an interrupt control unit 204, a table selection unit 205, and a pattern table 206.

  The header information extraction unit 201 is an example of the information extraction unit, and extracts access information from the memory access packet transmitted from the user circuit 31. An example of the format of the memory access packet is shown in FIG. The memory access packet includes a process ID (301) corresponding to an application (process) performing memory access, a virtual address (302) indicating an access destination, a command type (303), a data length (304), and data (305). Each has a field to store. The command type (303) for memory access by the user circuit 31 includes a read request to the memory requesting data read from the memory, a write request to the memory requesting data write to the memory, and access from the CPU (program IO) There is a PIO read response etc. to the CPU which responds to.

  The header information extraction unit 201 extracts, from the memory access packet from the user circuit 31, a process ID, a virtual address as an address, a command type as an access type, and a data length access information as an access size (burst length). When the command type is a read request or a write request, the header information extraction unit 201 outputs the registration control unit 202, the detection control unit 203, and the table selection unit 205 to the access information extracted from the memory access packet. Note that the header information extraction unit 201 may always output the access information extracted from the memory access packet, and may make it valid when the command type is a read request or a write request, and may make the others invalid.

  The registration control unit 202 is an example of a registration unit. The registration control unit 202 updates the pattern table corresponding to the process ID and the access type extracted from the memory access packet from the user circuit 31 in the registration mode. The registration control unit 202 registers the memory access pattern in the corresponding pattern table based on the access information extracted from the memory access packet from the user circuit 31. The registration control unit 202 has up to M sequential access determination units, and determines whether or not the current memory access from the user circuit 31 is a sequential access to a continuous area. Here, M is the number that can register information in the pattern table 206 as a sequential area.

  The sequential access determiner determines that sequential access is to be performed when access to a continuous address is permitted by the same command (access type) in a series of memory accesses issued from the user circuit 31, and that address section (start Hold address and end address) and command. Then, the registration control unit 202 updates the pattern table 206 based on the held address section and command. The sequential access determiner returns a hit if the memory access from the user circuit 31 matches the address section registered in the pattern table 206.

  The detection control unit 203 is an example of a detection unit. The detection control unit 203 compares the access information extracted from the memory access packet from the user circuit 31 in the detection mode with the information of the extracted process ID (application) and the pattern table 206 corresponding to the access type. It is determined whether the access patterns match. The detection control unit 203 registers the burst length of the <2> memory access in the pattern table 206 outside the range defined by the maximum address and the minimum address in which the address of the <1> memory access is registered in the pattern table 206. When any condition of exceeding the maximum burst length or accessing a sequential area registered in the <3> pattern table 206 with different commands is satisfied, it is determined that the memory access is abnormal and the interrupt control unit 204 Issue an interrupt notification request to That is, when the current memory access pattern does not match the memory access pattern registered in the pattern table 206, the detection control unit 203 issues an interrupt notification request to the interrupt control unit 204.

  When receiving the interrupt notification request from the detection control unit 203, the interrupt control unit 204 outputs an interrupt to the CPU 10. In addition to the interrupt to the CPU 10, information such as which condition is detected may be notified. The table selection unit 205 selects and outputs the pattern table 206 corresponding to the process ID and the access type extracted from the memory access packet from the user circuit 31 among the plurality of pattern tables 206.

  The pattern table 206 has information of maximum and minimum addresses of memory access, maximum burst length, and start and end addresses of M sets of sequential areas, as illustrated in FIG. Here, for example, when the start address of the sequential area is 0xFFFFFFFF, it indicates that the information of the sequential area is invalid. Although three pattern tables 206A, 206B and 206C are shown in the example shown in FIG. 2, the pattern table 206 is provided for each application (process ID) and each access type (read or write).

  As described above, in this embodiment, for example, when performing a test when introducing a product or a new application, the tracking unit 32 operates in advance in the registration mode, and the tracking unit 32 accesses the memory from the user circuit 31 of the FPGA 30 to the system memory 20 Is recorded as a pattern table 206 for each application (process ID) and each access type (read or write). Then, at the time of operation, the user circuit is operated in the detection mode, and the tracking unit 32 determines whether the memory access pattern from the user circuit 31 matches the memory access pattern registered in the pattern table 206 or not. Even when the area 31 is an accessible area, it is possible to detect memory access of a pattern different from a normal pattern.

  For example, by detecting during operation an abnormal memory access pattern from the user circuit 31 that occurs under a specific condition, it is possible to identify the problem of the user circuit 31 at an early stage. This is possible for both a malicious circuit as an example shown in FIG. 5 and a circuit including a bug causing an erroneous operation as an example shown in FIG.

  FIG. 5 is a diagram showing an operation example of the information processing system in the present embodiment. In FIG. 5, constituent elements having the same functions as the constituent elements shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. In the example shown in FIG. 5, the user circuit A 31 A of the FPGA 30 has a direct memory access (DMA) control unit 501. The DMA control unit 501 executes memory access in accordance with the page table 502. Here, it is assumed that the shared memory area A22A of the memory 20 is an area to which the user circuit A31A can access.

  When using the area 503 as the buffer A in the shared memory area A22A, first, an address indicating the area 503 is specified in the page table 502 of the DMA control unit 501 from the application AppA executed by the CPU core 11A (511). If the address specified in the page table 502 is an address indicating the area 503, the DMA control unit 501 executes a memory access to the area 503 of the memory 20 (512).

  However, it is assumed that the malicious circuit of the user circuit A31A rewrites the rewriting page table 502 to an address indicating an area 504 in which confidential data is stored, which is different from the area 503 in the shared memory A22A. The area 504 of the memory 20 is an area which is within the area accessible by the user circuit A31A but not allocated (designated) to the user circuit A31A.

  When the page table 502 is modified, the DMA control unit 501 executes memory access to the area 504 of the memory 20 which is outside the designated address according to the page table 502 (513). At this time, the tracking unit 32 refers to the pattern table to detect this access outside the address range registered as the memory access pattern (514). Then, the tracking unit 32 notifies the CPU core 11A (application AppA) of detection of abnormal memory access (515). Thereby, it can be recognized that the user circuit A31A of the FPGA 30 has some kind of malfunction.

  FIG. 6 is a diagram showing an operation example of the information processing system in the present embodiment. 6, the components having the same functions as the components shown in FIG. 1 are denoted by the same reference numerals, and the redundant description will be omitted. In the example shown in FIG. 6, the CPU core 11A executes the processing of the applications AppA and AppB by the virtual machine VM. Further, it is assumed that the user circuit A31A of the FPGA 30 performs a part of the processing of the application AppA, and the user circuit B31B of the FPGA 30 performs a part of the processing of the application AppB. When the applications AppA and AppB are operated by one virtual machine VM in this manner, the shared memory area of the memory 20 used by the applications AppA and AppB is one.

  When the application AppA and the user circuit A31A use the area 601 as the buffer A in the shared memory area A22A, an address indicating the area 601 is designated from the application AppA to the user circuit A31A (611). Executes a memory access to the area 601 of the memory 20 (612). Similarly, when the application AppB and the user circuit B31B use the area 602 in which the buffer B in the shared memory area A22A is used, an address indicating the area 602 is designated by the application AppB to the user circuit B31B (613). The user circuit B31B executes a memory access to the area 602 of the memory 20 (614).

  For example, when the user circuit B31B malfunctions due to a bug and the user circuit B31B erroneously executes a memory access to the area 601 which is made buffer A (616), the tracking unit 32 refers to the pattern table to perform memory access. This access is detected out of the address range registered as a pattern (617). Then, the tracking unit 32 notifies the CPU core 11A (application AppB) of detection of abnormal memory access (615). As a result, it can be recognized that the user circuit B31B of the FPGA 30 has some problems.

  Also, by utilizing the fact that the tracking unit 32 can acquire the memory access pattern from the user circuit 31 of the FPGA 30, the memory allocation is controlled according to the memory access pattern, and the memory arrangement for the application and user circuit 31 is optimized. It is possible to FIG. 7 is a block diagram showing another configuration example of the information processing system in the present embodiment. In FIG. 7, components having the same functions as the components shown in FIG. 1 will be assigned the same reference numerals and overlapping descriptions will be omitted.

  The information processing system shown in FIG. 7 has a memory 701 which operates faster than the system memory 20, in addition to the CPU 10, the system memory (main storage) 20, and the FPGA 30. The application AppA executed by the CPU core 11A uses the user circuit A31A of the FPGA 30, and the application AppA and the user circuit A31A communicate via the shared memory area A22A of the system memory 20. An area 702 of the shared memory area A22A is a memory area (Working Set) actually used by the user circuit A31A. In the CPU core 11B, a program (memory monitor) for allocating (mapping) a memory area is operating.

  A control procedure of memory area allocation in the information processing system shown in FIG. 7 will be described. In the following, the case where the memory area used by the user circuit A31A of the FPGA 30 is changed from the system memory 20 (shared memory area A22A) to the high speed memory 701 will be described as an example.

  In the CPU 10, the operating system (OS) normally executes the application AppA in the CPU core 11A, and the user circuit A 31A of the FPGA 30 executes a part of the processing. At this time, the tracking unit 32 operates in the registration mode, and records a pattern (address range) of memory access from the user circuit A 31A to the system memory 20. Also, the memory monitor operating on the CPU core 11B acquires the address range of the memory access to the system memory 20 from the user circuit A 31A recorded by the tracking unit 32.

  The memory monitor determines whether the address range of memory access from the user circuit A 31 A is smaller than the free space of the high speed memory 701. If it is determined that the address range of memory access from the user circuit A31A is smaller than the free space of the high-speed memory 701, the memory monitor sets the address range of memory access from the user circuit A31A to the IO memory management unit (IOMMU) 13. It instructs to allocate (remap) to the high speed memory 701.

  Thereafter, the tracking unit 32 is operated in the detection mode, and the operating system (OS) re-executes the application AppA in the CPU core 11A. As a result, the user circuit A31A of the FPGA 30 operates using the high speed memory 701, and can execute the application AppA at high speed. Here, for example, when the tracking unit 32 detects an abnormal memory access from the user circuit A31A, the memory monitor cancels the setting of the assignment of the high speed memory 702 to the user circuit A31A, and the address range of the memory access from the user circuit A31A. May be set in the system memory 20 (shared memory area A 22 A) and re-executed.

  As described above, the tracking unit 32 records the memory access pattern from the user circuit 31 and analyzes the memory usage of the user circuit 31, thereby reassigning the memory area to be used to the high-speed memory, etc. Memory placement for application and user circuitry 31 can be optimized. As a result, the memory access of the application and user circuit 31 can be speeded up, and the processing can be speeded up.

In addition, the said embodiment shows only an example of implementation in all in implementing this invention, and the technical scope of this invention should not be limitedly interpreted by these. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Further, the following appendices will be disclosed regarding the above-described embodiment.

(Supplementary Note 1)
A processing circuit that executes part of processing of an application, and is disposed between the processing circuit and the memory, which is formed by reconfiguring a programmable logic circuit based on circuit information, and the processing circuit An information extraction unit for extracting access information in memory access to the memory;
A registration unit that registers a memory access pattern based on the access information extracted by the information extraction unit in the first memory access from the processing circuit to the memory, for each of the applications;
When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access An information processing apparatus characterized by further comprising: a determination unit that determines whether the registered memory access pattern corresponding to the application that is to be matched matches.
(Supplementary Note 2)
The information processing apparatus according to claim 1, wherein the memory access pattern includes information of a maximum address and a minimum address accessed in the first memory access.
(Supplementary Note 3)
The information processing apparatus according to claim 2, wherein the memory access pattern includes at least one of a memory access granularity in the first memory access and information of an area in which sequential access is performed in the first memory access. .
(Supplementary Note 4)
The information processing apparatus according to any one of appendices 1 to 3, wherein the registration unit registers a memory access pattern for each of the applications and for each access type of the memory.
(Supplementary Note 5)
If the determination unit determines that the memory access pattern related to the second memory access does not match the registered memory access pattern, it outputs an interrupt to the application that performs the second memory access. The information processing apparatus according to any one of appendices 1 to 4, further comprising a load control unit.
(Supplementary Note 6)
The information extraction unit extracts, from the memory access packet from the processing circuit, information of a process ID, an address, an access type, and a data length according to the application. The information processing apparatus according to any one of the above.
(Appendix 7)
A processing circuit that executes part of processing of an application, and is disposed between the processing circuit and the memory, which is formed by reconfiguring a programmable logic circuit based on circuit information, and the processing circuit An information extraction unit for extracting access information in memory access to the memory;
And a registration unit that registers a memory access pattern based on the access information extracted by the information extraction unit for each of the applications.
An information processing apparatus, comprising: a plurality of memories having different access performances; and the allocation of the memories to the processing circuit based on a pattern of the memory access.
(Supplementary Note 8)
A processing circuit that executes part of processing of an application, and an information extraction unit disposed between the processing circuit and the memory, which is formed by reconfiguring a programmable logic circuit based on circuit information; Extracting access information in memory access to the memory from the processing circuit;
The memory access pattern is registered based on the access information extracted by the information extraction unit in the first memory access from the processing circuit to the memory for each application.
When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access And determining whether or not the registered memory access pattern corresponding to the application performing the step matches.
(Appendix 9)
An arithmetic processing unit for processing an application, a reconfigurable device capable of changing the configuration of a programmable logic circuit based on circuit information, and a processing circuit formed in the reconfigurable device and executing a part of the processing of the application An information processing system comprising: and a memory used by the application;
An information extraction unit disposed between the processing circuit and the memory for extracting access information in memory access to the memory from the processing circuit;
A registration unit that registers a memory access pattern based on the access information extracted by the information extraction unit in the first memory access from the processing circuit to the memory, for each of the applications;
When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access A determination unit that determines whether or not the registered memory access pattern corresponding to the application that is to be matched matches.

10 CPU
11 CPU core 12 memory management unit 13 IO memory management unit 20 system memory 21 kernel area 22 shared memory area 30 FPGA
31 user circuit 32 tracking unit 201 header information extraction unit 202 registration control unit 203 detection control unit 204 interrupt control unit 205 table selection unit 206 pattern table

Claims (8)

A processing circuit that executes part of processing of an application, and is disposed between the processing circuit and the memory, which is formed by reconfiguring a programmable logic circuit based on circuit information, and the processing circuit An information extraction unit for extracting access information in memory access to the memory;
A registration unit that registers a memory access pattern based on the access information extracted by the information extraction unit in the first memory access from the processing circuit to the memory, for each of the applications;
When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access An information processing apparatus characterized by further comprising: a determination unit that determines whether the registered memory access pattern corresponding to the application that is to be matched matches.   The information processing apparatus according to claim 1, wherein the memory access pattern includes information of a maximum address and a minimum address accessed in the first memory access.   3. The information processing according to claim 2, wherein the memory access pattern includes at least one of memory access granularity in the first memory access and information of an area to which sequential access is to be performed in the first memory access. apparatus.   The information processing apparatus according to any one of claims 1 to 3, wherein the registration unit registers a memory access pattern for each application and each access type of the memory.   If the determination unit determines that the memory access pattern related to the second memory access does not match the registered memory access pattern, it outputs an interrupt to the application that performs the second memory access. The information processing apparatus according to any one of claims 1 to 4, further comprising a load control unit. A processing circuit that executes part of processing of an application, and is disposed between the processing circuit and the memory, which is formed by reconfiguring a programmable logic circuit based on circuit information, and the processing circuit An information extraction unit for extracting access information in memory access to the memory;
And a registration unit that registers a memory access pattern based on the access information extracted by the information extraction unit for each of the applications.
An information processing apparatus, comprising: a plurality of memories having different access performances; and the allocation of the memories to the processing circuit based on a pattern of the memory access. A processing circuit that executes part of processing of an application, and an information extraction unit disposed between the processing circuit and the memory, which is formed by reconfiguring a programmable logic circuit based on circuit information; Extracting access information in memory access to the memory from the processing circuit;
The memory access pattern is registered based on the access information extracted by the information extraction unit in the first memory access from the processing circuit to the memory for each application.
When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access And determining whether or not the registered memory access pattern corresponding to the application performing the step matches. An arithmetic processing unit for processing an application, a reconfigurable device capable of changing the configuration of a programmable logic circuit based on circuit information, and a processing circuit formed in the reconfigurable device and executing a part of the processing of the application An information processing system comprising: and a memory used by the application;
An information extraction unit disposed between the processing circuit and the memory for extracting access information in memory access to the memory from the processing circuit;
A registration unit that registers a memory access pattern based on the access information extracted by the information extraction unit in the first memory access from the processing circuit to the memory, for each of the applications;
When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access A determination unit that determines whether or not the registered memory access pattern corresponding to the application that is to be matched matches.

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