JP2002063072A - Information processing device and printer having the same device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device, capable of enhancing program processing capacity. SOLUTION: A timer 9 is a circuit for interrupting a CPU 6 at fixed time intervals. When an interrupt is made by the timer 9, what part of a program 20 has been carried out can be known, by checking the value of an exception program counter 41 of the CPU 6 in an exception program. It is checked which block the value of the program counter 41 falls within the range of, and a value 1 is added to the frequency information of the relevant block. By carrying out this processing a certain number of times for a certain period of time, which blocks has been executed most frequently by the CPU 6 can be known. From the frequency information thus obtained, the block in a ROM(read only memory) proven to be most frequently executed by the CPU(central processing unit) 6 is reproduced in a RAM(random access memory) by copying. Then, a TLB(translation look-aside buffer) is reset, so as to convert the logical address of the CPU 6 into the physical address of the block copied in the RAM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and a printer having the information processing apparatus, and more particularly, to a ROM / RA.
The present invention relates to an information processing apparatus capable of executing a program at high speed using M, and to an information processing apparatus suitable for use as a printer control apparatus or the like.

[0002]

2. Description of the Related Art An information processing apparatus includes a CPU, a ROM, an RA,
M, a program to be executed by the CPU is stored in a ROM, which is a nonvolatile memory, and a RAM, which is a volatile memory, is used as a work area required during execution of the program.

In general, a RAM has a higher program execution speed than a ROM.
Executing on the RAM can be executed at higher speed than executing on the OM, and the performance of the information processing apparatus is also improved. However, since a RAM is generally more expensive than a ROM, a method for copying a program stored in the ROM onto the RAM and operating the RAM has been devised in order to improve the performance in a limited amount of mounted RAM. ing.

In an information processing apparatus having a plurality of memories of different speeds, a mechanism for converting a range of a certain virtual address in a logical address space of a CPU into one of physical addresses of a plurality of memories is provided. Widely used. For example, the TLB (Tr
anslation Look-aside Buffer) or M
A method using an MU (Memory Management Unit) is generally used.

If the above-mentioned conversion method is used, when a program is operated at a virtual address, the program is stored in a ROM.
It is not necessary to be aware of the difference between the data stored in the RAM and the data stored in the RAM. That is, whether to execute in ROM or R
It is possible to control whether the program is executed by AM without changing the program body.

For example, in Japanese Patent Application Laid-Open No. H11-129558, the free space of the RAM is determined in advance before the program starts processing, and all or a part of the ROM program is copied to a RAM not used as a work area. To run a program on a RAM.

[0007]

However, the method disclosed in Japanese Patent Application Laid-Open No. H11-129558 describes that the margin of the RAM is checked before the program is executed or before the job is started. Because the usage dynamically changes during the execution of the program, the RA
In the case of a method in which an area is reserved for M execution, RA
It is indispensable to add a margin to the estimation of the M usage amount, and it is difficult to use the limited mounted RAM to the limit.

Further, in the method disclosed in Japanese Patent Application Laid-Open No. H11-129558, since the area for executing the RAM is fixed during the execution of the program, R
Even if the AM area increases, there is a problem that the area cannot be used for executing the RAM.

Therefore, according to the present invention, the RA for RAM execution is
By dynamically securing and releasing M, the limited R
It is an object of the present invention to provide a control method of an information processing apparatus capable of allocating as much RAM as possible for execution of RAM within the range of the AM load and improving the processing capability of a program.

[0010]

In order to achieve the above object, the present invention provides a method for determining which part of a program is mainly executed while the program is executing processing in a virtual address space. It has means for measuring. With this measuring means, it is possible to specify a part of the program most frequently executed by the CPU within a certain period.

Further, by performing address conversion so that a portion most frequently executed by the CPU is executed on a higher-speed physical memory, it is more efficient than executing the entire program on the higher-speed physical memory. In addition, the performance of the program can be improved.

If the work area becomes insufficient during execution of the program, the least frequently executed part of the area mapped to the high-speed physical memory is executed on the lower-speed physical memory. In addition, by changing the mapping, it is possible to secure a work area for the program on a faster physical memory.

According to a first aspect of the present invention, a CPU and the CPU
A first memory storing a program executed in the first memory, a second memory capable of copying and holding a part of the contents of the first memory, and a physical address in the first memory area. Mapping means for converting either the physical address in the second memory area to the same virtual address in the logical address area of the CPU; And a detection unit for detecting which address of the program is being executed. The distribution of the address values detected by the detection unit during the execution of the program is totaled, and the virtual An area including an address is converted into a physical address of a faster one of the first memory and the second memory.

According to a second aspect of the present invention, in the first aspect, the program is an image processing program for converting input data into output data for generating an image.

According to a third aspect of the present invention, there is provided a printer having the second aspect and a printing mechanism capable of performing printing based on the output data.

[0016]

FIG. 1 is a schematic structural view for explaining an embodiment of a printer having an information processing apparatus according to the present invention. The printer 1 includes a printing mechanism 2 and a controller 3 therein. . The controller 3 converts print data input from the host computer into data that can be printed on paper by the printing mechanism 2. The controller 3 has an input interface 4 for receiving data from the host computer,
It comprises an output interface 5 for sending data to the printing mechanism 2, a CPU 6, a ROM 7 storing a program interpreted and executed by the CPU 6, a RAM 8 used as a work area of the program, and a timer 9. A communication circuit such as a bus for interconnecting the function modules in the controller 3 is omitted.

FIG. 2 is a diagram showing an example of a system for operating a program stored in the ROM 7 on the logical address space of the CPU 6, and utilizes an address translation mechanism (TLB) 150 built in the CPU 6. . The ROM 7 stores a program 20 for processing data input from the host computer and an exception program 30 for other exception processing. Program 20
Although it is stored from the physical address 100 of the ROM 7,
The logical address 300 via the address translator 150
To be executed by the CPU 6. Here, the TLB 150 is used for conversion from the logical address to the physical address. However, when the CPU 6 does not have the TLB 150, a similar configuration is possible by using an external address conversion circuit such as an MMU. is there.

FIG. 3 shows an example of a method for measuring the execution frequency of the program 20. The timer 9 is a circuit for interrupting the CPU 6 at regular intervals.
In the example shown in FIG. 3, the timer 9 is a circuit external to the CPU 6, but if the CPU 6 has a built-in timer function, it may be used. When an interrupt is received from the timer 9, the CPU 6 copies the contents of the program counter 40 storing the logical address of the currently executing program to the exception program counter 41. Next, the start address of the exception program 30 is loaded into the program counter 40, and the execution of the exception program 30 is started. The exception handling method itself by this interrupt is
It is very commonly used.

As shown in FIG. 3, the value of the exception program counter 41 of the CPU 6 can be checked in the exception program 30 to determine which part of the program 20 was being executed at the time of the interruption from the timer 9. You can know. The program 20 is divided into five fixed-length blocks (blocks 21 to 25). In the exception program 30, the exception program counter 41
Is checked in which block range, and the value 1 is added to the frequency information of the corresponding block. By performing this process a certain number of times over a certain period, it is possible to know which block in the program 30 has been executed the most by the CPU 6 and conversely which block has been executed the least by the CPU 6. Become.

Although it is convenient to make the size of each block of the program 20 a fixed length, the size may be different for each block depending on the processing content and importance of the block. Although the time interval of the timer 9 is not specified in the present embodiment, it is desirable that the time interval be sufficiently shorter than the execution period of the program 20. If the time interval of the timer 9 is too short, only the exception program 30 will be executed, and the execution of the original program 20 will not proceed. Conversely, if the time interval is too long, effective frequency information cannot be obtained. For example, a value such as a unit of 0.01 seconds can be considered. Further, the time interval does not necessarily have to be a fixed value, but may be variable.

FIG. 4 is a diagram showing an example of a method for correcting the conversion between the physical address and the logical address of the program 20 by using the frequency information of the program 20. If the entire program 20 is executed in the ROM 7 and the frequency information obtained by the present invention indicates that the block 24 is most frequently executed by the CPU 6, the ROM 7
Block 24 is copied to the RAM 8 to block 2
Create 4 '. Next, the logical address 340 of the CPU 6
TLB 150 can be reconfigured to translate to the physical address 240 of block 24 'of RAM 8.

Generally, the program execution speed on the RAM 8 is faster than the program execution speed on the ROM 7, so that the block 24 'can be executed faster than the block 24. In this way, by arranging and executing the block that is executed most frequently by the CPU 6 on a faster memory, the processing performance of the entire program 20 can be improved.

Conversely, during execution of the program 20, the RAM
If it is necessary to secure more work areas on the ROM 8, the block with the lowest execution frequency is selected from the blocks copied and executed on the RAM 8 at that time, and the block on the original ROM 7 is selected. To be converted to TL
By resetting B150, the area of the RAM 8 that can be used as a work area can be freely extended.

[0024]

As is apparent from the above description, in the information processing apparatus of the present invention, the translation between the physical memory and the virtual address is dynamically updated in accordance with the execution frequency during the execution of the program. The physical memory can be used optimally, and high-speed processing can be performed even when the amount of mounted high-speed physical memory is limited.

By applying the information processing apparatus of the present invention to a controller built in a printer, it is possible to optimally use a RAM mounted on the controller,
The processing performance of the controller is improved.

Further, in a printer incorporating a controller to which the present invention is applied, the balance between the processing performance and the amount of mounted RAM can be optimized. Therefore, if the processing performance is the same, the amount of mounted RAM can be further reduced. And the cost of the printer can be kept low.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating an embodiment of a printer having an information processing apparatus according to the present invention.

FIG. 2 is a diagram showing an example of a method of operating a program stored in a ROM on a logical address space of a CPU.

FIG. 3 is a diagram showing an example of a method for measuring the execution frequency of a program.

FIG. 4 is a diagram showing an example of a method for correcting conversion between a physical address and a logical address of a program using frequency information of the program.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Printer, 2 ... Printing mechanism, 3 ... Controller, 4 ...
Input interface, 5 ... Output interface, 6 ... C
PU, 7 ROM, 8 RAM, 9 timer, 20 program, 30 exception program, 40 program counter, 41 exception program counter, 100, 24
0: physical address, 150: address translation mechanism (TL
B), 300, 340... Logical addresses.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/10 501 G06F 12/10 501Z

Claims (3)

[Claims] 1. A CPU, a first memory storing a program executed by the CPU, a second memory capable of copying and holding a part of the contents of the first memory, Mapping means for converting either the physical address in the first memory area or the physical address in the second memory area to the same virtual address in the logical address area of the CPU; Detecting means for detecting which address in the logical address area the CPU is executing the program each time the CPU executes, and the distribution of the address values detected by the detecting means during program execution is totaled, Converting an area including a virtual address with a high execution frequency to a physical address of a faster one of the first memory and the second memory based on the totaling; Characteristic information processing device. 2. The information processing apparatus according to claim 1, wherein the program is an image processing program for converting input data into output data for generating an image. 3. A printer comprising: the information processing apparatus according to claim 2; and a printing mechanism capable of printing based on the output data.