WO2018193736A1 - Information processing device, information processing method, and information processing system - Google Patents

Information processing device, information processing method, and information processing system Download PDF

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Publication number
WO2018193736A1
WO2018193736A1 PCT/JP2018/008625 JP2018008625W WO2018193736A1 WO 2018193736 A1 WO2018193736 A1 WO 2018193736A1 JP 2018008625 W JP2018008625 W JP 2018008625W WO 2018193736 A1 WO2018193736 A1 WO 2018193736A1
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Prior art keywords
memory
memory access
information
access
application
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PCT/JP2018/008625
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French (fr)
Japanese (ja)
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貴史 三吉
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富士通株式会社
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory

Definitions

  • the present invention relates to an information processing apparatus, an information processing method, and an information processing system.
  • It has a CPU (Central Processing Unit) and an FPGA (Field Programmable Gate Array) that can change the configuration of a programmable logic circuit based on circuit information, and offloads part of the processing performed by the CPU to the FPGA.
  • CPU Central Processing Unit
  • FPGA Field Programmable Gate Array
  • the system memory is shared by the CPU and the FPGA, and data communication between the CPU and the FPGA is performed via the system memory.
  • the FPGA has a user circuit that performs application processing, and the area of the system memory that can be accessed by each user circuit is managed. When an attempt is made to access another area of the system memory due to a malfunction of the user circuit or malicious access (unauthorized access), the access is suppressed.
  • an object of the present invention is to provide an information processing apparatus capable of recording and analyzing a memory access pattern by a user circuit.
  • One aspect of the information processing apparatus is disposed between a processing circuit that executes a part of application processing and a memory, and extracts an access information in memory access from the processing circuit to the memory.
  • a registration unit for registering a pattern of memory access based on access information extracted by the first memory access from the processing circuit to the memory; and a second memory access from the processing circuit to the memory when the second memory access is detected.
  • a determination unit that determines whether or not a memory access pattern based on the access information extracted by the memory access matches a registered memory access pattern corresponding to the application that performs the second memory access.
  • an information processing apparatus capable of recording and analyzing a memory access pattern by a processing circuit that executes a part of application processing.
  • FIG. 1 is a diagram illustrating a configuration example of an information processing system according to an embodiment of the present invention.
  • FIG. 2 is a diagram illustrating a configuration example of the tracking unit in the present embodiment.
  • FIG. 3 is a diagram showing an example of the format of the memory access packet in the present embodiment.
  • FIG. 4 is a diagram for explaining a pattern table in the present embodiment.
  • FIG. 5 is a diagram illustrating an operation example of the information processing system in the present embodiment.
  • FIG. 6 is a diagram illustrating an operation example of the information processing system according to the present embodiment.
  • FIG. 7 is a diagram illustrating another configuration example of the information processing system according to the present embodiment.
  • FIG. 1 is a block diagram illustrating a configuration example of an information processing system according to an embodiment of the present invention.
  • the information processing system in this embodiment includes a CPU (Central Processing Unit) 10, a system memory 20, and an FPGA (Field Programmable Gate Array) 30.
  • CPU Central Processing Unit
  • FPGA Field Programmable Gate Array
  • the CPU 10 includes CPU cores 11A and 11B, a memory management unit (MMU) 12, and an IO memory management unit (IOMMU) 13.
  • the CPU 10 is an example of an arithmetic processing device.
  • the CPU cores 11A and 11B execute processing according to a program (application or the like) read from the system memory 20 or the like.
  • a program application or the like
  • FIG. 1 an example having two CPU cores 11 ⁇ / b> A and 11 ⁇ / b> B is shown, but the present invention is not limited to this, and the number of CPU cores 11 included in the CPU 10 is arbitrary.
  • the memory management unit (MMU) 12 controls access to the system memory 20 and performs, for example, conversion from a logical address to a physical address in the virtual memory space and data communication between the CPU 10 and the system memory 20.
  • the IO memory management unit (IOMMU) 13 manages the memory space for IO (for input / output devices). For example, conversion from a logical address in the virtual memory space to an address assigned to the IO device, or the CPU 10 and the FPGA 30. Data communication with is performed.
  • the system memory 20 is a memory that stores programs such as an operating system (OS) and applications, data, and the like.
  • the system memory 20 includes, for example, a kernel area 21 in which a kernel and the like are stored, and shared memory areas 22A and 22B that are shared and used by the CPU 10 and the FPGA 30.
  • the FPGA 30 is a reconfigurable device that can change the configuration of a programmable logic circuit based on circuit information.
  • the FPGA 30 includes a user circuit (user logic) 31 and a tracking 32.
  • the user circuit 31 is an example of a processing circuit. In the present embodiment, a part of the processing performed by the CPU 10 is offloaded to the user circuit 31 of the FPGA 30 for processing.
  • the user circuit A31A performs a part of the process of the application AppA executed by the CPU core 11A of the CPU 10, and the user circuit A31B performs a part of the process of the application AppB executed by the CPU core 11B of the CPU 10.
  • the application AppA communicates with the user circuit A31A via the shared memory area A22A
  • the application AppB communicates with the user circuit B31B via the shared memory area B22B.
  • the tracking unit 32 is arranged between the user circuit 31 of the FPGA 30 and the IO memory management unit (IOMMU) 13 of the CPU 10, and records and analyzes a memory access pattern by the user circuit 31.
  • the tracking unit 32 performs registration and abnormality detection of memory access from the user circuit 31 to the system memory 20.
  • the tracking unit 32 may be disposed between the user circuit 31 of the FPGA 30 and the IO memory management unit (IOMMU) 13 of the CPU 10 and may be disposed in the CPU 10 as well as in the FPGA 30. You may arrange
  • the tracking unit 32 registers the pattern of memory access from the user circuit 31 when operating in the registration mode, and detects abnormality of memory access from the user circuit 31 when operating in the detection mode. As described above, by separating the registration mode for registering the memory access pattern from the detection mode for detecting the memory access abnormality, pattern detection independent of the user circuit 31 and the application can be performed.
  • the tracking unit 32 learns the memory access pattern for each application (process ID) executed by the user circuit 31 and for each access type (read or write).
  • memory access patterns ⁇ 1> maximum and minimum addresses for memory access, ⁇ 2> memory access granularity (maximum burst length), and ⁇ 3> areas for sequential access are specified and registered.
  • the tracking unit 32 determines whether the registered memory access pattern corresponding to the process ID and the access type (read or write) in the current memory access matches the current memory access pattern. Determine. When it is determined that the registered memory access pattern does not match the current memory access pattern, the tracking unit 32 generates an interrupt to the CPU 10, for example. At this time, the memory access may be blocked, continuously operated, or controlled.
  • FIG. 2 is a block diagram illustrating a configuration example of the tracking unit 32 in the present embodiment.
  • the tracking unit 32 includes a header information extraction unit 201, a registration control unit 202, a detection control unit 203, an interrupt control unit 204, a table selection unit 205, and a pattern table 206.
  • the header information extraction unit 201 is an example of an information extraction unit, and extracts access information from a memory access packet transmitted from the user circuit 31.
  • An example of the format of the memory access packet is shown in FIG.
  • the memory access packet includes a process ID (301) corresponding to an application (process) that performs memory access, a virtual address (302) indicating an access destination, a command type (303), a data length (304), and data (305). Each has a field to store.
  • the command type (303) for memory access by the user circuit 31 includes a read request for a memory requesting data reading from the memory, a write request for a memory requesting data writing to the memory, and an access from the CPU (program IO). There is a PIO read response to the CPU responding to.
  • the header information extraction unit 201 extracts process information from the memory access packet from the user circuit 31, a virtual address as an address, a command type as an access type, and data length access information as an access size (burst length).
  • the header information extraction unit 201 outputs the access information extracted from the memory access packet to the registration control unit 202, the detection control unit 203, and the table selection unit 205.
  • the access information extracted from the memory access packet is always output by the header information extraction unit 201, and may be valid when the command type is a read request or a write request, and invalid otherwise.
  • the registration control unit 202 is an example of a registration unit.
  • the registration control unit 202 updates the pattern table corresponding to the process ID and access type extracted from the memory access packet from the user circuit 31 in the registration mode.
  • the registration control unit 202 registers the memory access pattern in the corresponding pattern table based on the access information extracted from the memory access packet from the user circuit 31.
  • the registration control unit 202 includes a maximum of M sequential access determiners, and determines whether or not the current memory access from the user circuit 31 is a sequential access to a continuous area.
  • M is the number of information that can be registered in the pattern table 206 as a sequential area.
  • the sequential access determination unit determines that the access is a sequential address with the same command (access type), and determines that it is a sequential access. Address and end address) and command. Then, the registration control unit 202 updates the pattern table 206 based on the held address section and command. The sequential access determiner returns a hit when the memory access from the user circuit 31 matches the address section registered in the pattern table 206.
  • the detection control unit 203 is an example of a detection unit.
  • the detection control unit 203 compares the access information extracted from the memory access packet from the user circuit 31 in the detection mode with the information in the pattern table 206 corresponding to the extracted process ID (application) and access type, It is determined whether or not the access patterns match.
  • the detection control unit 203 has ⁇ 1> memory access burst length registered in the pattern table 206 in addition to the range determined by the maximum address and the minimum address registered in the pattern table 206. If either of the conditions exceeds the maximum burst length or ⁇ 3> the sequential area registered in the pattern table 206 is accessed with a different command, it is determined that the memory access is abnormal, and the interrupt control unit 204 An interrupt notification request is issued. That is, when the current memory access pattern does not match the memory access pattern registered in the pattern table 206, the detection control unit 203 issues an interrupt notification request to the interrupt control unit 204.
  • the interrupt control unit 204 When the interrupt control unit 204 receives an interrupt notification request from the detection control unit 203, the interrupt control unit 204 outputs an interrupt to the CPU 10. In addition, information such as which condition is detected may be notified together with an interrupt to the CPU 10.
  • the table selection unit 205 selects and outputs the pattern table 206 corresponding to the process ID and access type extracted from the memory access packet from the user circuit 31 from among the plurality of pattern tables 206.
  • the pattern table 206 has information on the maximum address and minimum address of memory access, the maximum burst length, and the start address and end address of M sets of sequential areas.
  • the start address of the sequential area is 0xFFFFFFFF, it indicates that the information of the sequential area is invalid.
  • three pattern tables 206A, 206B, and 206C are shown, but the pattern table 206 is provided for each application (process ID) and each access type (read or write).
  • the tracking unit 32 is operated in the registration mode in advance, for example, when testing a product or a new application is introduced, and the tracking unit 32 accesses the system memory 20 from the user circuit 31 of the FPGA 30.
  • a pattern table 206 for each application (process ID) and each access type (read or write).
  • the operation is performed in the detection mode at the time of operation, and the tracking unit 32 determines whether or not the memory access pattern from the user circuit 31 matches the memory access pattern registered in the pattern table 206. Even if the area 31 is accessible, it is possible to detect a memory access having a pattern different from the normal one.
  • the problem of the user circuit 31 can be identified early by detecting an abnormal memory access pattern from the user circuit 31 that occurs under specific conditions during operation. This is possible for both a malicious circuit as shown in FIG. 5 and a circuit including a bug causing a malfunction as shown in FIG.
  • FIG. 5 is a diagram showing an operation example of the information processing system in the present embodiment. 5, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.
  • the user circuit A31A of the FPGA 30 includes a direct memory access (DMA) control unit 501.
  • the DMA control unit 501 performs memory access according to the page table 502.
  • the shared memory area A22A of the memory 20 is an area that can be accessed by the user circuit A31A.
  • an address indicating the area 503 is specified in the page table 502 of the DMA control unit 501 from the application AppA executed by the CPU core 11A (511). If the address specified in the page table 502 is an address indicating the area 503, the DMA control unit 501 executes memory access to the area 503 of the memory 20 (512).
  • the malicious circuit of the user circuit A31A modifies the rewritten page table 502 to an address indicating an area 504 in which confidential data is stored, which is different from the area 503 in the shared memory A22A.
  • the area 504 of the memory 20 is an area that is accessible to the user circuit A31A but is not assigned (not specified) to the user circuit A31A.
  • the DMA control unit 501 executes memory access to the area 504 of the memory 20 outside the designated address according to the page table 502 (513).
  • the tracking unit 32 refers to the pattern table and detects this access outside the address range registered as a memory access pattern (514). Then, the tracking unit 32 notifies the CPU core 11A (application AppA) of abnormal memory access detection (515). Thereby, it can be recognized that the user circuit A31A of the FPGA 30 has some trouble.
  • FIG. 6 is a diagram illustrating an operation example of the information processing system in the present embodiment.
  • the CPU core 11A executes the processes of the applications AppA and AppB by the virtual machine VM.
  • a part of the process of the application AppA is performed by the user circuit A31A of the FPGA 30, and a part of the process of the application AppB is performed by the user circuit B31B of the FPGA 30.
  • the shared memory area of the memory 20 used by the applications AppA and AppB is one.
  • the address indicating the area 601 is specified from the application AppA to the user circuit A31A (611), and normally the user circuit A31A. Executes memory access to the area 601 of the memory 20 (612).
  • the application AppB and the user circuit B31B use the area 602 to be the buffer B in the shared memory area A22A, the address indicating the area 602 from the application AppB is designated to the user circuit B31B (613), and it is normal.
  • the user circuit B31B performs memory access to the area 602 of the memory 20 (614).
  • the tracking unit 32 refers to the pattern table and performs memory access. This access outside the address range registered as a pattern is detected (617). Then, the tracking unit 32 notifies the CPU core 11A (application AppB) of abnormal memory access detection (615). Thereby, it can be recognized that the user circuit B31B of the FPGA 30 has some problem.
  • FIG. 7 is a block diagram showing another configuration example of the information processing system in the present embodiment.
  • components having the same functions as those shown in FIG. 7 are shown in FIG. 7 in FIG. 7, components having the same functions as those shown in FIG.
  • the 7 includes a memory 701 that operates faster than the system memory 20 in addition to the CPU 10, the system memory (main memory) 20, and the FPGA 30.
  • the application AppA executed by the CPU core 11A uses the user circuit A31A of the FPGA 30, and the application AppA and the user circuit A31A communicate via the shared memory area A22A of the system memory 20.
  • An area 702 of the shared memory area A22A is a memory area (Working Set) actually used by the user circuit A31A.
  • a program memory monitor for allocating (mapping) memory areas is operating.
  • the operating system normally executes the application AppA by the CPU core 11A, and a part of the processing is executed by the user circuit A31A of the FPGA 30.
  • the tracking unit 32 operates in the registration mode, and records a memory access pattern (address range) from the user circuit A31A to the system memory 20. Further, the memory monitor operating in the CPU core 11B acquires the address range of memory access from the user circuit A31A recorded by the tracking unit 32 to the system memory 20.
  • the memory monitor determines whether or not the memory access address range from the user circuit A31A is smaller than the free capacity of the high-speed memory 701. If it is determined that the memory access address range from the user circuit A31A is smaller than the free capacity of the high-speed memory 701, the memory monitor determines the memory access address range from the user circuit A31A to the IO memory management unit (IOMMU) 13. An instruction is given to assign (remapping) to the high-speed memory 701.
  • IOMMU IO memory management unit
  • the tracking unit 32 is operated in the detection mode, and the operating system (OS) re-executes the application AppA by the CPU core 11A.
  • the user circuit A31A of the FPGA 30 operates using the high-speed memory 701, and the application AppA can be executed at high speed.
  • the memory monitor cancels the setting of the allocation of the high-speed memory 702 to the user circuit A31A, and the address range of the memory access from the user circuit A31A May be set in the system memory 20 (shared memory area A22A) and re-executed.
  • the tracking unit 32 records the memory access pattern from the user circuit 31 and analyzes the memory usage of the user circuit 31, thereby reallocating the memory area to be used to the high-speed memory.
  • Memory placement for the application and user circuit 31 can be optimized. As a result, it is possible to speed up the memory access of the application and user circuit 31, and the processing can be speeded up.
  • a processing circuit that executes a part of processing of an application, and is arranged between the processing circuit formed by reconfiguring a programmable logic circuit based on circuit information and the memory, and from the processing circuit
  • An information extraction unit for extracting access information in memory access to the memory;
  • a registration unit for registering a memory access pattern based on the access information extracted by the information extraction unit in a first memory access from the processing circuit to the memory for each application;
  • a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access
  • An information processing apparatus comprising: a determination unit configured to determine whether or not a registered memory access pattern corresponding to the application performing the operation matches.
  • the memory access pattern includes information on a maximum address and a minimum address accessed by the first memory access.
  • the memory access pattern includes at least one of a memory access granularity in the first memory access and an area information in which sequential access is performed in the first memory access.
  • the registration unit registers a memory access pattern for each application and each access type of the memory. (Appendix 5) When the determination unit determines that the memory access pattern related to the second memory access does not match the registered memory access pattern, the interrupt output to the application that performs the second memory access is output. 5.
  • the information processing apparatus according to any one of appendices 1 to 4, further comprising an insertion control unit.
  • Appendix 6 Any one of Supplementary notes 1 to 5, wherein the information extraction unit extracts information on a process ID, an address, an access type, and a data length according to the application from a memory access packet from the processing circuit.
  • the information processing apparatus according to item.
  • a processing circuit that executes a part of processing of an application, and is arranged between the processing circuit formed by reconfiguring a programmable logic circuit based on circuit information and the memory, and from the processing circuit
  • An information extraction unit for extracting access information in memory access to the memory
  • a registration unit for registering a memory access pattern based on the access information extracted by the information extraction unit for each application;
  • the information processing apparatus according to claim 1, wherein the memory includes a plurality of memories having different access performances and controls allocation of the memory to the processing circuit based on the memory access pattern.
  • a processing circuit that executes a part of processing of an application, and an information extraction unit disposed between the processing circuit and the memory formed by reconfiguring a programmable logic circuit based on circuit information, Extracting access information in memory access from the processing circuit to the memory; For each application, register a memory access pattern based on the access information extracted by the information extraction unit in the first memory access from the processing circuit to the memory; When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access And determining whether or not the registered memory access pattern corresponding to the application to be executed matches.
  • Arithmetic processing device for processing application reconfigurable device capable of changing configuration of programmable logic circuit based on circuit information, and processing circuit formed in reconfigurable device and executing part of processing of application
  • an information processing system having a memory used by the application, An information extraction unit that is arranged between the processing circuit and the memory and extracts access information in memory access from the processing circuit to the memory; A registration unit for registering a memory access pattern based on the access information extracted by the information extraction unit in a first memory access from the processing circuit to the memory for each application; When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access
  • An information processing system comprising: a determination unit configured to determine whether or not a registered memory access pattern corresponding to the application performing the operation matches.

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Abstract

[Problem] To provide an information processing device capable of carrying out a recording or analysis of a pattern of memory access by a user circuit. [Solution] A tracking unit is positioned between a user circuit, which is inside an FPGA and executes a portion of an application process, and a system memory. A header information extraction unit of the tracking unit extracts access information regarding memory access from the user circuit to the system memory. For each application, a registration control unit of the tracking unit registers a memory access pattern on the basis of the extracted access information. If a memory access from the user circuit is detected, a detection control unit of the tracking unit assesses whether the memory access pattern drawn from the extracted access information matches the registered memory access pattern associated with the application. Due to the above, it is possible to carry out the recording or analysis of the pattern of memory access by the user circuit.

Description

情報処理装置、情報処理方法、及び情報処理システムInformation processing apparatus, information processing method, and information processing system
　本発明は、情報処理装置、情報処理方法、及び情報処理システムに関する。 The present invention relates to an information processing apparatus, an information processing method, and an information processing system.
　ＣＰＵ（Central Processing Unit）と、回路情報に基づいてプログラム可能な論理回路の構成を変更可能なＦＰＧＡ（Field Programmable Gate Array）とを有し、ＣＰＵが行う処理の一部をＦＰＧＡにオフロードして処理を高速化するシステムがある。このようなシステムにおいて、システムメモリは、ＣＰＵとＦＰＧＡが共有し、ＣＰＵとＦＰＧＡ間のデータ通信等がシステムメモリを介して行われる。 It has a CPU (Central Processing Unit) and an FPGA (Field Programmable Gate Array) that can change the configuration of a programmable logic circuit based on circuit information, and offloads part of the processing performed by the CPU to the FPGA. There are systems that speed up processing. In such a system, the system memory is shared by the CPU and the FPGA, and data communication between the CPU and the FPGA is performed via the system memory.
特開２００１－３２５１５０号公報JP 2001-325150 A 特開２００６－１１６９２号公報JP 2006-11692 A
　ＦＰＧＡは、アプリケーションの処理を行うユーザ回路を有し、各々のユーザ回路がアクセスできるシステムメモリの領域は管理されている。そして、ユーザ回路の誤動作や悪意あるアクセス（不正アクセス）で、システムメモリの他の領域へアクセスしようとした場合、そのアクセスは抑制される。 The FPGA has a user circuit that performs application processing, and the area of the system memory that can be accessed by each user circuit is managed. When an attempt is made to access another area of the system memory due to a malfunction of the user circuit or malicious access (unauthorized access), the access is suppressed.
　しかしながら、従来の方式では、ユーザ回路がアクセスできるシステムメモリの領域内であれば、ユーザ回路によるメモリアクセスのパタンが通常とは異なるパタンであったとしても、異常動作として検出することができなかった。１つの側面では、本発明の目的は、ユーザ回路によるメモリアクセスのパタンの記録や分析を行うことができる情報処理装置を提供することにある。 However, in the conventional method, if the memory access pattern by the user circuit is different from the normal pattern within the system memory area accessible by the user circuit, it cannot be detected as an abnormal operation. . In one aspect, an object of the present invention is to provide an information processing apparatus capable of recording and analyzing a memory access pattern by a user circuit.
　情報処理装置の一態様は、アプリケーションの処理の一部を実行する処理回路とメモリとの間に配置され、処理回路からメモリへのメモリアクセスにおけるアクセス情報を抽出する情報抽出部と、アプリケーション毎に、処理回路からメモリへの第１のメモリアクセスで抽出されるアクセス情報に基づいてメモリアクセスのパタンを登録する登録部と、処理回路からメモリへの第２のメモリアクセスを検出した場合、第２のメモリアクセスで抽出されるアクセス情報に基づくメモリアクセスのパタンと、第２のメモリアクセスを行うアプリケーションに対応する登録したメモリアクセスのパタンとが一致するか否かを判定する判定部とを有する。 One aspect of the information processing apparatus is disposed between a processing circuit that executes a part of application processing and a memory, and extracts an access information in memory access from the processing circuit to the memory. A registration unit for registering a pattern of memory access based on access information extracted by the first memory access from the processing circuit to the memory; and a second memory access from the processing circuit to the memory when the second memory access is detected. And a determination unit that determines whether or not a memory access pattern based on the access information extracted by the memory access matches a registered memory access pattern corresponding to the application that performs the second memory access.
　発明の一態様においては、アプリケーションの処理の一部を実行する処理回路によるメモリアクセスのパタンの記録や分析を行うことが可能な情報処理装置を提供することができる。 In one embodiment of the present invention, it is possible to provide an information processing apparatus capable of recording and analyzing a memory access pattern by a processing circuit that executes a part of application processing.
図１は、本発明の実施形態における情報処理システムの構成例を示す図である。FIG. 1 is a diagram illustrating a configuration example of an information processing system according to an embodiment of the present invention. 図２は、本実施形態におけるトラッキング部の構成例を示す図である。FIG. 2 is a diagram illustrating a configuration example of the tracking unit in the present embodiment. 図３は、本実施形態におけるメモリアクセスパケットのフォーマットの一例を示す図である。FIG. 3 is a diagram showing an example of the format of the memory access packet in the present embodiment. 図４は、本実施形態におけるパタンテーブルを説明する図である。FIG. 4 is a diagram for explaining a pattern table in the present embodiment. 図５は、本実施形態における情報処理システムの動作例を示す図である。FIG. 5 is a diagram illustrating an operation example of the information processing system in the present embodiment. 図６は、本実施形態における情報処理システムの動作例を示す図である。FIG. 6 is a diagram illustrating an operation example of the information processing system according to the present embodiment. 図７は、本実施形態における情報処理システムの他の構成例を示す図である。FIG. 7 is a diagram illustrating another configuration example of the information processing system according to the present embodiment.
　以下、本発明の実施形態を図面に基づいて説明する。
　図１は、本発明の一実施形態における情報処理システムの構成例を示すブロック図である。本実施形態における情報処理システムは、ＣＰＵ（Central Processing Unit）１０、システムメモリ２０、及びＦＰＧＡ（Field Programmable Gate Array）３０を有する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating a configuration example of an information processing system according to an embodiment of the present invention. The information processing system in this embodiment includes a CPU (Central Processing Unit) 10, a system memory 20, and an FPGA (Field Programmable Gate Array) 30.
　ＣＰＵ１０は、ＣＰＵコア１１Ａ、１１Ｂ、メモリ管理部（ＭＭＵ）１２、及びＩＯメモリ管理部（ＩＯＭＭＵ）１３を有する。ＣＰＵ１０は、演算処理装置の一例である。ＣＰＵコア１１Ａ、１１Ｂは、システムメモリ２０等から読み出したプログラム（アプリケーション等）に応じた処理を実行する。なお、図１に示した例では２つのＣＰＵコア１１Ａ、１１Ｂを有する例を示しているが、これに限定されるものではなく、ＣＰＵ１０が有するＣＰＵコア１１の数は任意である。 The CPU 10 includes CPU cores 11A and 11B, a memory management unit (MMU) 12, and an IO memory management unit (IOMMU) 13. The CPU 10 is an example of an arithmetic processing device. The CPU cores 11A and 11B execute processing according to a program (application or the like) read from the system memory 20 or the like. In the example shown in FIG. 1, an example having two CPU cores 11 </ b> A and 11 </ b> B is shown, but the present invention is not limited to this, and the number of CPU cores 11 included in the CPU 10 is arbitrary.
　メモリ管理部（ＭＭＵ）１２は、システムメモリ２０に対するアクセス等の制御を行い、例えば仮想メモリ空間の論理アドレスから物理アドレスへの変換やＣＰＵ１０とシステムメモリ２０との間のデータ通信を行う。ＩＯメモリ管理部（ＩＯＭＭＵ）１３は、ＩＯ用（入出力デバイス用）のメモリ空間を管理するものであり、例えば仮想メモリ空間の論理アドレスからＩＯデバイスに割り当てられたアドレスへの変換やＣＰＵ１０とＦＰＧＡ３０との間のデータ通信を行う。 The memory management unit (MMU) 12 controls access to the system memory 20 and performs, for example, conversion from a logical address to a physical address in the virtual memory space and data communication between the CPU 10 and the system memory 20. The IO memory management unit (IOMMU) 13 manages the memory space for IO (for input / output devices). For example, conversion from a logical address in the virtual memory space to an address assigned to the IO device, or the CPU 10 and the FPGA 30. Data communication with is performed.
　システムメモリ２０は、オペレーティングシステム（ＯＳ）やアプリケーション等のプログラムやデータ等を記憶するメモリである。システムメモリ２０には、例えばカーネル等が格納されるカーネル領域２１や、ＣＰＵ１０とＦＰＧＡ３０とが共有して使用する共有メモリ領域２２Ａ、２２Ｂ等が設けられる。 The system memory 20 is a memory that stores programs such as an operating system (OS) and applications, data, and the like. The system memory 20 includes, for example, a kernel area 21 in which a kernel and the like are stored, and shared memory areas 22A and 22B that are shared and used by the CPU 10 and the FPGA 30.
　ＦＰＧＡ３０は、回路情報に基づいてプログラム可能な論理回路の構成を変更可能な再構成デバイスである。ＦＰＧＡ３０は、ユーザ回路（ユーザロジック）３１及びトラッキング３２を有する。ユーザ回路３１は処理回路の一例である。本実施形態では、ＣＰＵ１０が行う処理の一部をＦＰＧＡ３０のユーザ回路３１にオフロードして処理を行う。 The FPGA 30 is a reconfigurable device that can change the configuration of a programmable logic circuit based on circuit information. The FPGA 30 includes a user circuit (user logic) 31 and a tracking 32. The user circuit 31 is an example of a processing circuit. In the present embodiment, a part of the processing performed by the CPU 10 is offloaded to the user circuit 31 of the FPGA 30 for processing.
　例えば、ＦＰＧＡ３０において、ユーザ回路Ａ３１Ａが、ＣＰＵ１０のＣＰＵコア１１Ａが実行するアプリケーションＡｐｐＡの処理の一部を行い、ユーザ回路Ａ３１Ｂが、ＣＰＵ１０のＣＰＵコア１１Ｂが実行するアプリケーションＡｐｐＢの処理の一部を行う。このとき、例えばアプリケーションＡｐｐＡでは、共有メモリ領域Ａ２２Ａを介してユーザ回路Ａ３１Ａと通信し、アプリケーションＡｐｐＢでは、共有メモリ領域Ｂ２２Ｂを介してユーザ回路Ｂ３１Ｂと通信する。 For example, in the FPGA 30, the user circuit A31A performs a part of the process of the application AppA executed by the CPU core 11A of the CPU 10, and the user circuit A31B performs a part of the process of the application AppB executed by the CPU core 11B of the CPU 10. . At this time, for example, the application AppA communicates with the user circuit A31A via the shared memory area A22A, and the application AppB communicates with the user circuit B31B via the shared memory area B22B.
　トラッキング部３２は、ＦＰＧＡ３０のユーザ回路３１とＣＰＵ１０のＩＯメモリ管理部（ＩＯＭＭＵ）１３との間に配置され、ユーザ回路３１によるメモリアクセスのパタンの記録及び分析を行う。トラッキング部３２は、ユーザ回路３１からシステムメモリ２０へのメモリアクセスの登録及び異常検出を行う。なお、トラッキング部３２は、ＦＰＧＡ３０のユーザ回路３１とＣＰＵ１０のＩＯメモリ管理部（ＩＯＭＭＵ）１３との間に配置されていればよく、ＦＰＧＡ３０内に限らず、ＣＰＵ１０内に配置してもよいし、ＣＰＵ１０及びＦＰＧＡ３０とは別の個別デバイス（ＩＣ）として配置してもよい。 The tracking unit 32 is arranged between the user circuit 31 of the FPGA 30 and the IO memory management unit (IOMMU) 13 of the CPU 10, and records and analyzes a memory access pattern by the user circuit 31. The tracking unit 32 performs registration and abnormality detection of memory access from the user circuit 31 to the system memory 20. The tracking unit 32 may be disposed between the user circuit 31 of the FPGA 30 and the IO memory management unit (IOMMU) 13 of the CPU 10 and may be disposed in the CPU 10 as well as in the FPGA 30. You may arrange | position as a separate device (IC) different from CPU10 and FPGA30.
　トラッキング部３２は、登録モードで動作しているとき、ユーザ回路３１からのメモリアクセスのパタンの登録を行い、検出モードで動作しているとき、ユーザ回路３１からのメモリアクセスの異常検出を行う。このように、メモリアクセスのパタンの登録を行う登録モードと、メモリアクセスの異常検出を行う検出モードとを分離することで、ユーザ回路３１及びアプリケーションに依存しないパタン検出が可能となる。 The tracking unit 32 registers the pattern of memory access from the user circuit 31 when operating in the registration mode, and detects abnormality of memory access from the user circuit 31 when operating in the detection mode. As described above, by separating the registration mode for registering the memory access pattern from the detection mode for detecting the memory access abnormality, pattern detection independent of the user circuit 31 and the application can be performed.
　トラッキング部３２は、登録モードでは、ユーザ回路３１が実行しているアプリケーション（プロセスＩＤ）毎及びアクセス種別（リード又はライト）毎にメモリアクセスのパタンの学習を行う。メモリアクセスのパタンとしては、＜１＞メモリアクセスの最大アドレス及び最小アドレス、＜２＞メモリアクセス粒度（最大バースト長）、及び＜３＞シーケンシャルアクセスを行う領域を特定して登録する。 In the registration mode, the tracking unit 32 learns the memory access pattern for each application (process ID) executed by the user circuit 31 and for each access type (read or write). As memory access patterns, <1> maximum and minimum addresses for memory access, <2> memory access granularity (maximum burst length), and <3> areas for sequential access are specified and registered.
　また、トラッキング部３２は、検出モードでは、現在のメモリアクセスにおけるプロセスＩＤ及びアクセス種別（リード又はライト）に対応する登録済みのメモリアクセスのパタンと現在のメモリアクセスのパタンとが一致するか否かを判定する。登録済みのメモリアクセスのパタンと現在のメモリアクセスのパタンとが一致しないと判定した場合、トラッキング部３２は、例えばＣＰＵ１０に対して割り込みを発生させる。このとき、そのメモリアクセスをブロックするか、継続動作させるか、制御するようにしてもよい。 In the detection mode, the tracking unit 32 determines whether the registered memory access pattern corresponding to the process ID and the access type (read or write) in the current memory access matches the current memory access pattern. Determine. When it is determined that the registered memory access pattern does not match the current memory access pattern, the tracking unit 32 generates an interrupt to the CPU 10, for example. At this time, the memory access may be blocked, continuously operated, or controlled.
　図２は、本実施形態におけるトラッキング部３２の構成例を示すブロック図である。トラッキング部３２は、ヘッダ情報抽出部２０１、登録制御部２０２、検出制御部２０３、割込制御部２０４、テーブル選択部２０５、及びパタンテーブル２０６を有する。 FIG. 2 is a block diagram illustrating a configuration example of the tracking unit 32 in the present embodiment. The tracking unit 32 includes a header information extraction unit 201, a registration control unit 202, a detection control unit 203, an interrupt control unit 204, a table selection unit 205, and a pattern table 206.
　ヘッダ情報抽出部２０１は、情報抽出部の一例であり、ユーザ回路３１から送信されるメモリアクセスパケットからアクセス情報を抽出する。メモリアクセスパケットのフォーマットの一例を図３に示す。メモリアクセスパケットは、メモリアクセスを行うアプリケーション（プロセス）に応じたプロセスＩＤ（３０１）、アクセス先を示す仮想アドレス（３０２）、コマンドタイプ（３０３）、データ長（３０４）、及びデータ（３０５）をそれぞれ格納するフィールドを有する。ユーザ回路３１によるメモリアクセスのコマンドタイプ（３０３）には、メモリからのデータ読み出しを要求するメモリに対するリードリクエスト、メモリへのデータ書き込みを要求するメモリに対するライトリクエスト、及びＣＰＵからのアクセス（プログラムＩＯ）に応答するＣＰＵに対するＰＩＯリードレスポンス等がある。 The header information extraction unit 201 is an example of an information extraction unit, and extracts access information from a memory access packet transmitted from the user circuit 31. An example of the format of the memory access packet is shown in FIG. The memory access packet includes a process ID (301) corresponding to an application (process) that performs memory access, a virtual address (302) indicating an access destination, a command type (303), a data length (304), and data (305). Each has a field to store. The command type (303) for memory access by the user circuit 31 includes a read request for a memory requesting data reading from the memory, a write request for a memory requesting data writing to the memory, and an access from the CPU (program IO). There is a PIO read response to the CPU responding to.
　ヘッダ情報抽出部２０１は、ユーザ回路３１からのメモリアクセスパケットからプロセスＩＤ、アドレスとして仮想アドレス、アクセス種別としてコマンドタイプ、及びアクセスサイズ（バースト長）としてデータ長のアクセス情報を抽出する。ヘッダ情報抽出部２０１は、コマンドタイプがリードリクエスト又はライトリクエストである場合、メモリアクセスパケットから抽出したアクセス情報を、登録制御部２０２、検出制御部２０３、及びテーブル選択部２０５出力する。なお、メモリアクセスパケットから抽出したアクセス情報をヘッダ情報抽出部２０１が常に出力し、コマンドタイプがリードリクエスト又はライトリクエストである場合に有効とし、それ以外は無効とするようにしてもよい。 The header information extraction unit 201 extracts process information from the memory access packet from the user circuit 31, a virtual address as an address, a command type as an access type, and data length access information as an access size (burst length). When the command type is a read request or a write request, the header information extraction unit 201 outputs the access information extracted from the memory access packet to the registration control unit 202, the detection control unit 203, and the table selection unit 205. Note that the access information extracted from the memory access packet is always output by the header information extraction unit 201, and may be valid when the command type is a read request or a write request, and invalid otherwise.
　登録制御部２０２は、登録部の一例である。登録制御部２０２は、登録モード時にユーザ回路３１からのメモリアクセスパケットから抽出されたプロセスＩＤ及びアクセス種別に対応するパタンテーブルを更新する。登録制御部２０２は、ユーザ回路３１からのメモリアクセスパケットから抽出されたアクセス情報に基づいて、対応するパタンテーブルにメモリアクセスのパタンを登録する。登録制御部２０２は、最大Ｍ個のシーケンシャルアクセス判定器を有し、現在のユーザ回路３１からのメモリアクセスが連続する領域へのシーケンシャルアクセスであるか否かを判定する。ここで、Ｍはパタンテーブル２０６にシーケンシャル領域として情報を登録可能な数である。 The registration control unit 202 is an example of a registration unit. The registration control unit 202 updates the pattern table corresponding to the process ID and access type extracted from the memory access packet from the user circuit 31 in the registration mode. The registration control unit 202 registers the memory access pattern in the corresponding pattern table based on the access information extracted from the memory access packet from the user circuit 31. The registration control unit 202 includes a maximum of M sequential access determiners, and determines whether or not the current memory access from the user circuit 31 is a sequential access to a continuous area. Here, M is the number of information that can be registered in the pattern table 206 as a sequential area.
　シーケンシャルアクセス判定器は、ユーザ回路３１から発行されている一連のメモリアクセスにおいて、同じコマンド（アクセス種別）で連続アドレスへのアクセスが認められる場合、シーケンシャルアクセスであると判定し、そのアドレス区間（開始アドレス及び終了アドレス）とコマンドを保持する。そして、登録制御部２０２は、保持されたアドレス区間及びコマンドに基づいて、パタンテーブル２０６を更新する。シーケンシャルアクセス判定器は、ユーザ回路３１からのメモリアクセスが、パタンテーブル２０６に登録されているアドレス区間がマッチすればヒットを返す。 In the series of memory accesses issued from the user circuit 31, the sequential access determination unit determines that the access is a sequential address with the same command (access type), and determines that it is a sequential access. Address and end address) and command. Then, the registration control unit 202 updates the pattern table 206 based on the held address section and command. The sequential access determiner returns a hit when the memory access from the user circuit 31 matches the address section registered in the pattern table 206.
　検出制御部２０３は、検出部の一例である。検出制御部２０３は、検出モード時にユーザ回路３１からのメモリアクセスパケットから抽出されたアクセス情報と、抽出されたプロセスＩＤ（アプリケーション）及びアクセス種別に対応するパタンテーブル２０６の情報とを比較し、メモリアクセスのパタンが一致するか否かを判定する。検出制御部２０３は、＜１＞メモリアクセスのアドレスがパタンテーブル２０６に登録されている最大アドレス及び最小アドレスで定まる範囲の外、＜２＞メモリアクセスのバースト長がパタンテーブル２０６に登録されている最大バースト長を超える、又は＜３＞パタンテーブル２０６に登録されているシーケンシャル領域に異なるコマンドでアクセス、の何れかの条件を満たす場合、異常なメモリアクセスであると判断し、割込制御部２０４に割り込み通知要求を発行する。すなわち、検出制御部２０３は、現在のメモリアクセスのパタンが、パタンテーブル２０６に登録されているメモリアクセスのパタンと一致しないとき、割込制御部２０４に割り込み通知要求を上げる。 The detection control unit 203 is an example of a detection unit. The detection control unit 203 compares the access information extracted from the memory access packet from the user circuit 31 in the detection mode with the information in the pattern table 206 corresponding to the extracted process ID (application) and access type, It is determined whether or not the access patterns match. The detection control unit 203 has <1> memory access burst length registered in the pattern table 206 in addition to the range determined by the maximum address and the minimum address registered in the pattern table 206. If either of the conditions exceeds the maximum burst length or <3> the sequential area registered in the pattern table 206 is accessed with a different command, it is determined that the memory access is abnormal, and the interrupt control unit 204 An interrupt notification request is issued. That is, when the current memory access pattern does not match the memory access pattern registered in the pattern table 206, the detection control unit 203 issues an interrupt notification request to the interrupt control unit 204.
　割込制御部２０４は、検出制御部２０３からの割り込み通知要求を受けるとＣＰＵ１０への割り込みを出力する。なお、ＣＰＵ１０への割り込みとともに、どの条件で検出されたか等の情報を通知するようにしてもよい。テーブル選択部２０５は、複数のパタンテーブル２０６の内から、ユーザ回路３１からのメモリアクセスパケットから抽出されたプロセスＩＤ及びアクセス種別に対応するパタンテーブル２０６を選択して出力する。 When the interrupt control unit 204 receives an interrupt notification request from the detection control unit 203, the interrupt control unit 204 outputs an interrupt to the CPU 10. In addition, information such as which condition is detected may be notified together with an interrupt to the CPU 10. The table selection unit 205 selects and outputs the pattern table 206 corresponding to the process ID and access type extracted from the memory access packet from the user circuit 31 from among the plurality of pattern tables 206.
　パタンテーブル２０６は、図４に例示するように、メモリアクセスの最大アドレス及び最小アドレス、最大バースト長、及びＭ個の組のシーケンシャル領域の開始アドレス及び終了アドレスの情報を有する。ここで、例えばシーケンシャル領域の開始アドレスが０ｘＦＦＦＦＦＦＦＦである場合、そのシーケンシャル領域の情報は無効であることを示す。なお、図２に示した例では、３つのパタンテーブル２０６Ａ、２０６Ｂ、２０６Ｃを示しているが、パタンテーブル２０６は、アプリケーション（プロセスＩＤ）毎及びアクセス種別（リード又はライト）毎に設けられる。 As illustrated in FIG. 4, the pattern table 206 has information on the maximum address and minimum address of memory access, the maximum burst length, and the start address and end address of M sets of sequential areas. Here, for example, when the start address of the sequential area is 0xFFFFFFFF, it indicates that the information of the sequential area is invalid. In the example shown in FIG. 2, three pattern tables 206A, 206B, and 206C are shown, but the pattern table 206 is provided for each application (process ID) and each access type (read or write).
　以上のように本実施形態では、例えば製品や新しいアプリケーションの導入時の試験等を実施するときなど、予め登録モードで動作させ、トラッキング部３２がＦＰＧＡ３０のユーザ回路３１からシステムメモリ２０へのメモリアクセスのパタンをアプリケーション（プロセスＩＤ）毎及びアクセス種別（リード又はライト）毎にパタンテーブル２０６として記録する。そして、運用時には検出モードで動作させ、トラッキング部３２がユーザ回路３１からのメモリアクセスのパタンがパタンテーブル２０６に登録されているメモリアクセスのパタンと一致するか否かを判定することで、ユーザ回路３１がアクセス可能な領域であっても、通常とは異なるパタンのメモリアクセスを検出することが可能となる。 As described above, in the present embodiment, the tracking unit 32 is operated in the registration mode in advance, for example, when testing a product or a new application is introduced, and the tracking unit 32 accesses the system memory 20 from the user circuit 31 of the FPGA 30. Are recorded as a pattern table 206 for each application (process ID) and each access type (read or write). Then, the operation is performed in the detection mode at the time of operation, and the tracking unit 32 determines whether or not the memory access pattern from the user circuit 31 matches the memory access pattern registered in the pattern table 206. Even if the area 31 is accessible, it is possible to detect a memory access having a pattern different from the normal one.
　例えば、特定の条件下で発生するユーザ回路３１からの異常なメモリアクセスのパタンを動作中に検出することで、ユーザ回路３１の問題を早期に特定することができる。これは、図５に一例を示すような悪意ある回路及び図６に一例を示すような誤動作を引き起こすバグを含む回路のどちらについても可能である。 For example, the problem of the user circuit 31 can be identified early by detecting an abnormal memory access pattern from the user circuit 31 that occurs under specific conditions during operation. This is possible for both a malicious circuit as shown in FIG. 5 and a circuit including a bug causing a malfunction as shown in FIG.
　図５は、本実施形態における情報処理システムの動作例を示す図である。図５において、図１に示した構成要素と同一の機能を有する構成要素には同一の符号を付し、重複する説明は省略する。図５に示す例では、ＦＰＧＡ３０のユーザ回路Ａ３１Ａは、ダイレクトメモリアクセス（Direct Memory Access：ＤＭＡ）制御部５０１を有する。ＤＭＡ制御部５０１は、ページテーブル５０２に従ってメモリアクセスを実行する。ここで、メモリ２０の共有メモリ領域Ａ２２Ａは、ユーザ回路Ａ３１Ａがアクセスできる領域であるとする。 FIG. 5 is a diagram showing an operation example of the information processing system in the present embodiment. 5, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted. In the example illustrated in FIG. 5, the user circuit A31A of the FPGA 30 includes a direct memory access (DMA) control unit 501. The DMA control unit 501 performs memory access according to the page table 502. Here, it is assumed that the shared memory area A22A of the memory 20 is an area that can be accessed by the user circuit A31A.
　共有メモリ領域Ａ２２Ａ内のバッファＡとする領域５０３を利用する場合、まず、ＣＰＵコア１１Ａが実行するアプリケーションＡｐｐＡから領域５０３を示すアドレスがＤＭＡ制御部５０１のページテーブル５０２に指定される（５１１）。ページテーブル５０２に指定されたアドレスが領域５０３を示すアドレスであれば、ＤＭＡ制御部５０１はメモリ２０の領域５０３に対してメモリアクセスを実行する（５１２）。 When the area 503 to be used as the buffer A in the shared memory area A22A is used, first, an address indicating the area 503 is specified in the page table 502 of the DMA control unit 501 from the application AppA executed by the CPU core 11A (511). If the address specified in the page table 502 is an address indicating the area 503, the DMA control unit 501 executes memory access to the area 503 of the memory 20 (512).
　しかし、ユーザ回路Ａ３１Ａの悪意ある回路が、共有メモリＡ２２Ａ内の領域５０３とは異なる、機密データが格納されている領域５０４を示すアドレスに書き換えページテーブル５０２を改変したとする。メモリ２０の領域５０４は、ユーザ回路Ａ３１Ａがアクセスできる領域内ではあるが、ユーザ回路Ａ３１Ａには割り当てられていない（指定されていない）領域である。 However, it is assumed that the malicious circuit of the user circuit A31A modifies the rewritten page table 502 to an address indicating an area 504 in which confidential data is stored, which is different from the area 503 in the shared memory A22A. The area 504 of the memory 20 is an area that is accessible to the user circuit A31A but is not assigned (not specified) to the user circuit A31A.
　ページテーブル５０２が改変された場合、ＤＭＡ制御部５０１は、ページテーブル５０２に従って、指定されたアドレス外であるメモリ２０の領域５０４に対してメモリアクセスを実行する（５１３）。このとき、トラキング部３２は、パタンテーブルを参照して、メモリアクセスのパタンとして登録されているアドレス範囲外へのこのアクセスを検出する（５１４）。そして、トラキング部３２は、ＣＰＵコア１１Ａ（アプリケーションＡｐｐＡ）に異常なメモリアクセスの検出を通知する（５１５）。これにより、ＦＰＧＡ３０のユーザ回路Ａ３１Ａに何らかの不具合のあることが認識できる。 When the page table 502 is modified, the DMA control unit 501 executes memory access to the area 504 of the memory 20 outside the designated address according to the page table 502 (513). At this time, the tracking unit 32 refers to the pattern table and detects this access outside the address range registered as a memory access pattern (514). Then, the tracking unit 32 notifies the CPU core 11A (application AppA) of abnormal memory access detection (515). Thereby, it can be recognized that the user circuit A31A of the FPGA 30 has some trouble.
　図６は、本実施形態における情報処理システムの動作例を示す図である。図６において、図１に示した構成要素と同一の機能を有する構成要素には同一の符号を付し、重複する説明は省略する。図６に示す例では、ＣＰＵコア１１Ａが仮想マシンＶＭによりアプリケーションＡｐｐＡ、ＡｐｐＢの処理を実行する。また、アプリケーションＡｐｐＡの処理の一部をＦＰＧＡ３０のユーザ回路Ａ３１Ａが行い、アプリケーションＡｐｐＢの処理の一部をＦＰＧＡ３０のユーザ回路Ｂ３１Ｂが行うものとする。このように１つの仮想マシンＶＭでアプリケーションＡｐｐＡ、ＡｐｐＢを動作させる場合、アプリケーションＡｐｐＡ、ＡｐｐＢが使用するメモリ２０の共有メモリ領域は１つとなる。 FIG. 6 is a diagram illustrating an operation example of the information processing system in the present embodiment. In FIG. 6, components having the same functions as those shown in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted. In the example illustrated in FIG. 6, the CPU core 11A executes the processes of the applications AppA and AppB by the virtual machine VM. Also, a part of the process of the application AppA is performed by the user circuit A31A of the FPGA 30, and a part of the process of the application AppB is performed by the user circuit B31B of the FPGA 30. As described above, when the applications AppA and AppB are operated on one virtual machine VM, the shared memory area of the memory 20 used by the applications AppA and AppB is one.
　アプリケーションＡｐｐＡとユーザ回路Ａ３１Ａが共有メモリ領域Ａ２２Ａ内のバッファＡとする領域６０１を利用する場合、アプリケーションＡｐｐＡから領域６０１を示すアドレスがユーザ回路Ａ３１Ａに指定され（６１１）、通常であればユーザ回路Ａ３１Ａはメモリ２０の領域６０１に対してメモリアクセスを実行する（６１２）。同様に、アプリケーションＡｐｐＢとユーザ回路Ｂ３１Ｂが共有メモリ領域Ａ２２Ａ内のバッファＢとする領域６０２を利用する場合、アプリケーションＡｐｐＢから領域６０２を示すアドレスがユーザ回路Ｂ３１Ｂに指定され（６１３）、通常であればユーザ回路Ｂ３１Ｂはメモリ２０の領域６０２に対してメモリアクセスを実行する（６１４）。 When the application AppA and the user circuit A31A use the area 601 to be the buffer A in the shared memory area A22A, the address indicating the area 601 is specified from the application AppA to the user circuit A31A (611), and normally the user circuit A31A. Executes memory access to the area 601 of the memory 20 (612). Similarly, when the application AppB and the user circuit B31B use the area 602 to be the buffer B in the shared memory area A22A, the address indicating the area 602 from the application AppB is designated to the user circuit B31B (613), and it is normal. The user circuit B31B performs memory access to the area 602 of the memory 20 (614).
　例えば、ユーザ回路Ｂ３１Ｂがバグにより誤動作し、ユーザ回路Ｂ３１Ｂが誤ってバッファＡとする領域６０１に対してメモリアクセスを実行すると（６１６）、トラキング部３２は、パタンテーブルを参照して、メモリアクセスのパタンとして登録されているアドレス範囲外へのこのアクセスを検出する（６１７）。そして、トラキング部３２は、ＣＰＵコア１１Ａ（アプリケーションＡｐｐＢ）に異常なメモリアクセスの検出を通知する（６１５）。これにより、ＦＰＧＡ３０のユーザ回路Ｂ３１Ｂに何らかの不具合のあることが認識できる。 For example, when the user circuit B31B malfunctions due to a bug and the user circuit B31B erroneously executes memory access to the area 601 that is designated as the buffer A (616), the tracking unit 32 refers to the pattern table and performs memory access. This access outside the address range registered as a pattern is detected (617). Then, the tracking unit 32 notifies the CPU core 11A (application AppB) of abnormal memory access detection (615). Thereby, it can be recognized that the user circuit B31B of the FPGA 30 has some problem.
　また、トラッキング部３２が、ＦＰＧＡ３０のユーザ回路３１からのメモリアクセスのパタンを取得できることを利用して、メモリアクセスのパタンに応じてメモリの割り当てを制御し、アプリケーション及びユーザ回路３１に対するメモリ配置を最適化することが可能である。図７は、本実施形態における情報処理システムの他の構成例を示すブロック図である。図７において、図１に示した構成要素と同一の機能を有する構成要素には同一の符号を付し、重複する説明は省略する。 Further, by utilizing the fact that the tracking unit 32 can acquire the memory access pattern from the user circuit 31 of the FPGA 30, the memory allocation is controlled in accordance with the memory access pattern, and the memory allocation for the application and the user circuit 31 is optimized. It is possible to FIG. 7 is a block diagram showing another configuration example of the information processing system in the present embodiment. In FIG. 7, components having the same functions as those shown in FIG.
　図７に示す情報処理システムは、ＣＰＵ１０、システムメモリ（主記憶）２０、及びＦＰＧＡ３０に加え、システムメモリ２０より動作が高速なメモリ７０１を有する。ＣＰＵコア１１Ａが実行するアプリケーションＡｐｐＡは、ＦＰＧＡ３０のユーザ回路Ａ３１Ａを利用し、アプリケーションＡｐｐＡとユーザ回路Ａ３１Ａはシステムメモリ２０の共有メモリ領域Ａ２２Ａを介して通信する。共有メモリ領域Ａ２２Ａの領域７０２が、ユーザ回路Ａ３１Ａが実際に使用するメモリ領域（Ｗｏｒｋｉｎｇ　Ｓｅｔ）である。また、ＣＰＵコア１１Ｂでは、メモリ領域の割り当て（マッピング）を行うプログラム（メモリモニタ）が動作している。 7 includes a memory 701 that operates faster than the system memory 20 in addition to the CPU 10, the system memory (main memory) 20, and the FPGA 30. The application AppA executed by the CPU core 11A uses the user circuit A31A of the FPGA 30, and the application AppA and the user circuit A31A communicate via the shared memory area A22A of the system memory 20. An area 702 of the shared memory area A22A is a memory area (Working Set) actually used by the user circuit A31A. In the CPU core 11B, a program (memory monitor) for allocating (mapping) memory areas is operating.
　図７に示した情報処理システムでのメモリ領域の割り当ての制御手順について説明する。以下では、ＦＰＧＡ３０のユーザ回路Ａ３１Ａが使用するメモリ領域を、システムメモリ２０（共有メモリ領域Ａ２２Ａ）から高速メモリ７０１に割り当てを変更する場合を一例に説明する。 The control procedure for memory area allocation in the information processing system shown in FIG. 7 will be described. Hereinafter, a case where the allocation of the memory area used by the user circuit A31A of the FPGA 30 is changed from the system memory 20 (shared memory area A22A) to the high-speed memory 701 will be described as an example.
　ＣＰＵ１０において、オペレーティングシステム（ＯＳ）は、ＣＰＵコア１１ＡでアプリケーションＡｐｐＡを通常実行し、その処理の一部をＦＰＧＡ３０のユーザ回路Ａ３１Ａが実行する。このとき、トラッキング部３２が、登録モードで動作し、ユーザ回路Ａ３１Ａからシステムメモリ２０へのメモリアクセスのパタン（アドレス範囲）を記録する。また、ＣＰＵコア１１Ｂで動作するメモリモニタが、トラッキング部３２が記録したユーザ回路Ａ３１Ａからシステムメモリ２０へのメモリアクセスのアドレス範囲を取得する。 In the CPU 10, the operating system (OS) normally executes the application AppA by the CPU core 11A, and a part of the processing is executed by the user circuit A31A of the FPGA 30. At this time, the tracking unit 32 operates in the registration mode, and records a memory access pattern (address range) from the user circuit A31A to the system memory 20. Further, the memory monitor operating in the CPU core 11B acquires the address range of memory access from the user circuit A31A recorded by the tracking unit 32 to the system memory 20.
　メモリモニタは、ユーザ回路Ａ３１Ａからのメモリアクセスのアドレス範囲が、高速メモリ７０１の空き容量より小さいか否かを判定する。ユーザ回路Ａ３１Ａからのメモリアクセスのアドレス範囲が高速メモリ７０１の空き容量より小さいと判定した場合、メモリモニタは、ＩＯメモリ管理部（ＩＯＭＭＵ）１３に対し、ユーザ回路Ａ３１Ａからのメモリアクセスのアドレス範囲を高速メモリ７０１に割り当てる（マッピングし直す）ように指示する。 The memory monitor determines whether or not the memory access address range from the user circuit A31A is smaller than the free capacity of the high-speed memory 701. If it is determined that the memory access address range from the user circuit A31A is smaller than the free capacity of the high-speed memory 701, the memory monitor determines the memory access address range from the user circuit A31A to the IO memory management unit (IOMMU) 13. An instruction is given to assign (remapping) to the high-speed memory 701.
　その後、トラッキング部３２を検出モードで動作させ、オペレーティングシステム（ＯＳ）は、ＣＰＵコア１１ＡでアプリケーションＡｐｐＡを再実行する。これにより、ＦＰＧＡ３０のユーザ回路Ａ３１Ａは高速メモリ７０１を使用して動作し、アプリケーションＡｐｐＡが高速に実行できるようになる。ここで、例えばトラッキング部３２がユーザ回路Ａ３１Ａからの異常なメモリアクセスを検出した場合、メモリモニタがユーザ回路Ａ３１Ａに対する高速メモリ７０２の割り当ての設定を解除し、ユーザ回路Ａ３１Ａからのメモリアクセスのアドレス範囲をシステムメモリ２０（共有メモリ領域Ａ２２Ａ）に設定して再実行するようにしてもよい。 Thereafter, the tracking unit 32 is operated in the detection mode, and the operating system (OS) re-executes the application AppA by the CPU core 11A. As a result, the user circuit A31A of the FPGA 30 operates using the high-speed memory 701, and the application AppA can be executed at high speed. Here, for example, when the tracking unit 32 detects an abnormal memory access from the user circuit A31A, the memory monitor cancels the setting of the allocation of the high-speed memory 702 to the user circuit A31A, and the address range of the memory access from the user circuit A31A May be set in the system memory 20 (shared memory area A22A) and re-executed.
　以上のように、トラッキング部３２がユーザ回路３１からのメモリアクセスのパタンを記録して、ユーザ回路３１のメモリ使用量を解析することで、使用するメモリ領域を高速メモリに割り当て直すなどして、アプリケーション及びユーザ回路３１に対するメモリ配置を最適化することができる。これにより、アプリケーション及びユーザ回路３１のメモリアクセスを高速化することが可能となり、処理を高速化することができる。 As described above, the tracking unit 32 records the memory access pattern from the user circuit 31 and analyzes the memory usage of the user circuit 31, thereby reallocating the memory area to be used to the high-speed memory. Memory placement for the application and user circuit 31 can be optimized. As a result, it is possible to speed up the memory access of the application and user circuit 31, and the processing can be speeded up.
　なお、前記実施形態は、何れも本発明を実施するにあたっての具体化のほんの一例を示したものに過ぎず、これらによって本発明の技術的範囲が限定的に解釈されてはならないものである。すなわち、本発明はその技術思想、またはその主要な特徴から逸脱することなく、様々な形で実施することができる。
　前述した実施形態に関し、さらに以下の付記を開示する。 The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
The following additional notes are disclosed with respect to the above-described embodiment.
（付記１）
　アプリケーションの処理の一部を実行する処理回路であって、回路情報に基づいてプログラム可能な論理回路を再構成して形成される前記処理回路とメモリとの間に配置され、前記処理回路から前記メモリへのメモリアクセスにおけるアクセス情報を抽出する情報抽出部と、
　前記アプリケーション毎に、前記処理回路から前記メモリへの第１のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づいてメモリアクセスのパタンを登録する登録部と、
　前記処理回路から前記メモリへの第２のメモリアクセスを検出した場合、前記第２のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づくメモリアクセスのパタンと、前記第２のメモリアクセスを行う前記アプリケーションに対応する登録したメモリアクセスのパタンとが一致するか否かを判定する判定部とを有することを特徴とする情報処理装置。
（付記２）
　前記メモリアクセスのパタンは、前記第１のメモリアクセスでアクセスする最大アドレス及び最小アドレスの情報を有することを特徴とする付記１記載の情報処理装置。
（付記３）
　前記メモリアクセスのパタンは、前記第１のメモリアクセスにおけるメモリアクセス粒度及び前記第１のメモリアクセスにてシーケンシャルアクセスを行う領域の情報の少なくとも一方を有することを特徴とする付記２記載の情報処理装置。
（付記４）
　前記登録部は、前記アプリケーション毎及び前記メモリのアクセス種別毎にメモリアクセスのパタンを登録することを特徴とする付記１～３の何れか１項に記載の情報処理装置。
（付記５）
　前記判定部が、前記第２のメモリアクセスに係るメモリアクセスのパタンが、登録したメモリアクセスのパタンと一致しないと判定した場合、前記第２のメモリアクセスを行う前記アプリケーションへの割り込みを出力する割込制御部を有することを特徴とする付記１～４の何れか１項に記載の情報処理装置。
（付記６）
　前記情報抽出部は、前記処理回路からのメモリアクセスパケットから、前記アプリケーションに応じたプロセスＩＤ、アドレス、アクセス種別、及びデータ長の情報を抽出することを特徴とする付記１～５の何れか１項に記載の情報処理装置。
（付記７）
　アプリケーションの処理の一部を実行する処理回路であって、回路情報に基づいてプロ
グラム可能な論理回路を再構成して形成される前記処理回路とメモリとの間に配置され、前記処理回路から前記メモリへのメモリアクセスにおけるアクセス情報を抽出する情報抽出部と、
　前記アプリケーション毎に、前記情報抽出部が抽出する前記アクセス情報に基づいてメモリアクセスのパタンを登録する登録部とを有し、
　前記メモリは、アクセス性能が異なる複数のメモリを有し、前記メモリアクセスのパタンに基づいて前記処理回路に対する前記メモリの割り当てを制御することを特徴とする情報処理装置。
（付記８）
　アプリケーションの処理の一部を実行する処理回路であって、回路情報に基づいてプログラム可能な論理回路を再構成して形成される前記処理回路とメモリとの間に配置された情報抽出部が、前記処理回路から前記メモリへのメモリアクセスにおけるアクセス情報を抽出し、
　前記アプリケーション毎に、前記処理回路から前記メモリへの第１のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づいてメモリアクセスのパタンを登録し、
　前記処理回路から前記メモリへの第２のメモリアクセスを検出した場合、前記第２のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づくメモリアクセスのパタンと、前記第２のメモリアクセスを行う前記アプリケーションに対応する登録したメモリアクセスのパタンとが一致するか否かを判定することを特徴とする情報処理方法。
（付記９）
　アプリケーションの処理を行う演算処理装置と、回路情報に基づいてプログラム可能な論理回路の構成を変更可能な再構成デバイスと、前記再構成デバイスに形成され前記アプリケーションの処理の一部を実行する処理回路と前記アプリケーションとで使用されるメモリとを有する情報処理システムであって、
　前記処理回路と前記メモリとの間に配置され、前記処理回路から前記メモリへのメモリアクセスにおけるアクセス情報を抽出する情報抽出部と、
　前記アプリケーション毎に、前記処理回路から前記メモリへの第１のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づいてメモリアクセスのパタンを登録する登録部と、
　前記処理回路から前記メモリへの第２のメモリアクセスを検出した場合、前記第２のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づくメモリアクセスのパタンと、前記第２のメモリアクセスを行う前記アプリケーションに対応する登録したメモリアクセスのパタンとが一致するか否かを判定する判定部とを有することを特徴とする情報処理システム。 (Appendix 1)
A processing circuit that executes a part of processing of an application, and is arranged between the processing circuit formed by reconfiguring a programmable logic circuit based on circuit information and the memory, and from the processing circuit An information extraction unit for extracting access information in memory access to the memory;
A registration unit for registering a memory access pattern based on the access information extracted by the information extraction unit in a first memory access from the processing circuit to the memory for each application;
When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access An information processing apparatus comprising: a determination unit configured to determine whether or not a registered memory access pattern corresponding to the application performing the operation matches.
(Appendix 2)
2. The information processing apparatus according to claim 1, wherein the memory access pattern includes information on a maximum address and a minimum address accessed by the first memory access.
(Appendix 3)
The information processing apparatus according to claim 2, wherein the memory access pattern includes at least one of a memory access granularity in the first memory access and an area information in which sequential access is performed in the first memory access. .
(Appendix 4)
4. The information processing apparatus according to claim 1, wherein the registration unit registers a memory access pattern for each application and each access type of the memory.
(Appendix 5)
When the determination unit determines that the memory access pattern related to the second memory access does not match the registered memory access pattern, the interrupt output to the application that performs the second memory access is output. 5. The information processing apparatus according to any one of appendices 1 to 4, further comprising an insertion control unit.
(Appendix 6)
Any one of Supplementary notes 1 to 5, wherein the information extraction unit extracts information on a process ID, an address, an access type, and a data length according to the application from a memory access packet from the processing circuit. The information processing apparatus according to item.
(Appendix 7)
A processing circuit that executes a part of processing of an application, and is arranged between the processing circuit formed by reconfiguring a programmable logic circuit based on circuit information and the memory, and from the processing circuit An information extraction unit for extracting access information in memory access to the memory;
A registration unit for registering a memory access pattern based on the access information extracted by the information extraction unit for each application;
The information processing apparatus according to claim 1, wherein the memory includes a plurality of memories having different access performances and controls allocation of the memory to the processing circuit based on the memory access pattern.
(Appendix 8)
A processing circuit that executes a part of processing of an application, and an information extraction unit disposed between the processing circuit and the memory formed by reconfiguring a programmable logic circuit based on circuit information, Extracting access information in memory access from the processing circuit to the memory;
For each application, register a memory access pattern based on the access information extracted by the information extraction unit in the first memory access from the processing circuit to the memory;
When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access And determining whether or not the registered memory access pattern corresponding to the application to be executed matches.
(Appendix 9)
Arithmetic processing device for processing application, reconfigurable device capable of changing configuration of programmable logic circuit based on circuit information, and processing circuit formed in reconfigurable device and executing part of processing of application And an information processing system having a memory used by the application,
An information extraction unit that is arranged between the processing circuit and the memory and extracts access information in memory access from the processing circuit to the memory;
A registration unit for registering a memory access pattern based on the access information extracted by the information extraction unit in a first memory access from the processing circuit to the memory for each application;
When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access An information processing system comprising: a determination unit configured to determine whether or not a registered memory access pattern corresponding to the application performing the operation matches.
　１０　ＣＰＵ
　１１　ＣＰＵコア
　１２　メモリ管理部
　１３　ＩＯメモリ管理部
　２０　システムメモリ
　２１　カーネル領域
　２２　共有メモリ領域
　３０　ＦＰＧＡ
　３１　ユーザ回路
　３２　トラッキング部
　２０１　ヘッダ情報抽出部
　２０２　登録制御部
　２０３　検出制御部
　２０４　割込制御部
　２０５　テーブル選択部
　２０６　パタンテーブル 10 CPU
11 CPU core 12 Memory management unit 13 IO memory management unit 20 System memory 21 Kernel area 22 Shared memory area 30 FPGA
31 User Circuit 32 Tracking Unit 201 Header Information Extraction Unit 202 Registration Control Unit 203 Detection Control Unit 204 Interrupt Control Unit 205 Table Selection Unit 206 Pattern Table

Claims (9)

  1. 　アプリケーションの処理の一部を実行する処理回路であって、回路情報に基づいてプログラム可能な論理回路を再構成して形成される前記処理回路とメモリとの間に配置され、前記処理回路から前記メモリへのメモリアクセスにおけるアクセス情報を抽出する情報抽出部と、
    　前記アプリケーション毎に、前記処理回路から前記メモリへの第１のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づいてメモリアクセスのパタンを登録する登録部と、
    　前記処理回路から前記メモリへの第２のメモリアクセスを検出した場合、前記第２のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づくメモリアクセスのパタンと、前記第２のメモリアクセスを行う前記アプリケーションに対応する登録したメモリアクセスのパタンとが一致するか否かを判定する判定部とを有することを特徴とする情報処理装置。     A processing circuit that executes a part of processing of an application, and is arranged between the processing circuit formed by reconfiguring a programmable logic circuit based on circuit information and the memory, and from the processing circuit An information extraction unit for extracting access information in memory access to the memory;
    A registration unit for registering a memory access pattern based on the access information extracted by the information extraction unit in a first memory access from the processing circuit to the memory for each application;
    When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access An information processing apparatus comprising: a determination unit configured to determine whether or not a registered memory access pattern corresponding to the application performing the operation matches.
  2. 　前記メモリアクセスのパタンは、前記第１のメモリアクセスでアクセスする最大アドレス及び最小アドレスの情報を有することを特徴とする請求項１記載の情報処理装置。 The information processing apparatus according to claim 1, wherein the memory access pattern includes information on a maximum address and a minimum address accessed by the first memory access.
  3. 　前記メモリアクセスのパタンは、前記第１のメモリアクセスにおけるメモリアクセス粒度及び前記第１のメモリアクセスにてシーケンシャルアクセスを行う領域の情報の少なくとも一方を有することを特徴とする請求項２記載の情報処理装置。 3. The information processing according to claim 2, wherein the memory access pattern includes at least one of memory access granularity in the first memory access and information on an area to be sequentially accessed in the first memory access. apparatus.
  4. 　前記登録部は、前記アプリケーション毎及び前記メモリのアクセス種別毎にメモリアクセスのパタンを登録することを特徴とする請求項１～３の何れか１項に記載の情報処理装置。 4. The information processing apparatus according to claim 1, wherein the registration unit registers a memory access pattern for each application and each access type of the memory.
  5. 　前記判定部が、前記第２のメモリアクセスに係るメモリアクセスのパタンが、登録したメモリアクセスのパタンと一致しないと判定した場合、前記第２のメモリアクセスを行う前記アプリケーションへの割り込みを出力する割込制御部を有することを特徴とする請求項１～４の何れか１項に記載の情報処理装置。 When the determination unit determines that the memory access pattern related to the second memory access does not match the registered memory access pattern, the interrupt output to the application that performs the second memory access is output. 5. The information processing apparatus according to claim 1, further comprising an insertion control unit.
  6. 　前記情報抽出部は、前記処理回路からのメモリアクセスパケットから、前記アプリケーションに応じたプロセスＩＤ、アドレス、アクセス種別、及びデータ長の情報を抽出することを特徴とする請求項１～５の何れか１項に記載の情報処理装置。 6. The information extraction unit according to claim 1, wherein the information extraction unit extracts information on a process ID, an address, an access type, and a data length corresponding to the application from a memory access packet from the processing circuit. The information processing apparatus according to item 1.
  7. 　アプリケーションの処理の一部を実行する処理回路であって、回路情報に基づいてプロ
    グラム可能な論理回路を再構成して形成される前記処理回路とメモリとの間に配置され、前記処理回路から前記メモリへのメモリアクセスにおけるアクセス情報を抽出する情報抽出部と、
    　前記アプリケーション毎に、前記情報抽出部が抽出する前記アクセス情報に基づいてメモリアクセスのパタンを登録する登録部とを有し、
    　前記メモリは、アクセス性能が異なる複数のメモリを有し、前記メモリアクセスのパタンに基づいて前記処理回路に対する前記メモリの割り当てを制御することを特徴とする情報処理装置。     A processing circuit that executes a part of processing of an application, and is arranged between the processing circuit formed by reconfiguring a programmable logic circuit based on circuit information and the memory, and from the processing circuit An information extraction unit for extracting access information in memory access to the memory;
    A registration unit for registering a memory access pattern based on the access information extracted by the information extraction unit for each application;
    The information processing apparatus according to claim 1, wherein the memory includes a plurality of memories having different access performances and controls allocation of the memory to the processing circuit based on the memory access pattern.
  8. 　アプリケーションの処理の一部を実行する処理回路であって、回路情報に基づいてプログラム可能な論理回路を再構成して形成される前記処理回路とメモリとの間に配置された情報抽出部が、前記処理回路から前記メモリへのメモリアクセスにおけるアクセス情報を抽出し、
    　前記アプリケーション毎に、前記処理回路から前記メモリへの第１のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づいてメモリアクセスのパタンを登録し、
    　前記処理回路から前記メモリへの第２のメモリアクセスを検出した場合、前記第２のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づくメモリアクセスのパタンと、前記第２のメモリアクセスを行う前記アプリケーションに対応する登録したメモリアクセスのパタンとが一致するか否かを判定することを特徴とする情報処理方法。     A processing circuit that executes a part of processing of an application, and an information extraction unit disposed between the processing circuit and the memory formed by reconfiguring a programmable logic circuit based on circuit information, Extracting access information in memory access from the processing circuit to the memory;
    For each application, register a memory access pattern based on the access information extracted by the information extraction unit in the first memory access from the processing circuit to the memory;
    When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access And determining whether or not the registered memory access pattern corresponding to the application to be executed matches.
  9. 　アプリケーションの処理を行う演算処理装置と、回路情報に基づいてプログラム可能な論理回路の構成を変更可能な再構成デバイスと、前記再構成デバイスに形成され前記アプリケーションの処理の一部を実行する処理回路と前記アプリケーションとで使用されるメモリとを有する情報処理システムであって、
    　前記処理回路と前記メモリとの間に配置され、前記処理回路から前記メモリへのメモリアクセスにおけるアクセス情報を抽出する情報抽出部と、
    　前記アプリケーション毎に、前記処理回路から前記メモリへの第１のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づいてメモリアクセスのパタンを登録する登録部と、
    　前記処理回路から前記メモリへの第２のメモリアクセスを検出した場合、前記第２のメモリアクセスにて前記情報抽出部が抽出する前記アクセス情報に基づくメモリアクセスのパタンと、前記第２のメモリアクセスを行う前記アプリケーションに対応する登録したメモリアクセスのパタンとが一致するか否かを判定する判定部とを有することを特徴とする情報処理システム。     Arithmetic processing device for processing application, reconfigurable device capable of changing configuration of programmable logic circuit based on circuit information, and processing circuit formed in reconfigurable device and executing part of processing of application And an information processing system having a memory used by the application,
    An information extraction unit that is arranged between the processing circuit and the memory and extracts access information in memory access from the processing circuit to the memory;
    A registration unit for registering a memory access pattern based on the access information extracted by the information extraction unit in a first memory access from the processing circuit to the memory for each application;
    When a second memory access from the processing circuit to the memory is detected, a memory access pattern based on the access information extracted by the information extraction unit in the second memory access, and the second memory access An information processing system comprising: a determination unit configured to determine whether or not a registered memory access pattern corresponding to the application performing the operation matches.
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