JP2018176638A - Image formation apparatus, printing system and integrated circuit for image transfer mounted on image formation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the proper handling even on a top page of a continuous printing operation, and reduce the load on the design for image handling in the design of control software of an image transfer unit to improve the design efficiency.SOLUTION: An image transfer unit includes: a Tag reception unit which receives Tag information one time per one page from an external controller; a Tag write DMA unit which outputs a set write process ID and accumulates the received Tag information in a memory region; and a Tag read DMA unit which outputs a set read process ID at the timing of receiving multi-value image data of each plate and reads the accumulated Tag information from the memory region to output the information. A memory access stop control unit stops a memory read operation by outputting a memory access stop request signal to the Tag read DMA unit when comparing the read process ID with the write process ID and determining that the page is the same during the operation of the Tag write DMA unit.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an image forming apparatus, a printing system, and an integrated circuit for image transfer mounted on the image forming apparatus.

  An image forming apparatus often transmits data from an external controller (for example, a higher-level device such as a digital front end (DFE)). On the printer engine (image forming apparatus) side, it is necessary to identify the data sent from the upper apparatus for each page.

  For example, Patent Document 1 proposes a technique for giving an identification number to data when a central processing unit on the engine side develops print data into a bit image. Here, a number (Tag information) for identifying the input interface is included in the assignment data, and the print engine reads the identification number and outputs a print completion message, thereby waiting for printing even if the input interface changes. Regardless of the state of the printer engine, reception and expansion processing of print data from a plurality of upper-level devices are performed without generation.

  In the image forming apparatus as described above, the engine side that prints small value data after data transfer unit (Data Transfer Unit: DTU) receives data and processes the image is used for printing each plate at the time of printing for convenience of mechanical layout. In most cases, the print timing of each color data is different. As an example, the Tag information is temporarily stored in the DTU-side memory, and the Tag information is read from the memory according to the transfer timing of the image data of each plane except for the drum top color, and various image processing is performed. In addition, it is assumed that four pages of memory are provided as the Tag's dedicated memory in order to absorb the delay between the drums.

  Reading of Tag information is started by a start instruction of write DMA (Direct Memory Access) for performing memory writing of data after image processing, and is executed following the progress of image processing. Also, the page memory for storing small value data after sending to the engine side is used to toggle for two pages, and transfer of print data to the engine side reads the data after this storage from the memory Is done.

  During continuous printing, reading of Tag information in the DTU of the above setting can be reliably performed after memory writing due to the distance between drums of each plate, that is, the difference in printing timing of each plate.

  However, for printing the first 2 pages or 2 pages or less of continuous printing, with the page memory for 2 pages described above, write DMA is executed regardless of the delay between drums, and image DMA is simply activated by software. If the instruction is given, the memory is read at the timing when the Tag is not written. As a result, there is a possibility that an abnormal image may be generated in print output on the first page in the case of continuous printing.

  In addition, even when the page memory of the image is not provided, the same occurs with a line memory for several lines provided inside an FPGA (Field-programmable gate array) device.

  In the DTU of the image forming apparatus, the start instruction to the write DMA, the start instruction of the DMA transfer of the print data to the engine side, and the like are implemented by software.

  Here, the timing to start reading the Tag, that is, the start instruction to start the image write DMA, needs to be surely performed after the Tag write, etc. It is necessary to properly execute according to the image data transfer timing of each version. The higher the speed of the main body, the more difficult the image handling tends to be.

  Therefore, in view of the above circumstances, the present invention enables appropriate handling even at the first page of continuous printing operation, and reduces the design burden on image handling in designing the control software of the image transfer unit, and the design efficiency It is an object of the present invention to provide an image forming apparatus capable of improving image quality.

In order to solve the above-mentioned subject, in one mode of the present invention,
An image forming apparatus connected to an external controller via an interface,
Receiving multi-level image data of a plurality of color plates, which are color components, and tag information identifying image types and attributes such as characters and photographs from the external controller, and performing image processing on the multi-level image data And an image forming engine including a writing unit that performs a printing operation on a recording medium based on data after image processing of each plate, and an image transfer unit that performs and reduces the value.
The image transfer unit is
Memory area,
A tag receiving unit that receives the tag information once per page from the external controller;
A tag write DMA unit that outputs the set write process ID and stores the received tag information in the memory area;
A tag read DMA unit that outputs the set read process ID at the timing of receiving multi-level image data of each version, and reads and outputs the stored Tag information from the memory area;
A memory access stop control unit that generates a memory access stop request signal according to the situation and outputs it to the Tag read DMA unit to instruct stop of the memory read operation in the Tag read DMA unit;
And d) an image processing unit that performs image processing by using the tag information read from the memory area to perform multi-valued image data of each of the received versions.
The memory access stop control unit determines whether the DMA transfer of the same page is performed by comparing the read process ID with the write process ID when the Tag write DMA unit is in operation, and it is the same page. The image forming apparatus is characterized in that the memory access stop request signal is output to the tag read DMA unit to stop the memory read operation.

  According to one aspect, in the image forming apparatus, proper handling is possible even in the first page of the continuous printing operation, and in designing the control software of the image transfer unit, the load on design regarding image handling is reduced, Efficiency can be improved.

FIG. 1 is a schematic block diagram of a configuration of a printing system including an image forming apparatus including an image transfer unit and a DFE. FIG. 2 is a detailed block diagram regarding control of the image forming apparatus shown in FIG. 1; FIG. 2 is a schematic view of a mechanical configuration of the image forming apparatus of FIG. 1; FIG. 2 is a block diagram of an FPGA of an image transfer unit according to an embodiment of the present invention. FIG. 5 is an internal configuration diagram of a Tag write DMAC included in the FPGA of FIG. 4; FIG. 5 is an internal configuration diagram of a Tag read DMAC included in the FPGA of FIG. 4; FIG. 5 is an internal configuration diagram of an example of a memory access stop control circuit included in the FPGA of FIG. 4; 8 is a timing chart for explaining image transfer at the time of one page printing using the memory access stop control circuit of FIG. 7; 6 is a timing chart illustrating image transfer in 4-page printing. FIG. 5 is an internal configuration diagram of another example of the memory access stop control circuit included in the FPGA of FIG. 4; 11 is a timing chart for explaining image transfer in the case of one page printing using the memory access stop control circuit of FIG. FIG. 5 is an internal configuration diagram of still another example of the memory access stop control circuit included in the FPGA of FIG. 4;

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following and the drawings, the same components are denoted by the same reference numerals, and duplicate descriptions may be omitted.

[Whole system]
FIG. 1 is a schematic block diagram of a configuration of a printing system 3 including an image forming apparatus 1 including an image transfer unit, and a DFE 2. The configuration of an image forming apparatus 1 with an image transfer unit 40, which is an embodiment of the present invention, will be described with reference to FIG.

  As shown in FIG. 1, the printing system 3 includes a digital front end (DFE: Digital Front End) 2 and an image forming apparatus (engine unit) 1.

  The image forming apparatus 1 includes, for example, a control unit 10, an operation unit 20, an image forming engine 30, and an image transfer unit 40. Specifically, the control unit 10 includes a controller 110, an image processing unit (IPU) 120, and a base control unit (BCU) 130. The image forming engine 30 includes a writing unit 300, a sensor 313, and the like.

  The DFE 2 is connected to the controller 110 of the image forming apparatus 1 via the GbE 91, and connected to the image transfer unit 40 of the image forming apparatus 1 via the high-speed serial I / F 92.

  The DFE 2 draws print data sent from the user. Then, DFE2 draws each plate of yellow (Y), magenta (M), cyan (C) and black (K) and special color (S) according to necessity at 1200 dpi / 8 bit, and high speed serial I / F 92 Transfer only the image data to the image transfer unit 40. The DFE 2 also sends a print command (print instruction) to the controller 110 via the GbE 91.

  The high-speed serial I / F 92 is an interface (I / F) for transferring image data from the DFE 2 to the image transfer unit 40 of the image forming apparatus 1. The transfer timing is generated by the image transfer unit 40.

  GbE (Giga Bit Ethernet: Gigabit Ethernet (registered trademark)) 91 is a transmission medium capable of communication at 1 GBps, and is used to send control commands (print instructions) from the DFE 2 to the controller 110 of the image forming apparatus 1 Be done. Here, a transmission medium for communicating (connecting) the DFE 2 and the image forming apparatus 1 according to the GbE standard is, for example, a STP (Shielded Twisted Pair) cable, a UTP (Unshielded Twisted Pair) cable, an optical fiber or the like.

  The DFE 2 further includes a communication interface such as a wired LAN or a wireless LAN for receiving the print information from the customer PC.

  In the image forming apparatus 1, the controller 110 of the control unit 10 receives print information and a command from the DFE 2, converts it into a command that can be interpreted by the BCU 130, sends the command to the BCU 130, and sends the image transfer information to the image transfer unit 40. Set to control the entire printing.

  The image transfer unit 40 is connected to the DFE 2 by the high-speed serial I / F 92, and transfers the image data drawn by the DFE 2 to the IPU 120 according to an instruction from the controller 110.

  The IPU 120 is a unit for image processing of copying, and only transfers image data at the time of printer operation.

  The BCU 130 controls the paper conveyance system of the image forming engine 30 and the like.

  A sensor 313 which is a part of the image forming engine 30 reads registration mark information for positioning, and reads out an image of the positioning registration mark in response to a request from the BCU 130.

  The image forming engine 30 in which the writing unit 300 is provided is a mechanical unit that is a mechanism for forming an image, and has a paper conveyance mechanism as described later with reference to FIGS. It has a function and is controlled by BCU130.

  The operation unit 20 is also connected to the controller 110 and has a UI (User Interface) function.

  As described above, in the present invention, the image transfer unit 40 is provided on the image forming apparatus 1 side in order to realize high-speed image transfer. In addition to the transfer path (GbE 91 / controller 110) between the controller 110 and DFE 2, this image transfer unit 40 prepares a transfer path (high-speed serial I / F 92 / image transfer unit 40 / IPU 120) for image data. Thus, high-speed image transfer can be realized. Therefore, even if the printing speed of the image forming engine 30 is increased, it is possible to avoid an error in which the image transfer speed in high-speed serial I / F or the transfer speed in GbE can not be in time.

  Further, in the present invention, since the transfer path for the image is provided on the image forming apparatus side, the image processing (screening, edge enhancement, γ correction) etc. is not performed on the image near the writing unit 300 instead of the DFE side. By arranging on the forming device 1 side, relatively real-time feedback becomes possible. Here, in consideration of the stability of the image quality, a dither processing circuit 416 (see FIG. 4) and an edge enhancement circuit 417 are provided in the image transfer unit 40 as an image processing unit.

Control block
FIG. 2 shows a detailed block diagram related to control of the image forming apparatus 1 shown in FIG. In FIG. 2, in the image forming apparatus 1, the controller 110, the IPU 120, the base control unit 130, the image transfer unit 40, the operation unit 20, and the sensor 313 which is a part of the image forming engine 30 are used as the control unit 10. Show. The configuration of the writing unit 300 will be described later with reference to FIG.

  As shown in FIG. 2, a PCIe 92 and a GbE 91 are provided as an interface for connecting the image forming apparatus 1 and the DFE 2 as an external controller. The PCIe 92 is a type of high-speed serial I / F 92 connecting parts to each other, and bi-directional communication is possible between the image transfer unit 40 and the DFE 2. Also, GbE 91 is a transmission medium of GbE standard, and is a dedicated interface for connecting DFE 2 and controller 110.

  The controller 110 illustrated in FIG. 2 includes a CPU 111, an LSI 112, an ASIC 113, an HDD 114, an NIC 115, a RAM 116, and a ROM 117. The controller 110 illustrated in FIG. 2 receives the print information and temporarily stores the print information in the RAM 116.

  Then, in response to the command from the DFE 2, the controller 110 transfers the print command (print instruction) to the BCU 130 through the PCIe 118, and sets the image acquisition information in the image transfer unit 40 through the PCIe 118, Control the entire printing.

  In the controller 110 of FIG. 2, a CPU (Central Processing Unit) 111 reads an initialization program from the ROM 117 and executes the program. In addition, the CPU 111 initializes the device mounted on the controller 110, initializes the PCIe 118 connected to the PCIe SW 43, initializes the PCIe unit 430 connected to the FPGA 41, and initializes the PCIe unit 128 of the ASICs 121 to 126 of the IPU 120. , Communication with the ASIC 127 can be controlled.

  An LSI (Large-Scale Integration) 112 is an integrated circuit used together with the CPU 111, and has peripheral interfaces such as PCIe and USB.

  ASIC (application specific integrated circuit) 113 is a dedicated ASIC for connection and transfer, and has an interface for PCIe 118 to connect to IPU 120, a DMAC (Direct Memory Access Controller) for transfer, etc. doing.

  The HDD (Hard Disk Drive) 114 stores programs, data, setting values, and the like. A NIC (Network Interface Card) 115 is a dedicated interface for connection to the DFE 2 connected to the LSI 112 by the PCIe 118.

  A random access memory (RAM) 116 is a memory used by the CPU 111 to operate, and is also used to temporarily store image data. A ROM (Read Only Memory) 117 stores an initialization program of the CPU 111 and a boot loader.

  The image transfer unit 40 illustrated in FIG. 2 includes an FPGA 41, RAMs (memory) 42A and 42B, a PCIe SW 43, a CPU 44, a ROM 45, a RAM 46, a high-speed serial interface (I / F) 47, and a BCU I / F 48.

  The image transfer unit 40 is connected to the controller 110 and the IPU 120 through the PCIe (118, 430, 47) via the PCIe SW 43. Also, the image transfer unit 40 is connected to the BCU 130 through the BCU I / F 48.

  The image transfer unit 40 receives the image data before image processing and the tag information from the DFE 2 through the high-speed serial I / F 92.

  The PCIe SW 43 is a PCIe (118, 430, 47) switch device, and is used to connect a plurality of PCIe devices. Also, the PCIe SW 43 is initialized by the controller 110.

  The CPU 44 executes the program of the ROM 45 to initialize the image transfer unit 40, and executes the content instructed by the command from the BCU 130. The CPU 44 sets a start address (process ID) for each page based on the image acquisition information set by the controller 110.

  The ROM 45 stores control programs and data of the data transfer unit 40. The RAM 46 is a work memory of the CPU 44.

  A field-programmable gate array (FPGA) 41 is a programmable gate array, which processes the image data received from the DFE 2 through the high-speed serial interface 92 to generate small-value image data, and generates it in the RAM 42B. accumulate. Then, in response to the transfer request of the IPU 120, the small value image data is transferred for each color plate. That is, the FPGA 41 is an integrated circuit for image transfer.

  Here, the role of the FPGA 41 is to receive, from an external controller (DFE 2), Tag information for identifying image types and attributes such as characters and photographs common to each version, to multi-level image data of each version and printing 1 page The image processing is performed, and the small value data is transmitted in response to a print request from the BCU 130 which controls the print timing in the image forming engine 30.

  The FPGA 41 of the image transfer unit 40 temporarily stores the tag information in the memories (RAMs 42A and 42B) in the image transfer unit 40, reads the tag information from the memory according to the transfer timing of each plate, and performs various image processing. ing.

  The RAMs 42A and 42B, which are memories, are memories for temporarily storing data of the FPGA 41, and store data for image processing used for image transfer. More specifically, the RAM 42A functions as a tag buffer memory 421, which is a memory for tags shown in FIG. 4, and absorbs inter-drum delay due to the difference in layout of the image forming engine 30, so that four pages of tag information can be stored. Memory. Furthermore, the RAM 42B functions as a small value image buffer memory 422, which is a memory for small value images shown in FIG. 4, and the small value image after image processing in the FPGA 41 is for front side printing and back side printing for each plate. Each of the two pages has a memory capable of storing four pages in total.

  The high-speed serial I / F 92 is a high-speed serial interface for transferring image data from the DFE 2. The transfer timing for transferring image data by the high-speed serial I / F 92 is instructed by the FPGA 41.

  The BCU I / F 48 is an interface for the BCU for exchanging data between the BCU 130 and the image transfer unit 40.

  An IPU (image processing unit) 120 is responsible for image transfer for each color plate, and is connected to the controller 110 at PCIes 118 and 47.

  Referring to FIG. 2, the IPU 120 includes a plurality of write control ASICs 121, 122, 123, 124, 125, a control ASIC 126, and an image processing ASIC 127.

  The ASIC 121 is a writing ASIC for Y (yellow) color, has a function of image correction (trapezoidal correction), and a correction parameter is set from the BCU 130.

  The ASIC 122 is a write ASIC for M (magenta) color, the ASIC 123 is a write ASIC for C (cyan) color, the ASIC 124 is a write ASIC for K (black) color, and these ASICs are similar to those for Y It has a function of (keystone correction) and is set from the BCU 130.

  The ASIC 125 is a special-color writing ASIC, and optionally, is a writing control ASIC additionally used when using the fifth color, and has a function of image correction (trapezoidal correction) as in the case of Y, and The parameters are set from the BCU 130.

  The ASIC 126 is an ASIC that controls the write control ASIC (121 to 125). The ASIC 127 is an image processing ASIC, performs image transfer from the controller 110, and is controlled by the BCU 130.

  The BCU 130 (base control unit) performs mechanical control such as paper conveyance and image transfer timing control. The BCU 130 shown in FIG. 2 includes a CPU 131, a RAM 132, and a ROM 133.

  The RAM 132 is a memory used by the CPU 131, and the ROM 133 stores programs / data of the CPU 131. The CPU 131 executes the program of the ROM 133 to initialize the IPU 120 and the BCU 130.

  The sensor 313 is an image sensor for reading out positioning marks. The image is read out by the BCU 130, and the mark coordinates are determined by the BCU 130.

  The operation unit 20 is a unit having a UI, and is connected to the controller 110. In FIG. 2, the operation unit 20 includes a CPU 21, a touch panel 22, an LCD 23, a key input unit 24, a ROM 25, a RAM 26, and an operation unit I / F 27.

  In the operation unit 20, the CPU 21 is a main control unit of the operation unit 20, starts from the program of the ROM 25 and waits for a command from the controller 110 when the entire operation unit 20 is initialized.

  The touch panel 22 detects an input from the user. An LCD (Liquid Crystal Display: Liquid Crystal Display) 23 functions as a display unit. A key input unit (KEY) 24 is a dedicated hard key that detects an input from the user.

  The ROM 25 is a memory for program / data storage of the operation unit 20. The RAM 26 is a work memory of the CPU 21 of the operation unit 20. The operation unit I / F 27 is an interface that connects the operation unit 20 and the controller 110.

[Image formation engine]
FIG. 3 shows a schematic view of a mechanical configuration of the image forming engine 30 of FIG. The mechanical configuration for performing image formation will be described with reference to FIG.

  The image forming engine 30 includes, as image forming units, photoreceptor units 301 to 304 of respective colors, a transfer belt 306, a registration unit 307, a transfer unit 308, a fixing unit 309, and a cooling unit 310.

  Further, the image forming engine 30 includes a sheet feed tray 311, a reversing unit 312, a sensor 313, a sensor 314, and the like as a conveyance unit.

  In FIG. 3, the Y color photosensitive unit 301 is a unit for forming an image in Y color, and the M color photosensitive unit 302 is a unit for forming an image in M color, and a C color photosensitive member The unit 303 is a unit for forming an image in C color, and the K photoconductor unit 304 is a unit for forming an image in K color.

  The transfer belt 306 is a belt for secondarily transferring the toner of the image for one page transferred from the photosensitive units 301 to 304 of the respective colors onto the sheet P. The registration unit 307 is a place where the sheet P is temporarily stopped for timing alignment. The transfer unit 308 is a unit that secondarily transfers a toner image from the transfer belt 306 to the sheet P.

  The fixing unit 309 is a unit that fixes the sheet P with the toner (to which the toner image is transferred) by heat and pressure. The cooling unit 310 is a unit that cools the sheet P warmed by fixing.

  In addition, as the transport unit, the sheet P is placed on the sheet feeding tray 311, and the sheet P is supplied as needed. The reversing unit 312 switches back the sheet P and reverses the front and back of the sheet P during duplex printing.

  A sensor (positioning sensor) 313 is a sensor for reading registration marks for positioning of the first surface and the second surface of the sheet P. A density sensor 314 is a sensor that reads the density of each color transferred to a roller (transfer roller), and is used for color matching and color registration.

  In the image forming engine 30 having such a mechanical configuration, at the time of printing, the sheet P is conveyed from the tray 311, and is stopped momentarily at the position for timing adjustment and the registration unit 307.

  In accordance with the timing, the IPU 120 transfers an image in order to draw a picture on the photoconductor of the Y photoconductor unit 301 with the leading color being Y. Subsequently, the image is transferred to the M color photosensitive unit 302, the image is transferred to the C color photosensitive unit 303, and the image is transferred to the K color photosensitive unit 304.

  These images are developed for each color using toners of respective colors and transferred to a transfer belt 306. At this time, the timing is adjusted so that the position of the image matches, and the image is primarily transferred onto the transfer belt 306 by the photosensitive unit 301, 302, 303, 304, and the image on the transfer belt 306 is transferred in the transfer unit 308. Secondary transfer to paper P.

  Thereafter, the sheet P is subjected to heat and pressure in the fixing unit 309 to fix the image and cooled in the cooling unit 310. In the case of single-sided printing, the sheet P is discharged as it is after cooling.

  In the case of double-sided printing, the sheet P is conveyed to the reversing unit 312, is switched back, and is conveyed with the second side facing up. Similarly, when printing on the second side by duplex printing, the paper P is stopped for a moment at the registration unit 307 and the image of each color is placed thereon. The image is transferred from the transfer belt 306 to the second side by the transfer unit 308 Is secondarily transferred, fixed, cooled, and discharged.

  In the image forming engine shown in FIG. 3, the case of one sheet feed tray has been described. However, the present invention is not limited to this, and a plurality of sheet feed trays may be provided. Although FIG. 3 describes the case where the image forming engine has four photosensitive members, the number of photosensitive members can be increased or decreased according to the color, and is not limited thereto.

[Image transfer unit]
Image transfer in the embodiment of the present invention will be described with reference to FIG. FIG. 4 shows the FPGA 41 in the image transfer unit 40, and the Tag buffer memory 421 and the small value image buffer memory 422 connected to the FPGA 41.

  The tag buffer memory 421 is realized by the RAM 42A of FIG. 2, and the small value image buffer memory 422 is realized by the RAM 42B.

  The FPGA 41 of the image transfer unit 40 includes a Tag reception circuit 411, plate reception circuits 412Y, 412M, 412C, and 412K for each color, Tag write DMAC 413, Tag read DMAC 414M, 414C, and 414K, parameter transmission unit 415, and dither processing circuits 416Y and 416M, 416C, 416K, edge enhance circuits 417Y, 417M, 417C, 417K, memory access stop control circuits 418M, 418C, 418K, and PCIe I / F circuit 419.

  The FPGA 41 further includes image light DMACs 491 Y, 491 M, 491 C and 491 K of the respective color plates, and image read DMACs 492 Y, 492 M, 492 C and 492 K of the respective color plates.

  The Tag receiving circuit 411 is a circuit for receiving Tag data (Tag information) as an image type from the DFE 2 which is an external controller.

  The multi-level image data receiving circuit (multi-level image data receiving unit) 412Y is a circuit that receives Y-level multi-level image data that is a yellow color component (color component) from DFE2. Similarly, reference numerals 412M, 412C, and 412K denote receiving circuits for receiving M-level, C-level, and K-level multi-valued image data, respectively.

  Here, the transfer color order of the image data sent from DFE 2 differs for each of a plurality of color components (Y version / M version / C version / K version), and in the case of the layout as shown in FIG. In accordance with this, the transfer order is as follows: Tag = Y version⇒M version⇒C version 版 K version. The order of the colors is an example, and the order of transfer is set in accordance with the order of the mechanical layout.

  The Tag write DMAC 413 and the Tag read DMACs 414 M, 414 C, and 414 K are connected to a CPU bus 440 connected to the CPU 44.

  The Tag write DMAC 413 is a DMA circuit (Tag write DMA unit, Tag information writing unit) that receives data from the Tag receiving circuit 411 and writes the data to the Tag buffer memory 421. The start address (process ID) for accessing the Tag buffer memory 421 is set in advance by the CPU 44 (see FIG. 2) of the image transfer unit 40.

  A tag buffer memory (Tag memory, memory area, first memory area, memory bus) 421 is a buffer memory for Tag, and stores image data in which Tag information is embedded.

  The tag read DMACs 414M, 414C, and 414K are DMA circuits (Tag read DMA unit, Tag information read unit) that are activated in accordance with the reception timing of the M version / C version / K version multilevel image. Specifically, the stored Tag information is read out at timing when the Tag read DMACs 414M, 414C, 414K receive multi-level image data of a plurality of color versions (M version / C version / K version), and an identifier (start address Extract and output.

  That is, using the Tag information and image data received from the Tag buffer memory 421 and the start address (process ID) received from the CPU 44, the Tag read DMACs 414M, 414C, and 414K determine whether each color data is desired data. It is determined whether or not to shift to image processing at different timings for each color.

  Three memory access stop control circuits (memory access stop control units) 418M, 418C and 418K are provided for the M / C / K version, and the Tag write DMAC 413 and Tag read DMACs 414M, 414C corresponding to the respective colors of the respective versions. Receive various signals from 414K. Then, the memory access stop control circuits 418M, 418C and 418K output memory access stop request signals to the tag read DMACs 414M, 414C and 414K.

  The dither processing circuit (Dither: value reduction circuit) 416Y is a circuit that reduces the value of the Y version of multi-level image data by image processing using a dither matrix of 64 pixels × 64 lines. Similarly, reference numerals 416M, 416C, and 416K denote circuits for performing image processing on M-level, C-level, and K-level multivalued image data, respectively.

  The parameter transmission unit 415 is a circuit that supplies parameters necessary for the dither processing to the dither processing circuits 416Y, 416M, 416C, and 416K as needed.

  The edge enhancement circuit 417Y is a circuit that performs edge correction of a character image. Similarly, 417M, 417C, and 417K are circuits for performing edge correction of M, C, and K version character images, respectively.

  The dither processing circuits 416Y to 416K, the parameter transmission unit 415, and the edge enhancement circuit 417 function as an image processing unit.

  The small value image buffer memory (memory for small value image data, second memory area) 422 is a buffer memory for small value image data after image processing, and two pages of page 2 for printing on the surface of each color plane And a total of four sides of two pages for printing on the back side. That is, the low-value image buffer memory 422 can store the image data after the low-value conversion by two pages of each plate for the front and back.

  The image write DMACs 491 Y, 491 M, 491 C and 491 K of the respective versions and the image read DMACs 492 Y, 492 M, 492 C and 492 K of the respective versions are connected to the CPU 44 via the CPU bus 440.

  The Y-version write DMAC (image write DMA unit) 491 Y is a DMA circuit that writes the image data after the reduction to the small value image buffer memory 422. The start address for accessing the small value image buffer memory 422 is set in advance by the CPU 44. The same applies to the other color plates in the image light DMACs 491M, 491C and 491K.

  The Y-plate read DMAC (image read DMA unit) 492Y is a DMA circuit that transfers K-plate data activated in response to a print request. The start address for accessing the small value image buffer memory 422 is set in advance by the CPU 44. The same applies to the other color plates in the image read DMAC 492M, 492C and 492K.

  As described above, in the present embodiment, the low-value data is temporarily stored in the low-value image buffer memory 422 of the image transfer unit 40 and read by the Y-version read DMAC (image read DMA unit) 492Y for use. Do.

<Tag write DMAC>
FIG. 5 shows the internal configuration of the Tag write DMAC 413 shown in FIG. 4, which will be described below.

  In the example shown in FIG. 5, the Tag write DMAC 413 includes a data input circuit 51, a bus I / F circuit 52, and a process ID / command / status setting unit 53. Inside the bus I / F circuit 52, a line counter 521 which is a write processing line number output unit is provided.

  In the tag write DMAC 413, in the process ID / command / status setting unit 53, a start address accessed from the CPU bus 44 and a process ID to be transferred (write process ID) are set in advance and activated. The write process ID is set in advance by software.

  After activation of the DMA, the bus I / F circuit 52 performs an operation of writing Tag data to the memory bus 421 which is a bus of the Tag buffer memory 421 as needed upon reception of Tag data from the DFE 2 to the data input circuit 51.

  In parallel with this operation, in the Tag write DMAC 413, the process ID / command / status setting unit 53 outputs a signal indicating the write process ID and the DMA activation state to the memory access stop control circuit 418. The bus I / F circuit 52 also outputs a line counter value which is a count value of the number of write processing lines indicating the progress of the transfer operation counted by the internal line counter 521.

<Tag read DMAC>
FIG. 6 shows the internal configuration of the Tag read DMAC 414M shown in FIG. 4, which will be described below. Although FIG. 6 is described using the Tag read DMAC 414M, 414C and 414K also have the same configuration.

  In the example shown in FIG. 6, the Tag read DMAC 414M includes a data output circuit 61, a bus I / F circuit 62, and a process ID / command / status setting unit 63. Inside the bus I / F circuit 62, a line counter 621 as a read processing line number output unit and a request stop circuit 622 are provided.

  In the tag read DMAC 414M, in the process ID / command / status setting unit 63, the start address accessed from the CPU bus and the process ID to be transferred are set in advance and activated. The read process ID is set in advance by software. However, with regard to activation, the tag write DMAC 413 is executed as hardware in conjunction with the page read state.

  After activating the DMA, the bus I / F circuit 52 performs an operation of reading Tag information, which is transfer data, from the memory bus 421. The data output circuit 61 transfers the read tag information and image data to the dither processing circuit 416 which is an image processing unit.

  Further, in the tag read DMAC 414 M, the process ID / command / status setting unit 63 outputs the process ID (read process ID) to the memory access stop control circuit 418. Also, the bus I / F circuit 62 outputs a line counter value which is a count value of the number of read processing lines indicating the progress of the transfer operation counted by the internal line counter 621.

  Further, the request stop circuit 622 of the bus I / F circuit 62 receives a stop request signal for stopping the memory read operation from the memory access stop control circuit 418, and accesses the memory while receiving the stop request signal. To stop the memory read operation.

<Configuration Example 1 of Memory Access Stop Control Circuit>
FIG. 7 shows an example of the internal configuration of the memory access stop control circuit 418 shown in FIG. 4, which will be described below. The memory access stop control circuit 418M is connected to the tag write DMAC 413 and the tag read DMAC 414M. The memory access stop control circuit 418C is connected to the tag write DMAC 413 and the tag read DMAC 414C. The memory access stop control circuit 418 K is connected to the Tag write DMAC 413 and the Tag read DMAC 414 K. In FIG. 7, the memory access stop control circuit 418 will be described without the sign at the end, but the memory access stop control circuits 418M, 418C and 418K have the same configuration except for the connection destination corresponding to the color. There is.

  In the example illustrated in FIG. 7, the memory access stop control circuit 418 includes a match determination unit 71 and an AND circuit 72.

  The coincidence determination unit 71 of the memory access stop control circuit 418 receives from the Tag write DMAC 413 a signal indicating a DMA activation state and a process ID (write process ID). Also, it receives a process ID (read process ID) from the tag read DMAC 414.

  In the memory access stop control circuit 418, the match determination unit 71 compares the process ID (read process ID) from the tag read DMAC 414 with the process ID (write process ID) of the tag write DMAC 413. And the AND circuit 72 is notified of the same data. The AND circuit 72 outputs a stop request to stop the read access of the Tag read DMACs 414M, 414C, and 414K under an AND condition as to whether the Tag write DMAC 413 is operating or not.

  As a result, after the Tag information of the same page is surely written to the Tag memory 421, the Tag information is read by the M / C / K version Tag read DMACs 414M, 414C, and 414K.

<Timing chart>
FIG. 8 is a timing chart for explaining image transfer at the time of one page printing using the memory access stop control circuits 418M, 418C, and 418K of FIG. A timing chart showing the write operation of the tag information and the write operation and the read operation of the image data of each plate is shown in FIG.

  FIG. 8 shows a case where one page is printed, and for the Y version, the received Tag information is used as it is because it is the leading color of the drum, and as indicated by a thick line, the Tag reception is triggered to the dither processing circuit 416Y. The image is transferred and image processing is performed.

  Further, in FIG. 8, the M / C / K version Tag Read DMACs 414M, 414C, and 414K wait for the end of the Tag write, and after performing the Tag Read and M / C / K version image processing after the end, The image write DMAC 491M, 491C, 491K performs a write operation to the small value image buffer memory 422 of small value data.

  The lower part of FIG. 8 shows how the image data stored in the low-value image buffer memory 422 of FIG. 4 is read and sent to the writing unit 300 (see FIG. 1) via the control unit 10. In the configuration shown in FIG. 3, the transfer order of the image data is Tag = Y version⇒M version⇒C version⇒K version for the convenience of the mechanical layout. When the mechanical layout shown in FIG. 3 is different, the order is appropriately changed in accordance with the layout.

  FIG. 9 shows a timing chart at which printing of four pages is performed. Since there is a small value image buffer memory 422 (see FIG. 4) for storing the image data after the small value conversion, the write operation of each plate is executed immediately after the write operation of the tag up to the first two pages. It is done.

  The third page after that is not executed immediately, but as shown by the dotted arrow, it waits until the printing operation starts, and the image processing is performed because the small value image buffer memory 422 has a space in the printing of the first page. Has been started. That is, as indicated by the dotted arrow, the write operation of the M-th page of the third page is executed at the timing of the end of reading of the small-value image of the first page of the M-type.

  In the portion enclosed by a frame in FIG. 9, the page of the write of Tag is the fourth page, and at the same timing, the image processing of the third page of the M version, that is, the read operation of the Tag of the third page is executed. Show that.

  At this time, the memory access stop control circuit 418 M compares the process IDs (read process ID and write process ID), and shows that the stop request is made inactive by the process ID being different.

  As described above, the read access of the Tag data is performed by the start instruction of the image write DMA in synchronization with the transfer timing of the image data. However, in hardware, each print page of the Tag write DMA 413 and the Tag read DMA 414M, 414C, 414K is used. Compare the process ID assigned to.

  As described above, by providing a mechanism for appropriately stopping the memory access when the process ID is the same, the write start instruction of the image write DMA 491 is performed independently of the execution status of the Tag write DMA 413. Is possible.

  As a result, in the design of control software for a DTU (data transfer unit), the load on the design aspect relating to image handling can be reduced, and design efficiency can be improved. As a result, DMA transfer is reliably performed on several pages immediately after the start of printing at the start of the printing operation, and an appropriate image similar to that during continuous printing is generated without generating an abnormal image. The formation can be performed.

<Configuration Example 2 of Memory Access Stop Control Circuit>
FIG. 10 is an internal configuration diagram of another example of the memory access stop control circuit included in the FPGA 41 of FIG. The configuration of the memory access stop control circuit 418α of this embodiment is applicable to the M / C / K version memory access stop control circuits 418M, 418C, and 418K. In the example of FIG. 10, the memory access stop control circuit 418α further includes a magnitude comparison unit 73 in addition to the configuration shown in FIG.

  In the example of FIG. 10, as the condition (stop condition) set by the memory access stop control circuit 418α, the line counter values of the Tag write DMAC 413 and the Tag read DMAC are used. The magnitude comparison unit 73 compares the write line counter value, which is the write count value, with the read line counter value, which is the read count value, and adds that the write side is smaller than the read side as a stop condition. There is. As a result, even when the tag write operation is being performed, reading of the tag is started, and printing preparation can be performed quickly.

  FIG. 11 shows a timing chart showing the situation. In this example, as shown in the upper part of FIG. 11, the read operation for receiving not only the Y version but all M, C, and K versions of multilevel image data is executed at the same timing as the Tag read. doing.

  With such settings, the memory read operation by accessing the Tag buffer memory 421 by the Tag read DMAs 414M, 414C, and 414K can be completed early, so that the preparation for the printing operation can be shortened. Therefore, in the present configuration, it is possible to speed up the printing operation as a whole without generating an abnormal image in the first few pages immediately after the start of the printing operation caused by the DMA transfer.

<Configuration Example 3 of Memory Access Stop Control Circuit>
FIG. 12 is an internal configuration diagram of still another example of the memory access stop control circuit included in the FPGA 41 of FIG. The configuration of the memory access stop control circuit 418β of this example is applicable to the M version / C version / K version memory access stop control circuits 418M, 418C, and 418K.

  FIG. 12 shows the configuration in the case where the process ID includes a number indicating that it is not in the DMA activated state and is assigned. In the memory access stop control circuit 418β shown in FIG. 12, only the process ID match determination unit 74 is provided.

  In this configuration, as an example, the process ID is represented by an 8-bit signal, and is represented by a value of 0 to 255. For example, assuming that 0 is assigned as a non-started state as a signal (predetermined value) indicating a process ID, it is possible to distinguish between an operating state and a stopped state by using 1 to 255 as an operating process ID. Set to a value.

  At this time, 0 is not used for the process ID used to read the Tag, so if the process ID of the Tag write DMAC 413 is 0, the match determination unit 74 of the memory access stop control circuit 418β will always disagree. A stop request will not occur. Thus, the circuit configuration of the memory access stop control circuit can be simplified.

  With such a setting, since the determination as to whether or not the DMA is activated is performed using the process ID, the configuration can be simplified, and an image forming apparatus excellent in cost performance can be provided.

  In any of the above embodiments, read access of Tag data is performed by the start instruction of the image write DMA in synchronization with the transfer timing of the image data. However, the print page of the Tag write DMA 413 and Tag read DMA is performed by hardware. By providing a mechanism to compare the process ID assigned to each time and to appropriately stop the memory access if they are identical, the start instruction of the image write DMA does not depend on the execution status of the Tag write DMA 413. Implementation is possible.

  In designing the control software of the image transfer unit (DTU), it is possible to reduce the design load on image handling, to improve the design efficiency, and to provide a high quality image forming apparatus.

  In the above, the case of an electrophotographic color printer has been described as the image forming apparatus. However, the present invention is not limited to this, and may be, for example, an optical plotter or a digital copying apparatus. Alternatively, the image forming apparatus may be applicable to an inkjet printer that sprays ink on a sheet to form an image.

  Further, in the above-described image forming apparatus, the image forming target has been described as a sheet, but the recording medium on which the image is formed is not limited to the sheet. For example, the recording medium means one to which the liquid can be attached at least temporarily, which adheres and adheres, or adheres and penetrates. Specific examples include recording media such as paper, recording paper, recording paper, film, cloth, electronic substrates, electronic components such as piezoelectric elements, and media such as powder layers (powder layers), organ models, and inspection cells. Yes, and all things to which liquid or powder adheres are included unless specifically limited. For example, the material of the above-mentioned "object" is paper, yarn, fiber, fabric, leather, metal, plastic, glass, wood, ceramics, etc., and it may be a material to which liquid can be attached temporarily.

  Although the preferred embodiments of the present invention have been described above in detail, the present invention is not limited to the specific embodiments, but within the scope of the subject matter of the embodiments of the present invention described in the claims. Various modifications and changes are possible.

1 Image forming apparatus 2 DFE (external controller, digital front end)
10 control unit 110 controller (control unit)
120 IPU (control unit)
130 BCU (control unit)
20 Operation Unit 30 Image Forming Engine 31 Writing Unit 313 Sensor 40 Image Transfer Unit (Data Transfer Unit, DTU)
41 FPGA (Integrated Circuit for Image Transfer)
42A, 42B RAM
44 CPU
411 Tag receiving circuit 412 (412Y, 412M, 412C, 412K) multi-level image data receiving circuit (multi-level data receiving unit)
412 Tag receiver (Tag receiver)
413 Tag write DMAC (Tag write DMA unit)
414 (414M, 414C, 414K) Tag read DMAC (Tag read DMA unit)
415 Parameter Transmission Unit (Image Processing Unit)
416 (416Y, 416M, 416C, 416K) Dither processing circuit (image processing unit)
417 (417Y, 417M, 417C, 417K) Edge enhancement circuit (image processing unit)
418, 418α, 418β (418Y, 418M, 418C, 418K) Memory access stop control circuit (memory access stop control unit)
419 PCIe I / F circuit 421 Tag buffer memory (memory, first memory area, memory area)
422 Low-value image buffer memory (low-value image data buffer memory, second memory area)
491K version write DMAC (image write DMA unit)
492 K version read DMAC (image read DMA unit)
51 data input circuit 52 bus I / F circuit 521 line counter (write processing line number output unit)
53 Process ID / Command / Status Setting Unit 61 Data Output Circuit 62 Bus I / F Circuit 621 Line Counter (Read Processing Line Number Output Unit)
622 Request stop circuit 63 Process ID / command / status setting unit 71 Match determination unit 72 AND circuit 73 Size comparison unit 74 Match determination unit P Sheet (recording medium)
Tag Tag information (tag)
PID process ID (process identifier, start address)

Patent 2828011 gazette

Claims (9)

An image forming apparatus connected to an external controller via an interface,
Receiving multi-level image data of a plurality of color plates, which are color components, and tag information identifying image types and attributes such as characters and photographs from the external controller, and performing image processing on the multi-level image data And an image forming engine including a writing unit that performs a printing operation on a recording medium based on data after image processing of each plate, and an image transfer unit that performs and reduces the value.
The image transfer unit is
Memory area,
A tag receiving unit that receives the tag information once per page from the external controller;
A tag write DMA unit that outputs the set write process ID and stores the received tag information in the memory area;
A tag read DMA unit that outputs the set read process ID at the timing of receiving multi-level image data of each version, and reads and outputs the stored Tag information from the memory area;
A memory access stop control unit that generates a memory access stop request signal according to the situation and outputs it to the Tag read DMA unit to instruct stop of the memory read operation in the Tag read DMA unit;
And d) an image processing unit that performs image processing by using the tag information read from the memory area to perform multi-valued image data of each of the received versions.
The memory access stop control unit determines whether the DMA transfer of the same page is performed by comparing the read process ID with the write process ID when the Tag write DMA unit is in operation, and it is the same page. An image forming apparatus, wherein the memory access stop request signal is output to the Tag read DMA unit, and the memory read operation is stopped. The Tag write DMA unit has a write processing line number output unit for outputting the number of write processing lines,
The Tag read DMA unit has a read processing line number output unit for outputting the number of read processing lines,
When the Tag write DMA unit is in operation, the memory access stop control unit determines that the DMA transfer of the same page is performed by comparing the read process ID with the write process ID, and the write process When the value of the number of lines is equal to or less than the value of the number of read processing lines, the memory access stop request signal is output to the Tag read DMA unit, and the memory read operation is stopped. The image forming apparatus according to claim 1. The image forming apparatus according to claim 1, wherein the write process ID is set to a predetermined value capable of identifying an operation state and a stop state of the tag write DMA unit. The image transfer unit is
A second memory area,
An image write DMA unit for storing image data reduced in value by the image processing unit in the second memory area;
And an image read DMA unit for reading out and outputting the image data of each plate after the reduction of the value from the second memory area,
The image forming apparatus according to any one of claims 1 to 3, wherein the second memory area stores image data after the reduction of the value for two pages. A digital front end that functions as the external controller that receives print data transmitted from a user, draws the print data, and creates multi-valued image data;
A printing system comprising: the image forming apparatus according to any one of claims 1 to 3 connected to the digital front end via an interface. An external controller receives, from an external controller, multi-level image data of each plate, which is a color component, and Tag information for identifying an image type such as a character or a photo, and performs image processing on the received data to reduce the image value. An integrated circuit for image transfer mounted on an image forming apparatus that transmits small value data in response to a print request from an engine.
Memory area,
A tag receiving unit that receives tag information from the external controller once per page;
A tag write DMA unit that outputs the set write process ID and stores the received tag information in the memory area;
A tag read DMA unit that outputs the set read process ID at the timing of receiving multi-level image data of each version, and reads and outputs the stored Tag information from the memory area;
A memory access stop control unit that generates a memory access stop request signal according to the situation and outputs it to the Tag read DMA unit to instruct stop of the memory read operation in the Tag read DMA unit;
And d) an image processing unit that performs image processing by using the tag information read from the memory area to perform multi-valued image data of each of the received versions.
The memory access stop control unit determines whether the DMA transfer of the same page is performed by comparing the read process ID with the write process ID when the Tag write DMA unit is in operation, and it is the same page. An integrated circuit comprising: outputting the memory access stop request signal to the tag read DMA unit to stop the memory read operation. The Tag write DMA unit has a write processing line number output unit for outputting the number of write processing lines,
The Tag read DMA unit has a read processing line number output unit for outputting the number of read processing lines,
When the Tag write DMA unit is in operation, the memory access stop control unit determines that the DMA transfer of the same page is performed by comparing the read process ID with the write process ID, and the write process When the value of the number of lines is equal to or less than the value of the number of read processing lines, the memory access stop request signal is output to the Tag read DMA unit, and the memory read operation is stopped. Integrated circuit as described in. The integrated circuit according to claim 6 or 7, wherein the write process ID is set to a predetermined value capable of identifying an operation state and a stop state of the tag write DMA unit. The integrated circuit according to any one of claims 6 to 8, wherein the integrated circuit is an FPGA.

Images