JP2018174252A - Power module and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power module capable of suppressing warpage of a substrate, and to provide a method of manufacturing the same.SOLUTION: A power module comprises: a substrate 61 that has anisotropy in its coefficient of thermal expansion; a semiconductor device 64 mounted on the substrate 61; and a resin 62 laminated on the substrate 61 so as to encapsulate the semiconductor device 64. When an arbitrary direction on the substrate surface is defined as an X-direction, and a direction orthogonal to the X-direction is defined as a Y-direction, the coefficient of thermal expansion of the substrate 61 in the Y-direction is smaller than that in the X-direction, and the coefficient of thermal expansion of the resin 62 in the Y-direction is smaller than that in the X-direction.SELECTED DRAWING: Figure 12

Description

  The present embodiment relates to a power module and a manufacturing method thereof.

  In recent years, there has been a demand for higher heat dissipation (lower thermal resistance) of power modules, and graphite substrates have attracted attention. Compared to the thermal conductivity of general copper (about 398 W / mK) and the thermal conductivity of aluminum (about 236 W / mK), graphite has a higher thermal conductivity of about 1500 W / mK (orientation plane direction). .

JP 2007-19130 A Japanese Patent Laid-Open No. 2005-210035

Satoshi Yamada, Yuki Kuno, Seito Sawaki, Yasunori Narita, Katsuhiro Takema, “Applicability of carbon-based anisotropic heat transfer materials to power semiconductor modules” Daido University Bulletin 50 (2014) pp. 133-pp. 135

  However, the thermal conductivity of graphite is about 5 W / mK in the normal direction perpendicular to the orientation in-plane direction, and the substrate is usually produced so that the orientation is vertical (XZ orientation) (described later). In this case, anisotropy occurs in the XY direction of the substrate. In particular, the CTE (Coefficient of Thermal Expansion) is about 25 ppm / K in the X direction and about -0.6 ppm / K in the Y direction, so the graphite substrate warps due to CTE mismatch in each direction. Resulting in. Repeating such warpage for each heat generation may reduce reliability due to disconnection of wiring in the power module or reduction in moisture resistance.

  The present embodiment provides a power module that can suppress the warpage of the graphite substrate used in the power module and improve the reliability, and a method for manufacturing the power module.

  According to one aspect of the present embodiment, an anisotropic substrate, a semiconductor device mounted on the substrate, and a resin stacked on the substrate are provided, and an arbitrary direction of the substrate surface is set. When the direction perpendicular to the X direction and the X direction is the Y direction, the substrate has a smaller coefficient of thermal expansion in the Y direction than the X direction, and the resin is in the Y direction compared to the X direction. A power module having a low coefficient of thermal expansion is provided.

  According to another aspect of the present embodiment, a step of forming a substrate having anisotropy, a step of mounting a semiconductor device on the substrate, and a step of laminating a resin on the substrate When the arbitrary direction of the substrate surface is the X direction and the direction orthogonal to the X direction is the Y direction, the substrate has a smaller thermal expansion coefficient in the Y direction than in the X direction. A method of manufacturing a power module is provided in which the resin is formed so that the thermal expansion coefficient is smaller in the Y direction than in the X direction.

  According to the present embodiment, it is possible to provide a power module capable of suppressing warpage and a manufacturing method thereof.

The typical bird's-eye view block diagram which shows the principal part of the power module which concerns on a comparative example. The typical bird's-eye view block diagram which shows the principal part of the power module which concerns on embodiment. The typical side surface block diagram which shows the anisotropy control method of the liquid crystal polymer with which the power module which concerns on embodiment is equipped. It is a typical bird's-eye view block diagram which shows the structural model of the simulation of the power module which concerns on embodiment, (a) decomposition | disassembly structure, (b) laminated structure. Explanatory drawing of the parameter used for the simulation of the power module which concerns on embodiment. FIG. 6 is a schematic bird's-eye view configuration diagram showing warpage of a structural model that occurs when simulation is performed under the conditions shown in FIGS. 4 and 5, (a) Low-CTE, (b) Middle-CTE, (c) High-CTE. (D) Asym-CTE. The graph which compares the curvature of four structural models shown by FIG. It is a typical bird's-eye view block diagram which shows the Mises stress concerning resin when simulating on the conditions shown in Drawing 4 and Drawing 5, and (a) Low-CTE, (b) Middle-CTE, (c) High-CTE, (D) Asym-CTE. The graph which compares the maximum value of the Mises stress concerning resin of four structural models shown by FIG. 6 is a schematic bird's-eye view showing the Mises stress applied to the graphite substrate when simulated under the conditions shown in FIG. 4 and FIG. 5, and (a) Low-CTE, (b) Middle-CTE, (c) High-CTE. (D) Asym-CTE. The graph which compares the maximum value of the Mises stress concerning the graphite substrate of four structural models shown by FIG. It is explanatory drawing of the power module which concerns on Example 1, (a) Typical side surface structure figure, (b) Typical plane structure figure. FIG. 6 is a schematic side view of a power module according to a second embodiment. The typical bird's-eye view block diagram of the laminated structure of the graphite sheet which comprises the graphite plate applicable to the power module which concerns on embodiment. It is an example of the graphite plate applicable to the power module which concerns on embodiment, Comprising: (a) Typical bird's-eye view block diagram which illustrates 1st graphite plate GP (XY), (b) 2nd graphite plate GP ( XZ) is a schematic bird's-eye view configuration diagram. It is a power module which concerns on embodiment, Comprising: (a) Typical circuit expression figure of SiC MOSFET of 1 in 1 (1 in 1) module, (b) Typical circuit expression figure of IGBT of 1 in 1 module. 1 is a detailed circuit representation of a 1 in 1 module SiC MOSFET, which is a power module according to an embodiment. It is a power module which concerns on embodiment, Comprising: (a) Typical circuit expression figure of SiC MOSFET of 2 in 1 (2 in 1) module, (b) Typical circuit expression figure of IGBT of 2 in 1 module. FIG. 4 is a schematic cross-sectional structure diagram of a SiC MOSFET including a source pad electrode SPD and a gate pad electrode GPD, which is an example of a semiconductor device applicable to the power module according to the embodiment. FIG. 4 is a schematic cross-sectional structure diagram of an IGBT including an emitter pad electrode EPD and a gate pad electrode GPD, which is an example of a semiconductor device applicable to the power module according to the embodiment. It is an example of the semiconductor device applicable to the power module which concerns on embodiment, Comprising: The typical cross-section figure of SiC DI (Double Implanted) MOSFET. It is an example of the semiconductor device applicable to the power module which concerns on embodiment, Comprising: The typical cross-section figure of SiC T (Trench) MOSFET. In the circuit configuration of the three-phase AC inverter configured using the power module according to the embodiment, (a) a circuit configuration example in which a SiC MOSFET is applied as a semiconductor device and a snubber capacitor is connected between the power supply terminal PL and the ground terminal NL (B) A circuit configuration example in which an IGBT is applied as a semiconductor device and a snubber capacitor is connected between a power supply terminal PL and a ground terminal NL. The circuit block diagram of the three-phase alternating current inverter which applied SiC MOSFET as a semiconductor device in the circuit structure of the three-phase alternating current inverter comprised using the power module which concerns on embodiment. The circuit block diagram of the three-phase alternating current inverter which applied IGBT as a semiconductor device in the circuit structure of the three-phase alternating current inverter comprised using the power module which concerns on embodiment. The power module which concerns on embodiment, Comprising: The typical bird's-eye view pattern block diagram of 2 in 1 module (module with a built-in half bridge) which applied SiC MOSFET as a semiconductor device. It is a power module which concerns on embodiment, Comprising: The typical bird's-eye view block diagram after resin molding of the half-bridge built-in module as a mold type module. It is a power module which concerns on embodiment, Comprising: The typical bird's-eye view pattern block diagram of a 6 in 1 (6 in 1) module. BRIEF DESCRIPTION OF THE DRAWINGS (a) Typical bird's-eye view pattern block diagram and (b) Typical plane pattern block diagram which show schematic structure of the power module which concerns on embodiment. BRIEF DESCRIPTION OF THE DRAWINGS (a) Typical bird's-eye view pattern block diagram and (b) Typical plane pattern block diagram which show schematic structure of the power module which concerns on embodiment.

  Next, the present embodiment will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness of each component and the planar dimensions is different from the actual one. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea, and do not specify the material, shape, structure, arrangement, etc. of each component. This embodiment can be modified in various ways within the scope of the claims.

[Comparative example]
First, a power module according to a comparative example will be described. The overall structure of the power module will be described later, and here, the description will be made focusing on the structure that causes the warp.

  The main part of the power module according to the comparative example is represented as shown in FIG. As shown in FIG. 1, the power module according to the comparative example employs a structure in which the surface of a graphite substrate 61 having anisotropy is sealed with an isotropic resin 62A. Generally, the sealing resin is transfer molded, and an epoxy resin having isotropic physical properties is used as the sealing resin. As already described, the CTE of the graphite substrate 61 is about 25 ppm / K in the X direction and about −0.6 ppm / K in the Y direction, so that the graphite substrate 61 is warped due to the CTE mismatch.

[Embodiment]
Hereinafter, the power module according to the embodiment will be described.

(Thermoplastic resin)
The main part of the power module according to the embodiment is represented as shown in FIG. As shown in FIG. 2, the power module according to the embodiment employs a structure that combines the CTE anisotropy of the thermoplastic resin 62 with the CTE anisotropy of the graphite substrate 61. Thereby, since CTE matching becomes possible, curvature can be suppressed.

  Specifically, the CTE of the graphite substrate 61 is about 25 ppm / K in the X direction and about −0.6 ppm / K in the Y direction. In this case, the CTE of the thermoplastic resin 62 is also about 25 ppm / K in the X direction and about −0.6 ppm / K in the Y direction. The thermoplastic resin (particularly the liquid crystal polymer) 62 has anisotropy according to the resin injection direction at the time of molding. This structure can be realized by controlling the molding conditions and the injection direction. In the following description, the same reference numeral 62 is used for the resin, the thermoplastic resin, and the liquid crystal polymer.

(Resin anisotropy control method)
The power module according to the embodiment is molded by injection molding, and a thermoplastic liquid crystal polymer 62 is used as a sealing resin. The liquid crystal polymer 62 has a small crystallization latent heat and is anisotropic in the flow direction. CTE is controlled by controlling the orientation of the liquid crystal polymer 62. Specifically, the CTE of the liquid crystal polymer 62 in the X direction and the Y direction is made to match the CTE of the graphite substrate 61 in the X direction and the Y direction.

  Matching CTEs does not mean that CTEs are completely matched. At least, if the graphite substrate 61 has a smaller thermal expansion coefficient in the Y direction than the X direction, the resin 62 only needs to have a smaller thermal expansion coefficient in the Y direction than the X direction.

  The anisotropy control method of the liquid crystal polymer 62 included in the power module according to the embodiment is expressed as shown in FIG. As shown in FIG. 3, since the liquid crystal is aligned in the flow direction 73 of the liquid crystal polymer 62, injection gates 71 and 72 of the liquid crystal polymer 62 are arranged in the low CTE direction. The CTE of the liquid crystal polymer 62 in the X direction and the Y direction is controlled by adjusting the injection speed at which the liquid crystal polymer 62 is injected from the injection gates 71 and 72, the gate positions of the injection gates 71 and 72, and the like. The injection directions 71A and 72A of the liquid crystal polymer 62 may be, for example, −45 degrees or more and +45 degrees or less with reference to the Y direction (flow direction 73).

  When such an anisotropic control method is employed, the gate marks 71B and 72B when the injection gates 71 and 72 are arranged in the low CTE direction are formed in the liquid crystal polymer 62. Thereby, it is possible to confirm that the injection gates 71 and 72 are arranged in the low CTE direction based on the gate marks 71B and 72B.

  In some cases, the alignment direction of the liquid crystal can be recognized by X-rays. In that case, it is also possible to confirm that the injection gates 71 and 72 are arranged in the low CTE direction based on the alignment direction of the liquid crystal recognized by the X-rays.

(Structural model of simulation)
The structural model of the power module simulation according to the embodiment is expressed as shown in FIG. As shown in FIG. 4, it is assumed that a 40 mm × 40 mm × 3 mm graphite substrate 61 is sealed with a resin 62 of 50 mm × 50 mm × 6 mm. FIG. 4 (b) represents the 1/4 model of FIG. 4 (a), showing that the surface and side surfaces of 61 are sealed with 62, and the lower right corner of the figure is the origin of displacement. The temperature condition is assumed to be heated from 40 ° C to 300 ° C.

  The parameters used for the simulation are expressed as shown in FIG. As shown in FIG. 5, the CTE of the graphite substrate GF is -0.6 ppm / K in the X direction, 25 ppm / K in the Y direction, and -0.6 ppm / K in the Z direction. The Young's modulus E of the graphite substrate GF is 50 GPa, and the Poisson's ratio ν of the graphite substrate GF is 0.3. On the other hand, as the resin 62, isotropic resin (Low-CTE), resin (Middle-CTE), resin (High-CTE), and anisotropic resin (Asym-CTE) are used. Hereinafter, resin (Low-CTE) is referred to as resin RA, resin (Middle-CTE) as resin RB, resin (High-CTE) as resin RC, and anisotropic resin (Asym-CTE) as resin RD.

  The CTE of the resin RA is -0.6 ppm / K, the CTE of the resin RB is 12 ppm / K, and the CTE of the resin RC is 25 ppm / K. The CTE of the resin RD is -0.6 ppm / K in the X direction, 25 ppm / K in the Y direction, and 12 ppm / K in the Z direction. The Young's modulus E of these four resins RA, RB, RC, and RD is all 10 GPa, and the Poisson's ratio ν is all 0.3.

(simulation result)
Next, simulation results will be described.

-Warping results-
The warpage of the structural model that occurs when simulation is performed under the conditions shown in FIGS. 4 and 5 is expressed as shown in FIGS. 6 and 7. FIG. 6A shows the warpage of the structural model 62a in which the graphite substrate GF is sealed with the resin RA. FIG. 6B shows the warpage of the structural model 62b in which the graphite substrate GF is sealed with the resin RB. FIG. 6C shows the warp of the structural model 62c in which the graphite substrate GF is sealed with the resin RC. FIG. 6D shows the warpage of the structural model 62d in which the graphite substrate GF is sealed with the resin RD. FIG. 7 compares the warpage of the four structural models 62a, 62b, 62c, and 62d shown in FIG.

  As shown in FIGS. 6A and 7, the structure model 62a sealed with the resin RA has a warped end of about +280 μm. Further, as shown in FIGS. 6B and 7, the end of the structural model 62b sealed with the resin RB is warped by about −130 μm to +130 μm. Further, as shown in FIGS. 6C and 7, the end of the structural model 62c sealed with the resin RC is warped by about −280 μm. Further, as shown in FIGS. 6D and 7, the structural model 62d sealed with the resin RD hardly warps.

  Thus, when isotropic resin RA, resin RB, and resin RC are used, even if CTE is changed, it is difficult to suppress warpage. On the other hand, when anisotropic resin RD is used, it is possible to suppress warpage.

―Stress results―
Next, the Mises stress applied to the resins RA, RB, RC, RD and the graphite substrate GF when simulated under the conditions shown in FIGS. 4 and 5 will be described. The Mises stress is one of the equivalent stresses used to show the stress state generated inside the object with a single value, as shown in the definition formula of [Equation 1]. In the definition formula, σ1 is the maximum principal stress, σ2 is the intermediate principal stress, and σ3 is the minimum principal stress.

The Mises stress σ _R applied to the resins RA, RB, RC, and RD when simulated under the conditions shown in FIGS. 4 and 5 is expressed as shown in FIGS. FIG. 8A shows the Mises stress σ _R applied to the resin RA of the structural model 62a. FIG. 8B shows Mises stress σ _R applied to the resin RB of the structural model 62b. FIG. 8C shows the Mises stress σ _R applied to the resin RC of the structural model 62c. FIG. 8D shows Mises stress σ _R applied to the resin RD of the structural model 62d. FIG. 9 compares the maximum value of the Mises stress σ _R applied to the resins RA, RB, RC, and RD of the four structural models 62a, 62b, 62c, and 62d shown in FIG.

As shown in FIG. 8A and FIG. 9, the Mises stress σ _{R of} about 80 MPa at the maximum is applied to the resin RA of the structural model 62a. Further, as shown in FIGS. 8B and 9, the Mises stress σ _{R of} about 70 MPa at the maximum is applied to the resin RB of the structural model 62b. Further, as shown in FIGS. 8C and 9, the Mises stress σ _{R of} about 140 MPa at the maximum is applied to the resin RC of the structural model 62c. Further, as shown in FIGS. 8D and 9, the Mises stress σ _{R of} about 50 MPa at the maximum is applied to the resin RD of the structural model 62d. That is, it can be seen that the Mises stress σ _R applied to the resins RA, RB, RC, and RD in which the graphite substrate GF and the CTE are matched is low.

The Mises stress σ _G applied to the graphite substrate GF when simulated under the conditions shown in FIGS. 4 and 5 is expressed as shown in FIGS. 10 and 11. FIG. 10A shows the Mises stress σ _G applied to the graphite substrate GF of the structural model 62a. FIG. 10B shows the Mises stress σ _G applied to the graphite substrate GF of the structural model 62b. FIG. 10C shows Mises stress σ _G applied to the graphite substrate GF of the structural model 62c. FIG. 10D shows the Mises stress σ _G applied to the graphite substrate GF of the structural model 62d. FIG. 11 compares the maximum value of the Mises stress σ _G applied to the graphite substrate GF of the four structural models 62a, 62b, 62c, and 62d shown in FIG.

As shown in FIG. 10A and FIG. 11, the Mises stress σ _{G of} about 310 MPa at the maximum is applied to the graphite substrate GF of the structural model 62a. Further, as shown in FIG. 10B and FIG. 11, the Mises stress σ _{G of} about 240 MPa at the maximum is applied to the graphite substrate GF of the structural model 62b. Further, as shown in FIGS. 10C and 11, a Mises stress σ _{G of} about 350 MPa at the maximum is applied to the graphite substrate GF of the structural model 62 c. Further, as shown in FIGS. 10D and 11, a Mises stress σ _{G of} about 120 MPa at the maximum is applied to the graphite substrate GF of the structural model 62d. That is, it can be seen that the Mises stress σ _G applied to the graphite substrate GF is lower in the RD with the matching CTE than in the resins RA, RB, and RC.

(Example)
Next, the power module according to the embodiment will be described. Here, a 1 in 1 type power module is illustrated as a basic structure.

Example 1
The schematic side structure of the power module according to the first embodiment is expressed as shown in FIG. 12A, and the schematic planar structure is expressed as shown in FIG. As illustrated in FIGS. 12A and 12B, the power module according to the first embodiment includes an anisotropic substrate 61, a semiconductor device (chip) 64 mounted on the substrate 61, and a substrate 61. When the arbitrary direction of the substrate surface is the X direction and the direction orthogonal to the X direction is the Y direction, the substrate 61 has a smaller coefficient of thermal expansion in the Y direction than in the X direction. The resin 62 has a smaller coefficient of thermal expansion in the Y direction than in the X direction.

  Specifically, the substrate 61 may be a graphite substrate 61.

  Moreover, the graphite substrate 61 may be provided with an orientation having a relatively higher thermal conductivity in the thickness direction than in the plane direction (described later).

  Further, the resin 62 may be a thermoplastic resin 62.

  The thermoplastic resin 62 may be a liquid crystal polymer 62.

  The power module is molded by injection molding, and the resin 62 has anisotropy in accordance with the injection direction at the time of molding, and the gate marks 71B and 72B when the injection gates 71 and 72 are arranged in the low thermal expansion coefficient direction. You may provide (refer FIG. 3).

  Further, the injection directions 71A and 72A of the resin 62 may be not less than −45 degrees and not more than +45 degrees with reference to the Y direction (see FIG. 3).

  Further, a copper layer 63 is formed on the substrate 61, a semiconductor device 64 is formed on the copper layer 63, the semiconductor device 64 is connected to the power terminal 66 through the wire 65, and a part of the power terminal 66 is excluded. It may be sealed with resin 62.

  The power module may include any one of a Si-based or SiC-based IGBT, a diode, a MOSFET, and a GaN-based FET.

  Further, the power module may constitute one of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module.

  As mentioned above, according to the power module which concerns on Example 1, since it injected the resin so that CTE might be matched, the curvature of the graphite board | substrate 61 can be suppressed.

-Example 2-
Next, the power module according to the second embodiment will be described only with respect to differences from the first embodiment.

  A schematic side structure of a power module according to the second embodiment is expressed as shown in FIG. As shown in FIG. 13, another graphite substrate 69 is disposed at a position facing the graphite substrate 61, and the facing surfaces and side surfaces of the graphite substrates 61 and 69 are sealed with a resin 62. The semiconductor device 64 is connected to the power terminal 66 through a spacer 67 (columnar electrode) such as copper and a copper layer 68 formed on the graphite substrate 69. In this case as well, the graphite substrates 61 and 69 have a smaller thermal expansion coefficient in the Y direction than the X direction, and the resin 62 has a smaller thermal expansion coefficient in the Y direction than the X direction. is there.

  As described above, even in the power module according to the second embodiment, CTE matching is possible as in the first embodiment, and the warpage of the graphite substrates 61 and 69 cancels each other, so that the warpage is further suppressed. can do.

-Manufacturing method of power module-
Next, the manufacturing method of the power module which concerns on an Example is demonstrated.

  The method for manufacturing a power module according to the embodiment includes a step of forming an anisotropic substrate 61, a step of mounting a semiconductor device 64 on the substrate 61, and a step of laminating a resin 62 on the substrate 61. When the arbitrary direction of the substrate surface is the X direction and the direction orthogonal to the X direction is the Y direction, the substrate 61 is formed so that the thermal expansion coefficient is smaller in the Y direction than in the X direction. The resin 62 is formed so that the thermal expansion coefficient is smaller in the Y direction than in the X direction.

  As described above, according to the method for manufacturing a power module according to the embodiment, since CTE matching is possible, it is possible to manufacture a power module capable of suppressing warpage.

  A step of disposing a second substrate above the semiconductor device so that the substrate faces the substrate (in the same direction as the anisotropy of the substrate), and each terminal, the substrate, and the second substrate; The method may further include a step of sealing with a resin except for a part of the opposite surface and the opposite surface.

(Graphite substrate)
Next, the graphite substrate 61 (69) will be described in detail.

  A schematic configuration (layered structure example) of the graphite sheet (graphene) GS constituting the graphite substrate 61 is expressed as shown in FIG.

  The graphite plate GP includes a first graphite plate GP (XY) having an XY orientation having a higher thermal conductivity in the plane direction than the thickness direction, and a first graphite plate GP (XY) having an XZ orientation having a higher thermal conductivity in the thickness direction than the plane direction. There are two graphite plates GP (XZ), the first graphite plate GP (XY) is represented as shown in FIG. 15 (a), and the second graphite plate GP (XZ) is shown in FIG. 15 (b). It is expressed as shown in

  As shown in FIG. 14, the graphite sheets GS1, GS2, GS3,... GSn on each side composed of n layers have a number of hexagonal covalent bonds in one laminated crystal structure, The graphite sheets GS1, GS2, GS3,..., GSn are joined together by van der Waals forces.

  That is, graphite, which is a carbon-based anisotropic heat transfer material, is a layered crystal of a hexagonal network structure of carbon atoms, and has an anisotropy in heat conduction, and the graphite sheets GS1, GS2,. GS3... GSn has a thermal conductivity (high thermal conductivity) greater than the thickness direction of the Z axis with respect to the crystal plane direction (on the XY plane).

  Therefore, as shown in FIG. 15A, the first graphite plate GP (XY) having the XY orientation is, for example, about X = 1500 (W / mK), Y = 1500 (W / mK), Z = It has a thermal conductivity of about 5 (W / mK).

  On the other hand, as shown in FIG. 15B, the second graphite plate GP (XZ) having XZ orientation has, for example, about X = 1500 (W / mK), about Y = 5 (W / mK), Z = It has a thermal conductivity of about 1500 (W / mK).

The first graphite plate GP (XY) and the second graphite plate GP (XZ) both have a density of about 2.2 (g / cm ³ ) and a thickness of about 0.7 mm to 10 mm. Yes, the size is about 40 mm × 40 mm or less.

  In the power module 2 according to the present embodiment, a 1 in 1 module (basic configuration) and a 2 in 1 module have been mainly described. However, the present invention is not limited to this, and for example, a four in one (4 in 1) module, a six in one (6 in 1) module, 7 in 1 (7 in 1) module with snubber capacitor in 6 in 1 module, Eight in one (8 in 1) module, Twelve in one (12 in 1) module, Fourteen in (14 in 1) It can also be applied to one module.

(Specific examples of semiconductor devices)
In the power module according to the embodiment, a schematic circuit representation of the SiC MOSFET of the 1 in 1 module 50 is expressed as shown in FIG. 16A, and a schematic circuit representation of the IGBT of the 1 in 1 module 50 Is expressed as shown in FIG. FIG. 16A shows a diode DI connected in reverse parallel to the MOSFET. The main electrode of the MOSFET is represented by a drain terminal DT and a source terminal ST. Similarly, FIG. 16B shows a diode DI connected in reverse parallel to the IGBT. The main electrode of the IGBT is represented by a collector terminal CT and an emitter terminal ET.

  Further, in the power module according to the embodiment, the detailed circuit expression of the 1-in-1 module 50 SiC MOSFET is expressed as shown in FIG.

  In the 1 in 1 module 50, for example, one MOSFET is built in one module, but the MOSFET may be a plurality of (for example, 2 to 5) semiconductor chips connected in parallel. In the case of using a SiC transistor, it is difficult to form with a large chip size, which is a particularly useful method. A part of each chip can be mounted for the diode DI.

  More specifically, as shown in FIG. 17, a sense MOSFET Qs is connected in parallel to the MOSFET Q. The sense MOSFET Qs is formed as a fine transistor in the same chip as the MOSFET Q. In FIG. 17, SS is a source sense terminal, CS is a current sense terminal, and G is a gate signal terminal. Also in the power module according to the embodiment, the MOSFET Qs for sensing may be formed as a fine transistor in the same chip.

(Circuit configuration)
The schematic circuit representation of the SiC MOSFET of the 2 in 1 module 100 in the power module according to the embodiment is expressed as shown in FIG. 18A, and the schematic circuit representation of the IGBT of the 2 in 1 module 100 Is expressed as shown in FIG.

  A power module according to the embodiment, which is a 2 in 1 type module in which two (set) semiconductor devices Q1 and Q4 are sealed in one mold resin will be described.

  As shown in FIG. 18A, the 2 in 1 module 100 to which SiC MOSFETs are applied as the semiconductor devices Q1 and Q4 has a half-bridge configuration in which two (set) SiC MOSFETs Q1 and Q4 are incorporated.

  Here, each semiconductor device can be regarded as one large transistor, but the built-in transistor may be one chip or a plurality of chips. The module includes 1 in 1, 2 in 1, 4 in 1, 6 in 1, and the like. For example, in one module, there are two modules having a built-in half bridge composed of two transistors (chips). A module incorporating two sets of in 1, 2 in 1 is called a 6 in 1 module having three sets of 4 in 1, 2 in 1 incorporated therein.

  As shown in FIG. 18A, the 2 in 1 module 100 includes two SiC MOSFETs Q1 and Q4 connected in series and diodes DI1 and DI4 connected in antiparallel to the SiC MOSFETs Q1 and Q4, respectively. . In FIG. 18A, G1 is a lead terminal for the gate signal of the MOSFET Q1, and S1 is a lead terminal for the source signal of the MOSFET Q1. Similarly, G4 is a lead terminal for the gate signal of the MOSFET Q4, and S4 is a lead terminal for the source signal of the MOSFET Q4. P is a positive power terminal, N is a negative power terminal, and O is an output terminal electrode.

  As the semiconductor devices Q1 and Q4, the 2 in 1 module 100 to which the IGBT is applied is antiparallel to the two IGBTQ1 and Q4 and the IGBTQ1 and Q4 connected in series as shown in FIG. Connected diodes DI1 and DI4 are incorporated. In FIG. 18B, G1 is a lead terminal for the gate signal of IGBTQ1, and E1 is a lead terminal for the emitter signal of IGBTQ1. Similarly, G4 is a lead terminal for the gate signal of IGBTQ4, and E4 is a lead terminal for the emitter signal of IGBTQ4.

  The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to the power module according to the embodiment.

(Device structure)
19 is an example of semiconductor devices Q1 and Q4 applicable to the power module according to the embodiment, and a schematic cross-sectional structure of SiC MOSFET 130A including source pad electrode SPD and gate pad electrode GPD is expressed as shown in FIG. The

As shown in FIG. 19, the SiC MOSFET 130A includes a semiconductor layer 31 made of an n ⁻ high resistance layer, a p body region 32 formed on the surface side of the semiconductor layer 31, and a source formed on the surface of the p body region 32. Connected to region 33, gate insulating film 34 disposed on the surface of semiconductor layer 31 between p body regions 32, gate electrode 35 disposed on gate insulating film 34, source region 33, and p body region 32 Source electrode 36, n ⁺ drain region 37 disposed on the back surface opposite to the surface of semiconductor layer 31, and drain electrode 38 connected to n ⁺ drain region 37.

  Gate pad electrode GPD is connected to gate electrode 35 disposed on gate insulating film 34, and source pad electrode SPD is connected to source electrode 36 connected to source region 33 and p body region 32. Further, as shown in FIG. 19, the gate pad electrode GPD and the source pad electrode SPD are disposed on a passivation interlayer insulating film 39 covering the surface of the SiC MOSFET 130A.

  Although not shown, a fine transistor structure may be formed in the semiconductor layer 31 below the gate pad electrode GPD and the source pad electrode SPD.

  Further, as shown in FIG. 19, the source pad electrode SPD may be extended and disposed on the passivation interlayer insulating film 39 also in the transistor structure at the center.

  In FIG. 19, the SiC MOSFET 130A is composed of a planar gate type n-channel vertical SiC MOSFET, but as shown in FIG. 22 described later, it is composed of a trench gate type n-channel vertical SiC TMOSFET 130D. Also good.

  Alternatively, as the semiconductor devices Q1 and Q4 applicable to the power module according to the embodiment, a GaN-based FET or the like can be employed instead of the SiC MOSFET 130A.

  The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to the power module according to the embodiment.

  Furthermore, for the semiconductor devices Q1 to Q6 applicable to the power module according to the embodiment, a semiconductor called a wide band gap type having a band gap energy of 1.1 eV to 8 eV, for example, can be used.

  Similarly, as an example of the semiconductor devices Q1 and Q4 applicable to the power module according to the embodiment, the schematic cross-sectional structure of the IGBT 130B including the emitter pad electrode EPD and the gate pad electrode GPD is as shown in FIG. expressed.

As shown in FIG. 20, the IGBT 130B includes a semiconductor layer 31 made of an n ⁻ high resistance layer, a p body region 32 formed on the surface side of the semiconductor layer 31, and an emitter region formed on the surface of the p body region 32. 33E, a gate insulating film 34 disposed on the surface of the semiconductor layer 31 between the p body regions 32, a gate electrode 35 disposed on the gate insulating film 34, and the emitter region 33E and the p body region 32. Emitter electrode 36E, p ⁺ collector region 37P disposed on the back surface opposite to the surface of semiconductor layer 31, and collector electrode 38C connected to p ⁺ collector region 37P.

  Gate pad electrode GPD is connected to gate electrode 35 disposed on gate insulating film 34, and emitter pad electrode EPD is connected to emitter region 33E and emitter electrode 36E connected to p body region 32. Further, as shown in FIG. 20, the gate pad electrode GPD and the emitter pad electrode EPD are arranged on the passivation interlayer insulating film 39 covering the surface of the IGBT 130B.

  Although not shown, a fine-structure IGBT structure may be formed in the semiconductor layer 31 below the gate pad electrode GPD and the emitter pad electrode EPD.

  Furthermore, as shown in FIG. 20, the emitter pad electrode EPD may be extended and disposed on the passivation interlayer insulating film 39 also in the central IGBT structure.

  In FIG. 20, the IGBT 130B is composed of a planar gate type n-channel vertical IGBT, but may be composed of a trench gate type n-channel vertical IGBT or the like.

  The same applies to the semiconductor devices Q2 and Q5 and the semiconductor devices Q3 and Q6 applicable to the power module according to the embodiment.

  As the semiconductor devices Q1 to Q6, SiC power devices such as SiC DIMOSFET and SiC TMOSFET described later, or GaN power devices such as GaN HEMT can be applied. In some cases, power devices such as Si-based MOSFETs and SiC-based IGBTs are also applicable.

―SiC DIMOSFET―
It is an example of the semiconductor device applicable to the power module which concerns on embodiment, Comprising: The typical cross-section of SiC DIMOSFET130C is represented as shown in FIG.

21 includes a semiconductor layer 31 made of an n ⁻ high resistance layer, a p body region 32 formed on the surface side of the semiconductor layer 31, and an n ⁺ source region formed on the surface of the p body region 32. 33, a gate insulating film 34 disposed on the surface of the semiconductor layer 31 between the p body regions 32, a gate electrode 35 disposed on the gate insulating film 34, and the source region 33 and the p body region 32. Source electrode 36, n ⁺ drain region 37 disposed on the back surface opposite to the surface of semiconductor layer 31, and drain electrode 38 connected to n ⁺ drain region 37.

In FIG. 21, in SiC DIMOSFET 130C, p body region 32 and n ⁺ source region 33 formed on the surface of p body region 32 are formed by double ion implantation (DII), and source pad electrode SPD is formed in source region 33. And to the source electrode 36 connected to the p body region 32.

  The gate pad electrode GPD not shown is connected to the gate electrode 35 disposed on the gate insulating film 34. Further, as shown in FIG. 21, the source pad electrode SPD and the gate pad electrode GPD are arranged on the passivation interlayer insulating film 39 so as to cover the surface of the SiC DIMOSFET 130C.

As shown in FIG. 21, in the SiC DIMOSFET 130C, a depletion layer as shown by a broken line is formed in a semiconductor layer 31 composed of an n ⁻ high resistance layer sandwiched between p body regions 32, so that a junction FET ( A channel resistance R _{JFET due} to the JFET) effect is formed. A body diode BD is formed between the p body region 32 and the semiconductor layer 31 as shown in FIG.

―SiC TMOSFET―
22 is an example of a semiconductor device applicable to the power module according to the embodiment, and a schematic cross-sectional structure of SiC TMOSFET 130D is expressed as shown in FIG.

22 includes an n-layer semiconductor layer 31N, a p body region 32 formed on the surface side of the semiconductor layer 31N, an n ⁺ source region 33 formed on the surface of the p body region 32, A trench gate electrode 35TG formed through a gate insulating film 34 and interlayer insulating films 39U and 39B in a trench penetrating the p body region 32 up to the semiconductor layer 31N, a source region 33, and a p body region 32 A source electrode 36 connected, an n ⁺ drain region 37 disposed on the back surface opposite to the surface of the semiconductor layer 31N, and a drain electrode 38 connected to the n ⁺ drain region 37 are provided.

  In FIG. 22, SiC TMOSFET 130D has a trench gate electrode 35TG formed through a gate insulating film 34 and interlayer insulating films 39U and 39B in a trench penetrating p body region 32 and extending to semiconductor layer 31N. Electrode SPD is connected to source electrode 36 connected to source region 33 and p body region 32.

  The gate pad electrode GPD (not shown) is connected to the trench gate electrode 35TG disposed on the gate insulating film 34. Further, as shown in FIG. 20, the source pad electrode SPD and the gate pad electrode GPD are disposed on the passivation interlayer insulating film 39U so as to cover the surface of the SiC TMOSFET 130D.

In the SiC TMOSFET 130D, the channel resistance R _JFET associated with the JFET effect as in the SiC DIMOSFET 130C is not formed. A body diode BD is formed between the p body region 32 and the semiconductor layer 31N, as in FIG.

(Application examples)
In the circuit configuration of the three-phase AC inverter 40A configured using the power module according to the embodiment, a circuit configuration example in which a SiC MOSFET is applied as a semiconductor device and a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL is as follows. This is expressed as shown in FIG. Similarly, a circuit configuration example of a three-phase AC inverter 40B in which an IGBT is applied as a semiconductor device and a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL is expressed as shown in FIG.

When the power module is connected to the power supply E and the switching operation is performed, the switching speed of the SiC MOSFET or IGBT is high due to the inductance L of the connection line, and thus a large surge voltage Ldi / dt is generated. For example, assuming that the current change di = 300 A and the time change dt = 100 nsec accompanying switching, di / dt = 3 × 10 ⁹ (A / s).

  Although the value of the surge voltage Ldi / dt varies depending on the value of the inductance L, the surge voltage Ldi / dt is superimposed on the power source E. The surge voltage Ldi / dt can be absorbed by the snubber capacitor C connected between the power supply terminal PL and the ground terminal NL.

(Concrete example)
Next, a three-phase AC inverter 42B to which SiC MOSFET is applied as a semiconductor device will be described with reference to FIG.

  As shown in FIG. 24, a three-phase AC inverter 42A includes a power module unit 200 in which a plurality of switching elements are formed, a gate driver (GD) 180 for controlling the switching operation of each switching element, and each switching element. Are connected to each other, a power source or a storage battery (E) 53, and a converter 55 that converts the power of the power source 53 and supplies the power to each switching element. The power module unit 200 is connected to U-phase, V-phase, and W-phase inverters corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 51.

  Here, the GD 180 is connected to each gate terminal of the SiC MOSFETs Q1 and Q4, the SiC MOSFETs Q2 and Q5, and the SiC MOSFETs Q3 and Q6, and controls the switching operation of each MOSFET.

  The power module unit 200 is connected between a plus terminal (+) P and a minus terminal (−) N of a converter 55 to which a power source or a storage battery (E) 53 is connected, and is configured as an inverter-structured SiC MOSFET Q1 · Q4, Q2 · Q5 and Q3 and Q6 are provided. Free wheel diodes DI1 to DI6 are connected in antiparallel between the sources and drains of the SiC MOSFETs Q1 to Q6, respectively.

  Next, with reference to FIG. 25, a three-phase AC inverter 42B configured by using an IGBT as a semiconductor device and using the power module according to the embodiment will be described.

  As shown in FIG. 25, the three-phase AC inverter 42 </ b> B includes a power module unit 200, a GD 180, a three-phase AC motor unit 51, a power source or storage battery (E) 53, and a converter 55. The power module unit 200 is connected to U-phase, V-phase, and W-phase inverters corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 51.

  Here, GD180 is connected to IGBTQ1 * Q4, IGBTQ2 * Q5, and IGBTQ3 * Q6.

  The power module unit 200 is connected between a plus terminal (+) P and a minus terminal (−) N of a converter 55 to which a storage battery (E) 53 is connected, and IGBTs Q1 · Q4, Q2 · Q5 having an inverter configuration, And Q3 and Q6. Free wheel diodes DI1 to DI6 are connected in antiparallel between the emitters and collectors of the IGBTs Q1 to Q6, respectively.

[Another embodiment 1]
Several power modules to which the configuration for suppressing warp as described above can be applied will be exemplified. In the power module exemplified below, it is possible to adopt a graphite substrate as the substrate, laminate the resin on the graphite substrate, and match the CTE in the X direction and Y direction of the resin to the CTE in the X direction and Y direction of the graphite substrate. It is. In the following description, the power module may be described as “PM”.

  In the PM 1 according to the embodiment, a schematic bird's-eye pattern configuration before resin molding is expressed as shown in FIG. Here, a 2 in 1 module type half-bridge built-in module to which SiC MOSFETs Q1 and Q4 are applied will be described as an example of a power element semiconductor device (power device).

  And as PM1 which concerns on embodiment, as a mold type module, the typical bird's-eye view structure after resin molding of the module with a built-in half bridge is expressed as shown in FIG.

  Note that the PM 1 according to the embodiment has a configuration of a half-bridge built-in module in which two SiC MOSFETs Q1 and Q4 connected in series are built in one module.

  As shown in FIG. 27, the PM 1 according to the embodiment includes a positive power input terminal electrode (positive power terminal) P and a negative power terminal P arranged on the first side of the ceramic substrate 21 covered with the resin mold layer 115. Side power input terminal electrode (negative power terminal) N, gate terminal (gate) GT1 and source sense terminal SST1 disposed on the second side adjacent to the first side, and the first side facing the first side Output terminal electrode (output terminal) O arranged on the third side, and a gate terminal GT4 and a source sense terminal SST4 arranged on the fourth side opposite to the second side.

  The PM 1 according to the embodiment is a power module having a four power terminal structure including two output terminals O.

  Here, as shown in FIGS. 26 to 27, the gate terminal GT1 and the source sense terminal SST1 are connected to the gate signal electrode pattern GL1 and the source signal electrode pattern SL1 of the SiC MOSFET Q1, and the gate terminal GT4 and the source sense terminal SST4 are The SiC MOSFET Q4 is connected to the gate signal electrode pattern GL4 and the source signal electrode pattern SL4.

  As shown in FIGS. 26 to 27, gate terminals GT1 and GT4 for external extraction and source sense terminals SST1 and SST4 are connected to the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 by soldering or the like. Is done.

  26 to 27, the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 are disposed on the signal substrates 261 and 264, and the signal substrates 261 and 264 are soldered on the ceramic substrate 21. Connected by attaching.

  The signal substrates 261 and 264 can be formed of a ceramic substrate. The ceramic substrate may be formed of, for example, Al2O3, AlN, SiN, AlSiC, or at least a surface of insulating SiC.

  Although not shown in FIGS. 26 to 27, diodes may be connected in antiparallel between D1 and S1 and between D4 and S4 of the SiC MOSFETs Q1 and Q4.

  The positive power terminal P, the negative power terminal N, the external extraction gate terminals GT1 and GT4, and the source sense terminals SST1 and SST4 can be formed of Cu, for example.

  The electrode patterns 25D1, 25D4, and 25DN that are main wiring conductors can be formed of Cu, for example.

  In the example shown in FIGS. 26 to 27, in the 2 in 1 module type half-bridge built-in module, the electrode pattern 25D1 functions as a drain electrode pattern for a high-side device (SiC MOSFET Q1). .

  Further, the electrode pattern 25D4 functions as a drain electrode pattern for a low-side device (SiC MOSFET Q4) and also functions as a source electrode pattern (25S1) for a high-side device. That is, the drain electrode pattern 25D4 is the drain electrode of the SiC MOSFET Q4 and at the same time the source electrode of the SiC MOSFET Q1.

  Further, the electrode pattern 25DN connected to the negative power terminal N also functions as a source electrode pattern (25S4) for the low-side device.

  That is, in PM1 according to the embodiment, as shown in FIGS. 26 to 27, SiC MOSFET Q1 is mounted on electrode pattern 25D1, drain D1 is connected to electrode pattern 25D1, and source S1 is a lead frame. It is connected to the electrode pattern 25D4 via SM1. Similarly, the SiC MOSFET Q4 is mounted on the electrode pattern 25D4, the drain D4 is connected to the electrode pattern 25D4, and the source S4 is connected to the electrode pattern 25DN via the lead frame SM4.

  In the following description, the junction between the source pad electrode SP1 and the lead frame SM1 is referred to as a device side junction (first junction) DC, which is separated from the device side junction DC and generates more heat than the device side junction DC. A junction between the lead frame SM1 and the source electrode pattern 25S1 having a relatively low temperature and a relatively low temperature is defined as a land-side junction (second junction) SC.

  As shown in FIGS. 26 to 27, in PM1 according to the embodiment, on the land side junction SC side, a source sense bonding wire (first bonding) for connecting the lead frame SM1 to the source signal electrode pattern SL1. Wire) SSW1 and a gate signal bonding wire (second bonding wire) GW1 for connecting the gate pad electrode GP1 to the gate signal electrode pattern GL1 on the device side junction DC side facing the land side junction SC.

  Similarly, on the land side junction SC side, a source sense bonding wire (first bonding wire) SSW4 for connecting the lead frame SM4 to the source signal electrode pattern SL4 and a device side junction DC facing the land side junction SC. On the side, a gate signal bonding wire (second bonding wire) GW4 for connecting the gate pad electrode GP4 to the gate signal electrode pattern GL4 is provided.

  FIG. 28 shows a schematic bird's-eye pattern configuration of the six-in-one (6 in 1) module, which is PM2 according to the embodiment.

  Note that PM2 according to the embodiment is an example in which three PM1s are arranged in parallel on a common ceramic substrate 21A to constitute a 6 in 1 module type switching module.

  Here, in the case of a 6 in 1 module type switching module, the basic structure is the same as that of a 1 in 1 module type PM or a 2 in 1 module type PM. That is, the PM2 according to the embodiment, which is a 6 in 1 module type switching module, includes 2 in 1 module type PMs 11, 12, and 13 as illustrated in FIG. 28.

  PM11 is mounted with, for example, SiC MOSFETs Q1 and Q4 as semiconductor devices, PM12 is mounted with, for example, SiC MOSFETs Q2 and Q5, PM13 is mounted with, for example, SiC MOSFETs Q3 and Q6, and PM11, 12, and 13 are the same as PM1. Yes, detailed explanation is omitted.

  In addition, it is PM2 which concerns on embodiment, Comprising: For example, the switching module of 6 in 1 module type integrates PM11 * 12 * 13 of 2 in 1 module type by common mold resin or a case not shown in figure. The structure formed by sealing is provided.

  That is, in the 6 in 1 module type switching module (PM2 according to the embodiment), PM11, 12, and 13 are arranged in parallel on a common ceramic substrate 21A, and an integrated package (resin mold layer not shown). ) And the back electrode pattern 23R can be shared (integrated).

  Alternatively, a 2-in-1 module type PM11, 12, 13 sealed separately by a separate molding resin or case is further arranged in parallel on a common ceramic substrate 21A, and a 6-in-1 module type switching module. It is also possible.

  Also in the case of the configuration of PM2 (6 in 1 module type switching module) according to such an embodiment, as shown in FIG. 28, the source pad electrodes SP1, SP4, SP2,. Lead frames SM1 and SM4 connected between SP5, SP3 and SP6 and the source electrode patterns 25S1 (25D4) and 25S4 (25DN), 25S2 (25D5) and 25S5 (25DN), 25S3 (25D6) and 25S6 (25DN) , SM2, SM5, SM3, SM6 and the lead frame SM1, SM4, SM2, SM5, SM3, SM6 of the land side junction SC and the source signal electrode patterns SL1, SL4, SL2, SL5, SL3, SL6 Source sense bonding wires SSW1, SSW4, By providing SSW2, SSW5, and SSW3, SSW6, it is possible to reduce the influence of heat on the wire connection due to high temperature operation, and it is possible to improve the heat resistance and reliability of the wire connectivity.

  The source sense bonding wires SSW1, SSW4, SSW2, SSW5, SSW3, SSW6 are on the land side junction SC side, and the source electrode patterns 25S1 (25D4), 25S4 (25DN), 25S2 (25D5), 25S5 (25DN) , 25S3 (25D6) / 25S6 (25DN).

[Another embodiment 2]
In the PM 1 according to the embodiment, a schematic bird's-eye pattern configuration before wire bonding and resin molding is represented as shown in FIG. 29 (a), and a schematic planar pattern configuration is shown in FIG. 29 (b). It is expressed in 29 (a) and 29 (b) show specific examples of the arrangement of the semiconductor devices in PM1, and a 2 in 1 module type in which SiC MOSFETs Q1 and Q4 are applied as the semiconductor devices Q. A half-bridge built-in module is illustrated.

  That is, the PM 1 according to the embodiment has a configuration of a half-bridge built-in module in which two SiC MOSFETs Q1 and Q4 connected in series are built in one module.

  The PM 1 according to the embodiment includes a positive power input terminal electrode (positive power terminal) P and a negative power input terminal electrode disposed on the first side of the ceramic substrate 21 covered with a resin mold layer (not shown). (Negative power terminal) N, gate terminal GT1 (gate G1) / source sense terminal SST1 (source S1) disposed on the second side adjacent to the first side, and the first side opposite to the first side Output terminal electrode (output terminal) O arranged on the third side, gate terminal GT4 (gate G4) and source sense terminal SST4 (source S4) arranged on the fourth side opposite to the second side. Prepare.

  In addition, PM1 which concerns on embodiment is a power module of the 4 electric power terminal structure provided with the two output terminals O. FIG.

  Here, as shown in FIGS. 29A and 29B, each of the two (set) SiC MOSFETs Q1 and Q4 includes three devices (chips), and each chip of the SiC MOSFET Q1 has a gate terminal. Commonly connected to GT1 and source sense terminal SST1 (connection of GT1 is not shown), and each chip of SiC MOSFET Q4 is commonly connected to gate terminal GT4 and source sense terminal SST4 (connection of GT4 is not shown).

  The gate terminal GT1 and the source sense terminal SST1 are connected to the gate signal electrode pattern GL1 and the source signal electrode pattern SL1 of the SiC MOSFET Q1, and the gate terminal GT4 and the source sense terminal SST4 are connected to the gate signal electrode pattern GL4 and the source signal electrode of the SiC MOSFET Q4. Connected to pattern SL4.

  As shown in FIG. 29A and FIG. 29B, the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 include gate terminals GT1 and GT4 for external extraction and source sense terminals SST1 and SST4. Are connected by soldering.

  As shown in FIGS. 29A and 29B, the gate signal electrode patterns GL1 and GL4 and the source signal electrode patterns SL1 and SL4 are arranged on the signal boards 261 and 264, and the signal boards 261 and 264 are It may be connected to the ceramic substrate 21 by soldering or the like.

  The signal substrates 261 and 264 can be formed of a ceramic substrate. The ceramic substrate may be formed of, for example, Al2O3, AlN, SiN, AlSiC, or at least a surface of insulating SiC.

  Although not shown in FIGS. 29 (a) and 29 (b), diodes (DI1.multidot.DI1.multidot.D1) are connected in parallel between the drains D1 and S1 and between the drains D4 and S4 of the SiC MOSFETs Q1 and Q4. DI4) may be connected.

  The positive power terminal P, the negative power terminal N, the external extraction gate terminals GT1 and GT4, and the source sense terminals SST1 and SST4 can be formed of Cu, for example.

  The surface electrode pattern 23 (23D1, 23D4, and 23DN) that is the main wiring conductor can be formed of Cu, for example.

  Here, in the example shown in FIGS. 29A and 29B, in the 2 in 1 module type half-bridge built-in module, the surface electrode pattern 23D1 is for the high side device (SiC MOSFET Q1). Function as a drain electrode pattern.

  Further, the surface electrode pattern 23D4 functions as a drain electrode pattern for a low-side device (SiC MOSFET Q4) and also functions as a source electrode pattern (23S1) for a high-side device. That is, the drain electrode pattern 23D4 is the drain electrode of the SiC MOSFET Q4 and at the same time the source electrode of the SiC MOSFET Q1.

  Further, the surface electrode pattern 23DN connected to the negative power terminal N functions as a source electrode pattern (23S4) for the row side device.

  That is, in PM1 according to the embodiment, as shown in FIGS. 29A and 29B, SiC MOSFET Q1 is mounted on surface electrode pattern 23D1, and drain D1 is connected to surface electrode pattern 23D1. At the same time, the source S1 is connected to the surface electrode pattern 23D4 via a bonding wire (source signal bonding wire not shown).

  Similarly, the SiC MOSFET Q4 is mounted on the surface electrode pattern 23D4, the drain D4 is connected to the surface electrode pattern 23D4, and the source S4 is connected to the surface electrode pattern via a bonding wire (source signal bonding wire not shown). 23DN.

  In PM1 according to the embodiment, although not shown, a source sense bonding wire for connecting the source sense pad electrode of SiC MOSFET Q1 to source signal electrode pattern SL1, and a gate pad electrode as a gate signal electrode pattern And a gate signal bonding wire connected to GL1.

  Similarly, although not shown, a source sense bonding wire for connecting the source sense pad electrode of the SiC MOSFET Q4 to the source signal electrode pattern SL4, and a gate signal bonding wire for connecting the gate pad electrode to the gate signal electrode pattern GL4, Is provided.

  That is, source sense bonding wires for connecting the source sense pad electrodes are wedge-bonded to the source signal electrode patterns SL1 and SL4 of the SiC MOSFETs Q1 and Q4.

  As shown in FIGS. 29 (a) and 29 (b), PM1 according to the embodiment includes a ceramic substrate 21, a graphite substrate 18GH disposed on the upper surface (first surface) of the ceramic substrate 21, and a graphite substrate. Front electrode patterns (second electrode patterns) 23D1, 23D4, and 23DN arranged on 18GH, and back electrode patterns (first electrode patterns) (not shown) arranged on the lower surface (second surface) of the ceramic substrate 21; And a plurality of SiC MOSFETs Q1 and Q4 arranged side by side along the direction of the arrow X on the surface electrode patterns 23D1 and 23D4.

  In PM1 according to the embodiment, the GH (YZ) orientation of graphite substrate 18GH is set to an orientation direction TD that is substantially perpendicular to the X direction of the arrangement of the plurality of SiC MOSFETs Q1 and Q4 and substantially coincides with the Y direction. That is, the allowable amount of deviation (allowable deviation amount) of the alignment direction PD1 with respect to the alignment direction TD of GH (YZ) of the SiC MOSFETs Q1 and Q4 arranged side by side in the X direction is the alignment direction PD corresponding to the X direction. On the plane of the graphite substrate 18GH (substrate surface), a range of angle θ of about −45 degrees to +45 degrees in the clockwise direction, preferably a range of angle θ of about −30 degrees to +30 degrees. Is done.

  In FIGS. 29A and 29B, when the semiconductor device Q is a SiC MOSFET, GT1 and GT4 are lead terminals (so-called gate terminals) for gate signals of the SiC MOSFETs Q1 and Q4, and SST1 SST4 is a source signal lead terminal (so-called source sense terminal) of the SiC MOSFETs Q1 and Q4.

  On the other hand, in the case of the IGBT, GT1 and GT4 are the lead terminals for the gate signals of IGBTQ1 and Q4, and SST1 and SST4 are the lead terminals for the emitter signals of IGBTQ1 and Q4.

  According to the PM 1 according to the embodiment, by adopting the graphite insulating substrate to which the graphite substrate 18GH is applied, the arrangement direction PD1 of the plurality of semiconductor devices Q is changed to the GH (XZ) / GH (YZ) orientation of the graphite substrate 18GH. A high thermal diffusion effect can be expected by approximating the alignment direction PD having a relatively low thermal conductivity substantially perpendicular to the alignment direction TD.

  That is, the PM1 according to the embodiment can provide a power module that has good thermal diffusivity, is structurally simple, is inexpensive, and can have a lower thermal resistance.

  The 2-in-1 module type PM1 can be applied to a structure having a source electrode pattern above the semiconductor devices Q1 and Q4, and is also limited to a 2-in-1 module type. Absent.

  A schematic bird's-eye pattern configuration of PM1 according to the embodiment is represented as shown in FIG. 30 (a), and a schematic planar pattern configuration is represented as shown in FIG. 30 (b). In addition, in FIG. 30 (a) and FIG.30 (b), the case where it applies to PM1 of 3 electric power terminal structure is illustrated.

  Here, as shown in FIGS. 30A and 30B, PM1 according to the embodiment has substantially the same configuration as PM1 according to the embodiment except for the power terminal structure.

  That is, as shown in FIG. 30A and FIG. 30B, the PM 1 according to the embodiment includes a ceramic substrate 21 and a graphite substrate 18GH disposed on the upper surface (first surface) of the ceramic substrate 21. Front electrode patterns (second electrode patterns) 23D1, 23D4, and 23DN arranged on the graphite substrate 18GH, and back electrode patterns (first electrode patterns) arranged on the lower surface (second surface) of the ceramic substrate 21 (not shown) And a plurality of semiconductor devices (modules) Q1 and Q4 arranged side by side in the direction of the arrow X on the surface electrode patterns 23D1 and 23D4.

  In PM1 according to the embodiment, the GH (YZ) orientation in the orientation direction TD of the graphite substrate 18GH is a direction substantially orthogonal to the orientation direction PD along the X direction of the plurality of semiconductor devices Q1 and Q4.

  30 (a) and 30 (b), P is a positive power supply input terminal electrode, N is a negative power supply input terminal electrode, O is an output terminal electrode, and one output It is PM of the 3 power terminal structure provided with the terminal electrode O.

  In FIGS. 30A and 30B, GL1 is a gate signal electrode pattern to which a gate signal lead terminal (not shown) of the SiC MOSFET Q1 is connected, and SL1 is a source signal of the SiC MOSFET Q1. This is a source signal electrode pattern to which a lead terminal (not shown) is connected. Similarly, GL4 is a gate signal electrode pattern to which a lead terminal (not shown) for the gate signal of the SiC MOSFET Q4 is connected, and SL4 is connected to a lead terminal (not shown) for the source signal of the SiC MOSFET Q4. It is a source signal electrode pattern.

  In the figure, BW1 is a source signal bonding wire for commonly connecting the source pad electrode of the SiC MOSFET Q1 to the surface electrode pattern 23D4 that also functions as the source electrode, and BW4 is the source pad electrode of the SiC MOSFET Q4. This is a source signal bonding wire for commonly connecting to the surface electrode pattern 23DN that also functions as a source electrode.

  Also by PM1 according to the embodiment, the orientation direction PD1 of the plurality of semiconductor devices Q1 and Q4 on the substrate surface of the graphite substrate 18GH is changed to an orientation direction (Y direction) TD corresponding to the GH (YZ) orientation of the graphite substrate 18GH. By adopting an orientation direction (X direction) PD that is substantially orthogonal to X, the thermal diffusibility is good, the structure is simple, the cost is low, and the thermal resistance can be further reduced.

  As described above, according to the present embodiment, it is possible to provide a power module capable of suppressing warpage and a method for manufacturing the power module.

[Other embodiments]
Although several embodiments have been described as described above, the discussion and drawings that form part of the disclosure are illustrative and should not be construed as limiting. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present embodiment includes various embodiments that are not described herein.

  The power module of the present embodiment can be used for various semiconductor module technologies such as IGBT modules, diode modules, and MOS modules using Si substrates, SiC substrates, and GaN substrates. HEV (Hybrid Electric Vehicle) / EV It can be applied to a wide range of application fields such as inverters for (Electric Vehicle), industrial equipment such as robots, and inverters and converters for home appliances.

61, 69, GF ... Substrate (graphite substrate)
64 ... Semiconductor device 62, RA, RB, RC, RD ... Resin (thermoplastic resin, liquid crystal polymer)
71, 72 (resin) injection gates 71B, 72B ... gate marks 71A, 72A ... (resin) injection direction 63, 68 ... copper layer 64 ... semiconductor device 65 ... wire 66 ... power terminal 67 ... spacer (columnar electrode)

Claims (20)

A substrate having anisotropy in thermal expansion coefficient;
A semiconductor device mounted on the substrate;
A resin layered on the substrate and sealing the semiconductor device,
When the arbitrary direction of the surface on which the semiconductor device of the substrate is mounted is the X direction, and the direction orthogonal to the X direction is the Y direction,
The substrate has a smaller coefficient of thermal expansion in the Y direction than in the X direction,
The power module, wherein the resin has a smaller coefficient of thermal expansion in the Y direction than in the X direction.   The power module according to claim 1, wherein the substrate is a graphite substrate.   The power module according to claim 2, wherein the graphite substrate has an orientation in which a thermal conductivity is relatively higher in a thickness direction than in a plane direction.   The power module according to claim 1, wherein the resin is a thermoplastic resin.   The power module according to claim 4, wherein the thermoplastic resin is a liquid crystal polymer. The resin of the power module is molded by injection molding,
The resin has anisotropy so that the thermal expansion coefficient in the direction along the injection direction at the time of molding is small, and has a gate mark when an injection gate is arranged at one end of the substrate in the low thermal expansion coefficient direction. The power module according to claim 1, wherein the power module is a power module.   The power module according to claim 6, wherein an injection direction of the resin is −45 degrees or more and +45 degrees or less with respect to the Y direction. A copper layer having a wiring pattern is formed on the substrate,
The semiconductor device is mounted on the copper layer,
The semiconductor device is connected to a power terminal and an output terminal;
The power module according to claim 1, wherein the power module is sealed with the resin except for a part of the terminals.   The power module according to any one of claims 1 to 8, wherein the power module includes any one of a Si-based or SiC-based IGBT, a diode, a MOSFET, and a GaN-based FET.   2. The power module comprises any one of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module. The power module according to any one of? 9. A step of forming a substrate having anisotropy in thermal expansion coefficient;
A step of mounting a semiconductor device on the substrate;
And a step of laminating a resin so as to seal the semiconductor device on the substrate,
When the arbitrary direction of the substrate surface is the X direction and the direction orthogonal to the X direction is the Y direction,
The substrate is formed to have a smaller thermal expansion coefficient in the Y direction than in the X direction,
The method for producing a power module, wherein the resin is formed by injecting resin from one end in the X direction.   The method of manufacturing a power module according to claim 11, wherein the substrate is a graphite substrate.   The method for manufacturing a power module according to claim 12, wherein the graphite substrate has an orientation in which a thermal conductivity is relatively higher in a thickness direction than in a plane direction.   The method for manufacturing a power module according to claim 11, wherein the resin is a thermoplastic resin.   The method of manufacturing a power module according to claim 14, wherein the thermoplastic resin is a liquid crystal polymer. The power module is molded by injection molding,
The resin has anisotropy so as to have a low coefficient of thermal expansion along the injection direction at the time of molding, and an injection gate is disposed in the same direction as the low coefficient of thermal expansion of the substrate. The manufacturing method of the power module of any one of 11-15.   The method of manufacturing a power module according to claim 16, wherein an injection direction of the resin is −45 degrees or more and +45 degrees or less with respect to the Y direction. Disposing a second substrate above the semiconductor device so as to face the substrate;
18. The method according to claim 11, further comprising a step of sealing with the resin except for a part of the surface opposite to the opposing surface of each terminal, the substrate, and the second substrate. A method for manufacturing the power module according to claim 1.   The method of manufacturing a power module according to any one of claims 11 to 18, wherein the power module includes any one of a Si-based or SiC-based IGBT, a diode, a MOSFET, and a GaN-based FET.   12. The power module comprises any one of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module. The manufacturing method of the power module of any one of -19.