JP2014022580A - Power module semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power module semiconductor device capable of eliminating a wiring pillar, downsizing, and weight saving of a thin SiC power module.SOLUTION: A power module semiconductor device comprises: a ceramic substrate 10; a first pattern D(K4) of a first Cu plate layer 10a arranged on a surface of the ceramic substrate 10; a first semiconductor device Q4 arranged on the first pattern D(K4); a first source pad electrode SP arranged on the first semiconductor device Q4; a first insulating film 60 arranged around the first source pad electrode SP on the first semiconductor device Q4 and having a film thickness thicker than that of the first source pad electrode SP; and a first top plate electrode 22 arranged on the first insulating film 60 and the first source pad electrode SP.

Description

  The present invention relates to a power module semiconductor device, and more particularly to a power module semiconductor device that can be reduced in wiring pillar size, size, and weight.

  Currently, many research institutions are conducting research and development of silicon carbide (SiC) devices. The characteristics of the SiC power device include low on-resistance, high-speed switching, and high-temperature operation that are superior to conventional Si power devices.

  In a conventional Si power device such as an insulated gate bipolar transistor (IGBT), the operable temperature range is up to about 150 ° C.

  However, SiC power devices can theoretically operate up to about 600 ° C.

  In the conventional Si power module, the loss of the Si power device is relatively large, and a large power cannot be output due to the problem of heat generation. Since the thermal resistance of the power module can be tolerated even if the power module cannot output a large amount of power, the power module is formed thick in consideration of the effects of warpage, but there is a limit to downsizing the power module. there were.

  In the SiC power module, since the loss of the SiC device is relatively small, a large current can be conducted and high-temperature operation is facilitated. However, the design of a thin power module to allow it is essential.

  A case type is adopted for the package of these SiC power devices.

  On the other hand, a semiconductor device sealed with a transfer mold is also disclosed (for example, refer to Patent Document 1).

  Moreover, the structure of the SiC power device which applies a wire bonding technique with respect to a source electrode is also disclosed (for example, refer patent document 2).

JP 2005-183463 A JP 2007-305962 A

  In the conventional Si power module, since the normalized on-resistance of the Si device is large, the chip size has to be increased to reduce the resistance, and the area of the entire module is large. For this reason, the module is likely to warp, and in order to suppress this warpage, the built-in substrate is thick, and the thickness of the entire module is also thick by design. Also, high temperature operation was not possible due to the thermal runaway of Si devices at high temperatures.

  In the SiC power module, a thin power module is required in terms of miniaturization. In the SiC power module, since the chip area of the SiC device is reduced, the thermal resistance is difficult to decrease, and high-temperature operation is also required, so that the warpage of the members of the thin power module becomes a problem.

  Moreover, in the conventional semiconductor module, there are many built-in members, and size reduction has been insufficient. Also, space saving cannot be achieved because the terminal layout is not optimized when mounted on the system. Further, in order to avoid a short circuit between the bonding wire and the built-in member, it is necessary to increase the thickness between the upper surface plate electrode and the substrate, and the size reduction is insufficient.

  An object of the present invention is to provide a power module semiconductor device capable of reducing the wiring pillar of a thin SiC power module, reducing the size, and reducing the weight.

  According to one aspect of the present invention for achieving the above object, the ceramic substrate, the first pattern of the first copper plate layer disposed on the surface of the ceramic substrate, and the first pattern are disposed on the first pattern. A first semiconductor device; a first source pad electrode disposed on the first semiconductor device; and a periphery of the first source pad electrode disposed on the first semiconductor device; There is provided a power module semiconductor device including a first insulating film having a thick film thickness, and a first upper surface plate electrode disposed on the first insulating film and the first source pad electrode.

  ADVANTAGE OF THE INVENTION According to this invention, the power module semiconductor device which can make wiring pillar-less of a thin SiC power module, size reduction, and weight reduction can be provided.

The typical plane pattern block diagram of the power module semiconductor device which concerns on 1st Embodiment. FIG. 2 is a schematic cross-sectional structure diagram taken along line II in FIG. 1. The typical cross-section figure of the power module semiconductor device which concerns on a comparative example. The typical plane pattern block diagram of the power module semiconductor device which concerns on a comparative example. FIG. 5 is a schematic cross-sectional structure diagram taken along line II-II in FIG. 4. The typical plane pattern block diagram explaining 1 process of the manufacturing method of the power module semiconductor device which concerns on 1st Embodiment. FIG. 7 is a schematic cross-sectional structure diagram (part 1) taken along line III-III in FIG. 6. Typical cross-section FIG. (2) explaining 1 process of the manufacturing method of the power module semiconductor device which concerns on 1st Embodiment. It is a power module semiconductor device which concerns on 1st Embodiment, Comprising: The typical bird's-eye view block diagram of a 2 in 1 module. The power module semiconductor device which concerns on 1st Embodiment, Comprising: In the two-in-one module, the typical bird's-eye view block diagram before forming the resin layer. The typical plane pattern block diagram of the upper surface board electrode applied to the power module semiconductor device which concerns on 1st Embodiment. The power module semiconductor device which concerns on 1st Embodiment, Comprising: In the two-in-one module, the typical bird's-eye view block diagram before forming an upper surface board electrode. It is a power module semiconductor device which concerns on 1st Embodiment, Comprising: The typical plane pattern block diagram of a 2 in 1 module. FIG. 14 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. 13. It is a power module semiconductor device which concerns on 1st Embodiment, Comprising: The typical back surface external appearance block diagram of a two-in-one module. 1 is a schematic circuit representation diagram of a two-in-one module, which is a power module semiconductor device according to a first embodiment. FIG. It is an example of the semiconductor device applied to the power module semiconductor device which concerns on 1st Embodiment, Comprising: The typical cross-section figure of SiC MOSFET. FIG. 4 is a schematic cross-sectional structure diagram of a SiC MOSFET that is an example of a semiconductor device applied to the power module semiconductor device according to the first embodiment and includes a source pad electrode SP and a gate pad electrode GP. The typical circuit block diagram of the three-phase alternating current inverter comprised using the power module semiconductor device which concerns on 1st Embodiment. FIG. 3 is a schematic plan configuration diagram in which three power module semiconductor devices according to the first embodiment are arranged in parallel to drive a three-phase AC inverter. The typical bird's-eye view block diagram which bent the signal terminal in the power module semiconductor device which concerns on 1st Embodiment. The typical plane block diagram which arrange | positions the three power module semiconductor devices which concern on 1st Embodiment in parallel, and drives a 3-phase alternating current inverter. It is a power module semiconductor device which concerns on 2nd Embodiment, Comprising: The typical circuit representation figure of a one-in-one module. It is a power module semiconductor device which concerns on 2nd Embodiment, Comprising: The detailed circuit representation figure of a one-in-one module. It is a power module semiconductor device which concerns on 2nd Embodiment, Comprising: The typical bird's-eye view block diagram of a one-in-one module. It is a power module semiconductor device which concerns on 2nd Embodiment, Comprising: The typical plane pattern block diagram of a one-in-one module. It is a power module semiconductor device which concerns on 2nd Embodiment, Comprising: The typical back surface external appearance block diagram of a 1 in 1 module. FIG. 27 is a schematic sectional view taken along line VV in FIG. 26. FIG. 29 is an enlarged schematic cross-sectional structure diagram of a portion A in FIG. 28. The typical plane pattern block diagram of the B section of FIG. FIG. 31 is a schematic sectional view taken along the line VI-VI in FIG. 30.

  Next, embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, structure, The layout is not specified as follows. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
(Configuration of semiconductor device)
A schematic planar pattern configuration of the power module semiconductor device according to the first embodiment is expressed as shown in FIG. 1, and a schematic cross-sectional structure taken along line II in FIG. 1 is shown in FIG. expressed. 1 to 2, the source pad electrode SP and the gate pad electrode GP of the semiconductor device 100 are arranged on the surface. The structure of the semiconductor device 100 will be described later (FIGS. 17 to 18).

  As shown in FIGS. 1 to 2, the power module semiconductor device according to the first embodiment includes a first semiconductor device Q, a first source pad electrode SP disposed on the first semiconductor device Q, A first insulating film 60 disposed on the periphery of the first source pad electrode SP on the semiconductor device Q and having a thickness larger than that of the first source pad electrode SP, and the first insulating film 60 and the first source pad electrode SP And a first upper surface plate electrode 22 disposed thereon. Here, as shown in FIG. 14 described later, the first semiconductor device Q may be disposed on the first pattern D (K4) of the first copper plate layer 10a disposed on the surface of the ceramic substrate 10. good.

  The first upper surface plate electrode 22 and the first source pad electrode SP may be connected via a first solder layer 80 as shown in FIGS.

  Further, the first insulating film 60 may be formed of a polyimide film. The thickness is preferably 50 μm or more, for example, from the viewpoint that insulation can be easily ensured and the height can be reduced. Alternatively, the first insulating film 60 may be formed of ceramics or a laminate thereof. In this case as well, it is desirable that the thickness is, for example, 50 μm or more, from the standpoint that insulation can be easily secured and a reduction in height can be achieved.

(Comparative example)
On the other hand, a schematic cross-sectional structure of a power module semiconductor device according to the comparative example, as shown in FIG. 3, arranged columnar electrodes 20 ₁ on the source pad electrode SP of the semiconductor devices Q _1, the ceramic substrate 10 and the upper plate electrode by make the distance between 22, thereby avoiding contact with the bonding wire connected to the upper plate electrode 22 and the semiconductor device Q _1.

  Further, a schematic planar pattern configuration of the power module semiconductor device according to the comparative example is expressed as shown in FIG. 4, and a schematic cross-sectional structure taken along line II-II in FIG. 4 is expressed as shown in FIG. The

In the power module semiconductor device according to the comparative example, by using the columnar electrodes 20 _1, by connecting the source pad electrode SP and the upper plate electrode 22 of the semiconductor device Q via a solder layer 3b, the solder flows (protruding) Etc., and the insulation between the upper surface and the side surface / back surface of the semiconductor device is secured.

  In addition, by using a column electrode structure as the wiring structure, it is possible to prevent the solder flow (extrusion) and the like, and the column electrode is simply compared to the structure in which the insulation between the top surface, side surface, and back surface of the semiconductor device is ensured. If the structure is eliminated and the structure in which the upper surface electrode and the upper surface of the semiconductor device are brought into contact with each other is formed, there is a possibility that the insulating property between the upper surface of the semiconductor device and the side surface / back surface may be impaired by the flowing out solder.

(Production method)
A schematic planar pattern configuration for explaining one process of the method for manufacturing the power module semiconductor device according to the first embodiment is expressed as shown in FIG. In FIG. 6, SS and CS represent a source sense pad electrode and a current sense pad electrode.

  Further, a schematic cross-sectional structure (part 1) along the line III-III in FIG. 6 is expressed as shown in FIG.

  A schematic cross-sectional structure (part 2) for explaining one step of the method for manufacturing the power module semiconductor device according to the first embodiment is expressed as shown in FIG.

(A) First, the first insulating film 60 having a thickness (D1 + D2) thicker than the thickness D1 of the first source pad electrode SP around the first source pad electrode SP disposed on the first semiconductor device Q. Form.

(B) Next, a solder layer 80 having a thickness greater than the thickness D2 is disposed on the first source pad electrode SP. That is, the solder layer 80 is arranged so that the upper surface 80a of the solder layer 80 is higher than the upper surface 60a of the first insulating film 60. In this case, as shown in FIG. 6, the solder layer 80 is disposed on the first source pad electrode SP so as to have a gap ΔW between the solder layer 80 and the first insulating film 60. In FIG. 6, the width W2 of the solder layer 80 with respect to the width W1 of the first source pad electrode SP, and W2−W1 = 2ΔW is established.

(C) Next, the first upper surface plate electrode 22 is disposed on the first insulating film 60 and the first source pad electrode SP, and the first upper surface plate electrode 22 and the first source pad electrode SP are interposed via the solder layer 80. And connect. In this case, it is desirable that the gap ΔW in FIGS. 6 to 7 is filled with the molten solder layer 80 without any gap. That is, in FIG. 7, the height of the upper surface 80a of the solder layer 80 is set to be higher than the upper surface 60a of the first insulating film 60, and a portion of the solder layer higher than the upper surface 60a of the first insulating film 60 is set. It is desirable that the volume of 80 is equal to or larger than the volume of the gap portion shown in FIGS. 6 to 7 in that the gap is filled with the molten solder layer 80.

(2 in 1 Module)
In the power module semiconductor device 1 according to the first embodiment, a schematic bird's-eye view configuration of a two-in-one module (2 in 1 Module) is expressed as shown in FIG.

  Further, a schematic bird's-eye view configuration before the resin layer 12 is formed is expressed as shown in FIG.

  As shown in FIGS. 9 and 10, the power module semiconductor device 1 according to the first embodiment includes a positive power input terminal P arranged on the first side of the ceramic substrate 10 covered with the resin layer 12. And the negative power supply input terminal N, the signal terminal group S1, G1, T1 arranged on the second side adjacent to the first side, and the output arranged on the third side facing the first side Terminal O and thermistor connection terminals B1 and B2, and signal terminal groups S2, G2, and T2 disposed on the fourth side opposite to the second side. Here, the signal terminal groups S1, G1, and T1 correspond to the source sense terminal, the gate signal terminal, and the current sense terminal of the semiconductor device Q1 shown in FIG. 16, and the signal terminal groups S2, G2, and T2 are shown in FIG. This corresponds to the source sense terminal, gate signal terminal, and current sense terminal of the semiconductor device Q4. The negative power input terminal N corresponds to the first power input terminal, and the positive power input terminal P corresponds to the second power input terminal.

Further, a schematic planar pattern configuration of the upper surface plate electrodes 22 ₁ and 22 ₄ applied to the power module semiconductor device 1 according to the _first embodiment is expressed as shown in FIG.

Furthermore, a schematic bird's-eye view configuration before forming the upper surface plate electrodes 22 ₁ and 22 ₄ is expressed as shown in FIG.

  Moreover, it is the power module semiconductor device 1 which concerns on 1st Embodiment, Comprising: The typical plane pattern structure of a two-in-one module is represented as shown in FIG. 13, and is typical cross section which follows the IV-IV line of FIG. The structure is represented as shown in FIG.

As shown in FIGS. 10 to 14, the power module semiconductor device 1 according to the first embodiment includes a first semiconductor device Q4, a first source pad electrode SP disposed on the first semiconductor device Q4, A first insulating film 60 (not shown) disposed on the first semiconductor device Q4 and around the first source pad electrode SP and having a thickness greater than that of the first source pad electrode SP, the first insulating film 60, and the first insulating film 60 And a first upper surface plate electrode 22 ₁ disposed on one source pad electrode SP.

The first upper surface plate electrode 22 ₁ and the first source pad electrode SP, are connected via a first solder layer 80.

  The first insulating film 60 can be formed of a polyimide film. The first insulating film 60 can be formed of ceramics or a laminate thereof.

Also includes a first connection electrode 18 _O disposed on the first pattern D (K4), and an output terminal O connected to the first connection electrode 18 _O.

Further, the second pattern EP of the first copper plate layer 10a, the second connection electrode 18 _n disposed on the second pattern EP, and the first power input terminal N connected to the second connection electrode 18 _n are provided. .

The first connection electrode 18 _O may include an extension electrode 25 disposed on the first pattern D (K4). In particular, the first pattern D (K4) portion where the first connection electrode 18 _O is disposed is formed with a narrow width, and thus the resistance value is likely to increase. Since this resistance value is arranged between the drain of the semiconductor device Q4 and the output terminal O, it becomes a parasitic series resistance and a parasitic series inductance connected to the drain of the semiconductor device Q4. By arranging the extension electrode 25 on the first pattern D (K4), such a parasitic series resistance and a parasitic series inductance can be reduced.

  Moreover, you may provide the 1st diode DI4 arrange | positioned adjacent to the 1st semiconductor device Q4 on the 1st pattern D (K4).

The first upper plate electrode 22 ₁ is connected to the anode electrode A4 of the first diode DI4.

  Moreover, you may provide the 2nd semiconductor device Q1 arrange | positioned on the 3rd pattern D (K1) of the 1st copper plate layer 10a.

  In addition, a second diode DI1 disposed adjacent to the second semiconductor device Q1 may be provided on the third pattern D (K1).

In addition, the second source pad electrode SP disposed on the second semiconductor device Q1 and the second source pad electrode SP disposed on the second semiconductor device Q1 and around the second source pad electrode SP are thicker than the second source pad electrode SP. a second insulating film 60 (not shown) having, may be provided with a second upper plate electrode 22 ₄ disposed on the second insulating film 60 and a second source pad electrode on SP.

Here, the second upper plate electrode 22 ₄ and the second source pad electrode SP, are connected via a second solder layer 80.

  The second insulating film 60 can be formed of a polyimide film. Further, it can be formed of ceramics or a laminate thereof.

The second top plate electrode 22 ₄ is connected to the anode electrode A1 of the second diode DI1.

  Since the power module semiconductor device 1 according to the first embodiment can form a thin SiC power module without wiring columns as shown in FIGS. A semiconductor device can be provided.

Further, the first upper surface plate electrode 22 ₄ and the second top plate electrode 22 _1, as shown in FIGS. 10 and 11, may have a L-shaped structure of the curved concave corner portion of the inner in a plan view . It is desirable to have a curved concave L-shaped structure at the inner corner in plan view. This is for avoiding contact with the bonding wire and reducing electrical resistance. In particular, as shown in FIG. 11, the minimum distance between the corner portion and the curved portion of the L-shaped structure is set to W1.

  In addition, a second power input terminal P connected to the third pattern D (K1) is provided.

  Further, a schematic circuit representation of the two-in-one module, which is the power module semiconductor device 1 according to the first embodiment, is expressed as shown in FIG.

  The power module semiconductor device 1 according to the first embodiment includes a two-in-one module configuration. That is, two MOSFETs Q1 and Q4 are built in one module.

  As an example, four chips (MOS transistor × 3, diode × 1) can be mounted on one side of the two-in-one module, and up to three MOSFETs Q1 and Q4 can be connected in parallel. Here, the MOSFETs Q1 and Q4 have a size of about 5 mm × about 5 mm, for example.

Power module semiconductor device 1 according to the first embodiment, as shown in FIGS. 9 to 14, in SiC TPM (Transfer mold Power Module) , the upper plate electrode 22 _1, 22 ₄ and the electrodes of the ceramic substrate 10 A negative power supply input terminal N and an output terminal O that also serve as connection electrodes 18 _O and 18 _n for electrically connecting the pattern (EP · D (K4)) are provided. The negative power input terminal N and output terminal O act as power terminals. The extension electrode 25 may be connected to the connection electrode 18 _O as shown in FIG.

  As shown in FIGS. 9 to 14, the power module semiconductor device 1 according to the first embodiment includes a signal terminal group (G1, S1, T1), (G4, S4, T4) or a positive power supply input terminal P. In a structure in which any one of the negative power supply input terminal N and output terminal O protrudes from all four sides (all side surfaces) of the package module, signal terminal groups (G1, S1, T1), ( G4, S4, T4) are arranged alternately.

  The first signal terminal group (S4, G4, T4) and the second signal terminal group (S1, G1, T1) may have an L-shaped structure as shown in FIGS.

Furthermore, as shown in FIGS. 9 to 14, in a plan view seen from the thickness direction of the ceramic substrate 10, the first upper surface plate electrode 22 ₁ covers directly above the first bonding wire group that has been stretched from the semiconductor device Q4 It is arranged so as not Hisara, second upper plate electrode 22 ₄ are arranged not Hisara cover directly above the second bonding wire group that has been stretched from the semiconductor device Q1.

By forming the signal terminal groups (G1, S1, T1) and (G4, S4, T4) in an L shape, the wiring of the bonding wires from the three-chip MOS transistors is arranged at a short distance and without a cross arrangement. Further, the upper surface plate electrodes 22 ₁ and 22 ₄ can be arranged so as not to cover the bonding wires extending from the chips of the semiconductor devices Q 1 and Q ₄ .

Further, as shown in FIGS. 2, 5 and 6, the semiconductor device Q4, a first diode D4, the first upper surface plate electrode 22 _4, and the first group of signal terminals and (S4 · G4 · T4), the semiconductor device Q1, a second diode D1, a second upper plate electrode 22 ₄ and a second group of signal terminals (S1 · G1 · T1) is a plan view as viewed from the thickness direction of the ceramic substrate 10, symmetrical with respect to the center of the ceramic substrate 10 May be arranged.

In the power module semiconductor device 1 according to the first embodiment, the connection electrodes 18 that electrically connect the upper surface plate electrodes 22 ₁ and 22 ₄ and the electrode pattern (EP · D (K4)) on the ceramic substrate 10. By providing the negative power input terminal N / output terminal O that also serves as _O · 18 _n, the number of members can be reduced, the power module size can be reduced, and the power density of the power module can be improved. be able to. As a result, the manufacturing cost can be reduced.

  Further, in the power module semiconductor device 1 according to the first embodiment, the signal terminal groups (G1, S1, T1), (G4, S4, T4) on the opposite sides are alternately arranged, so that 3 When the power modules are arranged in parallel, such as when building a phase inverter, the signal terminal groups (G1, S1, T1), (G4, S4, T4) do not hit each other, so the power module size can be saved. Can do.

  Techniques such as solder bonding, metal particle bonding, solid phase diffusion bonding, and liquid phase diffusion (TLP: Transient Liquid Phase) bonding can be applied to the formation of the bonding structure of each member.

  For example, the metal particle bonding is formed by baking a paste material containing conductive particles. The firing temperature of the paste material is, for example, about 200 to 400 ° C. The conductive particles are metal fine particles, such as silver particles, gold particles, nickel or copper particles. For example, when silver particles are applied as the metal fine particles, the concentration of the silver particles is, for example, about 80% by mass to about 95% by mass. The average particle size in the case of silver nanoparticles is about 10 nm to about 100 nm.

The output terminal O is connected to the positive power supply input terminal P through the MOSFET Q1, and is connected to the negative power supply input terminal N through the MOSFET Q4. Here, the output terminal O also serves as the connection electrode 18 _O / extension electrode 25, and the negative power supply input terminal N also serves as the connection electrode 18 _n .

  The positive-side power input terminal P does not have a connection electrode structure and is directly connected to the third pattern D (K1). Here, like the negative power input terminal N, the positive power input terminal P may also serve as a connection electrode structure.

As shown in FIG. 14, the output terminal O, the negative power supply input terminal N, the first upper surface plate electrode 22 _1, and the second upper surface plate electrode 22 ₄ can be arranged flush with each other.

  In the power module semiconductor device 1 according to the first embodiment, a schematic rear surface appearance configuration of the two-in-one module is expressed as shown in FIG. The second copper plate layer 10b disposed on the back surface of the ceramic substrate 10 functions as a heat spreader.

  In the power module semiconductor device 1 according to the first embodiment, at least one of the negative power input terminal N, the output terminal O, and the positive power input terminal P may have a bent structure. good.

The first pattern D (K4) of the first copper plate layer 10a is disposed on the surface of the ceramic substrate 10. The semiconductor device Q4 is arranged on the first pattern D (K4). The second copper plate layer 10 b is disposed on the back surface of the ceramic substrate 10. The first source pad electrode SP is disposed on the semiconductor device Q4. The resin layer 12 is formed on the surface of the ceramic substrate 10 with the first copper plate layer 10a, the semiconductor devices Q1 and Q4, the diodes D1 and D4, the upper surface plate electrodes 22 ₁ and 22 ₄ , the source pad electrode SP, and the connection electrode 18 _O. 18 _n , the extension electrode 25 and the like are covered, and the second copper plate layer 10 b is covered on the back surface of the ceramic substrate 10.

  In the power module semiconductor device 1 according to the first embodiment, the semiconductor devices Q1 and Q4 are formed by, for example, SiC MOSFETs, and the diodes D1 and 4 are, for example, SiC Schottky Barrier Diodes (SBD). It is formed with. A thermistor is connected between the thermistor connection terminals B1 and B2 on the ceramic substrate 10, and is used for temperature detection of the power module semiconductor device 1 according to the first embodiment.

For example, the ceramic substrate 10 may be formed of Al ₂ O ₃ , AlN, SiN, AlSiC, or at least a surface of insulating SiC.

  Further, the resin layer 12 may be formed of a transfer mold resin. The resin layer 12 may be formed of an epoxy resin or a silicone resin.

  The plurality of chips of the semiconductor devices Q1 and Q4 are disposed on the surface of the ceramic substrate 10 at positions separated from each other in a plan view when viewed from the thickness direction of the ceramic substrate 10, and are resin-molded by the resin layer 12.

The connection electrodes 18 _O and 18 _n may be formed of an electrode material having a relatively small CTE value, such as CuMo or Cu.

The upper plate electrodes 22 ₁ and 22 ₄ may be formed of an electrode material having a relatively small CTE value, for example, CuMo, Cu, or the like.

  The source pad electrode SP portion may be formed of an electrode material having a relatively small CTE value, for example, CuMo, Cu or the like.

  When materials of the same size having the same value of the coefficient of thermal expansion (CTE) are compared, the generated stress is larger in a material having a larger Young's modulus value. For this reason, a member with a small value of generated stress can be achieved by selecting a material having a smaller value of Young's modulus × CTE.

  CuMo has such advantages. Moreover, although CuMo is inferior to Cu, its electrical resistivity is relatively low.

Here, the separation distance along the surface between the upper surface plate electrodes 22 ₁ 22 ₄ is called a creepage distance. The value of the creepage distance is, for example, about 6 mm.

  As a first means for reducing the size and weight of the power module semiconductor device 1, the chip can be reduced in size by using SiC MOSFET. In the SiC MOSFET, the normalized on-resistance is about 1/10 that of the Si MOSFET. For this reason, when comparing devices having the same on-resistance, the chip area of the SiC MOSFET is about 1/10 of that of the Si MOSFET.

  As a second means for reducing the size and weight of the power module semiconductor device 1, it is possible to reduce the thickness of the ceramic substrate. AlN is generally used as a ceramic substrate, and its bending strength is small. Therefore, it is desirable to use SiN as the ceramic substrate. The merit of SiN is that it has high bending strength and is difficult to break even if it is thin. On the other hand, as a disadvantage, SiN has a lower thermal conductivity than AlN and CTE is higher than AlN. Here, as a specific numerical example, the bending strength of AlN is about 400 GPa, whereas the bending strength of SiN is about 850 GPa. On the other hand, the thermal conductivity of SiN is about 35 W / mK, whereas the thermal conductivity of AlN is about 170 W / mK. Also, the CTE of SiN is about 850 ppm / ° C., whereas the CTE of AlN is about 5.7 ppm / ° C.

(Configuration example of semiconductor device)
As an example of the semiconductor device 100 (Q1 and Q4) applied to the power module semiconductor device 1 according to the first embodiment, a schematic cross-sectional structure of the SiC MOSFET is an n ⁻ high resistance layer as shown in FIG. On the surface of the semiconductor substrate 26 between the p base region 28, the source region 30 formed on the surface of the p base region 28, the p base region 28 formed on the surface side of the semiconductor substrate 26, and the p base region 28. The gate insulating film 32 arranged, the gate electrode 38 arranged on the gate insulating film 32, the source electrode 34 connected to the source region 30 and the p base region 28, and the back surface opposite to the surface of the semiconductor substrate 26 And an n ⁺ drain region 24 disposed on the n ⁺ drain region 24 and a drain pad electrode 36 connected to the n ⁺ drain region 24.

  In FIG. 17, the semiconductor device 100 is composed of a planar gate type n-channel vertical SiC MOSFET, but may be composed of a trench gate type n-channel vertical SiC MOSFET.

  Further, a GaN-based FET or the like can be applied to the semiconductor device 100 (Q1 and Q4) applied to the power module semiconductor device 1 according to the first embodiment instead of the SiC MOSFET.

  For the semiconductor device 100 applied to the power module semiconductor device 1 according to the first embodiment, any one of SiC-based, GaN-based, or AlN-based power devices can be applied.

  Furthermore, the semiconductor device 100 applied to the power module semiconductor device 1 according to the first embodiment can use a semiconductor having a band gap energy of, for example, 1.1 eV to 8 eV.

  18 is an example of the semiconductor device 100 applied to the power module semiconductor device 1 according to the first embodiment, and a schematic cross-sectional structure of the SiC MOSFET including the source pad electrode SP and the gate pad electrode GP is as shown in FIG. It is expressed in The gate pad electrode GP is connected to the gate electrode 38 disposed on the gate insulating film 32, and the source pad electrode SP is connected to the source electrode 34 connected to the source region 30 and the p base region 28.

  Further, the gate pad electrode GP and the source pad electrode SP are disposed on a passivation interlayer insulating film 44 covering the surface of the semiconductor device 100 as shown in FIG. In the semiconductor substrate 26 below the gate pad electrode GP and the source pad electrode SP, although not shown in the configuration example of FIG. 16, as in the central portion of FIG. 17 or FIG. A transistor structure having a structure may be formed.

  Further, as shown in FIG. 18, the source pad electrode SP may be extended and disposed on the passivation interlayer insulating film 44 also in the transistor structure at the center.

(Application examples using semiconductor devices)
Next, a three-phase AC inverter configured using the power module semiconductor device 1 according to the first embodiment will be described with reference to FIG.

  As shown in FIG. 19, the three-phase AC inverter includes a gate drive unit 50, a power module unit 52 connected to the gate drive unit 50, and a three-phase AC motor unit 54. The power module unit 52 is connected to U-phase, V-phase, and W-phase inverters corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 54. Here, although the gate drive unit 50 is connected to the SiC MOSFETs Q1 and Q4 in FIG. 19, it is also connected to the SiC MOSFETs Q2 and Q5, and Q3 and Q6, though not shown.

  The power module 52 includes inverter-structured SiC MOSFETs Q1 and Q4, Q2 and Q5, and Q3 and Q3 between the plus terminal (+) and the minus terminal (−) to which the converter 48 to which the storage battery (E) 46 is connected is connected. Q6 is connected. Further, diodes D1 to D6 are connected in antiparallel between the sources and drains of the SiC MOSFETs Q1 to Q6, respectively.

  In the power module semiconductor device 1 according to the first embodiment, the structure of the single-phase inverter corresponding to the U-phase portion in FIG. 19 has been described. Thus, the three-phase power module portion 52 can be formed.

  In the power module semiconductor device 1 according to the first embodiment, the first signal terminal group (G4, S4, T4) and the second signal terminal group (G1, S1, T1) are bent in the thickness direction of the ceramic substrate 10. May be provided.

  In the power module semiconductor device 1 according to the first embodiment, a plurality of power module semiconductor devices may be arranged in parallel.

  A schematic planar configuration in which three power module semiconductor devices 1 according to the first embodiment are arranged in parallel to drive a three-phase AC inverter is expressed as shown in FIG.

Further, in the power module semiconductor device 1 according to the first embodiment, a schematic bird's-eye view configuration in which the signal terminal is bent is expressed as shown in FIG. Further, a schematic circuit configuration in which three power module semiconductor devices 1 according to the first embodiment are arranged in parallel and the three-phase AC inverter is driven is expressed as shown in FIG. 20 to 22, the thermistor connection terminals B1 and B2 are not shown.

  In the power module semiconductor device 1 according to the first embodiment, the signal terminals (G1, S1, T1), (G4, S4, T4) or the positive power input terminal P, the negative power input terminal N, and the output terminal In the structure in which any one of O protrudes from all four sides (all side surfaces) of the package module, signal terminals (G1, S1, T1, and G4, S4, and T4) on opposite sides are alternately arranged. Therefore, as shown in FIG. 20, the occupied area when the power module semiconductor devices 1 are arranged in parallel can be reduced. Further, as shown in FIG. 21, the power module semiconductor device 1 is arranged in parallel as shown in FIGS. 20 and 22 by bending the signal terminals (G1, S1, T1), (G4, S4, T4). The area occupied by the field can be reduced. For this reason, space saving and size reduction of the whole apparatus can be achieved.

  According to the first embodiment, it is possible to provide a power module semiconductor device capable of reducing the wiring pillar of the two-in-one thin SiC power module, reducing the size, and reducing the weight.

[Second Embodiment]
(One in one module: 1 in 1 Module)
In the power module semiconductor device 2 according to the second embodiment, a schematic circuit representation of a one-in-one module (1 in 1 Module) is expressed as shown in FIG. Further, in the power module semiconductor device 2 according to the second embodiment, the detailed circuit expression of the one-in-one module is expressed as shown in FIG.

  The power module semiconductor device 2 according to the second embodiment has a one-in-one module configuration. That is, one MOSFET Q is built in one module. As an example, six chips (MOS transistors × 6) can be mounted, and up to six MOSFETs Q can be connected in parallel. A part of the six chips can be mounted for the diode DI.

  FIG. 23 shows a diode DI connected in reverse parallel to the MOSFETQ. The main electrode of MOSFETQ is represented by a drain terminal DT and a source terminal ST.

  More specifically, as shown in FIG. 24, a sensing MOSFET Qs is connected in parallel to the MOSFET Q. The sense MOSFET Qs is formed as a fine transistor in the same chip as the MOSFET Q. In the first embodiment, the sensing MOSFETs Qs are formed as fine transistors in the same chip in the semiconductor devices Q1 and Q4.

  As shown in FIG. 25, the power module semiconductor device 2 according to the second embodiment includes a drain terminal DT and a source terminal ST arranged on the first side of the ceramic substrate 10 covered with the resin layer 12, Signal terminals SS, G, and CS arranged on opposite sides are provided on the first side. Here, the signal terminals SS, G, and CS are connected to the source sense terminal, the gate signal terminal, and the current sense terminal of the semiconductor device Q. In addition, although illustration is abbreviate | omitted, you may further provide the thermistor connection terminal B1 * B2. Here, the source terminal ST corresponds to a first power input terminal, and the drain terminal DT corresponds to a second power input terminal.

  Moreover, it is the power module semiconductor device 2 which concerns on 2nd Embodiment, Comprising: The typical plane pattern structure of a one-in-one module is represented as shown in FIG. 26, and is typical which follows the VV line of FIG. The cross-sectional structure is expressed as shown in FIG.

  Moreover, it is the power module semiconductor device 2 which concerns on 2nd Embodiment, Comprising: The typical back surface external appearance structure of a one-in-one module is represented as shown in FIG. The second copper plate layer 10b disposed on the back surface of the ceramic substrate 10 functions as a heat spreader.

  An enlarged schematic cross-sectional structure of portion A in FIG. 28 is expressed as shown in FIG. 29 is represented as shown in FIG. 30, and a schematic sectional structure taken along line VI-VI in FIG. 30 is represented as shown in FIG.

  As shown in FIGS. 26 to 31, the power module semiconductor device 2 according to the second embodiment includes a first semiconductor device Q (100) and a first source pad electrode disposed on the first semiconductor device Q. SP and SP, a first insulating film 60 disposed on the first semiconductor device Q and around the first source pad electrodes SP and SP, and having a thickness greater than that of the first source pad electrodes SP and SP; And a first upper surface plate electrode 22 disposed on the insulating film 60 and the first source pad electrode SP. Here, the first semiconductor device Q (100) may be disposed on the first pattern D of the first copper plate layer 10a disposed on the surface of the ceramic substrate 10, as shown in FIG.

  Further, the first upper surface plate electrode 22 and the first source pad electrode SP may be connected via a first solder layer 80 as shown in FIG.

  Further, the first insulating film 60 may be formed of a polyimide film. The thickness is preferably 50 μm or more, for example, from the viewpoint that insulation can be easily ensured and the height can be reduced. Alternatively, the first insulating film 60 may be formed of ceramics or a laminate thereof. In this case as well, it is desirable that the thickness is, for example, 50 μm or more, from the standpoint that insulation can be easily secured and a reduction in height can be achieved.

  As shown in FIGS. 25 to 31, the power module semiconductor device 2 according to the second embodiment can form a thin SiC power module without wiring pillars, and thus can be reduced in size and weight. A semiconductor device can be provided.

  In the power module semiconductor device 2 according to the second embodiment, as shown in FIG. 26, the semiconductor devices Q are arranged in three rows in two rows at the center of the ceramic substrate 10. Further, two signal terminal groups (GSP / CSP / SSP) are arranged in an L-shaped structure in the peripheral portion of the ceramic substrate 10. As shown in FIG. 26, the two signal terminal groups (GSP, CSP, SSP) are connected in common to each other, and are connected to the source sense terminal, gate signal terminal, and current sense terminal of the semiconductor device Q.

  The GP terminal, SP terminal, and CS terminal of each chip are connected by bonding wires toward the L-shaped signal terminal group (GSP, CSP, SSP) disposed in the peripheral portion.

  Further, as shown in FIG. 26, the top plate electrodes 22 and 22S are arranged so as not to cover the bonding wire group extending from the semiconductor device Q in a plan view as seen from the thickness direction of the ceramic substrate 10. Has been.

  By forming the signal terminal group (GSP, CSP, SSP) in an L shape, it becomes possible to arrange the wiring of the bonding wire from the three-chip MOS transistor at a short distance and without a cross arrangement. The electrodes 22 and 22S can be arranged so as not to cover the bonding wires extending from the chip of the semiconductor device Q.

As shown in FIGS. 25 to 31, the power module semiconductor device 2 according to the second embodiment is a connection that electrically connects the upper surface plate electrode 22 and the electrode pattern EP on the ceramic substrate 10 in the SiC TPM. A negative power supply input terminal N that also serves as an electrode 18 _n (not shown) is provided. The drain terminal DT also serves as a connection electrode 18 _p (not shown) that electrically connects the drain terminal DT and the electrode pattern D on the ceramic substrate 10. The source terminal ST / drain terminal DT functions as a power terminal.

In the power module semiconductor device 2 according to the second embodiment, the source terminal ST that also serves as the connection electrode 18 _n that electrically connects the upper surface plate electrode 22 and the electrode pattern EP on the ceramic substrate 10; By providing the drain terminal DT that also serves as the connection electrode 18 _p that electrically connects the drain terminal DT and the electrode pattern D on the ceramic substrate 10, the number of members can be reduced, and the size of the power module can be reduced. The power density of the power module can be improved by reducing the size. As a result, the manufacturing cost can be reduced.

  In the power module semiconductor device 2 according to the second embodiment, the number of constituent members is reduced, and as a result, the number of chips can be increased.

  Techniques such as solder bonding, metal particle bonding, solid phase diffusion bonding, and liquid phase diffusion bonding can be applied to the formation of the bonding structure of each member.

  Although not shown here, the first diode DI may be provided on the first pattern D so as to be adjacent to the semiconductor device Q. Further, in some cases, diodes DI may be arranged on all the chips on the first pattern D.

  Moreover, you may provide the upper surface board electrode 22 * 22S arrange | positioned on source pad electrode SP * SP.

  Although not shown, the upper plate electrode 22 may be provided on the source pad electrodes SP and SP and connected to the anode electrode A of the diode DI.

  As shown in FIG. 26, the upper surface plate electrodes 22 and 22S desirably have a curved concave L-shaped structure at an inner corner in a plan view. This is to reduce electrical resistance.

  Also in the power module semiconductor device 2 according to the second embodiment, the semiconductor device Q is formed of, for example, a SiC MOSFET, and the diode DI is formed of, for example, a SiC Schottky barrier diode (SBD). A thermistor is connected between the thermistor connection terminals B1 and B2 on the ceramic substrate 10, and is used for temperature detection of the power module semiconductor device 2 according to the second embodiment.

  Other configurations are the same as those of the power module semiconductor device 1 according to the first embodiment, and thus redundant description is omitted.

  As an example of the semiconductor device 100 (Q) applied to the power module semiconductor device 2 according to the second embodiment, a schematic cross-sectional structure of a SiC MOSFET is expressed in the same manner as in FIG. In FIG. 17, the semiconductor device 100 is composed of a planar gate type n-channel vertical SiC MOSFET, but may be composed of a trench gate type n-channel vertical SiC MOSFET.

  In addition, a GaN-based FET or the like can be applied to the semiconductor device 100 (Q) applied to the power module semiconductor device 2 according to the second embodiment instead of the SiC MOSFET.

  As the semiconductor device 100 applied to the power module semiconductor device 2 according to the second embodiment, any one of SiC-based, GaN-based, and AlN-based power devices can be applied.

  18 is an example of the semiconductor device 100 applied to the power module semiconductor device 2 according to the second embodiment, and the schematic cross-sectional structure of the SiC MOSFET including the source pad electrode SP and the gate pad electrode GP is the same as that in FIG. expressed.

  According to the second embodiment, it is possible to provide a power module semiconductor device that can reduce the wiring pillar of the one-in-one thin SiC power module, and can be reduced in size and weight.

  As described above, according to the present invention, it is possible to provide a power module semiconductor device capable of reducing the wiring pillar of a thin SiC power module, reducing the size, and reducing the weight.

[Other embodiments]
As described above, the first and second embodiments have been described. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are exemplary and limit the present invention. Absent. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present invention includes various embodiments not described herein.

  The power module semiconductor device of the present invention can be used for all power devices such as SiC power semiconductor modules and intelligent power modules, and particularly in fields where miniaturization and weight reduction are required, in-vehicle / solar cells / industrial equipment / consumer equipment. It can be applied to a wide range of application fields such as inverters and converters.

1,2 ... power module semiconductor device 3b, 80 ... solder layer 10 ... ceramic substrate 10a, 10b ... copper plate layer 12 ... resin layer _{18 O, 18 p, 18 n} ... connection electrodes 22,22 _1, 22 _4, 22S ... Top plate electrode 24 ... n ⁺ drain region 25 ... extension electrode 26 ... semiconductor substrate 28 ... p base region 30 ... source region 32 ... gate insulating film 34 ... source electrode 36 ... drain electrode 38 ... gate electrode 44 ... interlayer insulating film 46 ... Storage battery (E)
48 ... Converter 50 ... Gate drive unit 52 ... Power module unit 54 ... Three-phase motor unit 60 ... Insulating film 100, Q, Q1-Q6 ... Semiconductor device (SiC MOSFET, semiconductor chip)
D1 to D6, DI ... Diode GP ... Gate pad electrode SP ... Source pad electrode P ... Positive power supply input terminal (second power supply input terminal)
N ... Negative power input terminal (first power input terminal)
DT: Drain terminal (second power supply input terminal)
ST: Source terminal (first power input terminal)
O, U, V, W ... Output terminals G, G1, G4 ... Gate signal terminals SS, S1, S4 ... Source sense terminals CS, T1, T4 ... Current sense terminals B1, B2 ... Thermistor connection terminals A1, A4 ... Anode electrodes K1, K4 ... Cathode electrodes D, D (K1), D (K4) ... Drain electrode pattern EP ... Ground pattern SSP, CSP, GSP ... Signal terminal group

Claims (27)

A ceramic substrate;
A first pattern of a first copper plate layer disposed on a surface of the ceramic substrate;
A first semiconductor device disposed on the first pattern;
A first source pad electrode disposed on the first semiconductor device;
A first insulating film disposed on the first semiconductor device and around the first source pad electrode and having a thickness greater than that of the first source pad electrode;
A power module semiconductor device comprising: a first upper surface plate electrode disposed on the first insulating film and the first source pad electrode.   2. The power module semiconductor device according to claim 1, wherein the first upper surface plate electrode and the first source pad electrode are connected via a first solder layer.   The power module semiconductor device according to claim 1, wherein the first insulating film is formed of a polyimide film.   The power module semiconductor device according to claim 1, wherein the first insulating film is formed of ceramics or a laminate thereof. A first connection electrode disposed on the first pattern;
The power module semiconductor device according to claim 1, further comprising: an output terminal connected to the first connection electrode. A second pattern of the first copper plate layer;
A second connection electrode disposed on the second pattern;
The power module semiconductor device according to claim 1, further comprising: a first power input terminal connected to the second connection electrode.   The power module semiconductor device according to claim 1, wherein the first connection electrode includes an extension electrode disposed on the first pattern.   The power module semiconductor device according to claim 1, further comprising a first diode disposed adjacent to the first semiconductor device on the first pattern.   The power module semiconductor device according to claim 8, wherein the first upper surface plate electrode is connected to an anode electrode of the first diode.   The power module semiconductor device according to claim 1, further comprising a second semiconductor device disposed on the third pattern of the first copper plate layer.   11. The power module semiconductor device according to claim 10, further comprising: a second diode disposed adjacent to the second semiconductor device on the third pattern. A second source pad electrode disposed on the second semiconductor device;
A second insulating film disposed around the second source pad electrode on the second semiconductor device and having a thickness greater than that of the second source pad electrode;
The power module semiconductor device according to claim 10, further comprising: a second upper surface plate electrode disposed on the second insulating film and the second source pad electrode.   The power module semiconductor device according to claim 12, wherein the second upper surface plate electrode and the second source pad electrode are connected via a second solder layer.   The power module semiconductor device according to claim 12, wherein the second insulating film is formed of a polyimide film.   The power module semiconductor device according to claim 12, wherein the second insulating film is formed of ceramics or a laminate thereof.   The power module semiconductor device according to claim 12, wherein the second upper surface plate electrode is connected to an anode electrode of the second diode.   17. The power module semiconductor device according to claim 9, wherein the first upper surface plate electrode and the second upper surface plate electrode have an L-shaped structure having a curved concave shape at an inner corner in a plan view.   The power module semiconductor device according to claim 11, further comprising a second power supply input terminal connected to the third pattern. A first signal terminal group disposed on a first side of the ceramic substrate and connected to the first semiconductor device via a first bonding wire group;
A second signal terminal group disposed on a second side opposite to the first side of the ceramic substrate and connected to the second semiconductor device via a second bonding wire group; and the first signal terminal group, The power module semiconductor device according to claim 12, wherein the second signal terminal groups are arranged alternately.   The power module semiconductor device according to claim 19, wherein the first signal terminal group and the second signal terminal group have an L-shaped structure.   In a plan view as viewed from the thickness direction of the ceramic substrate, the first upper surface plate electrode is disposed so as not to cover the first bonding wire group extending from the first semiconductor device, and 21. The power module semiconductor device according to claim 19, wherein the two upper surface plate electrodes are disposed so as not to cover the second bonding wire group extending from the second semiconductor device. .   The first semiconductor device, the first diode, the first upper surface plate electrode, and the first signal terminal group, and the second semiconductor device, the second diode, the second upper surface plate electrode, and the second signal terminal group. The power module semiconductor device according to claim 21, wherein the power module semiconductor device is disposed point-symmetrically with respect to a center of the ceramic substrate in a plan view as viewed from a thickness direction of the ceramic substrate. The ceramic _{substrate, Al 2 O 3, AlN,} SiN, AlSiC, or at least the surface of the power module semiconductor device according to any one of claims 1 to 22, characterized in that SiC insulating.   The power module semiconductor device according to any one of claims 1 to 23, wherein the first source pad electrode and the second source pad electrode are CuMo or Cu.   The power module semiconductor device according to any one of claims 1 to 24, wherein the first upper surface plate electrode and the second upper surface plate electrode are CuMo or Cu.   The power module semiconductor device according to any one of claims 1 to 25, wherein the power module semiconductor device is covered with a transfer mold resin.   27. The power module semiconductor device according to any one of claims 1 to 26, wherein the semiconductor device is any one of a SiC-based power device, a GaN-based power device, and an AlN-based power device.

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