JP2018152503A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2018152503A
JP2018152503A JP2017048797A JP2017048797A JP2018152503A JP 2018152503 A JP2018152503 A JP 2018152503A JP 2017048797 A JP2017048797 A JP 2017048797A JP 2017048797 A JP2017048797 A JP 2017048797A JP 2018152503 A JP2018152503 A JP 2018152503A
Authority
JP
Japan
Prior art keywords
die pad
internal terminal
semiconductor device
terminal
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017048797A
Other languages
Japanese (ja)
Other versions
JP6821258B2 (en
Inventor
麻美 伊藤
Asami Itou
麻美 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Ablic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ablic Inc filed Critical Ablic Inc
Priority to JP2017048797A priority Critical patent/JP6821258B2/en
Publication of JP2018152503A publication Critical patent/JP2018152503A/en
Application granted granted Critical
Publication of JP6821258B2 publication Critical patent/JP6821258B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which there is no separation of an external terminal even when the semiconductor device is downsized and reduced in thickness and a resin encapsulated body has strong mechanical strength.SOLUTION: A semiconductor device comprises: a die pad 2 on which a semiconductor element 4 is mounted and which has die pad top edge tapered parts 2b on a top edge; external terminals 3 which are provided at a distance from the die pad; and internal terminals 3a each of which is upset from each external terminal and has an internal terminal bottom edge tapered part 3b on a bottom edge, in which the internal terminal bottom edge tapered part 3b and the die pad top edge tapered part 2b are parallel to each other.SELECTED DRAWING: Figure 1

Description

本発明は、樹脂封止したリードレスタイプの半導体装置に関する。   The present invention relates to a resin-sealed leadless type semiconductor device.

近年、スマートフォン、タブレットパソコン、腕時計型のウエアラブル端末などの著しい普及により、これらの機器に搭載される半導体装置について小型、薄型、低コストが求められている。その中でもリードレスタイプの小型、薄型の半導体装置の需要が高まってきており、薄型化のために半導体パッケージ総厚の削減だけではなく、半導体装置の製造に使用されるリードフレーム自体の厚さまでも薄くする傾向がある。そして、さらなる薄型化のために、薄い金属板に金属パターンを析出形成してこれをリードフレーム代わりとする基板なども使用されるようになってきている。   In recent years, with the remarkable spread of smartphones, tablet PCs, wristwatch-type wearable terminals, and the like, small, thin, and low cost semiconductor devices are required for these devices. Among them, the demand for leadless type small and thin semiconductor devices is increasing, and not only reducing the total thickness of the semiconductor package for thinning, but also the thickness of the lead frame itself used for manufacturing semiconductor devices. There is a tendency to make it thinner. In order to further reduce the thickness, a substrate that uses a metal pattern deposited on a thin metal plate as a substitute for a lead frame has been used.

特許文献１には、半導体装置の薄型化を実現するために薄い金属板上にフォトレジスト層を形成し、露出した金属面にメッキ法にて金属パターンを形成する技術を用いた半導体装置が開示されている。図５に示すように、この半導体装置は半導体素子１０４を搭載するダイパッド１０２および外部電極（以後、外部端子と呼ぶ）１０３の周縁部に複数の凹部を有し、これによって、樹脂の食付き効果を増加させ、樹脂体１０６と外部電極との結合強度の向上を図る構造となっている。   Patent Document 1 discloses a semiconductor device using a technique in which a photoresist layer is formed on a thin metal plate and a metal pattern is formed on an exposed metal surface by a plating method in order to reduce the thickness of the semiconductor device. Has been. As shown in FIG. 5, this semiconductor device has a plurality of recesses in the peripheral portion of the die pad 102 on which the semiconductor element 104 is mounted and the external electrode 103 (hereinafter referred to as an external terminal), whereby the resin biting effect is obtained. This increases the bonding strength of the resin body 106 and the external electrode.

特開２０１０−８０６５６号公報JP 2010-80656 A

特許文献１に記載の半導体装置では、凹部を大きく（深く）すること、すなわち、フランジ部の張り出しを大きく（長く）することで樹脂の食付きが良くなるが、フランジ部の張り出しが大きくなるとダイパッドと外部端子との距離が短くなり、凹部に樹脂が入り込みにくく、ダイパッドと外部端子間に充填された樹脂の機械的強度が弱くなる。これは樹脂中に含まれる応力緩和剤であるフィラーが近接したダイパッドと外部端子の間に凝集し、樹脂の流動を阻害することに起因する。   In the semiconductor device described in Patent Document 1, the biting of the resin is improved by enlarging the recess (ie, deepening), that is, by enlarging (extending) the overhang of the flange, but the die pad increases when the overhang of the flange increases. And the distance between the external terminal and the external terminal is reduced, the resin is less likely to enter the recess, and the mechanical strength of the resin filled between the die pad and the external terminal is reduced. This is due to the fact that the filler, which is a stress relaxation agent, contained in the resin aggregates between the adjacent die pad and the external terminal and inhibits the flow of the resin.

本発明は、かかる事情に鑑みてなされたもので、小型化、薄型化されても外部端子の脱落が起こりにくい、樹脂封止体の機械的強度が大きい半導体装置を提供することを目的としている。   The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device having a resin-sealed body with high mechanical strength in which external terminals are unlikely to fall off even when the size and thickness are reduced. .

本発明では上記課題解決のために以下の手段を用いた。   In the present invention, the following means are used to solve the above problems.

ダイパッドと、
前記ダイパッド上に載置された半導体素子と、
前記ダイパッドの周囲に離間して配置された外部端子と、
前記外部端子から屈曲部を経てアップセットされ、前記ダイパッド方向に延出された内部端子と、
前記ダイパッドと前記半導体素子と前記内部端子とを封止している封止体と、
前記内部端子の前記ダイパッド方向の下端に設けられた内部端子下端テーパ部と、
前記ダイパッドの上端部の周囲であって、前記内部端子と向き合う位置に設けられたダイパッド上端テーパ部と、
を備え、
前記ダイパッドおよび前記外部端子の裏面が前記封止体から露出しており、
前記内部端子下端テーパ部と前記ダイパッド上端テーパ部は互いに平行であることを特徴とする半導体装置とした。 Die pad,
A semiconductor element mounted on the die pad;
External terminals spaced apart around the die pad;
An internal terminal that is upset from the external terminal via a bent portion and extends in the die pad direction;
A sealing body sealing the die pad, the semiconductor element, and the internal terminal;
An internal terminal lower end tapered portion provided at the lower end of the internal terminal in the die pad direction;
A die pad upper end tapered portion provided around the upper end portion of the die pad and at a position facing the internal terminal;
With
The back surface of the die pad and the external terminal is exposed from the sealing body,
The internal terminal lower end taper portion and the die pad upper end taper portion are parallel to each other.

上記手段を用いることで、小型化、薄型化されても外部端子の脱落起こりにくい、樹脂封止体の機械的強度が大きい半導体装置とすることができる。   By using the above means, it is possible to obtain a semiconductor device in which the external terminal is not easily dropped even when the size is reduced and the thickness is reduced, and the mechanical strength of the resin sealing body is high.

本発明の第一の実施形態に係る半導体装置の断面図及び部分拡大図である。1 is a cross-sectional view and a partially enlarged view of a semiconductor device according to a first embodiment of the present invention. 本発明の第二の実施形態に係る半導体装置の端子部詳細図である。It is a terminal part detail drawing of the semiconductor device which concerns on 2nd embodiment of this invention. 本発明の第二の実施形態に係る半導体装置の端子部の上面図である。It is a top view of the terminal part of the semiconductor device which concerns on 2nd embodiment of this invention. 本発明の第三の実施形態に係る半導体装置の端子部詳細図である。It is a terminal part detail drawing of the semiconductor device which concerns on 3rd embodiment of this invention. 従来の半導体装置の断面図である。It is sectional drawing of the conventional semiconductor device.

以下、本発明の半導体装置を図面に基づいて説明する。
図１は、本発明の第一の実施形態に係る半導体装置の断面図及び部分拡大図である。図１（ａ）は、半導体装置１の全体断面図を図示している。ダイパッド２の上には半導体素子４が載置され、そして、ダイパッド２の周囲にはダイパッド２と離間して外部端子３が配置されている。また、外部端子３から屈曲部を経てアップセットされ、ダイパッド方向へ延出された内部端子３ａが設けられている。内部端子３ａの上面と半導体素子４はワイヤ５によって電気的に接続され、半導体素子４とワイヤ５と内部端子３ａはフィラー含有樹脂からなる封止体６によって被覆されている。ダイパッド２および外部端子３の裏面は封止体６から露出して実装基板との接続ができるようになっている。 Hereinafter, a semiconductor device of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view and a partially enlarged view of a semiconductor device according to a first embodiment of the present invention. FIG. 1A shows an overall cross-sectional view of the semiconductor device 1. A semiconductor element 4 is placed on the die pad 2, and an external terminal 3 is disposed around the die pad 2 so as to be separated from the die pad 2. Further, an internal terminal 3a is provided which is upset from the external terminal 3 through a bent portion and extends in the die pad direction. The upper surface of the internal terminal 3a and the semiconductor element 4 are electrically connected by a wire 5, and the semiconductor element 4, the wire 5, and the internal terminal 3a are covered with a sealing body 6 made of a filler-containing resin. The back surfaces of the die pad 2 and the external terminal 3 are exposed from the sealing body 6 and can be connected to the mounting substrate.

本図において点線丸囲いしたダイパッド・端子間領域Ａの拡大図を図１（ｂ）に示した。アップセットされた内部端子３ａの下には外部端子３の厚みよりも高さのある内部端子下方領域Ｂが形成され、樹脂中の応力緩和剤であるフィラーが入り込むのに十分な高さが設けられている。   FIG. 1B shows an enlarged view of the die pad-terminal area A surrounded by a dotted line in FIG. An internal terminal lower region B that is higher than the thickness of the external terminal 3 is formed under the upset internal terminal 3a, and is provided with a height that is sufficient to allow a filler that is a stress relaxation agent in the resin to enter. It has been.

なお、ここでの内部端子下方領域Ｂの高さとは外部端子の厚み方向における長さを示すものであり、この内部端子下方領域Ｂの高さに鑑みてフィラーの粒度分布を決める必要がある。両者は、以下の関係にあることが望ましい。
フィラーの最大粒径＜内部端子下方領域の高さ In addition, the height of the internal terminal lower area | region B here shows the length in the thickness direction of an external terminal, It is necessary to determine the particle size distribution of a filler in view of the height of this internal terminal lower area B. It is desirable that the two have the following relationship.
Maximum particle size of filler <height of inner terminal lower area

ダイパッドと対向する内部端子３ａの下端部には概ね平面を成す内部端子下端テーパ部３ｂが設けられ、樹脂封止時に内部端子下方領域Ｂに応力緩和剤であるフィラーや溶融した樹脂が入り込みやすい形状となっている。また、ダイパッド２の上端部の周囲にも、内部端子３ａと向き合う位置においては、概ね平面を成すダイパッド上端テーパ部２ｂが設けられ、該領域にフィラーや溶融した樹脂が入り込むことを助ける形状となっている。   The lower end portion of the internal terminal 3a facing the die pad is provided with a substantially flat internal terminal lower end taper portion 3b so that a filler or a melted resin can easily enter the lower region B of the internal terminal during resin sealing. It has become. In addition, a die pad upper end taper portion 2b having a substantially flat surface is also provided around the upper end portion of the die pad 2 at a position facing the internal terminal 3a, and is shaped to help the filler or molten resin enter the region. ing.

ダイパッドの厚みは外部端子の厚みと同じで内部端子下方領域Ｂよりも薄くなっており、さらに内部端子下端テーパ部３ｂとダイパッド上端テーパ部２ｂは互いに平行に形成されることでフィラーが含有された樹脂の流動がスムーズになる。ここで、互いに平行な内部端子下端テーパ部３ｂとダイパッド上端テーパ部２ｂとの間の距離は内部端子下方領域Ｂの高さよりも大きいことが望ましい。   The thickness of the die pad is the same as the thickness of the external terminal and is thinner than the lower region B of the internal terminal, and the internal terminal lower end taper portion 3b and the die pad upper end taper portion 2b are formed in parallel to each other to contain the filler. Smooth resin flow. Here, it is desirable that the distance between the internal terminal lower end taper portion 3b and the die pad upper end taper portion 2b which are parallel to each other is larger than the height of the internal terminal lower region B.

特許文献１に記載の半導体装置では、端子脱落を防止するためにフランジ部の張り出しを大きくしているが、これによりダイパッドと端子との間が狭くなり、そこに樹脂内のフィラーが凝集して樹脂の流入を阻害する可能性があった。   In the semiconductor device described in Patent Document 1, the flange portion is extended to prevent the terminal from falling off, but this narrows the space between the die pad and the terminal, and the filler in the resin aggregates there. There was a possibility of inhibiting the inflow of resin.

本発明の半導体装置１ではダイパッド２と内部端子３ａを異なる高さに配置し、ダイパッド２の上面を内部端子３ａの下面よりも低くし、さらに、ダイパッド２の上端面および内部端子の下端面にテーパ部２ｂ、３ｂを設けることでフィラー含有樹脂がダイパッド２外部端子３との間にスムーズに流入することを可能にした。   In the semiconductor device 1 of the present invention, the die pad 2 and the internal terminal 3a are arranged at different heights, the upper surface of the die pad 2 is made lower than the lower surface of the internal terminal 3a, and further on the upper end surface of the die pad 2 and the lower end surface of the internal terminal. By providing the taper portions 2b and 3b, the filler-containing resin can flow smoothly between the die pad 2 and the external terminals 3.

また、内部端子３ａ下の外部端子３横の領域Ｂの高さをフィラーの最大粒径よりも大きくすることで、外部端子と応力緩和効果を有するフィラーが分散されている封止体６との密着が良好になるため外部端子近傍における樹脂クラックを抑制でき、外部端子３の脱落防止が可能となる。   Moreover, by making the height of the region B beside the external terminal 3 below the internal terminal 3a larger than the maximum particle size of the filler, the sealing body 6 in which the external terminal and the filler having a stress relaxation effect are dispersed is used. Since adhesion becomes good, resin cracks in the vicinity of the external terminals can be suppressed, and the external terminals 3 can be prevented from falling off.

また、特許文献１に記載の半導体装置ではフランジ部の張り出し形成にメッキ法を利用しているが、この張り出しを大きくするためにはメッキ時間を長くする必要があり、製造コストが問題となるが、本発明の半導体装置の製造では内部端子下端テーパ部３ｂとダイパッド上端テーパ部２ｂは外部端子３や内部端子３ａ、そしてダイパッド２をプレス形成するときに同時にプレス加工することで形成できるので生産性が高く、本発明の半導体装置の製造に用いられるリードフレームの製造コストが上昇するという懸念はなく、従来の金属析出法並びエッチング法での製造方法よりも安価にすることができる。   Further, in the semiconductor device described in Patent Document 1, a plating method is used for forming the flange portion overhang. However, in order to increase the overhang, it is necessary to lengthen the plating time, and the manufacturing cost becomes a problem. In the manufacture of the semiconductor device of the present invention, the internal terminal lower end taper portion 3b and the die pad upper end taper portion 2b can be formed by pressing the external terminal 3, the internal terminal 3a, and the die pad 2 at the same time when they are press formed. Therefore, there is no concern that the manufacturing cost of the lead frame used for manufacturing the semiconductor device of the present invention will increase, and it can be made cheaper than the conventional metal deposition method and etching method.

図２は、本発明の第二の実施形態に係る半導体装置の端子部詳細図である。図２（ｂ）は外部端子および内部端子の側面図であり、これを左方から見た模式図を図２（ａ）に示した。図１（ａ）に示した第一の実施形態との違いは、図２（ａ）に示すように断面が四角形の内部端子３ａの下部に断面が逆台形となる傾斜凸部３ｄが下方の領域に向かって設けられている点である。   FIG. 2 is a detailed view of a terminal portion of the semiconductor device according to the second embodiment of the present invention. FIG. 2B is a side view of the external terminal and the internal terminal. FIG. 2A shows a schematic view of the external terminal viewed from the left side. The difference from the first embodiment shown in FIG. 1 (a) is that, as shown in FIG. 2 (a), an inclined convex portion 3d having a reverse trapezoidal cross section is formed below the internal terminal 3a having a square cross section. It is a point provided toward the region.

傾斜凸部３ｄは二つの傾斜面３ｈを有し、これらが交わる部分に端子下面平坦部３ｇが設けられた平頭形状の傾斜凸部３ｄである。図２（ｂ）では傾斜凸部３ｄがアップセットされた内部端子３ａの端部から屈曲部３ｅ、そして、外部端子３の一部に及んで形成されていることが理解できる。さらに、第一の実施形態同様、内部端子３ａの端部の傾斜凸部３ｄには内部端子下端テーパ部３ｂが形成されている。   The inclined convex portion 3d is a flat-headed inclined convex portion 3d having two inclined surfaces 3h and provided with a terminal lower surface flat portion 3g at a portion where they intersect. In FIG. 2B, it can be understood that the inclined convex portion 3 d is formed from the end portion of the internal terminal 3 a upset to the bent portion 3 e and a part of the external terminal 3. Furthermore, the internal terminal lower end taper part 3b is formed in the inclination convex part 3d of the edge part of the internal terminal 3a like 1st embodiment.

図３は本発明の第二の実施形態に係る半導体装置の端子部の上面図である。樹脂封止工程におけるフィラー含有樹脂の流動を模式化している。フィラー含有樹脂は図の左方から内部端子３ａの下方に流れ込む。   FIG. 3 is a top view of the terminal portion of the semiconductor device according to the second embodiment of the present invention. The flow of the filler-containing resin in the resin sealing step is schematically shown. The filler-containing resin flows from the left side of the drawing to the lower side of the internal terminal 3a.

樹脂流動方向を示す矢印Ｃ、Ｄのように二つの傾斜面３ｈに沿って屈曲部３ｅの底部まで入り込み、さらに外部端子３の側面の領域に流動することが示されている。フィラー含有樹脂内の応力緩和剤であるフィラーも溶融樹脂成分の流れとともには凝集することがなく内部端子３ａおよび外部端子３の周囲に一様に隙間無く充填されるため、第一の実施形態に係る半導体装置に比べ樹脂クラック耐性の強い樹脂封止体を有する半導体装置とすることができる。   As indicated by arrows C and D indicating the resin flow direction, it enters along the two inclined surfaces 3h to the bottom of the bent portion 3e, and further flows into the side region of the external terminal 3. Since the filler, which is a stress relaxation agent in the filler-containing resin, does not agglomerate with the flow of the molten resin component and is uniformly filled around the internal terminal 3a and the external terminal 3, there is no gap in the first embodiment. It can be set as the semiconductor device which has a resin sealing body with strong resin crack tolerance compared with the semiconductor device which concerns.

図４は、本発明の第三の実施形態に係る半導体装置の端子部詳細図である。図４（ｂ）は外部端子および内部端子の側面図であり、これを左方から見た模式図を図４（ａ）に示した。図２に示す第二の実施形態に係る半導体装置との違いは、端子下面平坦部を無くして傾斜凸部２３ｄの先端を尖頭２７とした点である。   FIG. 4 is a detailed view of a terminal portion of the semiconductor device according to the third embodiment of the present invention. FIG. 4B is a side view of the external terminal and the internal terminal. FIG. 4A shows a schematic view of the external terminal viewed from the left side. The difference from the semiconductor device according to the second embodiment shown in FIG. 2 is that the flat portion on the lower surface of the terminal is eliminated and the tip of the inclined convex portion 23d is a pointed tip 27.

二つの傾斜面２３ｈの交線部を舳先のように尖った形状の傾斜凸部２３ｄとし、内部端子２３ａの端部から屈曲部２３ｅ、そして、外部端子２３の一部におよぶ範囲まで形成している。さらに、第一の実施形態同様、内部端子２３ａの端部の傾斜凸部２３ｄには内部端子下端テーパ部２３ｂが形成されている。   The intersecting line part of the two inclined surfaces 23h is formed as an inclined convex part 23d having a pointed shape like a tip, and is formed from the end of the internal terminal 23a to the bent part 23e and a part of the external terminal 23. Yes. Further, as in the first embodiment, an internal terminal lower end taper portion 23b is formed on the inclined convex portion 23d of the end portion of the internal terminal 23a.

このような形状とすることで、フィラー含有樹脂内の応力緩和剤であるフィラーも溶融樹脂成分の流れとともには凝集することがなく、樹脂が内部端子３ａおよび外部端子３の周囲に一様に隙間無く充填されるため、樹脂クラック耐性の強い樹脂封止体を有する半導体装置とすることができる。   By adopting such a shape, the filler, which is a stress relaxation agent in the filler-containing resin, does not aggregate with the flow of the molten resin component, and the resin is uniformly spaced around the inner terminal 3 a and the outer terminal 3. Since it is completely filled, a semiconductor device having a resin sealing body with high resin crack resistance can be obtained.

１ 半導体装置
２ ダイパッド
２ｂ ダイパッド上端テーパ部
３、２３ 外部端子
３ａ、２３ａ 内部端子
３ｂ、２３ｂ 内部端子下端テーパ部
３ｄ、２３ｄ 傾斜凸部
３ｅ、２３ｅ 屈曲部
３ｇ 端子下面平坦部
３ｈ、２３ｈ 傾斜面
４ 半導体素子
５、２５ 導電性ワイヤ
６ 封止体
２７ 尖頭
Ａ ダイパッド・端子間領域
Ｂ 内部端子下方領域
Ｃ、Ｄ 樹脂流動方向 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Die pad 2b Die pad upper end taper part 3, 23 External terminal 3a, 23a Internal terminal 3b, 23b Internal terminal lower end taper part 3d, 23d Inclination convex part 3e, 23e Bending part 3g Terminal lower surface flat part 3h, 23h Inclined surface 4 Semiconductor element 5, 25 Conductive wire 6 Sealing body 27 Point A Die pad-terminal area B Internal terminal lower area C, D Resin flow direction

Claims (7)

ダイパッドと、
前記ダイパッド上に載置された半導体素子と、
前記ダイパッドの周囲に離間して配置された外部端子と、
前記外部端子から屈曲部を経てアップセットされ、前記ダイパッド方向に延出された内部端子と、
前記ダイパッドと前記半導体素子と前記内部端子とを封止している封止体と、
前記内部端子の前記ダイパッド方向の下端に設けられた内部端子下端テーパ部と、
前記ダイパッドの上端部の周囲であって、前記内部端子と向き合う位置に設けられたダイパッド上端テーパ部と、
を備え、
前記ダイパッドおよび前記外部端子の裏面が前記封止体から露出しており、
前記内部端子下端テーパ部と前記ダイパッド上端テーパ部は互いに平行であることを特徴とする半導体装置。 Die pad,
A semiconductor element mounted on the die pad;
External terminals spaced apart around the die pad;
An internal terminal that is upset from the external terminal via a bent portion and extends in the die pad direction;
A sealing body sealing the die pad, the semiconductor element, and the internal terminal;
An internal terminal lower end tapered portion provided at the lower end of the internal terminal in the die pad direction;
A die pad upper end tapered portion provided around the upper end portion of the die pad and at a position facing the internal terminal;
With
The back surface of the die pad and the external terminal is exposed from the sealing body,
The internal terminal lower end taper portion and the die pad upper end taper portion are parallel to each other. 前記内部端子の下の内部端子下方領域の高さが前記外部端子および前記ダイパッドの厚さに比べ大きいことを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a height of a region below the internal terminal below the internal terminal is larger than thicknesses of the external terminal and the die pad. 前記内部端子の下の内部端子下方領域の高さが前記封止体に含まれる応力緩和剤の最大粒径よりも大きいことを特徴とする請求項２記載の半導体装置。   3. The semiconductor device according to claim 2, wherein a height of a lower region of the internal terminal below the internal terminal is larger than a maximum particle size of the stress relaxation agent contained in the sealing body. 前記内部端子の下部に傾斜凸部を有することを特徴とする請求項１乃至請求項３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, further comprising an inclined protrusion at a lower portion of the internal terminal. 5. 前記傾斜凸部が前記内部端子から前記外部端子に至る屈曲部にも設けられていることを特徴とする請求項４記載の半導体装置。   5. The semiconductor device according to claim 4, wherein the inclined convex portion is also provided at a bent portion extending from the internal terminal to the external terminal. 前記傾斜凸部の先端が平頭であることを特徴とする請求項４または請求項５に記載の半導体装置。   6. The semiconductor device according to claim 4, wherein a tip of the inclined convex portion is a flat head. 前記傾斜凸部の先端が尖頭であることを特徴とする請求項４または請求項５に記載の半導体装置。   The semiconductor device according to claim 4, wherein a tip of the inclined convex portion is a pointed tip.
JP2017048797A 2017-03-14 2017-03-14 Semiconductor device Expired - Fee Related JP6821258B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2017048797A JP6821258B2 (en) 2017-03-14 2017-03-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017048797A JP6821258B2 (en) 2017-03-14 2017-03-14 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2018152503A true JP2018152503A (en) 2018-09-27
JP6821258B2 JP6821258B2 (en) 2021-01-27

Family

ID=63680567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017048797A Expired - Fee Related JP6821258B2 (en) 2017-03-14 2017-03-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JP6821258B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63157451A (en) * 1986-12-22 1988-06-30 Oki Electric Ind Co Ltd Lead frame for semiconductor device
JPH06314764A (en) * 1993-04-30 1994-11-08 Nec Kansai Ltd Resin sealed semiconductor device
JP2011066327A (en) * 2009-09-18 2011-03-31 Seiko Instruments Inc Resin-sealed semiconductor device and method for manufacturing the same
JP2012059782A (en) * 2010-09-06 2012-03-22 Seiko Instruments Inc Resin sealing type semiconductor device, and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63157451A (en) * 1986-12-22 1988-06-30 Oki Electric Ind Co Ltd Lead frame for semiconductor device
JPH06314764A (en) * 1993-04-30 1994-11-08 Nec Kansai Ltd Resin sealed semiconductor device
JP2011066327A (en) * 2009-09-18 2011-03-31 Seiko Instruments Inc Resin-sealed semiconductor device and method for manufacturing the same
JP2012059782A (en) * 2010-09-06 2012-03-22 Seiko Instruments Inc Resin sealing type semiconductor device, and method of manufacturing the same

Also Published As

Publication number Publication date
JP6821258B2 (en) 2021-01-27

Similar Documents

Publication Publication Date Title
JP6150938B2 (en) Semiconductor device
US7820486B2 (en) Method of fabricating a semiconductor device having a heat sink with an exposed surface
US12046541B2 (en) Packaging of a semiconductor device with a plurality of leads
TW201820580A (en) Semiconductor devices and methods of manufacturing the same
US9589871B2 (en) Semiconductor package structure and method for manufacturing the same
US8476746B2 (en) Package structure enhancing molding compound bondability
US20150235937A1 (en) Method For Manufacturing Semiconductor Device Using Mold Having Resin Dam And Semiconductor Device
JP5714157B1 (en) Power semiconductor device
TWI536516B (en) Semicomductor package with heat dissipation structure and manufacturing method thereof
CN108231704B (en) Semiconductor module
US10290563B2 (en) Semiconductor device including die pad with projections
JP7442333B2 (en) Semiconductor device and its manufacturing method
JP6821258B2 (en) Semiconductor device
US20120080783A1 (en) Thin flip chip package structure
US6737735B2 (en) Semiconductor device wiring lead frame having resin flow control plates
WO2019167218A1 (en) Semiconductor device
US20180211930A1 (en) Semiconductor device and method for manufacturing the same
JP6869602B2 (en) Semiconductor device
JP2012023409A (en) Circuit device and method for manufacturing thereof
US20210098358A1 (en) Semiconductor package
US20140120715A1 (en) Semiconductor manufacturing method, semiconductor structure and package structure thereof
WO2012111722A1 (en) Semiconductor chip and semiconductor device
JP6549003B2 (en) Semiconductor device
JP5477260B2 (en) Electronic device and manufacturing method thereof
CN217444382U (en) Semiconductor package frame and structure

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191205

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20201030

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20201104

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20201215

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210105

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210105

R150 Certificate of patent or registration of utility model

Ref document number: 6821258

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees