JP2018148364A - Time Digital Converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a time digital converter with reduced quantization error without using many analog elements.SOLUTION: A TDC 2 includes a clock circuit 10, a delay circuit 20, a counter circuit 6, an average calculation circuit 7, and a resistance element 3. The clock circuit 10 outputs a clock signal corresponding to output change of a first CMOS inverter 4. The delay circuit 20 outputs a delay trigger signal having a delay trigger timing obtained by delaying an input trigger timing according to the number of stages of an inverter chain 22. The counter circuit 6 counts the number of clocks from the input trigger timing to the delay trigger timing. The average calculation circuit 7 calculates a moving average of the number of clocks corresponding to the plurality of input trigger timings. One end of the resistance element 3 is connected to a power supply Vdd, and the other end is connected to voltage supply ends 12a and 22a of the first CMOS inverter 4 and a second CMOS inverter 5.SELECTED DRAWING: Figure 1

Description

  The technology disclosed in this specification relates to a time-to-digital converter. In particular, it relates to a technique for increasing the resolution of a time digital converter.

  Time digital converters that can output a predetermined time interval as a digital signal are known. The time digital converter has two advantages because the time interval can be converted directly into a digital signal. One is that the time interval can be measured with high resolution. The other is that it can be composed of digital elements and is suitable for miniaturization.

  The technique of the time digital converter is used for a temperature sensor, for example (for example, Patent Document 1). The temperature sensor disclosed in Patent Document 1 includes a delay circuit, a clock circuit, and a counter circuit. The delay circuit has an inverter chain in which a plurality of inverters are connected in series, and outputs a delay trigger signal having a delay trigger timing obtained by delaying the input trigger timing of the input trigger signal according to the number of stages of the inverter chain. . The counter circuit counts the number of clock signals output from the clock circuit between the input trigger timing and the delay trigger timing. The time from the input trigger timing to the delay trigger timing can be obtained as a digital value as the number of clocks. The operation speed of the inverter of the delay circuit has temperature dependency, and the temperature sensor of Patent Document 1 uses the temperature dependency. The time from the input trigger timing to the delay trigger timing varies depending on the environmental temperature of the delay circuit. Therefore, the number of clocks output from the counter circuit has a correlation with the ambient temperature of the delay circuit. By obtaining the correlation in advance, the ambient temperature of the delay circuit can be obtained from the number of clocks.

  One of the features of the time digital converter is its high resolution, but its accuracy is also limited. In the time digital converter, a quantization error occurs when the time interval from the input trigger timing to the delay trigger timing is digitized by the number of clocks. Specifically, the quantization error depends on the operation speed of the inverter provided in the clock circuit and the delay circuit.

  On the other hand, as a technique for reducing a quantization error, a technique called dithering is known in which low-pass filtering is performed on data obtained by intentionally adding noise to a digital processing circuit. It has been proposed to apply a dithering technique to a time digital converter (Patent Document 2). In the technique, a more accurate measurement result is obtained by averaging a plurality of measurement results obtained by randomly changing the delay time.

  Patent Document 2 does not disclose a specific means for randomly changing the delay time. On the other hand, Patent Document 3 discloses an example of the technique. Patent Document 3 utilizes the fact that the operation speed (ie, delay time) of the inverter depends on the supply voltage. That is, in the technique of Patent Document 3, a voltage including noise is generated and the voltage is applied to the inverter.

JP 2013-185985 A Special table 2011-526752 gazette JP 2014-217064 A

  In the technique of Patent Document 3, after a digital signal including fluctuation is generated, the digital signal is converted into an analog signal, and a supply voltage including noise is generated through a low-pass filter and an amplifier. As described above, one advantage of the time digital converter is that it is suitable for miniaturization because most of the time digital converter can be composed of digital elements. However, since the technique of Patent Document 3 uses several analog elements, the advantage of the time digital converter, which is a reduction in size, is hindered. The present specification provides a time-to-digital converter that can introduce dithering by simply adding a simple configuration and has an increased resolution without using many analog elements.

  The time digital converter disclosed in this specification includes a clock circuit, a delay circuit, a counter circuit, an average calculation circuit, and a resistance element. The clock circuit includes a ring oscillator in which a plurality of first CMOS inverters are connected in a ring shape, and outputs a clock signal corresponding to an output change of the first CMOS inverter. The delay circuit includes an inverter chain in which a plurality of second CMOS inverters are connected in series, and a delay trigger signal having a delay trigger timing obtained by delaying the input trigger timing of the input trigger signal according to the number of stages of the inverter chain. Output. The operation speed of the plurality of second CMOS inverters depends on the supply voltage. The counter circuit counts the number of clock signals from the input trigger timing to the delay trigger timing. The average calculation circuit calculates a moving average of the number of clocks corresponding to each of a plurality of input trigger timings included in the input trigger signal. One end of the resistance element is connected to the power supply, and the other end is connected to the voltage supply terminals of the first CMOS inverter and the second CMOS inverter. The CMOS inverter is an abbreviation for Complementary Metal Oxide Semiconductor Inverter, and is a circuit in which an n-type MOS transistor and a p-type MOS transistor are connected in series.

  The time digital converter disclosed in this specification uses a CMOS inverter for a clock circuit. In the CMOS inverter, no current flows while the output is held, but a through current flows when the output changes. When the through current flows, the voltage at the voltage supply terminal of the CMOS inverter decreases. When the magnitude of the through current is represented by IPr and the resistance value of the resistance element is represented by R, the voltage fluctuation value on the current downstream side of the resistance element due to the through current Ipr is Ipr × R [volt]. The voltage downstream of the current of the resistance element is equal to the voltage supplied to the second CMOS inverter of the delay circuit. That is, the supply voltage of the CMOS inverter of the delay circuit changes Ipr × R [volt] due to the through current Ipr when the output of the CMOS inverter in the clock circuit changes. In other words, noise of Ipr × R [volt] is added to the supply voltage. Since the operation speed of the second CMOS inverter of the delay circuit depends on the supply voltage, the operation speed of the delay circuit changes due to a change (noise) in the supply voltage, and the delay trigger timing of the delay trigger signal output from the delay circuit changes. . Since the delay trigger timing changes, the number of clocks counted by the counter circuit changes. By calculating the moving average of the number of clocks corresponding to each of the multiple input trigger timings included in the input trigger signal, the delay time (from the input trigger timing to the delay trigger timing) is higher than the resolution equivalent to one clock. Time). This time digital converter realizes high accuracy by dithering by superimposing noise on the supply voltage to the delay circuit by a clock circuit and a resistance element.

  As described above, the time digital converter disclosed in this specification can be realized with a simple configuration in which a resistance element is added between the first and second CMOSs and the power supply. In other words, the technique disclosed in the present specification provides a time digital converter having an increased resolution without using many analog elements. Hereinafter, in order to distinguish the above-described resistance element from other resistance elements, for the sake of convenience, it is referred to as a noise-inducing resistance element.

  As is clear from the above description, the resistance value R of the noise-inducing resistance element corresponds to the voltage fluctuation value obtained by multiplying the through current Ipr that flows when the output of the first CMOS inverter changes (when the output is inverted) by the resistance value R. The time change of the delay trigger timing is set to be equal to or longer than a half cycle of the clock signal. By setting the resistance value R of the noise-inducing resistance element as described above, the number of clocks to be counted always changes depending on the voltage fluctuation value (Ipr × R). As a result, quantization error can be reduced by dithering, and higher resolution can be reliably obtained.

  Specifically, the resistance value R of the noise-inducing resistance element is set to 50 ohms or more. For example, when the current Ipr flowing when the output of the first CMOS inverter changes is 0.2 [mA], the voltage change is 50 × 0.2 = 10 [mV]. Since the drive voltage (supply voltage) of the CMOS inverter is approximately 1 to 5 volts, the voltage change (that is, the amplitude of noise) is about 1/100 to 1/500 of the supply voltage. When noise of this size is added to the supply voltage, the delay time of the delay circuit (the time from the input trigger timing to the delay trigger timing) changes by about a half cycle (or more) of one clock. If the delay time is shifted by more than half a clock cycle, the number of clocks to be measured is shifted by at least one clock. The number of clocks from the input trigger timing to the delay trigger timing fluctuates due to the influence of noise. Obtaining a moving average of the number of clocks corresponding to each of a plurality of time-series input trigger timings (a number of clocks with fluctuations) reduces the quantization error of the time digital converter and provides a high resolution. .

  In the time digital converter described above, the operation of the clock circuit adds noise (voltage fluctuation) to the supply voltage to the delay circuit. The time digital converter disclosed in the present specification may include the following sub clock circuit so that noise for dithering is also added to the supply voltage to the first CMOS inverter of the clock circuit. The sub clock circuit includes another ring oscillator in which a plurality of third CMOS inverters are connected in a ring shape. The voltage supply terminal of the third CMOS inverter is connected to the other end of the resistance element. The operating speed of the first CMOS inverter depends on the supply voltage. Similarly to the clock circuit described above, the sub clock circuit also has a through current when the output of each third CMOS inverter changes, and the voltage at the other end of the resistance element changes. As a result, the supply voltage of the first CMOS inverter of the clock circuit changes (that is, noise is superimposed). As the supply voltage changes, the clock width (cycle) at that time changes. As the clock width of the clock signal output from the clock circuit changes, the number of clocks measured by the counter circuit changes. By providing the sub clock circuit, noise is also superimposed on the supply voltage to the clock circuit, and fluctuation (noise) from both the clock circuit and the sub clock circuit is also superimposed on the supply voltage to the delay circuit. For this reason, the noise becomes more complicated and becomes close to white noise. Therefore, higher resolution can be obtained. Further, since the sub clock circuit is also a digital circuit, a small time digital converter can be realized even if the sub clock circuit is included.

  One application of this time digital converter is a temperature sensor that employs a transistor whose operation speed is temperature dependent in the second CMOS inverter of the delay circuit. However, the time digital converter disclosed in this specification is not limited to application to a temperature sensor. Details and further improvements of the technology disclosed in this specification will be described in the following “DETAILED DESCRIPTION”.

It is a block diagram of the time digital converter of the 1st example. It is a circuit diagram of a CMOS inverter. It is a graph which shows the change of the input voltage and output voltage to a CMOS inverter, and the change of a through current. It is a block diagram of a clock circuit. It is a graph of the electric current which flows into the voltage supply end of a clock circuit. It is a figure explaining the influence of the change of delay time. FIG. 3A is an example of output when there is no noise. FIG. 3B is an example of the output when noise is added (before averaging). FIG. 3C shows an example of output when noise is added (after averaging). It is a block diagram of the time digital converter of 2nd Example.

  (First Embodiment) A time digital converter 2 of the first embodiment will be described with reference to the drawings. In the following, for convenience of explanation, the time-to-digital converter 2 is simply expressed as TDC2. The TDC 2 can be used as a temperature sensor. FIG. 1 shows a block diagram of the TDC 2.

  The TDC 2 includes a clock circuit 10, a delay circuit 20, a counter circuit 6, and an average calculation circuit 7. The clock circuit 10 includes a ring oscillator 12 in which a plurality of first CMOS inverters 4 are connected in a ring shape. The delay circuit 20 includes an inverter chain 22 in which a plurality of second CMOS inverters 5 are connected in series. The first CMOS inverter 4 of the clock circuit 10 and the second CMOS inverter 5 of the delay circuit 20 are constituted by a series connection of two voltage-driven transistors, and are supplied with voltage from the power supply Vdd via the resistance element 3.

  In the clock circuit 10, the input level of the first CMOS inverter 4 at the left end in the figure is inverted by a start circuit (not shown). Then, the output of the first CMOS inverter 4 at the left end is inverted. The output terminal of the first CMOS inverter 4 at the left end is connected to the input terminal of the second first CMOS inverter 4 from the left. When the output of the first CMOS inverter 4 at the left end is inverted, the input of the second first CMOS inverter 4 from the left is inverted, and the output of the first CMOS inverter 4 is inverted. Thus, the output inversion of the first CMOS inverter 4 occurs in a chained manner from left to right in the figure. The output end of the first CMOS inverter 4 at the right end is connected to the input end of the first CMOS inverter 4 at the left end, and the output inversion chain goes around the ring oscillator 12 infinitely. The output end of the first CMOS inverter 4 at the right end in the figure corresponds to the output end 10 a of the clock circuit 10. From the output terminal 10a, a clock signal CLK having a period corresponding to the operating speed of the first CMOS inverter 4 and the number of stages of the ring oscillator 12 is output.

  The operation of the delay circuit 20 will be described. An input trigger signal Sin having a rising edge is input to the input terminal 20a of the delay circuit 20. The time of the rising edge of the input trigger signal Sin is referred to as input trigger timing. Due to the input of the edge of the input trigger timing, the second CMOS inverter 5 constituting the inverter chain 22 inverts the output in a chained manner from left to right in the figure. As a result, a delay trigger signal Sd having a delay trigger timing obtained by delaying the input trigger timing of the input trigger signal Sin according to the number of stages of the inverter chain 22 is output from the output terminal 20 b of the delay circuit 20. The time from the input trigger timing (the rising edge of the input trigger signal Sin) to the delay trigger timing (the rising edge of the delay trigger signal Sd) is referred to as a delay time.

  The input trigger signal Sin, the delay trigger signal Sd, and the clock signal CLK are input to the counter circuit 6. The counter circuit 6 counts the number of clocks between the input trigger timing of the input trigger signal Sin and the delay trigger timing of the delay trigger signal Sd. Since the counter circuit 6 may have a known configuration, a detailed description thereof is omitted. The output (number of clocks) of the counter circuit 6 is sent to the average calculation circuit 7.

  Although not shown in FIG. 1, the input trigger signal Sin includes a plurality of input trigger timings (that is, a plurality of rising edges). The delay circuit 20 generates a delay trigger timing corresponding to each input trigger timing. The counter circuit 6 receives an input trigger signal Sin including a plurality of input trigger timings and a delay trigger signal Sd including delay trigger timings corresponding to the respective input trigger timings. The counter circuit 6 counts the number of clocks between the input trigger timing input in time series and the delay trigger timing corresponding to each input trigger timing, and sends it to the average calculation circuit 7. A plurality of count numbers are input to the average calculation circuit 7 in time series. The average calculation circuit 7 calculates and outputs a moving average of the time-series data of the count number. The output of the average calculation circuit 7 becomes the output of TDC2. Since the average calculation circuit 7 may be a known circuit, detailed description thereof is omitted.

  Most of the TDC 2 can be constituted by digital elements and is made into one chip. The one-chip TDC 2 is placed on a temperature measurement target. The operation speed of the second CMOS inverter 5 of the delay circuit 20 is temperature dependent. That is, the time interval (delay time) from the input trigger timing to the delay trigger timing varies depending on the ambient temperature of the TDC 2. The correlation between the delay time and the ambient temperature is examined in advance, and a temperature table (or a conversion formula) corresponding to the number of clocks representing the delay time (the number of clocks measured by the counter circuit 6) indicates the output of the average calculation circuit 7. It is stored in a temperature specifying circuit (not shown). The temperature specifying circuit specifies the ambient temperature from the number of clocks output from the average calculating circuit 7 using the table (or conversion formula) and outputs the specified ambient temperature.

  The counter circuit 6 counts the number of clocks in the time (delay time) from the input trigger timing to the delay trigger timing. Therefore, the time resolution of the counter circuit 6 is determined by a cycle of one clock. A time difference shorter than one clock cycle cannot be measured by the counter circuit 6. This is a quantization error. The TDC 2 includes a resistance element 3 in order to reduce quantization error and achieve higher accuracy. One end of the resistance element 3 is connected to the power supply Vdd, and the other end is connected to the voltage supply terminals 12 a of the plurality of first CMOS inverters 4 and the voltage supply terminals 22 a of the plurality of second CMOS inverters 5. Next, the role of the resistance element 3 will be described.

  The first CMOS inverter 4 of the clock circuit 10 is composed of a voltage-driven transistor, and no current flows while the output is held, but a through current Ipr flows when the output is inverted. When the resistance value of the resistance element 3 is represented by the symbol R, the voltage at the current downstream end 3a of the resistance element 3 varies by dV = Ipr × R every time the through current Ipr flows. This voltage fluctuation dV is superimposed as noise on the supply voltage to the second CMOS inverter 5 of the delay circuit 20. The second CMOS inverter 5 of the delay circuit 20 is a type in which the operation speed varies depending on the supply voltage, and the delay time (the time from the input trigger timing to the delay trigger timing) varies depending on the voltage variation dV. Dithering is performed using the variation of the delay time to reduce the quantization error. More specific description will be given below.

  FIG. 2 shows a circuit diagram of one first CMOS inverter 4. The first CMOS inverter 4 is constituted by a DC connection of two voltage-driven transistors 41 and 42. The first transistor 41 is a p-type MOSFET (Metal Oxide Field Effect Transistor), the drain is connected to the power supply Vdd, and the source is connected to the drain of the second transistor 42. The second transistor 42 is an n-type MOSFET, the drain is connected to the source of the first transistor 41, and the source is connected to the ground terminal Vss. The gate of the first transistor 41 and the gate of the second transistor 42 are connected to each other. A connection point between the first transistor 41 and the second transistor 42 is connected to gates of two transistors constituting the first CMOS inverter 4 in the next stage.

  FIG. 3 shows a graph for explaining the operation of the first CMOS inverter 4. When the input voltage Vin of the first CMOS inverter 4 (that is, the gate voltage of the two transistors 41 and 42) is the off voltage Voff (Low level voltage), the output voltage Vout of the first CMOS inverter 4 is the on voltage Von (High level voltage). It becomes. When the input voltage Vin is switched from the off voltage Voff to the on voltage Von, the output voltage Vout is switched from the on voltage Von to the off voltage Voff. In the switching section Tsw, since neither of the transistors 41 and 42 is in a completely off state, a current (through current Ipr) flows. The through current Ipr has a spike-like waveform that becomes maximum at time Tx when the input voltage Vin and the output voltage Vout intersect (see the lower diagram in FIG. 3).

  FIG. 4 shows a block diagram of the clock circuit 10 (ring oscillator 12). FIG. 5 shows a graph of the current (through current Ipr) flowing through the voltage supply terminal 12a of the ring oscillator 12 of the clock circuit 10 (that is, the plurality of first CMOS inverters 4). The clock circuit 10 (ring oscillator 12) has a structure in which a plurality of first CMOS inverters 4 shown in FIG. 2 are connected in a ring shape. In FIG. 4, the startup circuit that inverts the input of any of the first CMOS inverters 4 is omitted.

  In the ring oscillator 12, once the output of any of the first CMOS inverters 4 is inverted, the output inversion is chained clockwise in the figure. Each time the output of each first CMOS inverter 4 is inverted, the spike-like through current Ipr shown in FIG. 3 flows (see the broken line graph in FIG. 5). As a result, a slightly fluctuating current flows through the common voltage supply terminal 12a that applies a voltage to the plurality of first CMOS inverters 4 (see the solid line graph in FIG. 5). A minute fluctuation of the supply voltage caused by the through current Ipr of the clock circuit 10 is applied to the second CMOS inverter 5 of the delay circuit 20.

  The second CMOS inverter 5 has a characteristic that the operation speed depends on the supply voltage. When the supply voltage fluctuates (when noise is added), the operation speed of the second CMOS inverter 5 changes, and as a result, the delay time (the time from the input trigger timing to the delay trigger timing) changes. FIG. 6 is a diagram for explaining the influence of a change in delay time. FIG. 7 is a diagram for explaining the difference in output results depending on the presence or absence of noise. Since the number of clocks is an integer, the number of clocks is distributed within a range of a predetermined median value ± 1, for example, by adding noise. When the delay time changes in the range of dTd in FIG. 6, the number of clocks measured by the counter circuit 6 is distributed in the range of n ± 1. FIG. 7A shows the coefficient result of the counter circuit 6 when there is no noise. In this example, it is assumed that the number of clocks coefficientd by the counter circuit 6 is 1000 when there is no noise. That is, “n” in FIG. 6 corresponds to “1000” in FIG. 7, “n−1” in FIG. 6 corresponds to “999” in FIG. 7, and “n + 1” in FIG. 6 corresponds to “1001” in FIG. Is equivalent to. FIG. 7B is an example of the output of the counter circuit 6 when noise is added. The number of clocks coefficientd by the counter circuit 6 is distributed between “n−1” and “n + 1”, that is, between “999” and “1001”.

  Since the output of the counter circuit 6 is an integer value, the time resolution of the delay time in the output of the counter circuit 6 is equal to the clock cycle.

  When it is assumed that the delay time can be expressed including the decimal point of the clock number (that is, when there is no quantization error), the value of the clock number including the decimal point is the median value of an integer (in the case of FIG. 7). 1000), the shape of the distribution in FIG. 7B is biased toward the median plus 1 side (ie, “1001”). On the other hand, if the value of the number of clocks including the decimal point is shifted to the negative value side from the median value of the integer, the shape of the distribution in FIG. 7B is on the median minus 1 side (that is, “999”). Biased. Therefore, by calculating the moving average of the distribution of the number of clocks when noise is added, the number of clocks corresponding to the delay time can be obtained with precision below the decimal point. That is, the quantization error of the counter circuit 6 can be reduced. FIG. 7C shows the result of calculating a moving average of 30 samples for the time-series data of the number of clocks in FIG. 7B. As shown in FIG. 7C, by calculating the moving average, the number of clocks corresponding to the delay time can be expressed with an accuracy of a decimal point or less.

  From the above description, the conditions for the resistance value R of the resistance element 3 can also be found. The voltage fluctuation dV is obtained by multiplying the through current Ipr of the clock circuit 10 by the resistance value R of the resistance element 3 (dV = Ipr × R). On the other hand, the operation speed of the second CMOS inverter 5 depends on the supply voltage, and the delay time varies depending on the variation of the supply voltage. If the delay time fluctuates by at least a half cycle of one clock, the number of clocks (output of the counter circuit 6) is dispersed due to voltage fluctuation (noise). This is because when the clock output is used in addition to the output of the counter circuit for calculating the delay time, the number of clocks output from the counter circuit 6 changes by at least one clock even if the time change of the delay time is a half cycle of the clock. Because it does. The resistance value R of the resistance element 3 must be set so that the time change of the delay trigger timing with respect to the voltage fluctuation dV (= through current Ipr × resistance value R) is equal to or longer than a half cycle of the clock signal. The time change in the delay trigger timing corresponds to the change in the delay time. Therefore, in other words, the resistance value R of the resistance element 3 is such that the change in the delay time with respect to the voltage fluctuation dV (= through current Ipr × resistance value R) is equal to or greater than a half cycle of the clock signal. It may be expressed that it must be set.

  In general, the resistance value R of the resistance element 3 is desirably 50 ohms or more from the characteristics of a normal MOSFET. For example, when the through current Ipr of the clock circuit 10 is 0.2 [mA], the voltage fluctuation dV is 0.2 × 50 = 10 [mV]. When the voltage fluctuation is smaller than this, there is a high possibility that the delay time fluctuation (delay trigger timing fluctuation) in the delay circuit 20 will not be larger than the half cycle of the clock signal.

  (Second Embodiment) FIG. 8 shows a block diagram of a TDC 2a of the second embodiment. The TDC 2 is obtained by adding a sub clock circuit 50 to the TDC 2 in FIG. The sub clock circuit 50 includes another ring oscillator 52 in which a plurality of third CMOS inverters 9 are connected in a ring shape. The voltage supply terminals 52 a of the plurality of third CMOS inverters 9 are connected to the current downstream terminal 3 a of the resistance element 3. In the TDC 2, the plurality of first CMOS inverters 4 of the clock circuit 10 have a characteristic that their operation speed depends on the supply voltage. The configuration of the sub clock circuit 50 is the same as that of the clock circuit 10. Therefore, the voltage of the current downstream end 3a of the resistance element 3 also varies depending on the operation of the sub clock circuit 50. Due to the voltage fluctuation, not only the second CMOS inverter 5 of the delay circuit 20 but also the operation speed of the first CMOS inverter 4 of the clock circuit 10 changes. The change in the operation speed of the first CMOS inverter 4 changes the clock cycle of the clock signal CLK. As a result, the number of clocks measured during the delay time changes. The delay circuit 20 receives voltage fluctuation (noise 2 in FIG. 8) due to the operation of the third CMOS inverter 9 in addition to voltage fluctuation (noise 1 in FIG. 8) due to the operation of the first CMOS inverter 4. Since the voltage fluctuation received by the delay circuit 20 becomes complicated, the total noise becomes close to ideal white noise. By adding the sub clock circuit 50, the clock circuit 10 receives voltage fluctuations and the delay circuit 20 receives voltage fluctuations close to white noise, so that the quantization error can be further reduced. In other words, a more accurate output can be obtained.

  Since the sub-clock circuit 50 can also be composed of only digital elements, the TDC 2a can also be realized in a compact manner.

  The resistance value R of the resistance element 3 should satisfy the following conditions in addition to the previous conditions. That is, the number of clocks in the delay time is shifted by more than half a clock with respect to the voltage fluctuation value dV obtained by multiplying the through current Ipr flowing when the output of the third CMOS inverter 9 changes (when the output is inverted) by the resistance value R. The resistance value R is preferably selected for the above. The previous conditions are as follows. The time change of the delay trigger timing with respect to the voltage fluctuation value obtained by multiplying the resistance value R by the through current Ipr flowing when the output of the first CMOS inverter 4 changes (when the output is inverted) is equal to or longer than the cycle of the clock signal CLK. Thus, the resistance value R is selected. If the resistance value R is selected so that at least the number of clocks in the delay time is shifted by half a clock or more, the number of clocks (output of the counter circuit) is dispersed due to voltage fluctuation (noise). If the resistance value R is selected so that the number of clocks in the delay time is shifted by 1 clock or more, the number of clocks (the output of the counter circuit) is more reliably dispersed by voltage fluctuation (noise). In other words, if the resistance value R is selected so that the time change of the delay trigger timing is one period or more of the clock signal, higher accuracy by dithering can be expected more reliably.

  The transistor constituting the first CMOS inverter 4 may be the same type as the transistor constituting the second CMOS inverter 5. Furthermore, the transistor of the third CMOS inverter 9 may be the same type as the transistor of the second CMOS inverter 5.

  Since TDC2 and TDC2a can be constituted by digital elements other than the resistance element 3, they can be realized in a compact manner.

  Points to be noted regarding the technology described in the embodiments will be described. The TDC 2 of the example was applied to a temperature sensor. The technology disclosed in this specification is not limited to TDC applied to a temperature sensor.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2, 2a: Time digital converter 3: Resistance element 3a: Current downstream end 4: First CMOS inverter 5: Second CMOS inverter 6: Counter circuit 7: Average calculation circuit 9: Third CMOS inverter 10: Clock circuit 12: Ring oscillator 12a : Voltage supply end 20: Delay circuit 22: Inverter chain 22a: Voltage supply end 41, 42: Transistor 50: Sub clock circuit 52: Ring oscillator 52a: Voltage supply end

Claims (4)

A clock circuit that includes a ring oscillator in which a plurality of first CMOS inverters are connected in a ring shape, and that outputs a clock signal according to an output change of the first CMOS inverter;
A delay trigger timing obtained by delaying the input trigger timing of the input trigger signal in accordance with the number of stages of the inverter chain is provided. The inverter chain includes a plurality of second CMOS inverters whose operation speed depends on the supply voltage. A delay circuit for outputting a delay trigger signal having;
A counter circuit that counts the number of clocks of the clock signal between the input trigger timing and the delay trigger timing;
An average calculating circuit that calculates a moving average of the number of clocks corresponding to each of the plurality of input trigger timings included in the input trigger signal;
A resistance element having one end connected to a power source and the other end connected to a voltage supply terminal of the first CMOS inverter and the second CMOS inverter;
With time digital converter.   The time change of the delay trigger timing with respect to the voltage fluctuation value obtained by multiplying the through current flowing when the output of the first CMOS inverter changes by the resistance value of the resistance element is equal to or greater than a half cycle of the clock signal. The time digital converter according to claim 1, wherein a resistance value is set.   The time digital converter according to claim 1 or 2, wherein the resistance value of the resistance element is 50 ohms or more. A plurality of third CMOS inverters including a sub clock circuit including another ring oscillator connected in a ring shape;
A voltage supply terminal of the third CMOS inverter is connected to the other end of the resistance element;
The plurality of first CMOS inverters have an operation speed that depends on a supply voltage.
The time digital converter according to any one of claims 1 to 3.

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