CN114586340A

CN114586340A - Adaptive correlated multisampling with input signal level shifting

Info

Publication number: CN114586340A
Application number: CN201980101559.4A
Authority: CN
Inventors: 石井隆雄
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-10-23
Filing date: 2019-10-23
Publication date: 2022-06-03
Also published as: JP7412551B2; WO2021077329A1; JP2023500609A

Abstract

A single slope analog to digital converter (SS-ADC) comprising: a level shifter for adding one or more offset levels to an analog input during periods of respective AD conversions of a reset level and a signal level in response to an output of a comparator for comparing the analog input with a ramp signal step by step; a counter for measuring, for each count value of the AD conversion of the signal level having each offset level, a difference between the count value and a count value of the AD conversion of the reset level having the same offset level setting, respectively; and a controller for averaging outputs of the counters that successfully output the AD conversion results. The converter reduces temporal noise without increasing the conversion time.

Description

Adaptive correlated multisampling with input signal level shifting

Technical Field

The present invention relates to an analog-to-digital converter for an image sensor.

Background

Image sensors, such as Complementary Metal Oxide Semiconductor (CMOS) image sensors, Charge Coupled Device (CCD) image sensors, and the like, are classified as one of the most noise sensitive devices because most of them obtain a voltage output with a conversion gain in the order of microvolts. Therefore, several noise reduction techniques, such as multisampling techniques, have been developed. The multiple sampling technique is to average the results of the same N analog to digital (AD) conversions to reduce the temporal noise by a factor of 1/(square root of N). However, this technique also requires time to perform AD conversion N times, and limits the frame rate up-conversion.

Disclosure of Invention

The invention provides a method based on a multisampling technology, which is used for reducing time noise of a single slope analog-to-digital converter (SS-ADC) and analog input thereof (namely a column parallel ADC and a pixel source follower in a CMOS image sensor) and inhibiting the increase of conversion time of the SS-ADC. The present invention provides a method for obtaining CMS noise reduction, wherein the ramp signal includes only several falling ramps as reference analog levels for the reset level and the signal level, respectively.

According to a first aspect, there is provided a single slope analog to digital converter (SS-ADC), wherein the SS-ADC comprises: a level shifter for adding one or more offset levels to an analog input during periods of respective AD conversions of a reset level and a signal level in response to an output of a comparator for comparing the analog input with a ramp signal step by step; a counter for measuring, for each count value of the AD conversion of the signal level having each offset level, a difference between the count value and a count value of the AD conversion of the reset level having the same offset level setting, respectively; and a controller for averaging outputs of the counters that successfully output the AD conversion results.

In a first possible implementation form of the first aspect, the level shifter comprises a plurality of current sources connected to an output node of a pixel source follower, which makes it possible to set a voltage drop of 2 steps or more between an input and an output of the pixel source follower.

In a second possible implementation form of the first aspect, the level shifter comprises a summing amplifier of the analog input and the offset voltage, the summing amplifier being connected between the pixel source follower and the comparator, wherein the summing amplifier may be combined with the programmable gain amplifier.

According to a second aspect, there is provided an analog to digital (AD) conversion method, wherein the method comprises: adding one or more offset levels to the analog input during periods of respective AD conversions of a reset level and a signal level in response to an output of a comparator for comparing the analog input with a ramp signal step by step; for each count value of the AD conversion of the signal level having each offset level, measuring a difference between the count value and a count value of the AD conversion of the reset level having the same offset level setting, respectively; and averaging outputs of the counters that successfully output the AD conversion results.

According to a third aspect, there is provided a single slope analog to digital converter (SS-ADC), wherein the SS-ADC comprises: a level shifter for adding one or more offset levels to a ramp signal in a period of respective AD conversions of a reset level and a signal level in response to an output of a comparator for comparing an analog input with the ramp signal step by step; a counter for measuring, for each count value of the AD conversion of the signal level having each offset level, a difference between the count value and a count value of the AD conversion of the reset level having the same offset level setting, respectively; and a controller for averaging outputs of the counters that successfully output the AD conversion results.

In one possible implementation of the third aspect, the level shifter includes a plurality of current sources connected to a source follower between the output of the ramp generator and the comparator, and modulating a voltage difference between a gate and a source in a PMOS transistor of the source follower.

In a second possible implementation form of the third aspect, the level shifter comprises a summing amplifier of a ramp signal level and a variable offset level, the summing amplifier being connected between a ramp generator and the comparator, wherein the summing amplifier is not only used for a buffer amplifier of the ramp signal, but is also combined with a programmable gain amplifier.

According to a fourth aspect, there is provided an analog to digital (AD) conversion method, wherein the method comprises: adding one or more offset levels to a ramp signal in response to an output of a comparator for comparing an analog input with the ramp signal step by step, during periods of respective AD conversions of a reset level and a signal level; for each count value of the AD conversion of the signal level having each offset level, measuring a difference between the count value and a count value of the AD conversion of the reset level having the same offset level setting, respectively; and averaging outputs of the counters that successfully output the AD conversion results.

Drawings

In order to more clearly describe embodiments of the present invention or technical solutions in the prior art, the drawings required for describing the embodiments or the prior art are briefly introduced below. It is clear that the drawings in the following description only show some embodiments of the invention, and that a person skilled in the art can derive other drawings from them without inventive effort.

FIG. 1 is a schematic block diagram of an adaptive correlated multiple sampling SS-ADC (ACMS SS-ADC) provided by an embodiment of the present invention;

fig. 2 (a) shows an example of a RAMP waveform for Correlated Double Sampling (CDS);

fig. 2 (b) shows an example of a RAMP waveform for Correlated Multiple Sampling (CMS);

FIG. 3 (a) shows an example of a RAMP waveform of an ACMS SS-ADC;

fig. 3 (b) shows an example of a comparator output of a small signal level;

fig. 3 (c1) shows a count value 1 of the pixel output in fig. 3 (a);

fig. 3 (c2) shows a count value 2 of the pixel output in fig. 3 (a);

fig. 3 (c3) shows the count value 3 of the pixel output in fig. 3 (a);

fig. 3 (c4) shows a count value 4 output by the pixel in fig. 3 (a);

fig. 4 (a) shows an example of the RAMP waveform shown in fig. 3 (a);

fig. 4 (b) shows an example of a comparator output of a large signal level;

fig. 4 (c1) shows a count value 1 of the pixel output in fig. 4 (a);

fig. 4 (c2) shows a count value 2 output by the pixel in fig. 4 (a);

fig. 4 (c3) shows the count value 3 output by the pixel in fig. 4 (a);

fig. 4 (c4) shows a count value 4 output by the pixel in (a) of fig. 4;

FIG. 5 shows a schematic block diagram of an ACMS SS-ADC provided by another embodiment of the present invention;

FIG. 6 (a) shows another example of a RAMP waveform of an ACMS SS-ADC;

fig. 6 (b) shows an example of the comparator output of a small signal level;

FIG. 7 illustrates one implementation of the level shifter shown in FIG. 1;

FIG. 8 illustrates another implementation of the level shifter shown in FIG. 1;

FIG. 9 illustrates one implementation of the level shifter shown in FIG. 5;

fig. 10 shows another implementation of the level shifter shown in fig. 5.

Detailed Description

The technical solution in the embodiments of the present invention is clearly and completely described below with reference to the drawings in the embodiments of the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, belong to the protection scope of the present invention.

Fig. 1 shows a schematic block diagram of an adaptive correlated multiple sampling SS-ADC (ACMS SS-ADC) provided by an embodiment of the present invention. ACMS SS-ADC may be implemented by implementing some additional components, which are a level shifter (i.e., DC offset generator), control circuitry (CTRL logic), and a RAMP signal (RAMP) generator for generating a modified RAMP signal. The intra-column level shifters do not induce inter-column interaction because there are no signal paths and common signal lines to the next column.

Fig. 1 includes a part of the left pixel circuit: a Floating Diffusion (FD), a selection Switch (SEL), and a current source connected in series between a power supply voltage and ground. The ADC is connected to an output node (shown as a black dot) between the drain of SEL and the current source. The PIXEL signal (PIXEL) as an analog input is input into the inverting input terminal of the Comparator (CMP) through the capacitor, and the RAMP signal (RAMP) generated by the RAMP generator is input into the non-inverting input terminal of the CMP through the capacitor. The offset is added to the PIXEL step by step. The RAMP generator outputs a RAMP waveform for the ACMS SS-ADC, as shown in (a) of fig. 3. The RAMP generator may be shared by the SS-ADCs for pixels disposed in the same column. The output of the CMP inputs the CTRL logic and a plurality of Counters (CNT). In response to the output of CMP, the CTRL logic controls the level shifter to control the offset voltage added to the PIXEL. In one implementation, the number of CNTs corresponds to the number of AD conversions of the reset level. Each CNT counts a clock signal (CLK), e.g., it counts the number of cycles of CLK, and increments a count value for each cycle of CLK. The count value is averaged by a controller (not shown in fig. 1) to output a value corresponding to the analog input of the ADC.

Before explaining an example of a RAMP waveform provided by the present invention with reference to (a) in fig. 3, typical RAMP waveforms are explained with reference to (a) in fig. 2 and (b) in fig. 2. Fig. 2 (a) shows an example of a RAMP waveform for Correlated Double Sampling (CDS). The solid line represents the RAMP signal (RAMP) and the dashed line represents the pixel output at the reset level. The reset level and signal level are respectively sampled as follows: the first falling slope is used for AD conversion of the pixel output at the reset level, and the second falling slope is used for AD conversion of the pixel output at the signal level. CNTs are counted from the beginning of the first falling slope and until the first falling slope intersects the dashed line. The count value corresponds to a reset level. If there is no signal from the pixel, the signal level is the same as the reset level, i.e. the level of the dashed line does not change. CNTs are counted from the beginning of the second falling slope and counted until the second falling slope intersects the dashed line. If there is a signal from the pixel, the dashed line drops to a level corresponding to the signal amplitude below the reset level, and the CNT starts counting from the beginning of the second falling slope and counts until the second falling slope intersects the dashed line. The count value corresponds to the signal level. The output level is defined as the difference between the count value corresponding to the signal level and the count value corresponding to the reset level.

Fig. 2 (b) shows an example of a RAMP waveform for Correlated Multiple Sampling (CMS). To reduce temporal noise, the reset level is sampled three times, then the signal level is sampled three times, and accordingly the sampled values of the reset level and the sampled values of the signal level are averaged. The output level is defined as the difference between these average values. The number of sampling is not limited to three. Different numbers of samples are applicable. If the number of samples is 4, the temporal noise will be reduced to 1/(square root of 4) — 1/2. As can be seen from fig. 2 (a) and 2 (b), the time required for the CMS (fig. 2 (b)) is increased compared to the CDS (fig. 2 (a)).

Fig. 3 (a) to 3 (c4) show operation waveforms of the ACMS SS-ADC in a dark condition, i.e., in a condition where the level of the pixel output is relatively low. After the rising edge of the comparator output is generated, the analog input (i.e., pixel output) of the comparator is shifted, as indicated by the solid arrow. Thus, multiple edges of the comparator output can be obtained from one ramp signal for multiple sampling. Each count value of AD conversion of the reset level is stored separately. Next, each count value of the AD conversion of the reset level is subtracted from the corresponding AD conversion of the signal level. The level shift of the AD conversion of the signal level is the same as the level shift of the AD conversion of the reset level. CDS results for the corresponding level offsets are obtained and averaged. In this operation, the signal level is relatively low, and all CDS results of the ACMS SS-ADC are averaged in addition to all AD conversions that obtain the signal level corresponding to the AD conversion of the reset level. Different cases are explained with reference to (a) in fig. 4 to (c4) in fig. 4.

Fig. 3 (a) shows an example of a RAMP waveform of the ACMS SS-ADC. The solid line represents the RAMP signal (RAMP). With respect to the broken line in (a) in fig. 3, the first half represents the pixel output at the reset level, and the second half represents the pixel output at the small-signal level. In (a) in fig. 3, the small signal level is shown as if it is the same as the reset level. After the first falling slope of RAMP first intersects the horizontal dotted line, the level of the pixel output is shifted by a predetermined offset. The duration between the crossing and the shifting may be a delay in the circuit or may be a preset duration. The level of the pixel output becomes lower than the first falling slope, and the first falling slope of RAMP again intersects the horizontal dotted line. After the first falling slope of RAMP intersects the horizontal dashed line for the second time, the level of the pixel output is shifted by a predetermined offset. The level of the pixel output becomes lower than the first falling slope, and the first falling slope of RAMP again intersects the horizontal dotted line. After the first falling slope of RAMP intersects the horizontal broken line for the third time, the level of the pixel output is shifted by a predetermined offset. The level of the pixel output becomes lower than the first falling slope, and the first falling slope of RAMP again intersects the horizontal dotted line. Thus, the reset level is sampled 4 times.

After the first falling slope of RAMP ends, the level of the pixel output returns to the original reset level with no offset added. Before the second falling slope of RAMP starts, the pixel output changes from the reset level to the small signal level. In (a) in fig. 3, the small signal level is shown as if it is the same as the reset level. After the second falling slope of RAMP first intersects the horizontal broken line, the level of the pixel output is shifted by a predetermined offset. The level of the pixel output becomes lower than the second falling slope, and the second falling slope of RAMP again intersects the horizontal broken line. After the second falling slope of RAMP intersects the horizontal broken line for the second time, the level of the pixel output is shifted by a predetermined offset. The level of the pixel output becomes lower than the second falling slope, and the second falling slope of RAMP again intersects the horizontal broken line. After the second falling slope of RAMP intersects the horizontal broken line for the third time, the level of the pixel output is shifted by a predetermined offset. The level of the pixel output becomes lower than the second falling slope, and the second falling slope of RAMP again intersects the horizontal broken line. Thus, the signal level is sampled 4 times. After the second falling slope of RAMP ends, the level of the pixel output returns to the original signal level with no offset added.

The number of shifts is not limited to three. Different numbers of shifts are applicable. With respect to the above-described predetermined offset, the first offset, the second offset, and the third offset of the AD conversion of the reset level are the same as the first offset, the second offset, and the third offset, respectively, of the AD conversion of the signal level. However, the first offset, the second offset, and the third offset may not necessarily be the same.

Fig. 3 (b) shows an example of the comparator output of the pixel output at the reset level and the small-signal level (as indicated by the broken line in fig. 3 (a)). The pulse rises when the first falling slope of RAMP crosses the pixel output down and falls when the pixel output shifts at the first falling slope. After the fourth pulse rises, the pixel output does not shift down, and when the rising edge of RAMP intersects the dotted line, the pulse falls. A pulse corresponding to the second falling slope is similarly generated.

CNT counts from the beginning of the falling slope until the rising edge of the comparator output, as indicated by the dashed down arrow in (b) of fig. 3.

Fig. 3 (c1) to 3 (c4) show count values 1 to 4 output by the pixels in fig. 3 (a). In this case, the ACMS SS-ADC in FIG. 1 has four CNTs. Four CNTs are counted from the beginning of the first falling slope of RAMP. The first CNT count until a first pulse of the comparator output rises, the second CNT count until a second pulse of the comparator output rises, the third CNT count until a third pulse of the comparator output rises, and the fourth CNT count until a fourth pulse of the comparator output rises. The corresponding count value is converted to a negative number in the corresponding CNT. In another way of obtaining respective negative numbers corresponding to respective count values, four CNTs may be counted down from the beginning of the first falling slope of RAMP until the respective rising edge of the pulse of the comparator output, as shown by the dashed lines in (c1) in fig. 3 to (c4) in fig. 3.

Four CNTs are counted from the beginning of the second falling slope. The first CNT count until the fifth pulse of the comparator output rises, the second CNT count until the sixth pulse of the comparator output rises, the third CNT count until the seventh pulse of the comparator output rises, and the fourth CNT count until the eighth pulse of the comparator output rises. With the operation so far, for each count value of AD conversion of a signal level having each offset level, each CNT measures a difference between the count value and a count value of AD conversion of a reset level having the same offset level setting. The measured four values (i.e., the four count values output by the respective CNTs) are averaged to output a numerical value corresponding to the analog input of the ADC.

Fig. 4 (a) shows an example of a RAMP waveform of the ACMS SS-ADC. The solid line represents the RAMP signal (RAMP). In (a) in fig. 4, the pixel output has a large signal level, and the dotted line falls to a level corresponding to the signal amplitude below the reset level (indicated by a thick arrow in fig. 4). Therefore, the signal level is sampled twice, only two pulses of the comparator output corresponding to the second falling slope are generated, and the pulses of the comparator output are not generated to stop the counting by the third CNT and the fourth CNT. Accordingly, the first CNT and the second CNT successfully output the AD conversion result. Thus, although the reset level is sampled 4 times, only two count values are averaged.

Although the number of repetitions of multisampling decreases with increasing signal level amplitude, the disadvantage is limited because photon shot noise dominates over large signal areas. And the CMS is performed without the need for repeated generation of the ramp signal. Further, it is preferable to optimize the amplitude of the ramp signal and the combination of the offset level and the step size generated by the level shifter.

Fig. 5 shows a schematic block diagram of an ACMS SS-ADC provided by another embodiment of the present invention. Unlike fig. 1, an offset generated by a level shifter is added to a RAMP signal (RAMP).

Fig. 6 (a) shows another example of RAMP waveform of ACMS SS-ADC. The solid line represents the RAMP signal (RAMP). The portion of the original RAMP waveform shown in (a) of fig. 3 is also shown in dotted lines (portions of falling slope and rising edge). With respect to the horizontal broken line in (a) in fig. 6, the first half represents the pixel output at the reset level, and the second half represents the pixel output at the small-signal level. In (a) in fig. 6, the small signal level is shown as if it is the same as the reset level. After the first falling slope of RAMP intersects the horizontal dotted line, the level of the RAMP signal is shifted by a predetermined offset. The duration between the crossing and the shifting may be a delay in the circuit or may be a preset duration. The level of the pixel output becomes lower than the start of the second falling slope, which intersects the horizontal dotted line. After the second falling slope intersects the horizontal broken line, the level of the ramp signal is shifted by a predetermined offset. The level of the pixel output becomes lower than the start of the third falling slope, which intersects the horizontal dotted line. After the third falling slope intersects the horizontal broken line, the level of the ramp signal is shifted by a predetermined offset. The level of the pixel output becomes lower than the start of the fourth falling slope, which intersects the horizontal broken line. Thus, the reset level is sampled 4 times.

Before the start of the fifth falling slope, the pixel output changes from the reset level to the small-signal level. In (a) in fig. 6, the small signal level is shown as if it is the same as the reset level. After the fifth falling slope intersects the horizontal broken line, the level of the ramp signal is shifted by a predetermined offset. The level of the pixel output becomes lower than the start of a sixth falling slope, which intersects the horizontal broken line. After the sixth falling slope intersects the horizontal broken line, the level of the ramp signal is shifted by a predetermined offset. The level of the pixel output becomes lower than the start of a seventh falling slope, which intersects the horizontal broken line. After the seventh falling slope intersects the horizontal broken line, the level of the ramp signal is shifted by a predetermined offset. The level of the pixel output becomes lower than the start of an eighth falling slope which intersects the horizontal broken line. Thus, the signal level is sampled 4 times.

Fig. 6 (b) shows an example of the comparator output of a small signal level. The pulse rises when the falling slope of RAMP intersects the horizontal dashed line, and falls when the pixel output shifts above the level of the pixel output. After the fourth and eighth pulses rise, the pixel output does not shift, and when the rising edge of RAMP intersects the horizontal dashed line, the pulse falls. The CNTs operate in the same manner as described with reference to (c1) in fig. 3 to (c4) in fig. 3.

If the pixel output has a large signal level, the horizontal dotted line drops to a level corresponding to a signal amplitude below the reset level after the fourth falling slope ends. Waveforms of the comparator output and the count values 1 to 4 are the same as described with reference to (b) in fig. 4 and (c1) in fig. 4 to (c4) in fig. 4.

Fig. 7 shows an implementation of the level shifter shown in fig. 1, in which an offset is added to the pixel signal. An additional current source for the pixel source follower is implemented to generate the offset. As shown in FIG. 7, an additional current source is provided to control V of the amplifier transistor (not shown in FIG. 7)_gsThe amplifier transistor is provided, for example, between FD and SEL of the pixel source follower. By increasing the bias current, the output level is V_gsThe drop variation is cancelled out. By counting the number of comparator edges, the level shifter increases its setting by increasing the bias current per count.

Fig. 8 shows another implementation of the level shifter shown in fig. 1, in which an offset is added to the pixel signal. As a level shifter in fig. 1, a summing amplifier is implemented between a pixel source follower and a Comparator (CMP). If a Programmable Gain Amplifier (PGA) is implemented between the pixel source follower and the comparator, the ACMS SS-ADC can be implemented by implementing an adder function in the PGA, adding an offset to the output of the pixel source follower. The capacitance of the variable capacitor acts as an impedance, setting the offset step by step. The step size of the offset is adjusted by the ratio of the impedance or DC input of the capacitor to the additional port (a small rectangle to the left of the variable capacitor in fig. 8).

Fig. 9 illustrates one implementation of the level shifter shown in fig. 5, in which an offset is added to the ramp signal. The level shifter includes a plurality of current sources. A plurality of current sources are connected to a source follower, specifically, to the source of a P-channel Metal Oxide Semiconductor (PMOS) transistor, and to the non-inverting input of the comparator through a capacitor. The output terminal of the RAMP generator is connected to the gate of the PMOS transistor. A plurality of current sources modulate the voltage difference between the gate and the source in the PMOS transistor.

Fig. 10 shows another implementation of the level shifter shown in fig. 5, in which an offset is added to the ramp signal. The level shifter includes a summing amplifier of ramp signal levels and variable offset levels. In short, the circuit in fig. 8 including the summing amplifier between the pixel source follower and the inverting input terminal of the comparator is provided between the RAMP generator and the non-inverting input terminal of the comparator in fig. 10. The summing amplifier is not only used for the buffer amplifier of the ramp signal, but is also combined with a programmable gain amplifier.

The invention can be used for reducing the noise level of the CMOS image sensor. Under lower lighting conditions, the present invention halves the noise level by using 4 steps as the offset for the analog input, since the sampling is performed 4 times. In addition, this method also shortens the AD conversion period because the plural outputs of the comparator are obtained by one ramp signal.

The present invention can be used for fingerprint sensors in addition to CMOS image sensors, since the present invention works for single slope ADCs.

The effect of the above implementation of ACMS SS-ADC is as follows:

(1) the ADC time increase of CMS implementations can be suppressed.

(2) The CMS may be implemented using one common RAMP generator.

(3) The increase of the chip area is suppressed.

(4) There is no need to be concerned with the distortion of the RAMP waveform caused by the change in the connection of RAMP and comparator.

(5) There is no need to care about waveform matching.

The foregoing disclosure is only illustrative of the present invention and is, of course, not intended to limit the scope of the invention. It will be understood by those skilled in the art that all or part of the above-described embodiments may be implemented and equivalents thereof may be modified as required by the claims appended hereto.

Claims

1. A single slope analog to digital converter (SS-ADC), comprising:

a level shifter for adding one or more offset levels to an analog input during periods of respective AD conversions of a reset level and a signal level in response to an output of a comparator for comparing the analog input with a ramp signal step by step;

a counter for measuring, for each count value of the AD conversion of the signal level having each offset level, a difference between the count value and a count value of the AD conversion of the reset level having the same offset level setting, respectively;

a controller for averaging outputs of the counters that successfully output the AD conversion result.

2. The SS-ADC of claim 1 wherein said level shifter comprises a plurality of current sources connected to an output node of a pixel source follower.

3. The SS-ADC of claim 1 wherein said level shifter comprises a summing amplifier for said analog input and an offset voltage, said summing amplifier connected between a pixel source follower and said comparator.

4. An analog-to-digital (AD) conversion method, comprising:

adding one or more offset levels to the analog input during periods of respective AD conversions of a reset level and a signal level in response to an output of a comparator for stepwise comparing the analog input with a ramp signal;

for each count value of the AD conversion of the signal level having each offset level, measuring a difference between the count value and a count value of the AD conversion of the reset level having the same offset level setting, respectively;

averaging the outputs of the counters that successfully output the AD conversion results.

5. A single slope analog-to-digital converter (SS-ADC), comprising:

a level shifter for adding one or more offset levels to a ramp signal in a period of respective AD conversions of a reset level and a signal level in response to an output of a comparator for comparing an analog input with the ramp signal step by step;

6. The SS-ADC of claim 5 wherein said level shifter comprises a plurality of current sources connected to a source follower between an output of a ramp generator and said comparator.

7. The SS-ADC of claim 5 wherein said level shifter comprises a summing amplifier of a ramp signal level and a variable offset level, said summing amplifier connected between a ramp generator and said comparator, wherein said summing amplifier is not only used for a buffer amplifier of said ramp signal, but is also combined with a programmable gain amplifier.

8. An analog-to-digital (AD) conversion method, comprising:

adding one or more offset levels to a ramp signal in response to an output of a comparator for comparing an analog input with the ramp signal step by step, during periods of respective AD conversions of a reset level and a signal level;