JP2018148127A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which can improve connection reliability of a connection terminal.SOLUTION: A wiring board of the present disclosure comprises: a low thermal expansion rate substrate having a surface and a rear face; a wiring part arranged at least on the surface of the low thermal expansion rate substrate; an insulation resin layer having a surface and a rear face; and a low thermal expansion rate layer arranged on the surface of the insulation resin layer. The insulation resin layer is arranged in such a manner that the rear face covers the wiring part and part of the surface of the low thermal expansion rate substrate. The low thermal expansion rate layer forms an outermost layer. The low thermal expansion rate substrate and the low thermal expansion rate layer each is composed of a material having a thermal expansion rate not less than 0.1 ppm/K and not more than 12 ppm/K at a temperature within a range not less than 0°C and not more than 400°C. The wiring part has a connection terminal. The low thermal expansion rate layer has an opening from which the connection terminal is exposed. When the opening and the connection terminal are projected to a virtual plane perpendicular to a thickness direction of the low thermal expansion rate layer, a projection area of the opening is larger than a projection area of the connection terminal.SELECTED DRAWING: Figure 2

Description

  The present disclosure relates to a wiring board.

  2. Description of the Related Art As a wiring board used for an electric device, a circuit board in which a terminal for connection to the outside is arranged on the surface of a resin layer is known (see Patent Document 1). In the wiring board disclosed in Patent Document 1, swell and warp occur as the resin cures and shrinks. For this reason, with the recent miniaturization and high density of the wiring board, the flatness of the wiring board cannot be ignored, and the connection reliability is insufficient.

  Therefore, a wiring board using a substrate having a low coefficient of thermal expansion as a core base material has been proposed (see Patent Document 2).

JP 2008-300909 A JP 2014-236102 A

  In the wiring board of the above publication, when a plurality of low thermal expansion base materials are laminated with a resin layer and component terminals are connected to the wiring connection terminals by solder reflow or the like, the base material and the connection terminals or solder Difference in heat shrinkage occurs between the two. As a result, a large stress is applied to the solder and the connection terminals, and cracks are likely to occur in the connection portion such as solder.

  An object of one aspect of the present disclosure is to provide a wiring board capable of improving connection reliability in a connection terminal.

  One embodiment of the present disclosure includes a low thermal expansion coefficient substrate having a front surface and a back surface, a wiring portion disposed on at least the front surface of the low thermal expansion coefficient substrate, an insulating resin layer having a front surface and a back surface, and a surface of the insulating resin layer And a low thermal expansion layer disposed on the wiring board. The insulating resin layer is disposed so that the back surface covers part of the surface of the wiring portion and the low thermal expansion coefficient substrate. The low coefficient of thermal expansion layer constitutes the outermost layer. The low thermal expansion coefficient substrate and the low thermal expansion coefficient layer are each made of a material having a thermal expansion coefficient of 0.1 ppm / K or more and 12 ppm / K or less at 0 ° C. or more and 400 ° C. or less. The wiring part has a connection terminal. The low coefficient of thermal expansion layer has an opening that exposes the connection terminal. Further, when the opening and the connection terminal are projected onto a virtual plane perpendicular to the thickness direction of the low thermal expansion layer, the projected area of the opening is larger than the projected area of the connection terminal.

  According to such a configuration, since the outermost layer is composed of a low thermal expansion layer, the flatness of the surface of the wiring board is improved. Further, since the projected area of the opening exposing the connecting terminal is larger than the projected area of the connecting terminal, the connecting terminal and the outermost low thermal expansion coefficient layer are separated at least partially. Thereby, the stress due to the difference in thermal expansion coefficient at the time of solder connection is relieved, so that the connection reliability of the connection terminal is improved.

  In one aspect of the present disclosure, an insulating resin may be disposed around the connection terminal in the opening of the low thermal expansion coefficient layer. Further, the exposed surface of the insulating resin in the opening may be located on the inner side in the thickness direction than the outer surface of the low thermal expansion coefficient layer. According to such a configuration, the connection terminal and the low thermal expansion coefficient layer can be separated more reliably without causing the connection terminal to protrude from the low thermal expansion coefficient layer. Thereby, the relaxation of stress at the time of solder connection is promoted.

  In one aspect of the present disclosure, the exposed surface of the connection terminal in the opening is located on the inner side in the thickness direction with respect to the outer surface of the low thermal expansion coefficient layer and on the outer side in the thickness direction with respect to the exposed surface of the insulating resin. Good. According to such a configuration, the connection terminal has a convex shape protruding from the insulating resin. For this reason, solder is also connected to the side wall of the connection terminal during solder connection. Thereby, connection reliability is further improved.

  In one aspect of the present disclosure, the insulating resin in the opening may be a part of the insulating resin layer. According to such a configuration, the difference in thermal shrinkage between the insulating resin and the low thermal expansion layer is buffered by the insulating resin layer. As a result, the residual stress in the low thermal expansion coefficient layer can be reduced.

  In one aspect of the present disclosure, the connection terminal may not contact the inner wall of the opening of the low thermal expansion coefficient layer. According to such a configuration, since stress is not transmitted from the connection terminal to the low thermal expansion coefficient layer, the stress at the time of solder connection is more reliably relieved.

  In one embodiment of the present disclosure, an inorganic filler may be contained. According to such a configuration, the thermal expansion coefficient of the insulating resin layer can be reduced. As a result, relaxation of stress during solder connection is promoted.

  In one embodiment of the present disclosure, the average thickness of the low thermal expansion coefficient layer may be not less than 30 μm and not more than 100 μm. According to such a configuration, it is possible to achieve both miniaturization and securing of strength of the wiring board.

It is a typical sectional view showing a wiring board of an embodiment. 2A is a schematic partial enlarged cross-sectional view of the vicinity of the connection terminal in the wiring board of FIG. 1, and FIG. 2B is a schematic plan view of the vicinity of the connection terminal of the wiring board of FIG. 3A is a schematic cross-sectional view showing a process of the method for manufacturing the wiring board of FIG. 1, FIG. 3B is a schematic cross-sectional view showing a process subsequent to FIG. 3A, and FIG. 3D is a schematic cross-sectional view showing the next step of FIG. 3D, FIG. 3D is a schematic cross-sectional view showing the next step of FIG. 3C, and FIG. 3E is a schematic cross-sectional view showing the next step of FIG. FIG. 4A is a schematic cross-sectional view showing the next step of FIG. 3E, FIG. 4B is a schematic cross-sectional view showing the next step of FIG. 4A, and FIG. 4C is the next step of FIG. 4B. It is a typical sectional view showing. FIG. 5 is a schematic cross-sectional view showing a wiring board according to an embodiment different from FIG.

Hereinafter, embodiments to which the present disclosure is applied will be described with reference to the drawings.
[1. First Embodiment]
[1-1. Constitution]
A wiring board 1 shown in FIG. 1 includes one low thermal expansion coefficient substrate 2, a pair of front and back wiring portions 3A and 3B, a pair of front and back insulating resin layers 4A and 4B, and a pair of front and back low thermal expansion coefficient layers 5A. , 5B.

<Low thermal expansion coefficient substrate>
The low coefficient of thermal expansion substrate 2 has a front surface and a back surface. The low thermal expansion substrate 2 is made of a material having a thermal expansion coefficient of 0.1 ppm / K or more and 12 ppm / K or less (hereinafter also referred to as “low thermal expansion coefficient material”) at 0 ° C. or more and 400 ° C. or less. .

  The low coefficient of thermal expansion material has, for example, glass or ceramics as a main component. Here, the “main component” means a component containing 90% by mass or more. Examples of the glass or ceramic constituting the low thermal expansion coefficient substrate 2 include quartz glass, alkali-free glass, alkali glass, crystallized glass, borosilicate glass, glass ceramic, and alumina ceramic.

  The lower limit of the average thickness of the low thermal expansion coefficient substrate 2 is preferably 30 μm and more preferably 100 μm. On the other hand, the upper limit of the average thickness of the low thermal expansion coefficient substrate 2 is preferably 1100 μm, and more preferably 700 μm. When the average thickness of the low thermal expansion coefficient substrate 2 is smaller than the above lower limit, the strength may be insufficient. Conversely, if the average thickness of the low thermal expansion coefficient substrate 2 exceeds the above upper limit, the thickness of the wiring substrate 1 may become unnecessarily large.

  As shown in FIG. 1, the low thermal expansion coefficient substrate 2 is provided with one or more through holes 13. The through hole 13 penetrates the low thermal expansion coefficient substrate 2 in the thickness direction. A through conductor is disposed on the inner peripheral surface of the through hole 13, and the front side wiring portion 3 </ b> A and the back side wiring portion 3 </ b> B are electrically connected by the through conductor.

  The lower limit of the diameter of the through hole 13 is preferably 30 μm, and more preferably 50 μm. On the other hand, the upper limit of the diameter of the through hole 13 is preferably 1000 μm, and more preferably 500 μm.

<Wiring section>
Of the pair of wiring portions 3 </ b> A and 3 </ b> B, the front wiring portion 3 </ b> A is disposed on the surface of the low thermal expansion coefficient substrate 2, and the back wiring portion 3 </ b> B is disposed on the back surface of the low thermal expansion coefficient substrate 2.

  Each of the pair of wiring portions 3 </ b> A and 3 </ b> B includes one or more connection terminals 12, a via conductor 14, and a wiring pattern portion 15. The connection terminals 12 are electrode pads (that is, land portions) for connecting external terminals and the like with solder.

  As shown in FIG. 1, the connection terminal 12 of the front side wiring portion 3A is disposed on the surface of the front side insulating resin layer 4A. Further, the surface of the connection terminal 12 is exposed to the outside through the opening 11 provided in the front side low thermal expansion coefficient layer 5A. The connection terminal 12 is connected to the wiring pattern portion 15 of the front-side wiring portion 3A by a via conductor 14 that penetrates the front-side insulating resin layer 4A in the thickness direction. The configuration of the back side wiring part 3B is the same as that of the front side wiring part 3A.

  The planar shape of the connection terminal 12 is not particularly limited, and may be a polygonal shape such as a rectangle other than the circular shape shown in FIG. 2B. In addition, when making the planar shape of the terminal 12 for connection into a polygonal shape, it is good to chamfer a corner | angular.

  The pair of wiring portions 3A and 3B including the connection terminal 12 and the via conductor 14 have conductivity and contain metal as a main component. Examples of the metal include copper, silver, gold, platinum, nickel, titanium, aluminum, chromium, and alloys thereof. Among these, copper is preferable from the viewpoints of cost and conductivity.

<Insulating resin layer>
Of the pair of insulating resin layers 4A and 4B, the front-side insulating resin layer 4A is disposed on the surface of the wiring pattern portion 15 of the front-side wiring portion 3A opposite to the low thermal expansion coefficient substrate 2, and the back-side insulating resin layer 4B is The wiring pattern portion 15 of the back wiring portion 3B is disposed on the surface opposite to the low thermal expansion coefficient substrate 2.

  The front side insulating resin layer 4A has a front surface and a back surface. 4 A of front side insulating resin layers are arrange | positioned so that a back surface may cover the wiring pattern part 15 of the front side wiring part 3A, and the part in which the front side wiring part 3A is not arrange | positioned among the surfaces of the low thermal expansion coefficient board | substrate 2. . The back-side insulating resin layer 4B is configured by arranging the front-side insulating resin layer 4A substantially symmetrically with respect to the low thermal expansion coefficient substrate 2, and has the same configuration as the front-side insulating resin layer 4A.

  The pair of insulating resin layers 4A and 4B are mainly composed of an insulating resin and an inorganic filler. Examples of the insulating resin include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins, and thermoplastic resins such as cycloolefin resins, polycarbonate resins, acrylic resins, polyacetal resins, and polypropylene resins. Can be used. In addition, composite materials of these resins and inorganic fibers such as glass fibers or organic fibers such as polyamide fibers (for example, woven fabric and nonwoven fabric) can also be used. Furthermore, a composite material in which a three-dimensional network fluorine-based resin base material such as continuous porous polytetrafluoroethylene (PTFE) is impregnated with a thermosetting resin such as an epoxy resin can also be used.

  Inorganic fillers include silica, barium sulfate, silicon oxide, calcined talc, zinc oxide talc, barium titanate, titanium oxide, clay, alumina, mica, boehmite, zinc borate, zinc stannate, and other metal oxides Alternatively, metal hydrate, aluminum hydroxide, calcium carbonate, magnesium hydroxide, magnesium silicate, glass fiber, aluminum borate whisker, silicon carbonate whisker, or the like can be used. These inorganic fillers may be used alone or in combination of two or more. Of these inorganic fillers, those containing silica as the main component are preferred.

  The shape and size of the inorganic filler are not particularly limited, and inorganic fillers of different sizes can be used in combination. Furthermore, the inorganic filler may be surface-treated with a coupling agent or the like.

  In each of the pair of insulating resin layers 4A and 4B, the content ratio of the inorganic filler to the resin is preferably 40 parts by mass or more and 80 parts by mass or less with respect to 100 parts by mass of the resin. When content of an inorganic filler is smaller than the said minimum, there exists a possibility that the thermal expansion rate reduction effect may become inadequate. Conversely, if the content of the inorganic filler exceeds the above upper limit, the moldability of the insulating resin layer may be reduced.

  The pair of insulating resin layers 4 </ b> A and 4 </ b> B is preferably thinner than the low thermal expansion coefficient substrate 2. By doing in this way, the residual stress in the low thermal expansion coefficient board | substrate 2 can be reduced. The thickness of the pair of insulating resin layers 4A and 4B means the distance from the front or back surface of the low thermal expansion coefficient substrate 2 to the back surface of the pair of low thermal expansion coefficient layers 5A and 5B.

  The lower limit of the average thickness of each of the pair of insulating resin layers 4A and 4B is preferably 10 μm, and more preferably 15 μm. On the other hand, the upper limit of the average thickness of each of the pair of insulating resin layers 4A and 4B is preferably 500 μm, and more preferably 100 μm. If the average thickness of the pair of insulating resin layers 4A and 4B is smaller than the lower limit, the bonding strength between the pair of low thermal expansion layers 5A and 5B and the low thermal expansion substrate 2 may be insufficient. Conversely, if the average thickness of the pair of insulating resin layers 4A and 4B exceeds the above upper limit, there is a risk that the reduction of residual stress in the low thermal expansion coefficient substrate 2 will be insufficient.

<Low thermal expansion layer>
Of the pair of low thermal expansion layers 5A and 5B, the front side low thermal expansion layer 5A is arranged on the surface of the front side insulating resin layer 4A, and the back side low thermal expansion coefficient layer 5B is arranged on the surface of the back side insulating resin layer 4B. ing.

  The pair of low thermal expansion coefficient layers 5 </ b> A and 5 </ b> B is made of the same low thermal expansion coefficient material as that of the low thermal expansion coefficient substrate 2. The material of the pair of low thermal expansion coefficient layers 5A and 5B and the low thermal expansion coefficient substrate 2 may be different.

  The front side low thermal expansion layer 5A has a front surface and a back surface. The front side low thermal expansion layer 5 </ b> A constitutes the outermost layer on one side of the wiring substrate 1, and the surface thereof is one outermost surface of the wiring substrate 1. The front side low thermal expansion layer 5A has one or more openings 11 penetrating in the thickness direction. In the opening 11, the connection terminal 12 is exposed. The back side low thermal expansion coefficient layer 5B is configured by arranging the front side low thermal expansion coefficient layer 5A substantially symmetrically with respect to the low thermal expansion coefficient substrate 2, and has the same configuration as the front side low thermal expansion coefficient layer 5A.

  The thickness of the pair of low thermal expansion coefficient layers 5 </ b> A and 5 </ b> B is preferably the same as the thickness of the low thermal expansion coefficient substrate 2 or smaller than the thickness of the low thermal expansion coefficient substrate 2. In addition, the lower limit of the average thickness of each of the pair of low thermal expansion layers 5A and 5B is preferably 30 μm, and more preferably 40 μm. On the other hand, the upper limit of the average thickness of each of the pair of low thermal expansion layers 5A and 5B is preferably 100 μm, and more preferably 80 μm. If the average thickness of the pair of low thermal expansion layers 5A and 5B is smaller than the lower limit, the strength may be insufficient. Conversely, if the average thickness of the pair of low thermal expansion coefficient layers 5A and 5B exceeds the above upper limit, the thickness of the wiring board 1 may become unnecessarily large.

  Moreover, as a minimum of the diameter of the opening 11, 100 micrometers is preferable and 200 micrometers is more preferable. On the other hand, the upper limit of the diameter of the opening 11 is preferably 1000 μm, and more preferably 600 μm.

<Relationship between opening and connection terminal>
As shown in FIGS. 2A and 2B, when the opening 11 and the connection terminal 12 are projected onto a virtual plane perpendicular to the thickness direction of the front side low thermal expansion layer 5A or the back side low thermal expansion layer 5B, the projected area of the opening 11 is It is larger than the projected area of the connection terminal 12.

  In the present embodiment, the connection terminal 12 does not contact the inner wall of the opening 11 of the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B. That is, the connection terminal 12 and the opening 11 are separated from each other in plan view (that is, viewed from the thickness direction).

  The average distance D between the connection terminal 12 and the inner wall of the opening 11 is, for example, not less than 10 μm and not more than 100 μm. If the average interval is smaller than the lower limit, the solder may not contact the side wall of the connection terminal 12. Conversely, if the average interval exceeds the upper limit, the diameter of the opening 11 may become unnecessarily large. The average distance D is a value obtained by averaging the shortest distance between the side wall of the connection terminal 12 and the inner wall of the opening 11 over the entire outer periphery of the connection terminal 12.

  Further, in this embodiment, as shown in FIGS. 2A and 2B, an insulating resin 17 is disposed around the connection terminal 12 in the opening 11 of the front side low thermal expansion coefficient layer 5A and the back side low thermal expansion coefficient layer 5B. . The insulating resin 17 is one in which a part of the front side insulating resin layer 4 </ b> A or the back side insulating resin layer 4 </ b> B enters the opening 11.

  In the opening 11, the exposed surface of the insulating resin 17 (that is, the surface opposite to the low thermal expansion coefficient substrate 2) is more in the thickness direction than the surface (that is, the outer surface) of the front side low thermal expansion coefficient layer 5 A or the back side low thermal expansion coefficient layer 5 B. Located inside. Further, in the opening 11, the exposed surface of the connection terminal 12 is located on the inner side in the thickness direction than the surface of the front side low thermal expansion coefficient layer 5 </ b> A or the back side low thermal expansion coefficient layer 5 </ b> B and is thicker than the exposed surface of the insulating resin 17. Located outside in the direction.

  That is, in the opening 11, from the outside in the thickness direction, the surface of the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B, the exposed surface of the connection terminal 12, and the exposed surface of the insulating resin 17 (that is, the front side insulating resin layer 4A or It is arranged in the order of the surface of the back side insulating resin layer 4B.

  With such a configuration, the side wall of the connection terminal 12 is exposed in the opening 11. Therefore, as shown in FIG. 2A, the solder 20 contacts not only the surface of the connection terminal 12 but also the side wall. Thereby, the crack tolerance of the solder 20 is increased and the connection reliability is improved.

  In addition, as shown to FIG. 2A, the opening 11 is diameter-reduced toward the low thermal expansion coefficient board | substrate 2 side (upper side in a figure). The insulating resin 17 is formed so that the thickness increases as it approaches the inner wall of the opening 11 from the center side of the opening 11. That is, the exposed surface of the insulating resin 17 is a curved surface having a recessed central portion with respect to the outside of the wiring substrate 1. Since the opening 11 and the insulating resin 17 have such shapes, workability in solder connection is improved and the shape of the solder is stabilized.

[1-2. Production method]
Next, a method for manufacturing the wiring board 1 will be described.
The manufacturing method of the wiring board 1 includes a wiring pattern portion arranging step, a laminated body arranging step, a connection terminal arranging step, and a blade cutting step.

<Wiring pattern section installation process>
In this step, first, as shown in FIG. 3A, a low thermal expansion coefficient substrate 2 provided with a through hole is prepared. Next, as shown in FIG. 3B, the wiring pattern portions 15 of the front-side wiring portion 3A and the back-side wiring portion 3B are disposed on the front surface and the back surface of the low thermal expansion coefficient substrate 2, respectively.

  The arrangement of the wiring pattern portion 15 can be performed by a known method such as a subtractive method, a semi-additive method, or a full additive method. Specifically, for example, the wiring pattern portion 15 is formed by etching a copper foil or printing a conductive paste. The copper foil can be formed by sputtering, chemical vapor deposition (CVD), electroless copper plating, electrolytic copper plating, or the like.

<Laminated body arrangement process>
In this step, first, as shown in FIG. 3C, a pair of insulating resin layers 4A and 4B are disposed so as to cover the wiring pattern portion 15 on both the front and back sides of the low thermal expansion coefficient substrate 2 on which the wiring pattern portion 15 is disposed. . Further, as shown in FIG. 3D, the pair of low thermal expansion layers 5A and 5B provided with the openings 11 are disposed outside the pair of insulating resin layers 4A and 4B.

  The pair of insulating resin layers 4A and 4B and the pair of low thermal expansion layers 5A and 5B are laminated by vacuum bonding while heating. Moreover, after bonding, these laminated bodies are further heated to thermally cure the pair of insulating resin layers 4A and 4B. Alternatively, a pair of low thermal expansion layers 5A and 5B may be laminated on the pair of insulating resin layers 4A and 4B, respectively, and then the laminate may be attached to the low thermal expansion coefficient substrate 2.

  By this step, a part of the pair of insulating resin layers 4A and 4B (that is, the insulating resin 17 in FIG. 2B) enters the opening 11 of the pair of low thermal expansion layers 5A and 5B. When a part of the pair of insulating resin layers 4A and 4B is flush with or protrudes from the outer surface of the pair of low thermal expansion coefficient layers 5A and 5B (that is, when the opening 11 is buried). Thin this part by laser processing or desmear.

<Connecting terminal arrangement process>
In this step, first, as shown in FIG. 3E, a via 16 is formed in a portion overlapping the opening 11 of the pair of thermally cured insulating resin layers 4A and 4B. The via 16 penetrates the pair of insulating resin layers 4A and 4B in the thickness direction, and can be formed by, for example, a laser drill.

  Next, as shown in FIG. 4A, resist patterns 6 are formed on the surfaces of the pair of low thermal expansion layers 5A and 5B by photolithography. The resist pattern 6 covers the inner walls of the openings 11 of the pair of low thermal expansion layers 5A and 5B.

  Further, as shown in FIG. 4B, the via conductor 14 is filled in the via 16 by plating or the like, and the connection terminal 12 is formed thereon. At this time, the connection terminal 12 is formed inside the resist pattern 6 in the via 16. Thereafter, when the resist pattern 6 is removed, as shown in FIG. 4C, the connection terminals 12 separated from the pair of low thermal expansion layers 5A and 5B are obtained.

  Note that the connection terminal 12 is preferably subjected to surface plating such as nickel, palladium, or gold. Further, the surface of the pair of low thermal expansion coefficient layers 5A and 5B may be formed by plasma treatment or the like.

<Blade cutting process>
Although not shown, a multi-piece substrate (so-called mother board) including a plurality of wiring boards 1 is formed by the above-described process.

  Therefore, in this process, the low thermal expansion coefficient substrate 2, the pair of insulating resin layers 4A and 4B, and the laminated portion of the pair of insulating resin layers 4A and 4B are cut in the thickness direction by a blade (for example, a dicer). Thereby, the separated wiring board 1 is obtained.

[1-3. effect]
According to the embodiment detailed above, the following effects can be obtained.
(1a) Since the outermost layer is composed of a pair of low thermal expansion coefficient layers 5A and 5B, the flatness of the surface of the wiring board 1 is enhanced and the stress relating to the solder connection portion is relaxed. Further, since the projected area of the opening 11 exposing the connecting terminal 12 onto the virtual plane is larger than the projected area of the connecting terminal 12, the pair of low thermal expansion layers 5 </ b> A that are the outermost layer with the connecting terminal 12. , 5B are at least partially separated from each other. Thereby, the stress due to the difference in thermal expansion coefficient at the time of solder connection is relieved. As a result, the connection reliability of the connection terminal 12 is improved.

(1b) Since the insulating resin 17 is disposed around the connection terminal 12 in the opening 11, the connection terminal 12 is stably fixed.
Moreover, the exposed surface of the insulating resin 17 in the opening 11 is located on the inner side in the thickness direction than the outer surface of the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B. Therefore, the connection terminal 12 and the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B are more reliably separated without protruding the connection terminal 12 from the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B. it can. Thereby, the relaxation of stress at the time of solder connection is promoted.

  (1c) The exposed surface of the connection terminal 12 in the opening 11 is located on the inner side in the thickness direction than the outer surface of the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B and is thicker than the exposed surface of the insulating resin 17. Located outside in the direction. Thereby, the connection terminal 12 has a convex shape protruding from the insulating resin 17. Therefore, solder is also connected to the side wall of the connection terminal 12 at the time of solder connection, and connection reliability is further improved.

  (1d) The insulating resin 17 in the opening 11 is a part of the front-side insulating resin layer 4A or the back-side insulating resin layer 4B. Therefore, the difference in thermal shrinkage between the insulating resin 17 and the front side low thermal expansion layer 5A or the back side low thermal expansion layer 5B is buffered by the front side insulating resin layer 4A or the back side insulating resin layer 4B. As a result, the residual stress in the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B can be reduced.

  (1e) The connection terminal 12 does not contact the inner wall of the opening 11 of the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B. Thereby, since stress is not transmitted from the connection terminal 12 to the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B, the stress at the time of solder connection is more reliably relieved. Further, the contact area between the connection terminal 12 and the solder can be increased.

  (1f) Since the pair of insulating resin layers 4A and 4B each contain an inorganic filler, the coefficient of thermal expansion is reduced. As a result, the difference in thermal expansion coefficient between the pair of insulating resin layers 4A and 4B and the low thermal expansion coefficient substrate 2 and the pair of low thermal expansion coefficient layers 5A and 5B is reduced, and stress relaxation during solder connection is promoted. Is done.

[2. Other Embodiments]
As mentioned above, although embodiment of this indication was described, it cannot be overemphasized that this indication can take various forms, without being limited to the above-mentioned embodiment.

  (2a) In the wiring substrate 1 of the above embodiment, the wiring portions do not necessarily have to be provided on both surfaces of the low thermal expansion coefficient substrate 2. That is, the wiring board 1 may be a single-sided board in which wiring parts are arranged only on the surface of the low thermal expansion coefficient board 2.

  (2b) Conversely, the wiring board 1 of the above embodiment may have a multilayer structure of three or more layers. A wiring substrate 101 shown in FIG. 5 is an example of such a multilayer structure. In addition to the configuration of the wiring substrate 1, the wiring substrate 101 is arranged on the outer side of the pair of low thermal expansion layers 5A and 5B, respectively, and the pair of second insulating resin layers 104A and 104B, and the pair of second insulating resin layers 104A and 104B. 2 It has low thermal expansion coefficient layers 105A and 105B.

  In the wiring board 101, the pair of second low thermal expansion layers 105A and 105B constitute the outermost layer. Further, the connection terminals 112 of the pair of wiring portions 3A and 3B are exposed in the openings 111 provided in the pair of second low thermal expansion layers 105A and 105B, respectively.

  The connection terminal 112 is connected to the connection portion 113 corresponding to the connection terminal 12 of the wiring board 1 of FIG. 1 by a second via conductor 114 that penetrates the pair of second insulating resin layers 104A and 104B.

  (2c) In the wiring board 1 of the above embodiment, the insulating resin 17 does not necessarily have to be disposed around the connection terminal 12 in the opening 11. That is, the insulating resin 17 may not be present in the opening 11.

Further, when the insulating resin 17 is disposed in the opening 11, the exposed surface of the insulating resin 17 may be located outside the outer surface of the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B.
Furthermore, the insulating resin 17 may not be part of the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B.

  (2d) In the wiring substrate 1 of the above embodiment, the exposed surface of the connection terminal 12 may be located outside the outer surface of the front side low thermal expansion coefficient layer 5A or the back side low thermal expansion coefficient layer 5B, or the insulating resin 17 It may be located inside the exposed surface.

  (2e) In the wiring substrate 1 of the above embodiment, if the projected area of the opening 11 onto the virtual plane is larger than the projected area of the connecting terminal 12, a part of the connecting terminal 12 contacts the inner wall of the opening 11. May be.

  (2f) The functions of one component in the above embodiment may be distributed as a plurality of components, or the functions of a plurality of components may be integrated into one component. Moreover, you may abbreviate | omit a part of structure of the said embodiment. In addition, at least a part of the configuration of the above embodiment may be added to or replaced with the configuration of the other embodiment. In addition, all the aspects included in the technical idea specified from the wording described in the claims are embodiments of the present disclosure.

[3. Example]
Hereinafter, a comparison between Example 1 and Comparative Examples 1 and 2 performed to confirm the effect of the present disclosure will be described.

Example 1
A wiring substrate 1 shown in FIG. 1 was produced. The low coefficient of thermal expansion substrate 2 was a glass substrate having a 300 mm square and an average thickness of 300 μm. The pair of wiring portions 3A and 3B were formed by performing electroless copper plating and electrolytic copper plating on the low thermal expansion coefficient substrate 2, and then performing photolithography and etching.

  As the pair of insulating resin layers 4A and 4B, an ABF film (manufactured by Ajinomoto Fine Techno Co., Ltd.) having an average thickness of 30 μm was used. The pair of low thermal expansion coefficient layers 5A and 5B were glass plates each having a 300 mm square and an average thickness of 50 μm. In addition, the wiring board 1 was separated into pieces using the dicer with respect to the mother board | substrate which laminated | stacked the said member.

  For this wiring board 1, a solder layer was formed on the connection terminals 12 by printing. Thereafter, electronic components were placed on the wiring board 1 and the terminals of the electronic components were electrically connected to the connection terminals 12 by solder reflow.

  Thus, the thermal shock test was done with respect to the wiring board 1 which mounted the electronic component. Specifically, the temperature cycle from −65 ° C. to 150 ° C. was repeated 500 cycles. After the test, no cracks were found in the solder at the connection.

(Comparative Example 1)
In the wiring board 1, a wiring board provided with a pair of cover layers with a solder resist instead of the pair of low thermal expansion coefficient layers 5A and 5B was produced. In addition, electronic components were mounted on this wiring board in the same manner as in Example 1.

  A thermal shock test similar to that of Example 1 was performed on the wiring board after mounting the electronic component. As a result, cracks were found in the solder at some of the connection terminals. This is thought to be due to the fact that the expansion and contraction of the cover layer due to temperature change is increased because the solder resist has a coefficient of thermal expansion of 70 ppm / K and is larger than the coefficient of thermal expansion of 3.3 ppm / K. In addition, the low flatness of the cover layer increases the stress at the solder connection portion, and the partial reduction in the amount of solder is considered to be a cause of the crack.

(Comparative Example 2)
In the wiring board 1, a wiring board in which the projected area of the opening 11 on the virtual plane and the projected area of the connection terminal 12 were equal was manufactured. In addition, electronic components were mounted on this wiring board in the same manner as in Example 1.

  A thermal shock test similar to that of Example 1 was performed on the wiring board after mounting the electronic component. As a result, terminal peeling of the electronic component from the connection terminal was observed. In Comparative Example 2, the copper connection terminal, the glass low thermal expansion layer, and the solder are in contact with each other. Moreover, the thermal expansion coefficient of copper and solder is about 18 ppm / K, and the difference from the thermal expansion coefficient of glass is large. Therefore, it is considered that a large stress is applied to the solder connection portion and the terminal is peeled off.

DESCRIPTION OF SYMBOLS 1 ... Wiring board, 2 ... Low thermal expansion coefficient board, 3A ... Front side wiring part, 3B ... Back side wiring part,
4A ... front side insulating resin layer, 4B ... back side insulating resin layer, 5A ... front side low thermal expansion coefficient layer,
5B: Back side low thermal expansion coefficient layer, 6 ... Resist pattern, 11 ... Opening, 12 ... Terminal for connection,
13 ... through hole, 14 ... via conductor, 15 ... wiring pattern part, 16 ... via,
17 ... insulating resin, 20 ... solder, 101 ... wiring board,
104A, 104B ... second insulating resin layer, 105A, 105B ... second low thermal expansion layer,
111 ... Opening, 112 ... Connecting terminal, 113 ... Connecting portion, 114 ... Second via conductor.

Claims (7)

A low coefficient of thermal expansion substrate having a front surface and a back surface;
A wiring portion disposed on at least a surface of the low thermal expansion coefficient substrate;
An insulating resin layer having a front surface and a back surface, the back surface being disposed so as to cover a part of the surface of the wiring portion and the low thermal expansion coefficient substrate;
A low thermal expansion layer disposed on the surface of the insulating resin layer and constituting the outermost layer;
With
The low thermal expansion substrate and the low thermal expansion layer are each composed of a material having a thermal expansion coefficient of 0.1 ppm / K or more and 12 ppm / K or less at 0 ° C. or more and 400 ° C. or less,
The wiring portion has a connection terminal,
The low coefficient of thermal expansion layer has an opening that exposes the connection terminal;
When the opening and the connection terminal are projected onto a virtual plane perpendicular to the thickness direction of the low thermal expansion layer, the projected area of the opening is larger than the projected area of the connection terminal. In the opening of the low coefficient of thermal expansion layer, an insulating resin is disposed around the connection terminal,
The wiring board according to claim 1, wherein an exposed surface of the insulating resin in the opening is located on an inner side in a thickness direction than an outer surface of the low thermal expansion coefficient layer.   The exposed surface of the connection terminal in the opening is located on the inner side in the thickness direction than the outer surface of the low thermal expansion coefficient layer, and is located on the outer side in the thickness direction than the exposed surface of the insulating resin. The wiring board described.   The wiring board according to claim 2, wherein the insulating resin in the opening is a part of the insulating resin layer.   The wiring board according to claim 1, wherein the connection terminal does not contact an inner wall of the opening of the low thermal expansion coefficient layer.   The wiring board according to claim 1, wherein the insulating resin layer contains an inorganic filler.   The wiring board according to any one of claims 1 to 6, wherein an average thickness of the low thermal expansion coefficient layer is not less than 30 µm and not more than 100 µm.