JP2018139465A - Dc/ac inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress power loss of a DC/AC inverter.SOLUTION: A DC/AC inverter relating to one embodiment according to the present invention inputs a DC voltage via a first input terminal and a second input terminal, and outputs an AC voltage generated by converting the DC voltage, via a first output terminal and a second output terminal. The DC/AC inverter comprises a first transistor, a second transistor, a reactor, a current detection circuit, and a drive control circuit. The reactor is inserted between a node between the first transistor and the second transistor, and the first output terminal. The current detection circuit detects a reactor current flowing toward the first output terminal from the reactor. The drive control circuit controls each of the first transistor and the second transistor in such a manner that the reactor current crosses zero at least two times in a switching period of the first transistor.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a DC / AC inverter.

  In order to generate AC power from DC power, a DC (Direct Current) / AC (Alternative Current) inverter is used. The DC / AC inverter includes two FETs (Field Effect Transistors) connected in series (which are also referred to as an upper arm and a lower arm, respectively). The upper arm and the lower arm repeat ON / OFF alternately. However, in order to prevent a short circuit between the upper and lower arms, there is a dead time during which both the upper and lower arms are turned off between the time when one arm changes from ON to OFF and the time when the other arm changes from OFF to ON. It has been.

  For example, it is assumed that a current flows through the body (parasitic) diode of the lower arm during the dead time (that is, the body diode is ON). In this case, it is necessary for the upper arm to charge the output capacity (Coss) of the lower arm after transition from OFF to ON, resulting in power loss. In this case, a recovery current flows through the body diode of the lower arm. In addition to causing power loss, the recovery current instantaneously changes the current greatly, which may increase noise and damage the lower arm.

JP 2013-115933 A

  An object of this invention is to suppress the power loss of a DC / AC inverter.

  A DC / AC inverter according to one embodiment of the present invention inputs a DC voltage via a first input terminal and a second input terminal and converts an AC voltage generated by converting the DC voltage into a first output terminal. And output via the second output terminal. The DC / AC inverter includes a first transistor, a second transistor, a reactor, a current detection circuit, and a drive control circuit. The first transistor includes a first terminal, a second terminal, and a control terminal, and the first terminal is connected to the first input terminal. The second transistor includes a first terminal, a second terminal, and a control terminal, the first terminal is connected to the first terminal of the first transistor, and the second terminal is connected to the second input terminal. Connected. The reactor is inserted between a node between the first transistor and the second transistor and the first output terminal. The current detection circuit detects a reactor current flowing from the reactor toward the first output terminal. The drive control circuit controls the first transistor and the second transistor so that the reactor current zero-crosses at least twice within the switching period of the first transistor.

  According to the present invention, power loss of a DC / AC inverter can be suppressed.

1 is a block diagram illustrating a DC / AC inverter according to a first embodiment. FIG. 2 is a block diagram illustrating a drive control circuit in FIG. 1. FIG. 3 is a block diagram illustrating the event detection circuit of FIG. 2. The block diagram which illustrates the basic circuit of a DC / AC inverter. The graph which shows the output voltage of the DC / AC inverter of FIG. 4, a reactor current, and an output current. The graph which shows the output voltage of the DC / AC inverter of FIG. 1, a reactor current, and an output current. The figure which illustrates the equivalent circuit of the DC / AC inverter in dead time. The graph which illustrates the relationship between the output capacitance of a super junction FET, and the drain-source voltage. The graph which illustrates the behavior of FET 102-4 as a super junction FET. FIG. 4 is an explanatory diagram of events detected by the event detection circuit of FIG. 3.

  Hereinafter, embodiments will be described with reference to the drawings. Hereinafter, the same or similar elements as those already described are denoted by the same or similar reference numerals, and redundant description is basically omitted. For example, when there are a plurality of identical or similar elements, a common reference may be used to explain each element without distinction, and the common reference may be used to distinguish each element. In addition, branch numbers may be used.

(First embodiment)
FIG. 4 illustrates a basic circuit of a full bridge DC / AC inverter. Although the DC / AC inverter of FIG. 4 does not have a mechanism for suppressing power loss, which will be described later, the basic operation principle is common to the DC / AC inverter according to the first embodiment.

  The DC / AC inverter of FIG. 4 inputs a DC voltage (Vin) from the DC voltage source 201 via a first input terminal and a second input terminal (for example, grounded), and converts the DC voltage. Is output to the load 206 (RL) via the first output terminal and the second output terminal. For example, the DC voltage source 201 may be a solar cell module (panel). As described above, when the load 206 (RL) is a pure resistance or a power system (during reverse power flow), the output current (Io) of the DC / AC inverter is in phase with the output voltage (Vo). Therefore, if the output current (Io) is controlled, the output voltage (Vo) can also be controlled at the same timing.

  The DC / AC inverter in FIG. 4 includes an FET 202-1, an FET 202-2, an FET 202-3, an FET 202-4, a reactor 204, and a capacitor 205.

  The FET 202-1 has a drain terminal connected to the first input terminal of the DC / AC inverter, a gate terminal connected to a drive circuit (not shown), and a source terminal connected to the second output terminal of the DC / AC inverter. Connected to. The FET 202-1 receives a drive signal from the drive circuit via the gate terminal, and is turned ON / OFF by the drive signal.

  The FET 202-2 has a drain terminal connected to the second output terminal of the DC / AC inverter, a gate terminal connected to a drive circuit (not shown), and a source terminal connected to the second input terminal of the DC / AC inverter. (Eg, grounded). The FET 202-2 receives a drive signal from the drive circuit via the gate terminal, and is turned ON / OFF by the drive signal.

  The FET 202-3 has a drain terminal connected to the first input terminal of the DC / AC inverter, a gate terminal connected to a drive circuit (not shown), and a source terminal connected to the DC / DC via the reactor 204 (L1). Connected to the first output terminal of the AC inverter. The FET 202-3 receives a drive signal from the drive circuit via the gate terminal, and is turned ON / OFF by the drive signal.

  The FET 202-4 has a drain terminal connected to the first output terminal of the DC / AC inverter via the reactor 204 (L1), a gate terminal connected to a drive circuit (not shown), and a source terminal connected to the DC / AC. Connected to the second input terminal of the AC inverter (eg, grounded). The FET 202-4 receives a drive signal from the drive circuit via the gate terminal, and is turned ON / OFF by the drive signal.

  The drive circuit (not shown) drives the FET 202-1, FET 202-2, FET 202-3, and FET 202-4, respectively, to turn on or off AC power of, for example, 50 Hz or 60 Hz, which is a commercial frequency. To the first output terminal and the second output terminal. As an example, the drive circuit switches FET 202-1 and FET 202-2 at the same frequency as the output voltage (Vo) of the DC / AC inverter, and FET 202-3 and FET 202-4 at a higher frequency (fsw). Switch.

  Reactor 204 (L1) has one end connected in common to the source terminal of FET 202-3 and the drain terminal of FET 202-4, and the other end connected to the first output terminal of the DC / AC inverter. The capacitor 205 (C1) is inserted between the first output terminal and the second output terminal of the DC / AC inverter.

  Reactor 204 (L1) and capacitor 205 (C1) constitute a smoothing (low-pass filter). This smoothing filter generates the output current (Io) of the DC / AC inverter by smoothing the reactor current (IL) flowing through the reactor 204 (L1).

  The reactor current (IL) generally has a low frequency current component having the same frequency and phase as the output voltage (Vo) of the DC / AC inverter, and the same frequency as the switching frequency (fsw) of the FET 202-3 and the FET 202-4. High-frequency current component. For example, as shown in FIG. 5, the smoothing filter can generate a substantially sinusoidal output current (Io) by suppressing a high-frequency current component included in the reactor current (IL).

  In the DC / AC inverter of FIG. 4, for example, if the body diode (not shown) of the FET 202-4 is ON during the dead time, the FET 202-3 transitions from OFF to ON after the FET 202-4 transitions from OFF to ON. The output capacity (Coss, not shown) needs to be charged. The magnitude of this power loss can be expressed by the following formula (1).

  As shown in Equation (1), this power loss depends on the magnitude of Coss, but Coss is generally larger as the FET has a smaller ON resistance. Therefore, when a FET having a small ON resistance is employed as the FET 202-4 in order to suppress conduction loss, the power loss accompanying charging of the output capacity of the FET 202-4 is generally large.

  Coss changes depending on the drain-source voltage (VDS). For example, in the latest super junction FET known at the time of filing of the present application, Coss in a region where VDS is low is about 300 times larger than Coss in a region where VDS is close to the maximum rating. For example, when a super junction FET is adopted as the FET 202-4, most of the charging power of the output capacity of the FET 202-4 is 1/10 of the power supply voltage (Vin). It is consumed by the FET 202-3 during the period until it rises.

  Since the power loss due to the charging of the output capacity of the FET cannot be reduced even if the switching speed of the FET is increased, it is a great obstacle to improving the efficiency of the DC / AC inverter.

  Furthermore, in the DC / AC inverter of FIG. 4, for example, if the body diode of the FET 202-4 is ON during the dead time, a recovery current flows through the body diode of the FET 202-4 after the dead time ends. In addition to causing power loss, the recovery current instantaneously changes the current greatly, and thus may increase noise and damage the FET 202-4.

  Here, the fact that the body diode of the FET 202-4 is ON during the dead time means that the reactor current (IL) continues to flow in the same direction as the forward current of the body diode during the dead time. To do.

  Therefore, the DC / AC inverter according to the first embodiment starts the dead time by turning off the FET in which current flows from the source terminal to the drain terminal (that is, the FET in which the body diode is ON). The timing is determined as follows. Specifically, the DC / AC inverter starts the dead time by turning off the FET when the direction of the reactor current is reversed (that is, zero crossing) or thereafter. As a result, as will be described later, the output capacity of the FET is charged by the inverted reactor current during the dead time, and further, no recovery current flows through the body diode of the FET after the dead time ends. A DC / AC inverter according to this embodiment is illustrated in FIG.

  The DC / AC inverter shown in FIG. 1 is generated by inputting a DC voltage from a DC voltage source 101 via a first input terminal and a second input terminal (for example, grounded) and converting the DC voltage. An alternating voltage is output to the load 106 via the first output terminal and the second output terminal. For example, the DC voltage source 101 may be a solar cell module (panel). Thus, when the load 106 (RL) is a pure resistor or a power system (in reverse power flow), the output current (Io) of the DC / AC inverter is in phase with the output voltage (Vo). Therefore, if the output current (Io) is controlled, the output voltage (Vo) can also be controlled at the same timing.

  The DC / AC inverter of FIG. 1 includes an FET 102-1, an FET 102-2, an FET 102-3, an FET 102-4, a current detection circuit 103, a reactor 104, a capacitor 105, and a drive control circuit. 110. Note that other types of transistors can be used instead of FETs.

  The FET 102-1 has a drain terminal connected to the first input terminal of the DC / AC inverter, a gate terminal connected to the drive control circuit 110, and a source terminal connected to the second output terminal of the DC / AC inverter. Connected to. The FET 102-1 receives a drive signal from the drive control circuit 110 via the gate terminal, and is turned ON / OFF by the drive signal.

  The FET 102-2 has a drain terminal connected to the second output terminal of the DC / AC inverter, a gate terminal connected to the drive control circuit 110, and a source terminal connected to the second input terminal of the DC / AC inverter. (Eg, grounded). The FET 102-2 receives a drive signal from the drive control circuit 110 via the gate terminal, and is turned ON / OFF by the drive signal.

  The FET 102-3 has its drain terminal connected to the first input terminal of the DC / AC inverter, its gate terminal connected to the drive control circuit 110, and its source terminal via the current detection circuit 103 and the reactor 104. Connected to the first output terminal of the DC / AC inverter. The FET 102-3 receives a drive signal from the drive control circuit 110 via the gate terminal, and is turned ON / OFF by the drive signal.

  The FET 102-4 has a drain terminal connected to the first output terminal of the DC / AC inverter via the current detection circuit 103 and the reactor 104, a gate terminal connected to the drive control circuit 110, and a source terminal connected to the first output terminal. Connected to the second input terminal of the DC / AC inverter (eg, grounded). The FET 102-4 receives a drive signal from the drive control circuit 110 via the gate terminal, and is turned ON / OFF by the drive signal.

  The current detection circuit 103 has a first terminal commonly connected to the source terminal of the FET 102-3 and the drain terminal of the FET 102-4, a second terminal connected to one end of the reactor 104, and an output terminal thereof. Is connected to the drive control circuit 110. The current detection circuit 103 detects a current that flows from one end to the other end, in other words, a reactor current (IL) that flows from the reactor 104 toward the first output terminal of the DC / AC inverter. For example, the current detection circuit 103 performs a current-voltage conversion on the reactor current (IL) and outputs a signal having this voltage to the drive control circuit 110.

  Reactor 104 has one end connected to current detection circuit 103 and the other end connected to the first output terminal of the DC / AC inverter. The capacitor 105 is inserted between the first output terminal and the second output terminal of the DC / AC inverter. Reactor 104 and capacitor 105 constitute a smoothing filter. The smoothing filter smoothes the reactor current (IL) flowing through the reactor 104, thereby generating an output current of the DC / AC inverter.

  Reactor current (IL) generally includes a low-frequency current component having the same frequency and phase as the output voltage of the DC / AC inverter and a high-frequency current component having the same frequency as the switching frequency of FET 102-3 and FET 102-4. . The smoothing filter can generate a substantially sinusoidal output current by suppressing the high-frequency current component contained in the reactor current (IL).

  The drive control circuit 110 performs ON / OFF driving of the FET 102-1, the FET 102-2, the FET 102-3, and the FET 102-4, for example, so that AC power of 50 Hz or 60 Hz, which is a commercial frequency, is converted into a DC / AC inverter To the first output terminal and the second output terminal.

  Specifically, as illustrated in FIG. 6, the drive control circuit 110 performs FET 102-3 during a period in which the reference sine wave that defines the target value of the output current (Io) of the DC / AC inverter is positive. FET 102-3 and FET 102-4 based on the detection result by the current detection circuit 103 so that the reactor current (IL) zero-crosses at least twice (that is, changes from positive → negative → positive) within the switching period of To control. Similarly, in the period in which the reference sine wave of the DC / AC inverter is negative, the drive control circuit 110 zero-crosses the reactor current (IL) at least twice within the switching period of the FET 102-4 (ie, negative → The FET 102-3 and the FET 102-4 are controlled based on the detection result by the current detection circuit 103 so as to change from positive to negative.

  In this way, the drive control circuit 110 controls the maximum value of the reactor current (IL) to be a sine wave during the period in which the reference sine wave is positive, and sets the minimum value of the reactor current (IL) to a constant negative value. Control to be. Similarly, during a period in which the reference sine wave is negative, the drive control circuit 110 controls the minimum value of the reactor current (IL) to be a sine wave, and the maximum value of the reactor current (IL) becomes a constant positive value. To control. Such control can be realized using a comparator, as will be described later with reference to FIG. In this case, since the switching frequency is automatically determined by the load current flowing through the load 106 and the input / output voltage of the DC / AC inverter, the control can be simplified.

  The drive control circuit 110 may switch the FET 102-1 and the FET 102-2 at the same frequency as the output voltage of the DC / AC inverter, and may switch the FET 102-3 and the FET 102-4 at a higher frequency. Alternatively, the switching frequency of the FET 102-1 and the FET 102-2 may be the same as the switching frequency of the FET 102-3 and the FET 102-4.

  In the DC / AC inverter of FIG. 1, the reactor current (IL) decreases in a situation where the FET 102-3 is in the OFF state and the FET 102-4 is in the ON state. On the other hand, in a situation where the FET 102-3 is in the ON state and the FET 102-4 is in the OFF state, the reactor current (IL) increases. The drive control circuit 110 performs control to bring the reactor current (IL) closer to the reference sine wave using such a relationship. For example, when the reactor current (IL) becomes too small (below the target minimum value), the drive control circuit 110 sets the FET 102-3 to the ON state after a dead time (event 2 and event 3 described later). On the other hand, when the reactor current (IL) becomes excessive (greater than or equal to the target maximum value), the drive control circuit 110 sets the FET 102-4 to the ON state after a dead time (event 1 and event 4 described later). The inclination of the increase / decrease of the reactor current (IL) depends on the inductance of the reactor 104, and the inclination increases as the inductance decreases.

  For example, if the reactor current (IL) becomes excessive during a period in which the reference sine wave is positive, the drive control circuit 110 turns on the FET 102-4 and decreases the reactor current (IL). Thereafter, the drive control circuit 110 switches the FET 102-4 to the OFF state and starts the dead time in order to return the FET 102-3 to the ON state and increase the reactor current (IL).

  An equivalent circuit of the DC / AC inverter in this dead time is illustrated in FIG. If the reactor current (IL) remains positive and the FET 102-4 is turned off to start the dead time, the body diode of the FET 102-4 is turned on. That is, when the FET 102-3 is subsequently turned on to end the dead time, the output capacity of the FET 102-4 needs to be charged and a recovery current is generated.

  Therefore, in the above situation, the drive control circuit 110 waits for the reactor current (IL) to become zero or less, and then turns off the FET 102-4 to start the dead time. If the FET 102-4 is controlled in this way, the body diode of the FET 102-4 is not turned ON during the dead time. Furthermore, since the reactor current (IL) continues to decrease in the range of zero or less during the dead time, the reactor current (IL) flows from the first output terminal of the DC / AC inverter to the drain terminal of the FET 102-4. That is, the output capacity of the FET 102-4 can be charged (resonant charging) by this reactor current. Therefore, even if the FET 102-3 is turned on after that to end the dead time, the charging of the output capacity of the FET 102-4 becomes unnecessary (at least the power to be charged is reduced) and the recovery current is Does not occur.

  Similarly, for example, when the reactor current (IL) becomes excessive during the period in which the reference sine wave is negative, the drive control circuit 110 turns on the FET 102-3 and increases the reactor current (IL). Thereafter, the drive control circuit 110 switches the FET 102-3 to the OFF state and starts the dead time in order to return the FET 102-4 to the ON state again and reduce the reactor current (IL).

  If the reactor current (IL) remains negative and the FET 102-3 is turned off to start the dead time, the body diode of the FET 102-3 is turned on. That is, when the FET 102-4 is subsequently turned on to end the dead time, the output capacity of the FET 102-3 needs to be charged and a recovery current is generated.

  Therefore, in the above situation, the drive control circuit 110 waits for the reactor current (IL) to become zero or more, and turns off the FET 102-3 to start the dead time. If the FET 102-3 is controlled in this way, the body diode of the FET 102-3 is not turned ON during the dead time. Furthermore, since the reactor current (IL) increases during the dead time, the reactor current (IL) flows from the source terminal of the FET 102-3 to the first output terminal of the DC / AC inverter. That is, the output capacity of the FET 102-3 can be charged (resonant charging) by this reactor current. Therefore, even if the FET 102-4 is turned ON after that to end the dead time, it is not necessary to charge the output capacity of the FET 102-3 (at least the power to be charged is reduced) and the recovery current is Does not occur.

  Accordingly, the DC / AC inverter of FIG. 1 can effectively suppress power loss after the dead time and can achieve high power conversion efficiency. Furthermore, this DC / AC inverter can also prevent noise and FET damage due to the recovery current. In addition, this DC / AC inverter also has an effect of reducing costs by eliminating the need for an element for countermeasures against noise caused by the recovery current.

  As described above, the drive control circuit 110 waits for the reactor current (IL) to be less than or equal to (or greater than or equal to zero) during the period in which the reference sine wave is positive (or negative), and the FET 102 -4 (or FET 102-3) is turned OFF to start the dead time. Such control keeps the FET 102-4 (or FET 102-3) ON for a longer time than when the reactor current (IL) is positive (or negative) and the dead time is started (i.e., The switching frequency of the FET 102-4 (or the FET 102-3) needs to be lowered). Alternatively, if the inductance of the reactor 104 is designed to be small, the increase / decrease slope of the reactor current (IL) increases, so that the reactor current (IL) zero-crosses in a short time. That is, the switching frequency of the FET 102-4 (or the FET 102-3) can be kept high.

  It is preferable that the dead time start timing coincides with the timing at which the reactor current (IL) crosses zero (hereinafter referred to as zero cross timing). If the start time of the dead time is earlier than the zero cross timing, the body diode of the FET 102-4 (or the FET 102-3) is turned on during the dead time, so the above-described effect is impaired. On the other hand, if the start timing of the dead time coincides with the zero cross timing, the charging of the output capacity of the FET 102-4 (or the FET 102-3) can be started early. Therefore, the absolute value of the minimum value when the reactor current (IL) is controlled from positive to negative to positive, and the absolute value of the maximum value when the reactor current (IL) is controlled from negative to positive to negative are minimized. Can be That is, the effective value of the charging current with respect to the output capacity of the FET 102-4 (or the FET 102-3), and hence the power loss can be minimized.

  However, for example, it is detected by a comparator that the voltage corresponding to the reactor current (IL) matches zero, and a drive signal for immediately switching the FET 102-4 (or FET 102-3) to the OFF state is generated. Even if the current is supplied to the FET 102-4 (or FET 102-3), the time from when the reactor current (IL) reaches zero until the FET 102-4 (or FET 102-3) is turned off. There is a delay time. Therefore, the start timing of the dead time is delayed by an amount corresponding to this delay time compared to the zero cross timing.

  Therefore, for example, the drive control circuit 110 may compare a voltage corresponding to the reactor current (IL) with a reference voltage corresponding to a predetermined positive current (or negative current). The predetermined positive current (or negative current) is determined based on the decrease amount (or increase amount) of the reactor current (IL) over this delay time. Therefore, the drive control circuit 110 can detect that the reactor current (IL) reaches zero earlier than the reactor current (IL) actually reaches zero by an amount corresponding to this delay time. In other words, this delay time can be compensated to suppress a delay in the start timing of the dead time.

  The dead time end timing is the timing when the charging of the output capacitance of the FET 102-4 (or the FET 102-4) is completed (that is, the voltage across the output capacitance becomes substantially equal to the voltage across the DC voltage source 101). (Hereinafter referred to as charging end timing) is preferable.

  If the dead time end timing is earlier than the charging end timing, the dead time ends with insufficient charging of the output capacity of the FET 102-3 (or FET 102-4). Must continue to charge the output capacity. On the other hand, if the dead time continues even though the charging of the output capacity of the FET 102-4 (or the FET 102-3) is completed, the reactor current (IL) decreases or increases more than necessary. Power loss associated with charging increases. Further, since the drive control circuit 110 needs to control the reactor current (IL) so that the average value thereof matches the reference sine wave, the reactor current (IL) decreases (or increases) more than necessary during the dead time. ), The reactor current (IL) needs to be significantly increased (or decreased) after the dead time. Therefore, the effective value and peak value of the reactor current (L1), and consequently the copper loss and core loss in the reactor 104 are increased.

  Note that the charge end timing can be derived in advance based on, for example, the time when the time integral value of the reactor current (IL) becomes equal to the amount of electricity of the output capacity at the end of charge. Therefore, the drive control circuit 110 may end the dead time, for example, at the timing when the above time has elapsed from the start timing of the dead time.

  Alternatively, if a super junction FET is employed as the FET 102-4 (or FET 102-3), charging can be automatically terminated at an appropriate timing as described below.

  FIG. 8 illustrates the relationship between the output capacitance (Coss) of the super junction FET and the drain-source voltage (VDS). In the example of FIG. 8, the capacitance of Coss is about 30 pF when VDS> 100V, but the capacitance of Coss increases from 3000 pF to 10000 pF or more at VDS <20V. If the characteristic that the capacitance of the output capacitance (Coss) rapidly decreases when the VDS rises to some extent in this way, the charging of the output capacitance (Coss) of the FET 102-4 can be suppressed to the necessary minimum.

  Specifically, as illustrated in FIG. 9, the charging of the output capacitance (Coss) of the FET 102-4 starts from timing A when the gate voltage of the FET 102-4 becomes 0. Then, the output capacitance (Coss) of the FET 102-4 is charged by the reactor current (IL) in the negative direction, but the capacitance of the output capacitance (Coss) is large when the VDS of the FET 102-4 is near 0. Therefore, the VDS of the FET 102-4 hardly increases (Q = CV). In addition, since the absolute value of the negative direction reactor current (IL) gradually increases, the rate at which charges are accumulated in the FET 102-4 also gradually increases. When the VDS of the FET 102-4 reaches a certain threshold value (Vx in FIG. 9), the output capacitance (Coss) of the FET 102-4 decreases rapidly, and conversely, the VDS of the FET 102-4 increases rapidly. Then, it approaches the DC voltage (Vin) generated by the DC voltage source 101. As a result, the output capacitance (Coss) of the FET 102-4 is charged by a necessary minimum amount of electricity represented by the area of the triangle ABC in FIG.

  When attention is paid to the behavior of the VDS in FIG. 9, even if the VGS of the FET 102-4 is set to 0 V at the timing A, the FET 102-4 behaves as if it is in an ON state (reactor in the negative direction). Current (IL) flows in). Then, at the time when the charging of the output capacitance (Coss) of the FET 102-4 is close to completion (timing C), the VDS rapidly increases as if the FET 102-4 has been switched to the OFF state. As described above, when a FET with low on-resistance (low loss) such as a super junction FET is used as the FET 102-4, the output capacitance (Coss) is obtained by utilizing the VDS dependency of the output capacitance (Coss). The charging end timing (that is, the substantial OFF timing of the FET 102-4) can be optimized.

  The drive control circuit 110 includes an event detection circuit 120 and a drive signal generator 130 as illustrated in FIG. The event detection circuit 120 receives the detection result of the reactor current (IL), compares it with the reference sine wave and the reference voltage, and detects the occurrence of a predetermined dead time start event. The event detection circuit 120 outputs a signal indicating the detection result to the drive signal generator 130. The drive signal generator 130 generates drive signals for ON / OFF driving the FET 102-1, the FET 102-2, the FET 102-3, and the FET 102-4 based on the detection result in the event detection circuit 120. And output.

  Specifically, the event detection circuit 120 includes a reference sine wave generator 121, a reference voltage source 122, a comparator 123, and a comparator 124, as illustrated in FIG.

  The reference sine wave generator 121 generates a reference sine wave and applies it to the inverting input terminal of the comparator 123. The reference voltage source 122 generates a reference voltage and applies it to the non-inverting input terminal of the comparator 124.

  The comparator 123 receives the output signal of the current detection circuit 103 at the non-inverting input terminal, and receives the reference sine wave at the inverting input terminal. The comparator 123 compares the voltage applied to the non-inverting input terminal with the voltage applied to the inverting input terminal, and outputs an L level signal if the former is smaller than the latter, and an H level signal otherwise. That is, the comparator 123 generates an output signal indicating whether or not the reactor current (IL) (the voltage corresponding to it) is equal to or higher than the reference sine wave (OSC).

  The comparator 124 receives the reference voltage at the non-inverting input terminal, and receives the output signal of the current detection circuit 103 at the inverting input terminal. The comparator 124 compares the voltage applied to the non-inverting input terminal with the voltage applied to the inverting input terminal, and outputs an L level signal if the former is smaller than the latter, and an H level signal otherwise. That is, the comparator 124 generates an output signal indicating whether or not the reference voltage is equal to or higher than a voltage corresponding to the reactor current (IL).

  As illustrated in FIG. 10, the event detection circuit 120 detects the occurrence of a dead time start event for turning back the change in the reactor current (IL) from increase to decrease or from decrease to increase. Details of each event are shown in Table 1 below.

  The event detection circuit 120 triggers an event 1 triggered by the reactor current (IL) increasing to OSC during a period in which the reference sine wave (OSC) is positive, that is, when the output of the comparator 123 transitions from L to H. To detect. When event 1 is detected, the drive signal generator 130 generates a drive signal for turning off the FET 102-3 and outputs the drive signal to the FET 102-3. Since there is a slight delay from when the reactor current (IL) increases to the OSC until the FET 102-3 is turned off, the IL turns back and decreases after the OSC is exceeded. The dead time in the event 1 starts when the FET 102-3 is turned off. After the dead time ends, the drive signal generator 130 generates a drive signal for turning on the FET 102-4 and outputs the drive signal to the FET 102-4.

  The event detection circuit 120 triggers an event 2 triggered by the fact that the reactor current (IL) decreases to 0 in a period in which the reference sine wave (OSC) is positive, that is, the output of the comparator 124 transitions from L to H. To detect. When event 2 is detected, the drive signal generator 130 generates a drive signal for turning off the FET 102-4 and outputs the drive signal to the FET 102-4. When the FET 102-4 is turned off, the dead time in the event 2 starts. In event 2, the reactor current (IL) zero-crosses at least twice as described above. After the end of the dead time, the drive signal generator 130 generates a drive signal for turning on the FET 102-3 and outputs the drive signal to the FET 102-3.

  The event detection circuit 120 triggers an event 3 triggered by a decrease in the reactor current (IL) to OSC, that is, when the output of the comparator 123 transitions from H to L during a period in which the reference sine wave (OSC) is negative. To detect. When event 3 is detected, the drive signal generator 130 generates a drive signal for turning off the FET 102-4 and outputs the drive signal to the FET 102-4. Since there is a slight delay from when the reactor current (IL) decreases to the OSC until the FET 102-4 is turned off, the IL falls below the OSC and then increases. When the FET 102-4 is turned off, the dead time in the event 3 starts. After the end of the dead time, the drive signal generator 130 generates a drive signal for turning on the FET 102-3 and outputs the drive signal to the FET 102-3.

  The event detection circuit 120 triggers an event 4 triggered by the fact that the reactor current (IL) increases to 0 during the period in which the reference sine wave (OSC) is negative, that is, the output of the comparator 124 transitions from H to L. To detect. When event 4 is detected, the drive signal generator 130 generates a drive signal for turning off the FET 102-3 and outputs the drive signal to the FET 102-3. When the FET 102-3 is turned off, the dead time in the event 4 starts. At event 4, the reactor current (IL) zero crosses at least twice as described above. After the dead time ends, the drive signal generator 130 generates a drive signal for turning on the FET 102-4 and outputs the drive signal to the FET 102-4.

  As described above, the DC / AC inverter according to the first embodiment controls the transistor so that the reactor current zero-crosses at least twice within the switching period of the transistor. Therefore, according to this DC / AC inverter, the body diode of the transistor is not turned ON during the dead time. Further, a reactor current flows from the output terminal of the DC / AC inverter to the drain terminal of the transistor. In other words, the output capacity of the transistor can be charged (resonant charging) by this reactor current. Therefore, even if the dead time is ended after that, charging of the output capacitance of the transistor becomes unnecessary (at least power to be charged is reduced) and no recovery current is generated.

  The above-described embodiments are merely specific examples for helping understanding of the concept of the present invention, and are not intended to limit the scope of the present invention. The embodiment can add, delete, or convert various components without departing from the gist of the present invention.

101, 201: DC voltage source 102-1, 102-2, 102-3, 102-4, 202-1, 202-2, 202-3, 202-4 ... transistor 103 ... current detection Circuits 104, 204 ... Reactors 105, 205 ... Capacitors 106, 206 ... Load 110 ... Drive control circuit 120 ... Event detection circuit 121 ... Reference sine wave generator 122 ... Reference Voltage source 123, 124 ... Comparator 130 ... Drive signal generator

Claims (6)

DC which inputs a DC voltage through the first input terminal and the second input terminal, and outputs an AC voltage generated by converting the DC voltage through the first output terminal and the second output terminal / AC inverter,
A first transistor comprising a first terminal, a second terminal and a control terminal, the first terminal being connected to the first input terminal;
A first terminal; a second terminal; and a control terminal, wherein the first terminal is connected to a first terminal of the first transistor, and the second terminal is connected to the second input terminal. A second transistor,
A reactor inserted between a node between the first transistor and the second transistor and the first output terminal;
A current detection circuit for detecting a reactor current flowing from the reactor toward the first output terminal;
A DC / AC inverter comprising: a drive control circuit that controls each of the first transistor and the second transistor so that the reactor current zero crosses at least twice within a switching period of the first transistor.   In the drive control circuit, the reactor current becomes zero or negative over a dead time from when the first transistor transitions from ON to OFF until the second transistor transitions from ON to OFF. The DC / AC inverter of claim 1, wherein each of the first transistor and the second transistor is controlled to be maintained. The drive control circuit includes:
An event detection circuit for detecting that the reactor current reaches zero;
A first drive signal and a second drive signal for driving the first transistor and the second transistor are generated, respectively, to the control terminal of the first transistor and the control terminal of the second transistor, respectively. A drive signal generator for supplying,
When it is detected that the reactor current reaches zero when the first transistor is in the ON state, the drive signal generator causes the first transistor to transition from ON to OFF. Generate a drive signal,
The DC / AC inverter according to claim 1 or 2. The current detection circuit detects the reactor current in the form of a corresponding voltage;
The event detection circuit compares a voltage corresponding to the reactor current with a reference voltage corresponding to a predetermined positive current, and detects that the reactor current reaches zero based on a comparison result.
The DC / AC inverter according to claim 3.   The reference voltage is determined based on a decrease amount of the reactor current over a delay time from when it is detected that the reactor current reaches zero until the first transistor transitions to an OFF state. 4. The DC / AC inverter according to 4. A third transistor comprising a first terminal, a second terminal and a control terminal, wherein the first terminal is connected to the first input terminal;
A first terminal; a second terminal; and a control terminal, wherein the first terminal is connected to the first terminal of the third transistor, and the second terminal is connected to the second input terminal. A fourth transistor, and
The drive control circuit further controls each of the third transistor and the fourth transistor,
The switching frequency of the third transistor and the fourth transistor is lower than the switching frequency of the first transistor and the second transistor,
The DC / AC inverter according to any one of claims 1 to 5.