JP2018137841A - Power factor improvement circuit and charger - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power factor improvement circuit capable of suppressing a rise in an output capacitor voltage even if an input voltage varies and capable of achieving miniaturization of an apparatus by reducing the capacitance of a capacitor.SOLUTION: The power factor improvement circuit, step-up converting an input AC voltage into a DC voltage, includes: output current detection means 25 for detecting an output current; input current amplitude prediction means 27 for predicting an input current amplitude using an input current; output voltage detection means 24 for detecting an output voltage; a voltage compensator 28 for calculating a compensation voltage corresponding to a difference between the output voltage and a target output voltage; and input current command value creation means 18 for creating an input current command value for controlling an input current using a predicted input current amplitude and the compensation voltage.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power factor correction circuit and a charging device including the same.

  Conventionally, PFC (Power Factor Correction) circuits have been used in electronic devices that require a large-capacity power supply in order to suppress harmonic current. The PFC circuit is also called a power factor correction circuit.

  Japanese Patent Application Laid-Open No. 2004-133830 discloses that a boost type power factor correction circuit that reduces the pulsation of the output voltage of the boost circuit is realized by temporarily increasing the response speed of the voltage error amplifier even when the load suddenly changes. The purpose is to provide a phase compensator that increases the phase compensation impedance of the voltage error amplifier to increase the response speed of the voltage error amplifier when the output voltage of the boost circuit falls outside a predetermined range. .

JP 2014-99970 A

  In a power factor correction circuit, a pulsation component with a constant amplitude is included in the output capacitor voltage. Therefore, a large output capacitor is usually used to prevent harmonic distortion from occurring in the input current due to the influence of this pulsation component. Is done. Therefore, in the method of increasing the response speed of the error amplifier as described above, the influence of the pulsation component is more likely to appear as the capacitor capacity is smaller. As a result, the capacitor capacity cannot be reduced, and the device is downsized. Becomes difficult.

  An object of the present invention is to provide a technique capable of reducing the size of a device by reducing the capacitance of a capacitor while suppressing the influence of a pulsating component.

  The present invention relates to a power factor correction circuit for boosting and converting an input AC voltage into a DC voltage, an output current detecting means for detecting an output current, and an input current amplitude for predicting an input current amplitude using the output current. A prediction means; an output voltage detection means for detecting an output voltage; a voltage compensation means for calculating a compensation voltage according to a difference between the output voltage and a target output voltage; the predicted input current amplitude and the compensation voltage; It is a power factor improvement circuit provided with the input current command value production | generation means which produces | generates the input current command value for controlling an input current using.

  In one embodiment of the present invention, the input current amplitude predicting means predicts the input current amplitude using the output current, the target output voltage, and the input voltage effective value.

  In another embodiment of the present invention, the input current command value generation means calculates a prediction error correction amount using the compensation voltage, corrects the predicted input current amplitude with the prediction error correction amount, and Generate input current command value.

  The present invention is also a charging device in which an isolated DCDC converter is connected to an output of a power factor correction circuit that boosts and converts an input AC voltage into a DC voltage, the isolated DCDC converter including a transformer, A smoothing coil is provided on the secondary side of the transformer, current detection means for detecting the primary side current of the transformer, and average input current estimation for estimating the average input current of the isolated DCDC converter using the primary side current Means, input current amplitude predicting means for predicting an input current amplitude using the estimated average input current, output voltage detecting means for detecting an output voltage of the power factor correction circuit, the output voltage and the power factor The voltage compensation means for calculating the compensation voltage according to the difference from the target output voltage of the improvement circuit, and the input current is controlled using the predicted input current amplitude and the compensation voltage. A charging device and an input current command value generating means for generating an input current command value.

  In one embodiment of the present invention, the average input current estimation means estimates the average input current using the primary side current and a time ratio at which a voltage is applied to the primary side of the transformer.

  In another embodiment of the present invention, the apparatus further comprises peak current command value generating means for generating a peak current command value of the smoothing coil using the primary side current, and the average input current estimating means includes the peak current command The average input current is estimated using the value.

  In still another embodiment of the present invention, the input current amplitude predicting unit predicts the input current amplitude using the average input current, the target output voltage, and an input voltage effective value.

  In still another embodiment of the present invention, the input current command value generation means calculates a prediction error correction amount using the compensation voltage, and corrects the predicted input current amplitude with the prediction error correction amount. The input current command value is generated.

  According to the power factor correction circuit of the present invention, it is possible to suppress an increase in output capacitor voltage even if the input voltage waveform fluctuates due to fluctuations in the input power supply or load. Therefore, the output capacitor capacity can be reduced, and the circuit can be miniaturized.

  Further, according to the charging device of the present invention, even when the output current of the power factor correction circuit varies due to the load variation of the charging device or the change of the load current command value, the variation of the output capacitor voltage can be suppressed. . Accordingly, the output capacitor capacity can be reduced, and the apparatus can be miniaturized.

1 is an overall configuration block diagram of a power factor correction circuit according to Embodiment 1. FIG. It is a circuit block diagram of a power factor improvement circuit. It is a timing chart of each part. It is a simulation result figure of a conventional circuit. It is a simulation result figure of an embodiment circuit. FIG. 6 is an overall configuration block diagram of a charging device in a second embodiment. It is a simulation result of the conventional charging device. It is a simulation result figure of an embodiment device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Embodiment 1>
FIG. 1 shows a configuration block diagram of a power factor correction circuit in the present embodiment. The power factor improving circuit includes a boost converter 10, an input voltage detector 12, an input current detector 14, an input current command value generator 18, a current error detector 20, a switch controller 22, an output voltage detector 24, and an output current. A detection unit 25, a voltage error detection unit 26, an input current amplitude prediction unit 27, and a voltage compensator 28 are provided.

  The step-up converter 10 steps up the input AC voltage to a DC voltage and outputs it. The step-up converter 10 includes a switching element, and on / off of the switching element is controlled by the switch controller 22.

  The input voltage detector 12 detects the input voltage of the boost converter 10. The input voltage detection unit 12 supplies the detected input voltage to the input current command value generation unit 18.

  The input current detection unit 14 detects the input current of the boost conversion unit 10. The input current detection unit 14 supplies the detected input current to the current error detection unit 20.

  The input current command value generation unit 18 generates an input current command value based on the input voltage detected by the input voltage detection unit 12, the output voltage, and the output current and supplies the input current command value to the current error detection unit 20.

  The current error detection unit 20 generates a drive signal based on the input current command value and the input current detected by the input current detection unit 14 and supplies the drive signal to the switch control unit 22.

  The output voltage detector 24 detects the output voltage of the boost converter 10. The output voltage detection unit 24 supplies the detected output voltage to the voltage error detection unit 26.

  The voltage error detection means 26 detects an error between the detected output voltage and the reference voltage (DC target voltage), and supplies it to the voltage compensator 28.

  The voltage compensator 28 generates a voltage for compensation based on the detected error and supplies it to the input current command value generation means 18. The input current command value generation unit 18 supplies the generated input current command value to the current error detection unit 20.

  The output current detector 25 detects the output current of the boost converter 10. The output current detection unit 25 supplies the detected output current to the input current amplitude prediction unit 27.

  The input current amplitude predicting unit 27 predicts an input current amplitude value that can maintain the power balance between the input and output based on the detected output, and supplies the predicted value to the input current command value generating unit 18. As described above, the input current command value generation unit 18 generates an input current command value based on the input voltage detected by the input voltage detection unit 12, the output voltage, and the output current. The input current command value is generated based on the input voltage, the voltage error from the voltage compensator 28, and the input current amplitude predicted value.

  A characteristic block in the present embodiment is a block including an input current command value generating means 18, an output current detecting means 25, and an input current amplitude predicting means 27, whereby an input is made so as to maintain a power balance between input and output. The current command value is adjusted.

  In FIG. 1, it is also possible to grasp the boost conversion means 10 as a power factor correction circuit main body and the other blocks as a control circuit for driving and controlling the power factor improvement circuit main body. The control circuit is also referred to as a power factor correction circuit.

  FIG. 2 shows a specific circuit configuration of the configuration block shown in FIG.

The step-up conversion means 10 is a bridgeless PFC circuit, which steps up an AC voltage from a power source and outputs it as a DC voltage. The bridgeless PFC circuit includes a step-up chopper circuit, specifically a reactor connected to an AC power supply, a switching element (switching transistor), a body diode connected in reverse parallel to the switching element, and a diode connected in series to the switching element And an output capacitor _CVH . This output capacitor C _VH is an output capacitor whose capacity is to be reduced. A load 30 is connected to the output capacitor _CVH .

The input voltage detection unit 12 includes a voltage sensor 12a and an A / D 12b connected to an AC power supply, converts the detected input voltage _Vac into a digital value, and supplies the digital value to the input current command value generation unit 18.

Input current detecting means 14 is composed of the current sensor 14a and A / D14B connected to the AC power source, for supplying an input current i _ac detected current error detection means 20 is converted into a digital value.

Output voltage detection means 24, the output of the boost converter 10, that is, the output consists of the connected voltage sensors 24a and A / D24b the capacitor C _VH, voltage error detection and converts the detected output voltage V _vh into a digital value Supply to means 26.

The voltage error detection unit 26 includes a differentiator, and calculates a voltage error by calculating a difference between the output voltage from the output voltage detection unit 24 and the DC target voltage V _vh ^(REF) .

The voltage compensator 28 includes a processor such as a CPU, calculates a voltage (compensation voltage) V _c for compensating the calculated error, and supplies the calculated voltage (compensation voltage) V _c to the input current command value generation means 18.

The output current detection means 25 is composed of an output of the boost conversion means 10, that is, a current sensor 25a and an A / D 25b connected to the output capacitor C _VH , and converts the detected output current i _vh into a digital value to obtain an input current amplitude. It supplies to the prediction means 27.

The input current amplitude prediction unit 27 is configured by a processor such as a CPU, and predicts the input current amplitude value I _ac ^(EST) using the output current i _vh . A specific prediction method will be described later.

The input current command value generating means 18 is constituted by a processor such as a CPU, and generates a sine wave whose frequency and phase are synchronized with the input voltage waveform, and the compensation voltage Vc generated by the voltage compensator 28, and further the input current. Together with the input current amplitude I _ac ^(EST) predicted by the amplitude prediction means 27, the input current command value at the current time is calculated.

  The current error detection means 20 is constituted by a subtractor, calculates the difference between the input current command value and the detected input current as an error, and supplies it to the switch control means 22.

  The switch control means 22 is composed of a PWM 22a and a driver (DRV) 22b. The current error is subjected to PWM modulation (pulse width modulation) and supplied to the driver 22b. Control.

  Hereinafter, the processes of the input current amplitude prediction unit 27 and the input current command value generation unit 18 will be described more specifically.

The input current amplitude prediction means 27 predicts an input current amplitude value I _ac ^(EST) that can maintain a power balance between input and output with respect to the current average output current, using the detected output current. That is, based on the average output current value i _vh ,
To predict. Here, V _vh ^(TGT) is an output voltage target value, and V _ac ^(RMS) is an effective value of the input voltage. In the derivation of the above formula, the diode, the PFC coil, and the capacitor are considered ideal, and the forward voltage, the DC resistance component, and the like are omitted.

The input current amplitude predicted value I _ac ^(EST) obtained by the above equation is an approximate value to the last, and thus includes an error.

Therefore, the input current command value generating means 18 obtains the input current amplitude prediction error correction amount ΔI _ac based on the output of the voltage compensator 28 according to the following equation.

The input current amplitude predicted value and the prediction error correction amount are added to _{obtain an} input current amplitude I _ac ^(REF) .

Thereafter, using a sine wave in phase with the input voltage waveform, an input current command value i _ac ^{(REF) in} which the power balance between the input and output is balanced with respect to the current average output current is generated.

  FIG. 3 shows an operation timing chart of the input current amplitude prediction means 27 and the input current command value generation means 18. The waveform of each part in case load current rises rapidly at the time of the point A is shown typically. The input voltage, input voltage (full wave rectification), input voltage (effective value), output current, input current amplitude prediction value, prediction error correction amount, input current amplitude, and input current command value are shown in order from the top. The input current amplitude prediction value is a waveform calculated by the input current amplitude prediction means 27, and the prediction error correction amount, the input current amplitude, and the input current command value are waveforms generated by the input current command value generation means 18.

  The prediction error correction amount is updated at the time when the input voltage waveform crosses zero. When the load fluctuation (output current fluctuation) is detected, the input current amplitude prediction means 27 generates a predicted value according to the above mathematical formula (1). The voltage compensator 28 is initialized so that the output becomes zero.

  Thereby, the input current command value is immediately corrected according to the output current fluctuation, and the fluctuation of the output voltage is suppressed.

  4 and 5 show the circuit simulation results by the computer. FIG. 4 shows a simulation result of a conventional circuit that does not include the output current detection means 25 and the input current amplitude prediction means 27, and FIG. 5 shows a simulation result of the circuit of this embodiment. In both figures, waveforms of input voltage, input current, output voltage, and output current are shown.

  In the conventional circuit, the output voltage fluctuates greatly because the control of the input current is slow when the output current suddenly rises or falls, whereas in the circuit of this embodiment, the output is controlled by immediately controlling the input current. It can be seen that the voltage fluctuation is suppressed. Therefore, the capacity of the output capacitor can be reduced and the circuit can be miniaturized.

<Embodiment 2>
FIG. 6 shows a circuit configuration of a charging apparatus in which a phase shift type full bridge DCDC converter 50 is cascade-connected as an example of an isolated DCDC converter to the power factor correction circuit of the first embodiment. Hereinafter, the DCDC converter is abbreviated as DDC as appropriate.

  The power factor correction circuit includes a boost converter 10, an input voltage detector 12, an input current detector 14, an input current command value generator 18, a current error detector 20, a switch controller 22, an output voltage detector 24, and a voltage error. A detection unit 26, an input current amplitude prediction unit 27, and a voltage compensator 28 are provided. The input voltage detection means 12 includes a voltage sensor 12a and an A / D 12b. The input current detection means 14 includes a current sensor 14a and an A / D 14b. The current error detection means 20 is composed of a differentiator. The switch control means 22 includes a PWM 22a and a driver 22b. The output voltage detection means 24 includes a voltage sensor 24a and an A / D 24b. The voltage error detecting means 26 is composed of a differentiator.

  The output of the step-up conversion means 10 is connected to a phase shift type full-bridge DCDC converter 50 that steps up and outputs a direct-current voltage. Further, the alternating current sensors 54a and A / D 54b as current detection means, output voltage detection Voltage sensor 56a and A / D 56b as means, smoothing coil peak current estimation means 58, peak current command value generation means 60, difference unit 66 as current error detection means, switch means 62, DDC average input current estimation means 64, compensation 68, a phase shift clock 70 and a driver 72. A secondary battery 52 is connected to the output of the phase shift type full bridge DCDC converter 50 as a load, and the secondary battery 52 is charged by the power factor correction circuit and the phase shift type full bridge DCDC converter 50.

The phase shift type full bridge DCDC converter 50 includes a switching element, a transformer, a smoothing coil, and a smoothing capacitor (output capacitor), and the peak current command value of the smoothing coil is adjusted so as to obtain a desired output power. The peak current i _LP of the smoothing coil is converted from the current waveform i _T1 on the primary side of the transformer using a relatively inexpensive AC current sensor 54a. Note that the phase shift type full bridge DCDC converter 50 itself is known, and in a normal full bridge type DCDC converter, switching loss occurs when the switching element is turned on and off. In the phase shift method, the left and right arms (each arm is connected in series) The switching loss is suppressed by changing the on / off phase difference of a pair of switching elements.

The alternating current sensor 54a detects the current i _T1 on the primary side of the transformer and supplies it to the A / D 54b. The A / D 54 b converts the transformer primary-side current i _T1 into a digital value and supplies it to the smoothing coil peak current estimating means 58, the peak current command value generating means 60, and the switch means 62.

The peak current command value generating means 60 is constituted by a processor such as a CPU, and based on the transformer primary side current i _T1 and the output voltage V _pv , the peak current command value i _pk ^{( REF)} . The peak current command value generation means 60 supplies the generated peak current command value i _pk ^(REF) to the current error detection means 66 and the switch means 62.

The switch means 62 inputs the current on the primary side of the transformer from the A / D 54b and the peak current command value i _pk ^(REF) from the peak current command value generating means 60, and selectively performs DDC averaging on these two signals. This is supplied to the input current estimating means 64.

The DDC average input current estimation means 64 is constituted by a processor such as a CPU, and uses the current i _T1 on the transformer primary side or the peak current command value i _pk ^(REF) to calculate the average input current of the phase shift type full bridge DCDC converter 50. Is estimated.

<When estimating the average input current from the transformer primary current>
The DDC average input current estimation means 64 estimates the average input current i _vh by the following equation.

Here, D _d is a time ratio (hereinafter referred to as a time ratio) in which a voltage is applied to the transformer primary side, and i _T1 is an average value of a waveform obtained by full-wave rectifying the transformer primary current. i _T1 is calculated by filtering the full-wave rectified waveform. Alternatively, as shown in the following equation, it can also be calculated from the peak value of the transformer primary current waveform.

Here, i _T1p is the peak value of the transformer primary-side current waveform, V _vh is the input voltage of the phase shift type full bridge DCDC converter 50 (ie, equal to the output voltage of the power factor correction circuit), and L _m is the transformer primary. Excitation inductance, N is transformer winding ratio, L _pv is inductance of smoothing coil, V _pv is output voltage of phase shift type full bridge DCDC converter 50 detected by voltage sensor 56a and A / D 56b, and T _SW is right and left This is the period of the phase shift clock 70 (duty = 50%) for shifting the phase of the arm.

<When estimating the average input current from the peak current command value>
The DDC average input current estimation means 64 estimates the average input current i _vh by the following equation.

Here, i _Lp is the average current of the smoothing coil, and is calculated by the following equation using the peak current command value i _Lp ^(PK) of the smoothing coil.

As described above, the DDC average input current estimation means 64 estimates the average input current i _vh using the transformer primary-side current i _T1 or the peak current command value i _pk ^(REF) . The DDC average input current estimation means 64 supplies the estimated average input current i _vh to the input current amplitude prediction means 27 as i _vh ^(EST) .

The input current amplitude predicting means 27 is configured by a processor such as a CPU, and similarly to the first embodiment, the input current amplitude predicting unit 27 calculates an input current amplitude value I _ac ^(EST) that can maintain a power balance between input and output with respect to the current average input current. Predict. However, the estimated average input current is used instead of the average output current in the first embodiment.

The subsequent steps are the same as in the first embodiment, and the input current command value generation means 18 obtains the input current amplitude prediction error correction amount ΔI _ac based on the output of the voltage compensator 28, and calculates the input current amplitude prediction value and the prediction error correction. The sum of the amounts is defined as the input current amplitude I _ac ^(REF) . Then, by using a sine wave having the same phase as the input voltage waveform, the power balance between the input and output with respect to the current average input current of the phase shift type full bridge DCDC converter 50, that is, the current average output current for the power factor correction circuit. The input current command value i _ac ^{(REF) from} which the value is removed is generated.

  7 and 8 show circuit simulation results by the computer. FIG. 7 shows a simulation result of a conventional charging device that does not include the DDC average input current estimation means 64 and the input current amplitude prediction means 27, and FIG. 8 shows a simulation result of the charging device of this embodiment. In both figures, waveforms of input voltage, input current, output voltage, DDC input current, and smoothing coil current are shown. It is a waveform when the peak current command value of the smoothing coil is changed stepwise. In the circuit simulation, the DDC average input current is estimated from the peak current command value of the smoothing coil.

  In the conventional charging device shown in FIG. 7, the output voltage fluctuates greatly because the control of the input current is slow when the peak current command value suddenly rises or falls rapidly. The DDC input current and the DDC output current fluctuate in order to supply On the other hand, in the charging apparatus of this embodiment shown in FIG. 8, it can be seen that fluctuations in the output voltage are suppressed by controlling the input current immediately, and fluctuations in the DDC input current and the DDC output current are suppressed. . Therefore, in addition to the output capacitor of the power factor correction circuit, the capacity of the output capacitor of the phase shift type full bridge DCDC converter 50 can be reduced, and the charging device can be downsized.

  In the first embodiment, the capacity of the output capacitor of the power factor correction circuit can be reduced. However, in the second embodiment, it is noted that the capacity of the output capacitor of the power factor correction circuit and the output capacitor of the isolated DCDC converter can be reduced. I want.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to this embodiment, A various deformation | transformation is possible. Hereinafter, modified examples will be described.

<Modification 1>
In the first embodiment, the input current amplitude predicting means 27, the input current command value generating means 18, and the voltage compensator 28 are configured by a processor such as a CPU. In the second embodiment, in addition to these, a peak current command value generating means 60, The DDC average input current estimation means 64 is configured by a processor such as a CPU, and in each embodiment, each calculation is executed by a processing program stored in a ROM or the like. Alternatively, distributed processing may be performed by these processors. Further, instead of software processing such as execution of a processing program by the processor, at least one of these blocks may be hardware processing using a dedicated circuit such as an ASIC or FPGA (Field Programmable Gate Array).

<Modification 2>
In the second embodiment, the switch means 62 is used to supply either the transformer primary-side current i _T1 or the peak current command value i _pk ^(REF) to the DDC average input current estimation means 64. 62 may be omitted, and the transformer primary side current i _T1 may be supplied to the DDC average input current estimation unit, or the peak current command value i _pk ^(REF) may be supplied to the DDC average input current estimation unit 64. It is good.

The peak current command value i _pk ^(REF) is the peak current command value of the smoothing coil as described above, and the peak current of the smoothing coil is detected by the AC current sensor 54a that detects the transformer primary side current. , Which is generated in order to control the peak current of the smoothing coil so as to obtain a desired output power. Therefore, since the peak current command value i _pk ^(REF) is also generated from the transformer primary side current, it can be said that the DDC average input current estimation means 64 eventually estimates the average input current using the transformer primary side current.

10 boost conversion means, 12 input voltage detection means, 14 input current detection means, 18 input current command value generation means, 20 current error detection means, 22 switch control means, 24 output voltage detection means, 25 output current detection means, 26 voltage Error detection means, 27 input current amplitude prediction means, 28 voltage compensator, 50 phase shift type full bridge DCDC converter (DDC), 60 peak current command value generation means, 64 DDC average input current estimation means.

Claims (8)

A power factor correction circuit that boosts and converts an input AC voltage into a DC voltage,
Output current detection means for detecting the output current;
Input current amplitude prediction means for predicting input current amplitude using the output current;
Output voltage detecting means for detecting the output voltage;
Voltage compensation means for calculating a compensation voltage according to the difference between the output voltage and the target output voltage;
An input current command value generating means for generating an input current command value for controlling the input current using the predicted input current amplitude and the compensation voltage;
Power factor correction circuit with The power factor correction circuit according to claim 1, wherein the input current amplitude predicting unit predicts the input current amplitude using the output current, the target output voltage, and an input voltage effective value. The input current command value generation means calculates a prediction error correction amount using the compensation voltage, and corrects the predicted input current amplitude with the prediction error correction amount to generate the input current command value. The power factor correction circuit according to any one of 1 and 2. A charging device in which an isolated DCDC converter is connected to the output of a power factor correction circuit that boosts and converts an input AC voltage into a DC voltage,
The insulated DCDC converter includes a transformer and a smoothing coil on the secondary side of the transformer,
Current detection means for detecting a primary side current of the transformer;
Average input current estimating means for estimating an average input current of the isolated DCDC converter using the primary side current;
An input current amplitude predicting means for predicting an input current amplitude using the estimated average input current;
Output voltage detection means for detecting the output voltage of the power factor correction circuit;
Voltage compensation means for calculating a compensation voltage according to a difference between the output voltage and a target output voltage of the power factor correction circuit;
An input current command value generating means for generating an input current command value for controlling the input current using the predicted input current amplitude and the compensation voltage;
A charging device comprising: The charging device according to claim 4, wherein the average input current estimation unit estimates the average input current using the primary side current and a time ratio at which a voltage is applied to the primary side of the transformer. A peak current command value generating means for generating a peak current command value of the smoothing coil using the primary side current;
The charging device according to claim 4, wherein the average input current estimation unit estimates the average input current using the peak current command value. The charging device according to claim 4, wherein the input current amplitude prediction unit predicts the input current amplitude using the average input current, the target output voltage, and an input voltage effective value. The input current command value generation means calculates a prediction error correction amount using the compensation voltage, and corrects the predicted input current amplitude with the prediction error correction amount to generate the input current command value. The charging device according to any one of 4 to 7.