JP2018137840A - Power factor improvement circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power factor improvement circuit capable of suppressing a rise in an output capacitor voltage even if an input voltage fluctuates and capable of achieving miniaturization of an apparatus by reducing the capacity of a capacitor.SOLUTION: The power factor improvement circuit, having step-up conversion means 10, includes: voltage ripple extraction means 25 that extracts, as an output voltage ripple, a difference between an output voltage and a DC target voltage of the output voltage; reference signal generation means 16a that generates, as a reference signal, a cosine wave and a sine wave with a frequency of an integral multiplication of an input voltage waveform; steady voltage ripple generation means 16b that generates a voltage ripple under a steady state, using the voltage ripple and the reference signal; and input current command value generation means 18 that creates an input current command value for controlling an input current using the voltage ripple under the steady state.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power factor correction circuit.

  Conventionally, PFC (Power Factor Correction) circuits have been used in electronic devices that require a large-capacity power supply in order to suppress harmonic current. The PFC circuit is also called a power factor correction circuit.

  Japanese Patent Application Laid-Open No. 2004-133830 discloses that a boost type power factor correction circuit that reduces the pulsation of the output voltage of the boost circuit is realized by temporarily increasing the response speed of the voltage error amplifier even when the load suddenly changes. The purpose is to provide a phase compensator that increases the phase compensation impedance of the voltage error amplifier to increase the response speed of the voltage error amplifier when the output voltage of the boost circuit falls outside a predetermined range. .

JP 2014-99970 A

  In a power factor correction circuit, a pulsation component with a constant amplitude is included in the output capacitor voltage. Therefore, a large output capacitor is usually used to prevent harmonic distortion from occurring in the input current due to the influence of this pulsation component. Is done. Therefore, in the method of increasing the response speed of the error amplifier as described above, the influence of the pulsation component is more likely to appear as the capacitor capacity is smaller. As a result, the capacitor capacity cannot be reduced, and the device is downsized. Becomes difficult.

  An object of the present invention is to provide a technique capable of reducing the size of a device by reducing the capacitance of a capacitor while suppressing the influence of a pulsating component.

  The present invention is a power factor correction circuit that boosts and converts an input AC voltage to a DC voltage, and extracts a difference between an output voltage and a DC target voltage of the output voltage as an output voltage ripple, and Reference signal generating means for generating a cosine wave and a sine wave having a frequency that is an integral multiple of the input voltage waveform as a reference signal, and a steady voltage ripple generating means for generating a voltage ripple in a steady state using the voltage ripple and the reference signal And an input current command value generating means for generating an input current command value for controlling the input current using the voltage ripple in the steady state.

  In one embodiment of the present invention, the steady voltage ripple generating means calculates an average value of the output voltage ripple every half cycle period of the input voltage waveform, and the absolute value of the average value is equal to or less than a predetermined value. And determining means for determining the steady state and determining a non-steady state when the first predetermined value is exceeded, and using the reference signal and the output voltage ripple with a half cycle period of the input voltage waveform as a basic period Fourier coefficient calculation means for calculating a Fourier coefficient, and among the Fourier coefficients, the Fourier coefficient determined by the determination means as the steady state is used, and instead of the Fourier coefficient determined by the determination means as an unsteady state. And generating means for generating a voltage ripple in the steady state using a Fourier coefficient determined as the previous steady state.

  Further, in another embodiment of the present invention, the input current command value generating means generates the input voltage waveform when the absolute value of the difference between the output voltage ripple and the voltage ripple in the steady state is equal to or less than a second predetermined value. The input current command value is generated at a period of zero crossing, and the input current command value is shorter than the period when the absolute value of the difference between the output voltage ripple and the voltage ripple in the steady state exceeds a second predetermined value. Generate a value.

  According to the present invention, even if the input voltage waveform fluctuates due to fluctuations in the input power supply or load, an increase in output capacitor voltage can be suppressed. Therefore, the output capacitor capacity can be reduced, and the circuit can be miniaturized.

It is a whole block diagram of a power factor improvement circuit. It is a circuit block diagram of a power factor improvement circuit. It is a timing chart (the 1) of each part. It is a timing chart (the 2) of each part. It is a simulation result figure of a conventional circuit. It is a simulation result figure of an embodiment circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration block diagram of a power factor correction circuit in the present embodiment. The power factor correction circuit includes a boost converter 10, an input voltage detector 12, an input current detector 14, a reference signal generator 16a, a steady voltage ripple generator 16b, an input current command value generator 18, a current error detector 20, A switch control unit 22, an output voltage detection unit 24, a voltage ripple extraction unit 25, a voltage error detection unit 26, and a voltage compensator 28 are provided.

  The step-up converter 10 steps up the input AC voltage to a DC voltage and outputs it. The step-up converter 10 includes a switching element, and on / off of the switching element is controlled by the switch controller 22.

  The input voltage detector 12 detects the input voltage of the boost converter 10. The input voltage detection unit 12 supplies the detected input voltage to the reference signal generation unit 16 a and the input current command value generation unit 18.

  The input current detection unit 14 detects the input current of the boost conversion unit 10. The input current detection unit 14 supplies the detected input current to the current error detection unit 20.

  The reference signal generation means 16a generates a cosine wave and a sine wave with a period of 1 / integer as a basic period, with the interval of zero crossing times of the input voltage waveform detected by the input voltage detection means 12 as a basic voltage ripple. It supplies to the production | generation means 16b.

  The steady voltage ripple generating means 16 b detects the steady state of the input voltage waveform, generates a voltage ripple in the steady state (steady voltage ripple), and supplies it to the voltage error detecting means 26.

  The input current command value generation unit 18 generates an input current command value based on the input voltage detected by the input voltage detection unit 12 and the output voltage and supplies the input current command value to the current error detection unit 20.

  The current error detection unit 20 generates a drive signal based on the input current command value and the input current detected by the input current detection unit 14 and supplies the drive signal to the switch control unit 22.

  The output voltage detector 24 detects the output voltage of the boost converter 10. The output voltage detection unit 24 supplies the detected output voltage to the voltage ripple extraction unit 25.

  The voltage ripple extracting means 25 extracts the voltage ripple included in the output voltage waveform and supplies it to the voltage error detecting means 26 and the steady voltage ripple generating means 16b. The steady voltage ripple generating means 16b generates the steady voltage ripple as described above, but generates the steady voltage ripple using the output voltage ripple extracted by the voltage ripple extracting means 25.

  The voltage error detection means 26 detects an error between the extracted output voltage ripple and the generated steady voltage ripple, and supplies it to the voltage compensator 28.

  The voltage compensator 28 generates a voltage for compensation based on the detected error and supplies it to the input current command value generation means 18. The input current command value generation means 18 generates an input current command value based on the input voltage detected by the input voltage detection means 12 and the output voltage as described above, and outputs it to the current error detection means 20. More specifically, an input current command value is generated based on the input voltage detected by the input voltage detection means 12 and the compensation voltage generated by the voltage compensator 28 and is output to the current error detection means 20.

  A characteristic block in the present embodiment is a block 16 including a reference signal generation unit 16a and a steady voltage ripple generation unit 16b, and adjusts an input current command value in consideration of a steady state ripple.

  In FIG. 1, it is also possible to grasp the boost conversion means 10 as a power factor correction circuit main body and the other blocks as a control circuit for driving and controlling the power factor improvement circuit main body. The control circuit is also referred to as a power factor correction circuit.

  FIG. 2 shows a specific circuit configuration of the configuration block shown in FIG.

The step-up conversion means 10 is a bridgeless PFC circuit, which steps up an AC voltage from a power source and outputs it as a DC voltage. The bridgeless PFC circuit includes a step-up chopper circuit, specifically a reactor connected to an AC power supply, a switching element (switching transistor), a body diode connected in reverse parallel to the switching element, and a diode connected in series to the switching element And an output capacitor _CVH . This output capacitor C _VH is an output capacitor whose capacity is to be reduced. A load 30 is connected to the output capacitor _CVH .

The input voltage detection means 12 is composed of a voltage sensor 12a and an A / D 12b connected to an AC power supply, converts the detected input voltage _Vac into a digital value, and generates a reference signal generation means 16a and an input current command value generation means 18. To supply.

Input current detecting means 14 is composed of the current sensor 14a and A / D14B connected to the AC power source, for supplying an input current i _ac detected current error detection means 20 is converted into a digital value.

  The reference signal generating means 16a is constituted by a processor such as a CPU, and generates a cosine wave and a sine wave having a period of 1 / integer as a basic period at an interval of zero-crossing times of the input voltage waveform to generate a steady voltage ripple Supply to means 16b. In the figure, the reference signal generating means 16a generates and outputs cosωt, cos2ωt,..., CosNωt, and sinωt, sin2ωt,.

On the other hand, the output voltage detecting means 24, the output of the boost converter 10, i.e., is composed of a voltage sensor 24a and A / D24b connected to the output capacitor C _VH, voltage and converts the detected output voltage V _vh into a digital value This is supplied to the ripple extraction means 25.

The voltage ripple extraction unit 25 includes a differentiator, calculates a difference between the detected output voltage waveform and the reference output voltage waveform V _vh ^(REF) , extracts a voltage ripple, and detects the voltage error detection unit 26 and the steady voltage. This is supplied to the ripple generating means 16b. The reference voltage waveform V _vh ^(REF) is a DC target voltage of the output voltage.

  The steady voltage ripple generating means 16b is composed of a processor such as a CPU, and generates a steady voltage ripple using the cosine wave and sine wave from the reference signal generating means 16a and the voltage ripple from the voltage ripple extracting means 25. The steady voltage ripple generating unit 16b includes a determination unit that determines whether the functional module is in a steady state or an unsteady state, a Fourier coefficient calculation unit that calculates a Fourier coefficient using the reference signal and the output voltage ripple, Among the Fourier coefficients, the Fourier coefficient determined by the determination means as the steady state is used, and the Fourier coefficient determined as the previous steady state is used instead of the Fourier coefficient determined as the non-steady state by the determination means. A generating means for generating a voltage ripple in the state; A specific generation method in the steady voltage ripple generation means 16b will be described later.

  The voltage error detecting means 26 includes a differentiator, and calculates a voltage error by calculating a difference between the voltage ripple from the voltage ripple extracting means 25 and the steady voltage ripple from the steady voltage ripple generating means 16b.

The voltage compensator 28 includes a processor such as a CPU, calculates a voltage (compensation voltage) V _c for compensating the calculated error, and supplies the calculated voltage (compensation voltage) V _c to the input current command value generation means 18.

  The input current command value generation means 18 is composed of a processor such as a CPU, generates a sine wave whose frequency and phase are synchronized with the input voltage waveform, and combines the compensation voltage generated by the voltage compensator 28 at the current time. Calculate the input current command value.

  The current error detection means 20 is constituted by a subtractor, calculates the difference between the input current command value and the detected input current as an error, and supplies it to the switch control means 22.

  The switch control means 22 is composed of a PWM 22a and a driver (DRV) 22b. The current error is subjected to PWM modulation (pulse width modulation) and supplied to the driver 22b. Control.

  Hereinafter, the processing of the steady voltage ripple generating unit 16b, the input current command value generating unit 18, and the voltage compensator 28 will be described more specifically.

  A current having a similar shape to the waveform obtained by full-wave rectification of the input voltage flows into the output capacitor of the boost converter 10. As a result, the output voltage includes a ripple component whose frequency is an even multiple of the input power supply frequency in addition to the DC component. The steady voltage ripple generating means 16b calculates a Fourier coefficient using the waveform of the voltage ripple in the steady state, and generates a steady voltage ripple waveform. The procedure for generating a steady voltage ripple waveform is as follows.

(1) Determination of Steady State The steady voltage ripple generating means 16b calculates the average value of the output voltage ripple in the immediately preceding half cycle period at each time when the input voltage waveform crosses zero, and the absolute value is set as the first predetermined value. Compare size. If the absolute value is equal to or less than the first predetermined value, it is determined that the steady state is present, and the steady state detection flag is set. If the absolute value exceeds the first predetermined value, it is determined that the state is unsteady, and the steady state detection flag is not set.

(2) Calculation of Fourier coefficient The steady voltage ripple generating means 16b calculates the Fourier coefficient of the basic period using the following equation using the cosine wave and sine wave reference signals generated from the reference signal generating means 16a.

  In actual calculation, a ripple waveform is captured at a period shorter than the basic period, multiplied by the cos value and sin value at that time, and a provisionally determined value of the Fourier coefficient is calculated at each zero crossing time. At that time, the integrated value is cleared at every zero crossing.

  If the steady state detection flag is set when the Fourier coefficient is tentatively determined, it is determined and determined that the Fourier coefficient in the steady state has been correctly obtained. When the steady state detection flag is not set, the provisionally determined value is discarded, and the currently held Fourier coefficient, that is, the Fourier coefficient in the previous steady state is maintained.

(3) Calculation of steady voltage ripple The steady voltage ripple generating means 16b calculates the steady voltage ripple at the current time based on the following equation using the Fourier coefficients determined in the steady state and the unsteady state.

Here, V _th ^(RIP) is a steady voltage ripple.

  Further, the output of the voltage compensator 28 is determined at the time when the input voltage waveform crosses zero in the steady state, and is determined in a cycle shorter than the predetermined zero crossing cycle in the other non-steady state. To do. In addition, the effective value of the input voltage waveform is calculated using the waveform data of the immediately preceding half cycle period at each time when the input voltage waveform crosses zero.

  The voltage error detection means 26 subtracts the steady voltage ripple generated according to the above procedure from the output voltage ripple at the current time to calculate the output voltage error, and determines that the steady state is in the absolute value if the absolute value is equal to or less than a predetermined value. .

If it is determined that the steady state, the current time is to update the output V _c of the input voltage times the consistent with long as the voltage compensator 28 where the waveform zero crossing, otherwise, the voltage compensator 28 currently held The output V _c is maintained.

On the other hand, if it is determined that the non-steady-state, predetermined, and updates the output V _c of the voltage compensator 28 in a shorter period than the zero crossing period.

Based on the output V _c of the voltage compensator 28, the input current command value generating unit 18 updates the input current amplitude. That is,
It is.

Here, V _ac ^(RMS) is an effective value of the input voltage, V _c is an output (compensation voltage) of the voltage compensator 28, and I _ac ^(REF) is an input current amplitude.

  Then, the input current command value at the current time is output using this input current amplitude.

Here, i _ac ^(REF) (t) is an input current command value at time t.

  As described above, the input current command value is generated based on the effective value of the input voltage and the compensation voltage, that is, the voltage ripple and the steady voltage ripple, and the switching element of the boost converter 10 is on / off controlled. Since the input current command value is generated using the voltage ripple in the steady state, the input current command value is not affected by the voltage ripple in the unsteady state.

FIG. 3 is an operation timing chart of the steady voltage ripple generating means 16b. The waveform of each part in case an input voltage rises rapidly at the time of A point is shown. In the figure, in order from the top, input voltage, input voltage (full-wave rectification), output voltage ripple, output voltage ripple average value, steady state detection flag, reference signal, integration every shortest cycle, Fourier coefficient (provisional decision value), Fourier coefficient (determined value) and regenerative steady voltage ripple. The output voltage ripple is a waveform extracted by the voltage ripple extracting means 25. The steady state detection flag is set by the steady voltage ripple generating means 16b. That is, the steady voltage ripple generating means 16b determines whether or not the absolute value of the output voltage ripple average value is equal to or smaller than the first predetermined value. If the absolute value is equal to or smaller than the first predetermined value, the steady state detection flag is set (in the figure). The steady state detection flag is not set if the first predetermined value is exceeded (Low state in the figure). The reference signal is a waveform generated by the reference signal generating means 16a. The integration for each shortest cycle is a waveform generated by the steady voltage ripple generating means 16b, and is an example where N = 2. The integrated value is cleared every zero crossing period. The Fourier coefficient (temporarily determined value) is a waveform generated by the steady voltage ripple generating means 16b, and is calculated regardless of whether or not it is in a steady state, that is, regardless of the state of the steady state detection flag. The Fourier coefficient (determined value) is a waveform generated by the steady voltage ripple generating means 16b, and is a waveform generated based on the Fourier coefficient (provisional determined value) and the steady state detection flag. That is,
Fourier coefficient (temporarily determined value) when the steady state detection flag is set
→ Fourier coefficient (decision value)
Fourier coefficient (temporarily determined value) when the steady state detection flag is not set
→ Fourier coefficient (determined value) in a state where the state is a discard and the steady state detection flag is not set is maintained as it is. In the figure, when the steady state detection flag is not set, the Fourier coefficient (temporarily determined value) is discarded as x, and the currently held Fourier coefficient (determined value) is maintained. The steady voltage ripple is a waveform generated by the steady voltage ripple generating means 16b and is a waveform calculated using a Fourier coefficient (determined value).

FIG. 4 is an operation timing chart of each part. The waveform of each part in case an input voltage rises rapidly at the time of A point is shown. In the figure, in order from the top, input voltage, input voltage (full wave rectification), input voltage (effective value), output voltage ripple, steady output voltage ripple, output voltage error, steady state determination flag, compensator output, and input current Amplitude. The input voltage (effective value) is a waveform generated by the input current command value generation means 18. The output voltage ripple is a waveform extracted by the voltage ripple extracting means 25. The steady output voltage ripple is a waveform generated by the steady voltage ripple generating means 16b. The output voltage error is a waveform generated by the voltage error detection means 26. The steady state determination flag is a waveform generated by the voltage compensator 28. That is, the voltage compensator 28 determines whether or not the voltage error, that is, the absolute value of the voltage error calculated by the difference between the steady output voltage ripple and the output voltage ripple is equal to or smaller than the second predetermined value. If it is below, the flag is set (Hi state in the figure), and the flag is not set when the second predetermined value is exceeded (Low state in the figure). Compensator output is waveform generated by the voltage compensator 28, if the steady state determination flag is set input voltage waveform updates the compensator output V _c at a period zero crossing, set the steady state determination flag is the input voltage waveform unless updates the compensator output V _c in a short predetermined period than the cycle of the zero crossing. In the figure, the state in which the compensator output _Vc is updated in a relatively short period when the steady state determination flag is not set is shown. Input current amplitude is a waveform that is generated by the input current command value generating unit 18, a waveform is calculated by using the compensator output V _c.

As described above, when the steady state is not established, the compensator output _Vc is updated in a shorter cycle than in the steady state, and the input current command value can be generated to control the input current.

  5 and 6 show circuit simulation results by the computer. FIG. 5 shows a simulation result of the conventional circuit in which the block 16 in FIG. 1 does not exist, and FIG. 6 shows a simulation result of the circuit of this embodiment. In both figures, waveforms of input voltage, input current, and output voltage are shown. In the conventional circuit, as shown in FIG. 5, the output voltage fluctuates greatly because the control of the input current is slow when the input voltage suddenly rises or falls, whereas in the circuit of this embodiment, as shown in FIG. It can be seen that the fluctuation of the output voltage is suppressed by immediately controlling the input current when the input voltage suddenly rises or falls. Therefore, in the circuit of the present embodiment, the output capacitor capacity of the boost converter 10 can be reduced, and the circuit can be reduced in size.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to this embodiment, A various deformation | transformation is possible. Hereinafter, modified examples will be described.

<Modification 1>
In the embodiment, the absolute value of the average value of the output voltage ripple is compared with the first predetermined value to determine whether or not the steady state is reached, and the steady voltage ripple at the current time is calculated using the Fourier coefficient in the steady state. Although the input current command value is generated, the first predetermined value functions as a threshold value, and is not necessarily fixed and may be adjusted as appropriate. The same applies to the second predetermined value. The accuracy of the steady state determination can be improved by confirming that a situation where the absolute value of the average value is equal to or less than the first predetermined value or a situation where the absolute value of the difference is equal to or less than the second predetermined value continues for a certain period of time. . Usually, the first predetermined value and the second predetermined value are different values, but may be simplified as the same value.

  In the embodiment, the steady voltage ripple generating means 16b determines whether or not the steady state is obtained by comparing the absolute value of the average value of the output voltage ripple with the first predetermined value. In the device 28, the absolute value of the difference between the output voltage ripple and the steady voltage ripple is compared with the second predetermined value to determine whether or not the steady state is reached. However, these steady state determinations may be shared. . For example, the steady-state determination result in the steady-state voltage ripple generating means 16b is used as the steady-state determination result in the voltage compensator 28.

<Modification 2>
In the embodiment, the reference signal generating means 16a, the steady voltage ripple generating means 16b, the input current command value generating means 18, and the voltage compensator 28 are constituted by a processor such as a CPU, and each calculation is performed by a processing program stored in a ROM or the like. However, in addition to processing with a single processor, distributed processing may be performed with a plurality of processors. Further, instead of software processing such as execution of a processing program by the processor, at least one of these blocks may be hardware processing using a dedicated circuit such as an ASIC or FPGA (Field Programmable Gate Array).

<Modification 3>
An isolated DCDC converter may be connected to the output of the power factor correction circuit of the embodiment to function as a charging device for a battery mounted on a vehicle, for example, and the charging device can be reduced in size by reducing the output capacitor capacity. It becomes possible to plan.

10 step-up conversion means, 12 input voltage detection means, 14 input current detection means, 16a reference signal generation means, 16b steady voltage ripple generation means, 18 input current command value generation means, 20 current error detection means, 22 switch control means, 24 Output voltage detection means, 25 voltage ripple extraction means, 26 voltage error detection means, 28 voltage compensator.

Claims (3)

A power factor correction circuit that boosts and converts an input AC voltage into a DC voltage,
Voltage ripple extracting means for extracting the difference between the output voltage and the DC target voltage of the output voltage as an output voltage ripple;
A reference signal generating means for generating a cosine wave and a sine wave having a frequency that is an integral multiple of the input voltage waveform as a reference signal;
A steady voltage ripple generating means for generating a voltage ripple in a steady state using the voltage ripple and the reference signal;
An input current command value generating means for generating an input current command value for controlling an input current using a voltage ripple in the steady state;
Power factor correction circuit with The steady voltage ripple generating means includes:
An average value of the output voltage ripple is calculated every half cycle period of the input voltage waveform, and when the absolute value of the average value is less than or equal to a predetermined value, the steady state is determined and when the average value exceeds the first predetermined value, Determination means for determining a steady state;
Fourier coefficient calculation means for calculating a Fourier coefficient using the reference signal and the output voltage ripple, with a half cycle period of the input voltage waveform as a basic period;
Among the Fourier coefficients, the Fourier coefficient determined by the determination unit as the steady state is used, and the Fourier coefficient determined as the previous steady state by the determination unit instead of the Fourier coefficient determined as the unsteady state by the determination unit Generating means for generating a voltage ripple in the steady state using a coefficient;
The power factor correction circuit according to claim 1. The input current command value generating means generates the input current command value at a cycle in which the input voltage waveform crosses zero when the absolute value of the difference between the output voltage ripple and the voltage ripple in the steady state is equal to or less than a second predetermined value. The force according to claim 2, wherein the input current command value is generated at an interval shorter than the cycle when an absolute value of a difference between the output voltage ripple and the voltage ripple in the steady state exceeds a second predetermined value. Rate improvement circuit.