JP2018136491A - Image display system and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display system having a combination of an imaging device and a display device.SOLUTION: An image display system includes: an imaging device having plural pixel blocks; and a display device having plural display areas. After displaying image data acquired by a first imaging mode as an image on the display device, the image display system switches a mode to a second imaging mode and acquires data representing presence/absence of a change of a subject. When any change is generated on the subject, the image display system switches the mode to the first imaging mode and acquires new image data to display a new image on the display device. When no change is generated on the subject, the image display system maintains display of an image stored in the display area and does not update the image.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a system for displaying an image with low power consumption.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, An operation method or a manufacturing method thereof can be given as an example.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.

An oxide semiconductor has attracted attention as a semiconductor material applicable to a transistor. For example, Patent Document 1 discloses an imaging device having a structure in which a transistor including an oxide semiconductor is used as part of a pixel circuit.

Further, Patent Document 2 discloses a liquid crystal display device which includes a transistor including an oxide semiconductor in a pixel and holds the image signal in the pixel for a long time by turning off the transistor.

JP 2011-119711 A JP 2011-141522 A

In an electronic device having an imaging device, a display device, and the like, it is desired to capture and display a high-definition image. On the other hand, as the image becomes higher definition, more data processing is required, and thus the power consumption of the electronic device tends to increase.

In one embodiment of the present invention, an object is to provide an image display system including an imaging device and a display device. Another object is to provide an image display system with low power consumption including an imaging device and a display device. Another object is to provide an image display system including an imaging device that can divide and drive pixels and a plurality of display devices arranged in a matrix. Another object is to provide an image display system including an imaging device having a difference detection function and a display device that operates while retaining image information. Another object is to provide an image display system including a novel imaging device and display device. Another object is to provide a novel semiconductor device or the like.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention relates to an image display system including an imaging device having a plurality of pixel blocks and a display device having a plurality of display areas.

One embodiment of the present invention is an image display system including an imaging device and a display device, the imaging device including a first pixel block, a second pixel block, an encoding device, and a storage device. Each of the first pixel block and the second pixel block has an imaging pixel, and the encoding apparatus includes a first block dividing unit and a second block dividing unit, The first block division unit has a function of dividing the first image data output from the first pixel block, and the second block division unit includes the second block output from the second pixel block. The encoding apparatus has a function of dividing image data, and the encoding apparatus compresses the first and second image data output from the first block dividing unit and the second block dividing unit to create third image data Storage function , Having a function of recording the third image data output from the encoding device, the display device has a first display region, a second display region, a decoding device, and a playback device, Each of the first display area and the second display area has a display pixel, and the decoding device has a first block reconstruction unit and a second block reconstruction unit, and a reproduction device Has a function of reading out the third image data, and the decoding device decompresses the third image data and outputs the data to each of the first block reconstruction unit and the second block reconstruction unit The first block reconstruction unit has a function of reconstructing the first image data from the input data and outputting the first image data to the first display area, and the second block reconstruction unit The second image data is reconstructed from the input data and the second An image display system having a function of outputting the display area.

The imaging apparatus has a first mode for acquiring image data and a second mode for detecting whether or not a subject has changed, and after acquiring image data in the first and second pixel blocks , A function of switching to the second mode, a function of switching the first and / or second pixel block that has detected a change in the subject to the first mode, and the first and / or first of switching to the first mode And a function of acquiring new image data with two pixel blocks.

In the first display area and the second display area, the display device has a function of storing image data in each of the display pixels, a function of displaying the image data as an image in each of the display pixels, And a function of rewriting only one of the images displayed in the second display area.

The first and second pixel blocks include imaging pixels arranged in a matrix, a drive circuit, and a data conversion circuit. The imaging pixels include a photoelectric conversion element and an oxide semiconductor as a semiconductor. The drive circuit has a second transistor having silicon as an active layer or active region, and the data conversion circuit has a third transistor having silicon as an active layer or active region. The photoelectric conversion element can have a region overlapping with the first transistor, and the photoelectric conversion element can have a region overlapping with the second transistor or the third transistor.

The first and second display regions include display pixels arranged in a matrix and a driver circuit, and the display pixels include a fourth transistor using an oxide semiconductor as a semiconductor layer. it can.

In addition, the first and second display areas may have flexibility.

The oxide semiconductor preferably includes indium, zinc, and M (M is aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium).

By using one embodiment of the present invention, an image display system including an imaging device and a display device can be provided. Alternatively, an image display system with low power consumption including an imaging device and a display device can be provided. Alternatively, it is possible to provide an image display system including an imaging device that can drive pixels in a divided manner and a plurality of display devices arranged in a matrix. Alternatively, an image display system including an imaging device having a difference detection function and a display device that operates while retaining image information can be provided. Alternatively, an image display system including a novel imaging device and display device can be provided. Alternatively, a novel semiconductor device or the like can be provided.

Note that one embodiment of the present invention is not limited to these effects. For example, one embodiment of the present invention may have effects other than these effects depending on circumstances or circumstances. Alternatively, for example, one embodiment of the present invention may not have these effects depending on circumstances or circumstances.

The figure explaining an image display system. FIG. 6 illustrates an imaging device. The figure explaining an encoding apparatus and a decoding apparatus. The figure explaining the data transmission method of an image display system. The flowchart explaining operation | movement of an image display system. The figure explaining operation | movement of an image display system. 3A and 3B each illustrate a pixel circuit of an imaging device. 6 is a timing chart illustrating operation of a pixel circuit of an imaging device. 6 is a timing chart illustrating operation of a pixel circuit of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 3 is a block diagram illustrating an imaging device, a circuit diagram of a CDS circuit, and a block diagram of an A / D conversion circuit. 2A and 2B are a top view and a perspective view illustrating a structure of an imaging device. FIG. 14 is a cross-sectional view illustrating a structure of an imaging device. FIG. 6 is a top view illustrating a display panel. Sectional drawing explaining a display panel. Sectional drawing explaining a display panel. FIG. 6 is a block diagram illustrating a display panel and a circuit diagram of a pixel. FIG. 14 illustrates a display device having a plurality of display regions. The figure explaining idling stop drive. The perspective view and sectional drawing of the package which accommodated the imaging device. The perspective view and sectional drawing of the package which accommodated the imaging device. 10A and 10B each illustrate an electronic device.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. Note that hatching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings.

The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

(Embodiment 1)
In this embodiment, the structure and operation of an image display system which is one embodiment of the present invention will be described.

One embodiment of the present invention is an image display system including an imaging device having a plurality of pixel blocks and a display device having a plurality of display areas. Note that in this specification, the pixel block means a region having imaging pixels. The display area means an area having display pixels.

For example, pixel blocks included in the imaging device are arranged in a matrix, and imaging pixels included in the pixel block are arranged in a matrix. Display regions included in the display device are arranged in a matrix, and display pixels included in the display region are arranged in a matrix.

The image data output from one pixel block is displayed as an image in one preset display area.

Each pixel block can be operated in a first imaging mode in which image data of a subject is acquired or in a second imaging mode in which data on whether or not a subject has changed is acquired. The display pixels in the display area can store image data.

That is, in the image display system of one embodiment of the present invention, first, the imaging device is operated in the first imaging mode, and the acquired image data is transmitted to the display device. Then, the imaging device is switched to the second imaging mode to acquire data on whether or not there is a change in the subject. When a change occurs in the subject, the mode is switched again to the first imaging mode, new image data is acquired, and a new image is transmitted to the display device. The display device displays the image data transmitted from the imaging device in each display area. In the display area where new image data has not been transmitted, the displayed image data is maintained and the image is not rewritten. Alternatively, an operation for reducing the frequency of rewriting is performed.

In the imaging apparatus, the power consumption can be reduced by switching to the second imaging mode. Further, when acquiring new image data, it is only necessary to switch the pixel block whose subject has changed to the first imaging mode. In each display area of the display device, the frequency of rewriting image data can be changed in accordance with a signal sent from each pixel block of the imaging device. In addition, since both the imaging device and the display device can operate each block in parallel, the operation speed can be reduced and power consumption can be reduced.

FIG. 1A is a block diagram illustrating an imaging device 100 and a display device 200 included in an image display system of one embodiment of the present invention.

The imaging device 100 includes a sensor unit 101, an encoding device 102, and a storage device 103. Image data output from the sensor unit 101 is compressed by the encoding device 102 and stored in the storage device 103. Then, it is output from the storage device 103 to the outside as necessary.

The sensor unit 101 has a plurality of pixel blocks arranged in a matrix. In FIG. 1A, pixel blocks 111 to 114, 121 to 124, 131 to 134, and 141 to 144 arranged in 4 rows and 4 columns are illustrated as an example, but not limited thereto, m rows and n columns. You may have the pixel block arrange | positioned (m and n are natural numbers greater than or equal to 1 except 1 line 1 column).

In the sensor portion 101, the pixel array 32 having a configuration in which the pixel arrays 21a to 21p shown in FIG. 2A are arranged in a matrix and the circuit portions 35a to 35p shown in FIG. 2B are arranged in a matrix. A stacked structure with the circuit portion 36 having the above structure (see FIG. 2C).

That is, each pixel block has a pixel array and a circuit part individually. Each pixel array includes an imaging pixel, and each circuit unit can include a circuit for driving the stacked pixel array, a data conversion circuit, a noise removal circuit, and the like. For example, the pixel block 111 illustrated in FIG. 1A includes a pixel array 21a and a circuit portion 35a.

In order to realize the configuration of the imaging device 100, it is preferable to use a configuration in which the pixel array and the circuit unit are stacked as described above. In the configuration in which the pixel array 21 provided with the drive circuit and the like at the end is arranged in a matrix, an area where pixels cannot be arranged is formed in the pixel array, and image information is missing when the entire pixel array is imaged. Part will occur.

The sensor unit 101 has a function of acquiring one image as a whole, but the pixel blocks 111 to 114, 121 to 124, 131 to 134, and 141 to 144 are individually independently imaged, data conversion, and data output operations. Etc. can also be performed.

Image data and the like output from the sensor unit 101 can be input to the encoding device 102 and the storage device 103 that perform data conversion, and can be output to the outside.

FIG. 3A is a block diagram illustrating an example of the encoding apparatus 102. The encoding apparatus 102 includes block division units 303 and 304, a frequency conversion unit 305, a quantization unit 306, an encoding unit 307, an inverse quantization unit 308, an inverse frequency conversion unit 309, an intra-screen prediction unit 310, and a motion compensation prediction unit 311. , A control unit 313, a subtraction circuit, an addition circuit, a selector circuit, and the like.

The number of block division units corresponds to the number of pixel blocks, and each block division unit can recursively divide an image. For example, it is possible to perform operations such as dividing the entire image acquired by the pixel block into four and further dividing one of them into four. Further, the division is repeated to obtain the optimum size (number of pixels) for processing. Subsequent processing is performed in units of divided ones (referred to as processing units). The process of dividing one pixel block and the subsequent processes are the same as those in general H.264. This can be realized by encoding according to the H.264 standard or the HEVC standard.

In the imaging device 100 of one embodiment of the present invention, since the sensor unit 101 is divided into a plurality of pixel blocks, some image division operations can be omitted as compared with an undivided sensor. As shown in FIG. 1, when the sensor unit 101 is divided into 16, the data of each pixel block can be read out. Therefore, an initial operation until the entire necessary image is divided into 1/16 can be omitted in an undivided sensor. Therefore, image compression processing and the like can be performed at high speed.

Signals 301 and 302 are image data output from different pixel blocks, and are input to the block division units 303 and 304. The data output from the block division units 303 and 304 is input to the frequency conversion unit 305 and becomes image data compressed through the quantization unit 306 and the encoding unit 307, respectively. The image data is stored in the storage device 103.

Further, the image data quantized by the quantization unit 306 is input to the intra-screen prediction unit 310 and the motion compensation prediction unit 311 via the inverse quantization unit 308 and the inverse frequency conversion unit 309. The in-screen prediction unit 310 predicts the value of the target pixel block using data of the adjacent upper pixel block and left pixel block.

Here, when the image data captured by one pixel block is not changed, each pixel block outputs a signal 312 indicating the unchanged state when detecting the unchanged state. The encoding apparatus 102 can receive the signal 312 at the control unit 313 and stop the generation of the corresponding block division unit, frequency conversion unit 305, quantization unit 306, clock signal, and power supply. In addition, data 314 representing an invariant state calculated in advance can be output.

The display device 200 includes a display unit 201, a playback device 202, and a decoding device 203. The display unit 201 has a plurality of display areas arranged in a matrix. In FIG. 1, display areas 211 to 214, 221 to 224, 231 to 234, and 241 to 244 arranged in 4 rows and 4 columns are illustrated as an example, but not limited thereto, m rows and n columns (m and n) n may be a natural number greater than or equal to 1, except for one row and one column).

One display area can be one of a plurality of divided display panels. Alternatively, one display area can be one display panel. In one embodiment of the present invention, the former is preferably the latter because the control becomes complicated.

In the playback device 202, the data recorded in the storage device 103 of the imaging device 100 is played back. Data decompressed by the decoding device 203 is output to the display unit 201 and displayed as an image.

FIG. 3B is a block diagram illustrating an example of the decoding device 203. The decoding device 203 includes a decoding unit 321, an inverse quantization unit 322, a reconstruction unit 323, an intra-screen prediction unit 324, a motion compensation prediction unit 325, an addition circuit, a selector circuit, and the like. Note that the reconstruction unit 323 includes block reconstruction units corresponding to the number of display areas.

Data reproduced by the reproduction apparatus 202 is decompressed by the decoding unit 321 and input to the reconstruction unit 323 via the inverse quantization unit 322.

The reconstruction unit 323 reconstructs the recursively divided image and improves the image quality of the boundary. Here, the recursively divided video is distributed to the block reconstructing units 331 and 332 and reconstructed in parallel. Eventually, the boundary between the image of the block reconstruction unit 331 and the image of the block reconstruction unit 332 is improved by the mutual information, but the image data is not combined and is output individually to different display areas. That is, in the display device 200 of one embodiment of the present invention, since the display portion 201 is divided into a plurality of display areas, an operation of combining image data in the reconstruction portion 323 can be omitted. Therefore, the read image data can be displayed at high speed.

Here, when the case where there is no change in the image of one display area is set as an invariant state, the block reconstructing units 331 and 332 can detect the invariant state from the data string of the motion compensation prediction unit 325. The block reconstruction units 331 and 332 can output invariant signals in addition to image data, and can stop writing new image data to the display area.

Specifically, a state where the motion vector is zero and the encoded image is zero in a desired region is detected. Alternatively, for example, in a standard having a signal called a skip macroblock, an invariant state can be detected by the signal. Thus, in one embodiment of the present invention, unlike the existing standard, the invariant state can be used not only for compression but also for control of the display device.

Transmission of data from the imaging device 100 to the display device 200 can be performed using a transmission line 351 connecting the storage device 103 and the playback device 202 as shown in FIG. Alternatively, the data stored in the storage device 103 may be moved to a removable recording medium, and the data may be displayed on the display device 200 by reading the data on the recording medium with the playback device 202.

Note that the storage device 103 and the playback device 202 are not limited to the configuration in which the storage device 103 and the playback device 202 are directly connected to each other, but may have a configuration in which data is transmitted by wireless communication using the electromagnetic wave 352 as illustrated in FIG. . In this case, data transmission may be performed via the repeater 150 as shown in FIG. Further, the wireless communication using the electromagnetic wave 352 may be performed between all elements between the encoding device 102 and the decoding device 203 as shown in FIG. Note that the element described as being capable of wireless communication has a data transmission function or a reception function.

By using wireless communication in this manner, data transmission can be performed conveniently even when the imaging apparatus 100 and the display apparatus 200 are at a long distance or when there is an obstacle between the two. it can. In addition, since the storage device 103 can be separated from the imaging device 100, the imaging device 100 can be reduced in size. Similarly, since the playback device 202 can be separated from the display device 200, the degree of freedom such as the installation location of the display device 200 can be increased.

Here, the pixel block included in the sensor unit 101 and the display area included in the display device 200 preferably have the same number of rows and columns. However, the operation is possible even if the two do not match. In addition, it is preferable that the number of effective imaging pixels included in each pixel block and the number of effective display pixels included in each display panel are substantially the same. It should be noted that image information can be up-converted or down-converted by an external device so that the image information can be operated even if they do not match.

Image data output from one pixel block is displayed as an image in one display area corresponding to a row and a column. For example, the image data acquired in the pixel block 111 and transmitted to the display device 200 is displayed in the display area 211. However, the correspondence between the pixel block and the display area may be different from the above when the image is displayed in an inverted manner or when a special display is performed. That is, the image data output from one pixel block can be set to be displayed as an image in an arbitrary display area.

A specific operation method of the image display system of one embodiment of the present invention will be described with reference to a flowchart shown in FIG. 5 and FIG.

Note that in the image display system of one embodiment of the present invention, the first operation mode in which image data is repeatedly acquired at a constant frame frequency and the entire image is rewritten at the constant frame frequency, and a difference from the initial image data is detected. In this case, the second operation mode for rewriting an image in a part of the display area or in the entire display area can be selected.

Although the control of the first operation mode is simple, the power consumption is large because the image is rewritten at regular intervals even when there is no change in the imaging target. In addition, the amount of data output from the imaging device 100 is enormous. Below, the 2nd operation mode which can reduce power consumption using the characteristic which divided | segmented the sensor part 101 and the display part 201 is demonstrated.

First, the imaging apparatus 100 performs imaging in the first imaging mode (S1). The first imaging mode is a mode in which image data such as gradation and color is acquired at each pixel, and imaging is performed at all pixel blocks.

Next, the image data is transmitted to the display device 200 via the encoding device 102 and the storage device 103 (S2).

In the display device 200, the transmitted image data is input to each display area corresponding to each pixel block via the reproduction device 202 and the decoding device 203, and an initial image is displayed (S3).

The operation from S1 to S3 will be described with reference to FIG. FIG. 6A shows an example of capturing an image of a person and a stationary background. The pixel blocks 111 to 114, 121 to 124, 131 to 134, and 141 to 144 operate in the first imaging mode to acquire image data and transmit it to the display device 200.

The human images captured by dividing the pixel blocks 123, 124, 133, 134, 143, and 144 are displayed in the display areas 223, 224, 233, 234, 243, and 244, respectively. Background images captured by other pixel blocks are displayed in other corresponding display areas.

Next, the same subject is imaged by switching to the second imaging mode (S4). The second imaging mode is a mode for detecting only changes in the position and brightness of the subject, and imaging is performed with all pixel blocks.

In the second imaging mode, first, the brightness data of the subject is stored in each pixel, and whether or not there is a change in brightness is determined every certain period. Since the difference between the reference data and the current data is detected, it can also be referred to as a difference detection mode. In order to operate in this manner, a transistor with a low off-state current using an oxide semiconductor (hereinafter referred to as an OS transistor) that is suitable for holding the potential of the charge holding portion is preferably used for the pixel of the imaging device 100.

The presence or absence of a difference is determined (S5). If it is determined that there is no difference, the process returns to S4 and the difference determination is performed again. During the period in which it is determined that there is no difference, the display unit 201 continues the display without rewriting the initial image displayed in S3. Alternatively, the initial image data is written again and displayed at a very low frame frequency (for example, 1.16 × 10 ⁻⁵ Hz (frequency about once a day) to 1 Hz). In order to operate in this manner, an OS transistor with low off-state current which is suitable for holding the potential of the storage capacitor is preferably used for the pixel of the display device 200. In addition, in the present specification, an operation for extremely reducing the frequency of image rewriting as described above is referred to as idling stop driving.

Also, the presence / absence of a difference is determined (S5). If it is determined that there is a difference, only the pixel block in which the difference is detected is switched to the first imaging mode and the same subject is imaged (S6).

Next, the image data acquired by the pixel block is transmitted to the display device 200 via the encoding device 102 and the storage device 103 (S7).

Next, in the display device 200, the transmitted image data is read out via the reproduction device 202 and the decoding device 203, and the image in the display area corresponding to the pixel block is rewritten (S8). Then, the process returns to S4 and the difference determination is performed again. In order to prevent malfunction and maintain display quality, an operation may be performed to return to S1 and retake the entire image at regular intervals regardless of whether there is a difference or not.

The operation from S4 to S8 will be described with reference to FIGS.

FIG. 6B shows the operation when no difference is detected in S4 and S5 (the person and the background are not changed). The shaded pixel blocks 111 to 114, 121 to 124, 131 to 134, 141 to 144 operate in the second imaging mode, and the shaded display areas 211 to 124, 221 to 224, 231 to 234, 241 to 244 are displayed. Has idling stop drive. Data without difference output from all the pixel blocks is transmitted to the display device 200, and the display unit 201 continuously displays the image displayed in S3.

FIG. 6C shows an operation when a difference is detected in S4 to S8. A person image indicated by a broken line in the sensor unit 101 and the display unit 201 indicates an initial position of the person. In nine blocks of pixel blocks 122, 123, 124, 132, 133, 134, 142, 143, and 144 without diagonal lines, a difference is detected in the second imaging mode by the movement of a person, and the first imaging mode is switched to. New image data is acquired. In addition, since there is no change in the background in the seven blocks including the shaded pixel blocks 111, 112, 113, 114, 121, 131, and 141, the imaging in the second imaging mode is continued.

The image data newly picked up by the 9 blocks and the data without difference of the 7 blocks are transmitted to the display device 200, and the images of the display areas 222, 223, 224, 232, 233, 234, 242, 243, 244 are displayed. Rewritten. In the seven blocks of the display areas 211, 212, 213, 214, 221, 231, and 241, the image displayed in S3 is continuously displayed.

As described above, in the imaging apparatus 100, after acquiring initial images in all the pixel blocks in the first imaging mode, all the pixel blocks are switched to the second imaging mode, and only the pixel blocks in which differences are detected are detected. Switch to the first imaging mode and reacquire the image. Then, the imaging in the second imaging mode is performed again for all the pixel blocks, and the operation of acquiring the image by switching to the first imaging mode only for the pixel block in which the difference is detected is repeatedly performed.

In the second imaging mode, it is not necessary to reset the potential of the charge holding node of the imaging pixel even if imaging is repeated. When a difference is detected, only the corresponding pixel block is switched to the first imaging mode to acquire a new image. Therefore, it can operate with low power consumption. Further, in the second imaging mode, it is only necessary to detect the presence or absence of a difference, and the A / D converter can reduce the number of bits of data to be read and reduce power consumption.

Further, in the display device 200, after the initial image is displayed, the image display can be continued by idling stop driving unless new image data is transmitted from the imaging device 100. Therefore, since the rewriting frequency can be reduced, power consumption can be reduced. In addition, the ability to rewrite an image in units of display areas, not the entire display unit 201, contributes to a reduction in power consumption.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of a pixel circuit which can be used for a pixel included in the imaging device 100 described in Embodiment 1 and a driving method thereof will be described.

FIG. 7A illustrates an example of a pixel circuit included in the imaging device 100. Note that although an example in which the transistor is an n-ch type is illustrated in FIG. 7A and the like, one embodiment of the present invention is not limited thereto, and some transistors are replaced with p-ch transistors. Also good.

The pixel circuit can include a photoelectric conversion element PD, a transistor 41, a transistor 42, a transistor 43, a transistor 44, a transistor 45, a capacitor C1, and a capacitor C2. Note that the capacitor C2 may not be provided.

One terminal of the photoelectric conversion element PD is electrically connected to one of the source and the drain of the transistor 41. The other of the source and the drain of the transistor 41 is electrically connected to one of the source and the drain of the transistor 42. The other of the source and the drain of the transistor 41 is electrically connected to one terminal of the capacitor C1. The other terminal of the capacitor C <b> 1 is electrically connected to one of the source and the drain of the transistor 45. The other terminal of the capacitor C <b> 1 is electrically connected to the gate of the transistor 43. The other terminal of the capacitive element C1 is electrically connected to one terminal of the capacitive element C2. One of the source and the drain of the transistor 43 is electrically connected to one of the source and the drain of the transistor 44. The other terminal of the capacitor C <b> 2 is electrically connected to the other of the source and the drain of the transistor 43.

Here, a node to which the other of the source and the drain of the transistor 41, one of the source and the drain of the transistor 42, and one terminal of the capacitor C1 are connected is FD1. Further, a node to which the other terminal of the capacitor C1, one of the source and the drain of the transistor 45, the gate of the transistor 43, and one terminal of the capacitor C2 are connected is FD2.

The other terminal of the photoelectric conversion element PD is electrically connected to the wiring 71 (VPD). The other of the source and the drain of the transistor 42 is electrically connected to the wiring 72 (VPR). The other of the source and the drain of the transistor 45 is electrically connected to the wiring 74 (VCS). The other of the source and the drain of the transistor 43 and the other terminal of the capacitor C2 are electrically connected to the wiring 73 (VPI). The other of the source and the drain of the transistor 44 is electrically connected to the wiring 91 (OUT1).

The wiring 71 (VPD), the wiring 72 (VPR), the wiring 73 (VPI), and the wiring 74 (VCS) can function as power supply lines. For example, the wiring 71 (VPD) and the wiring 74 (VCS) can function as low potential power supply lines. The wiring 72 (VPR) and the wiring 73 (VPI) can function as high potential power supply lines.

A gate of the transistor 41 is electrically connected to the wiring 61 (TX). A gate of the transistor 42 is electrically connected to the wiring 62 (PR). A gate of the transistor 45 is electrically connected to the wiring 65 (W). A gate of the transistor 44 is electrically connected to the wiring 63 (SE).

The wiring 61 (TX), the wiring 62 (PR), the wiring 63 (SE), and the wiring 65 (W) can function as signal lines that control conduction of the transistors.

In the above structure, the other terminal of the capacitor C2 may be connected not to the wiring 73 (VPI) but to other wiring or the like that can supply a fixed potential.

Note that the transistor included in the pixel circuit may be provided with a back gate as illustrated in FIG. FIG. 7B illustrates a structure in which a constant potential is applied to the back gate, and the threshold voltage can be controlled.

Different potentials can be individually supplied to the wirings 75 to 79 connected to the respective back gates. Note that a wiring connected to the back gate of the transistor 43 and the transistor 44 may be electrically connected.

When the transistor is an n-ch type, the threshold voltage shifts in the positive direction when a potential lower than the source potential is applied to the back gate. Conversely, when a potential higher than the source potential is applied to the back gate, the threshold voltage shifts in the negative direction.

In the circuits illustrated in FIGS. 7A and 7B, it is desirable that the potential holding ability of the node FD1 and the node FD2 is high. Therefore, transistors with low off-state current are preferably used as the transistors 41, 42, and 45. By applying a potential lower than the source potential to the back gates of the transistors 41, 42, and 45, the off-state current can be further reduced. Accordingly, the potential holding ability of the nodes FD1 and FD2 can be increased. For example, OS transistors are preferably used as the transistors 41, 42, and 45.

Further, as described above, it is preferable to use a transistor with a high on-state current as the transistors 43 and 44. By applying a potential higher than the source potential to the back gates of the transistors 43 and 44, the on-state current can be further increased. Accordingly, the read potential output to the wiring 91 (OUT1) can be quickly determined, that is, the operation can be performed at a high frequency. For example, the transistors 43 and 44 are preferably transistors using silicon in the active region or active layer (hereinafter referred to as Si transistors).

Note that the transistor 44 may have a structure in which the same potential as that of the front gate is applied to the back gate as illustrated in FIG. The transistors 43 and 44 may be OS transistors instead of Si transistors. Although the on-state current of the OS transistor is relatively small, the on-state current can be increased by providing a back gate capable of supplying the same potential as that of the front gate, and can be operated at a high frequency.

In addition, in addition to each power supply potential, a plurality of potentials such as a signal potential and a potential applied to the back gate are used inside the imaging device. When a plurality of potentials are supplied from the outside of the imaging device, the number of terminals and the like increase. Therefore, it is preferable to have a power supply circuit that generates a plurality of potentials inside the imaging device.

Since the OS transistor has extremely low off-state current characteristics, the low off-current characteristics of the transistors 41, 42, and 43 can significantly increase the period during which charges can be held in the node FD1 and the node FD2. Therefore, it is possible to apply a global shutter system in which charge accumulation operation is simultaneously performed in all pixels without complicating a circuit configuration and an operation method. Note that the imaging device of one embodiment of the present invention can also be operated by a rolling shutter system.

The OS transistor can be used in a very wide temperature range because the temperature dependence of the electrical characteristic variation is smaller than that of the Si transistor. Therefore, an imaging device and a semiconductor device having an OS transistor are suitable for mounting on automobiles, aircraft, spacecrafts, and the like.

The OS transistor has a higher drain breakdown voltage than the Si transistor. In a photoelectric conversion element using a selenium-based material as a photoelectric conversion layer, avalanche multiplication can be used, and it is preferable to operate by applying a relatively high voltage (for example, 10 V or more). Therefore, by combining an OS transistor and a photoelectric conversion element using a selenium-based material as a photoelectric conversion layer, an imaging device with high reliability can be obtained.

The pixel circuit described in this embodiment holds the difference data between the operation in the first operation mode in which normal imaging is performed and the image data of the initial frame and the image data of the current frame, and according to the difference data It is possible to perform the operation in the second operation mode that can output the received signal. In the second operation mode, difference data can be output without performing comparison processing or the like in an external circuit. Therefore, the pixel circuit is preferably used for the imaging device 100 described in Embodiment 1.

A case where the pixel circuit illustrated in FIG. 7A is operated in the first operation mode is described with reference to a timing chart illustrated in FIG.

From time T1 to time T2, the wiring 61 (TX) is set to “H”, the wiring 62 (PR) is set to “H”, and the wiring 65 (W) is set to “H”. At this time, the potential of the node FD1 is set to the potential VPR of the wiring 72 (VPR), and the potential of the node FD2 is set to the potential VCS of the wiring 74 (VCS) (reset operation).

From time T2 to time T3, the wiring 61 (TX) is set to “H”, the wiring 62 (PR) is set to “L”, and the wiring 65 (W) is set to “L”. Here, when the potential of the node FD1 decreases in accordance with the light applied to the photoelectric conversion element PD, the potential of the node FD2 also decreases due to capacitive coupling. Assuming that the reduced potential amount of the node FD1 at time T3 is VA, the potential of the node FD1 is VPR−VA. Further, the potential of the node FD2 decreases by VB and becomes VCS−VB (accumulation operation). Note that in the circuit configuration illustrated in FIG. 7A, the potential of the node FD1 and the node FD2 decreases as the light applied to the photoelectric conversion element PD increases.

From time T3 to time T4, when the wiring 61 (TX) is “L”, the wiring 62 (PR) is “L”, and the wiring 65 (W) is “L”, the potentials of the nodes FD1 and FD2 are held. .

From time T4 to time T5, when the wiring 63 (SE) is set to “H”, a signal corresponding to image data is output to the wiring 91 (OUT1) in accordance with the potential of the node FD2 (selection operation). The above is the description of the first operation mode.

Next, the case where the pixel circuit illustrated in FIG. 7A is operated in the second operation mode is described. In the second operation mode, a data difference between the first frame (reference frame) and the second frame (difference target frame) is output. First, a data acquisition operation in the first frame will be described with reference to a timing chart shown in FIG.

From time T1 to time T2, the wiring 61 (TX) is set to “H”, the wiring 62 (PR) is set to “H”, and the wiring 65 (W) is set to “H”. At this time, the potential of the node FD1 is set to the potential VPR of the wiring 72 (VPR), and the potential of the node FD2 is set to the potential VCS of the wiring 74 (VCS).

From time T2 to time T3, the wiring 61 (TX) is set to “H”, the wiring 62 (PR) is set to “L”, and the wiring 65 (W) is set to “H”. Here, the potential of the node FD1 decreases in accordance with the light applied to the photoelectric conversion element PD. Assuming that the reduced potential amount of the node FD1 at time T3 is VA, the potential of the node FD1 is VPR−VA. Note that in the circuit configuration in FIG. 7A, the potential of the node FD1 decreases as the light applied to the photoelectric conversion element PD increases.

From time T3 to time T4, when the wiring 61 (TX) is “L”, the wiring 62 (PR) is “L”, and the wiring 65 (W) is “H”, the potential of the node FD1 is held.

From time T4 to time T5, when the wiring 61 (TX) is “L”, the wiring 62 (PR) is “L”, and the wiring 65 (W) is “L”, the potential of the node FD1 and the potential of the node FD2 are held. Is done.

Next, a data acquisition operation in the second frame will be described with reference to a timing chart shown in FIG. In FIG. 9A, it is assumed that there is no difference in data between the first frame and the second frame, that is, the case where the images captured in the first frame and the second frame are the same.

From time T1 to time T2, when the wiring 61 (TX) is “H”, the wiring 62 (PR) is “H”, and the wiring 65 (W) is “L”, the potential of the node FD1 rises by VA, The potential of FD2 rises by VB due to capacitive coupling. Here, VA and VB are potentials that reflect the illuminance of the first frame.

From time T2 to time T3, when the wiring 61 (TX) is “H”, the wiring 62 (PR) is “L”, and the wiring 65 (W) is “L”, the light is applied to the photoelectric conversion element PD. The potentials of the nodes FD1 and FD2 are lowered. Assuming that the decrease potential amount of the node FD1 at time T3 is VA ', the potential of the node FD1 becomes VPR-VA', but becomes VP-VA because VA '= VA. Further, the potential of the node FD2 decreases by VB ′ due to capacitive coupling and becomes VCS + VB−VB ′, but becomes VCS when VB ′ = VB.

From time T3 to time T4, when the wiring 61 (TX) is “L”, the wiring 62 (PR) is “L”, and the wiring 65 (W) is “L”, the potentials of the nodes FD1 and FD2 are held. .

From time T4 to time T5, when the wiring 63 (SE) is set to “H”, a signal corresponding to the image data is output to the wiring 91 (OUT1) in accordance with the potential of the node FD2. At this time, the potential of the node FD2 is “VCS” which is a reset potential, and it is determined that there is no significant difference in the comparison of the data of the first frame and the second frame from the output signal.

Next, when there is a difference in data between the first frame and the second frame using the timing chart shown in FIG. 9B, that is, images captured in the first frame and the second frame are different. The operation assuming the case of an image will be described. Note that the illuminance of light incident on the target pixel has a relationship of first frame <second frame.

From time T1 to time T2, when the wiring 61 (TX) is “H”, the wiring 62 (PR) is “H”, and the wiring 65 (W) is “L”, the potential of the node FD1 rises by VA, The potential of FD2 rises by VB due to capacitive coupling. Here, VA and VB are potentials that reflect the illuminance of the first frame.

From time T2 to time T3, when the wiring 61 (TX) is “H”, the wiring 62 (PR) is “L”, and the wiring 65 (W) is “L”, the light is applied to the photoelectric conversion element PD. The potentials of the nodes FD1 and FD2 are lowered. Assuming that the reduced potential amount of the node FD1 at time T3 is VA ', the potential of the node FD1 is VPR-VA'. Further, the potential of the node FD2 decreases by VB ′ due to capacitive coupling and becomes VCS + VB−VB ′.

From time T3 to time T4, when the wiring 61 (TX) is “L”, the wiring 62 (PR) is “L”, and the wiring 65 (W) is “L”, the potentials of the nodes FD1 and FD2 are held. .

From time T4 to time T5, when the wiring 63 (SE) is set to “H”, a signal corresponding to the image data is output to the wiring 91 (OUT1) in accordance with the potential of the node FD2. At this time, the potential of the node FD2 is VCS + VB−VB ′. VB is a potential that reflects the illuminance of the first frame, and VB 'is a potential that reflects the illuminance of the second frame. The above is the description of the second operation mode for outputting the data difference between the first frame and the second frame.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, a specific configuration of the imaging device 100 described in Embodiments 1 and 2 will be described.

FIGS. 10A, 10 </ b> B, and 10 </ b> C are diagrams illustrating a specific configuration of a pixel circuit corresponding to FIG. 7A or 7 </ b> B. 10A is a cross-sectional view illustrating the channel length direction of the transistors 41, 42, 43, and 44. FIG. 10B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 10A and illustrates a cross section of the transistor 41 in the channel width direction. 10C is a cross-sectional view taken along dashed-dotted line Y1-Y2 in FIG. 10A and represents a cross section of the transistor 43 in the channel width direction.

The imaging device of one embodiment of the present invention includes a layer 1100, a layer 1200, and a layer 1300 as illustrated in FIG.

The layer 1100 can include a photoelectric conversion element PD. For example, a two-terminal photodiode can be used for the photoelectric conversion element PD. As the photodiode, a pn-type photodiode using a single crystal silicon substrate, an amorphous silicon thin film, a pin-type photodiode using a microcrystalline silicon thin film or a polycrystalline silicon thin film, a photo using selenium or a compound of selenium. A diode or a photodiode using an organic compound can be used.

The layer 1200 can include the transistors 41, 42, and 45. As the transistors 41, 42, and 45, OS transistors are preferably used. The transistor 45 is not shown.

The layer 1300 can include the transistor 43 and the transistor 44. As the transistors 43 and 44, transistors using silicon as an active layer or an active region are preferably used. A transistor having silicon as an active layer or an active region has a large on-state current, and can efficiently amplify the potential of the node FD2.

Note that although the capacitor C1 has a structure in which the conductive layer 84 and the conductive layer 85 are used as electrodes and the insulating layer 83 is used as a dielectric layer in the layer 1300, the capacitor C1 may be provided in the layer 1200. Further, although the capacitor C2 is not illustrated, the capacitor C2 may be provided in any of the layer 1200 and the layer 1300.

In the cross-sectional views described in this embodiment, wirings, electrodes, metal layers, and contact plugs (conductors 82) are illustrated as individual elements. However, in the case where they are electrically connected, they are the same. It may be provided as an element. The form in which elements such as wiring, electrodes, and metal layers are connected via the conductor 82 is merely an example, and each element may be directly connected without passing through the conductor 82.

Over each element such as a transistor, insulating layers 81a to 81i having a function as a protective film, an interlayer insulating film, or a planarization film are provided. For example, the insulating layers 81a to 81i can be formed using an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film. Alternatively, an organic insulating film such as an acrylic resin or a polyimide resin may be used. The top surfaces of the insulating layers 81a to 81i and the like are preferably subjected to planarization treatment by a CMP (Chemical Mechanical Polishing) method or the like as necessary.

Note that some of the wirings and the like illustrated in the drawings may not be provided, or wirings, transistors, and the like that are not illustrated in the drawings may be included in each layer. In addition, a layer not shown in the drawing may be included in the stacked structure. In addition, some of the layers shown in the drawings may not be included.

Insulating layers 80a and 80b having a function of preventing hydrogen diffusion are provided between the region where the OS transistor is formed and the region where the Si device (Si transistor or Si photodiode) is formed. Hydrogen in the insulating layer provided near the active region of the transistors 43 and 44 terminates the dangling bond of silicon. On the other hand, hydrogen in the insulating layer provided in the vicinity of the oxide semiconductor layer which is an active layer of the transistors 41 and 42 is one of the factors that generate carriers in the oxide semiconductor layer.

The reliability of the transistors 43 and 44 can be improved by confining hydrogen in one layer by the insulating layers 80a and 80b. In addition, since the diffusion of hydrogen from one layer to the other layer is suppressed, the reliability of the transistors 41 and 42 can be improved.

As the insulating layers 80a and 80b, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used. it can.

In FIG. 10A, the photoelectric conversion element PD included in the layer 1100 is a photodiode including selenium in the photoelectric conversion layer. The photoelectric conversion element PD can include a photoelectric conversion layer 561, a light-transmitting conductive layer 562, an electrode 566, a partition wall 567, and a wiring 571.

The layer 1200 is provided with a transistor 41 and a transistor 42 which are OS transistors. Although the transistors 41 and 42 both have a configuration having a back gate, some transistors, for example, only the transistor 41 may have a back gate. In some cases, the back gate is electrically connected to a front gate of a transistor provided to face the back gate as illustrated in FIG. Alternatively, the back gate may be supplied with a fixed potential different from that of the front gate.

In FIG. 10A, a non-self-aligned top gate transistor is illustrated as the OS transistor. However, as shown in FIG. 11A, a self-aligned transistor may be used.

As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium. For example, a CAC-OS described later can be used.

The semiconductor layer is represented by an In-M-Zn-based oxide containing indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It can be a membrane.

In the case where the oxide semiconductor included in the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is In ≧ M, Zn It is preferable to satisfy ≧ M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 3, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8 etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.

As the semiconductor layer, an oxide semiconductor with low carrier density is used. For example, the semiconductor layer has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, more preferably 1 × 10 ¹³ / cm ³ or less, more preferably 1 × 10 ¹¹ / cm 3. ³ or less, more preferably less than 1 × 10 ¹⁰ / cm ³ , and an oxide semiconductor having a carrier density of 1 × 10 ⁻⁹ / cm ³ or more can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Accordingly, it can be said that the oxide semiconductor has stable characteristics because the impurity concentration is low and the density of defect states is low.

Note that the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (such as field-effect mobility and threshold voltage) of the transistor. In addition, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the semiconductor layer have appropriate carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like. .

In the oxide semiconductor constituting the semiconductor layer, when silicon or carbon, which is one of Group 14 elements, is included, oxygen deficiency increases and the n-type semiconductor is formed. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when alkali metal and alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, which may increase off-state current of the transistor. For this reason, the concentration of alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. To.

In addition, when nitrogen is contained in the oxide semiconductor included in the semiconductor layer, electrons as carriers are generated, the carrier density is increased, and the oxide semiconductor is easily n-type. As a result, a transistor including an oxide semiconductor containing nitrogen is likely to be normally on. Therefore, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

The semiconductor layer may have a non-single crystal structure, for example. The non-single-crystal structure includes, for example, a CAAC-OS (C-Axis Crystalline Oxide Semiconductor Semiconductor having a crystal oriented in the c-axis, or a C-Axis Aligned and A-B-Plane Annealed Crystal Oxide Crystal Structure, Includes a microcrystalline structure or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

An oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystal component. Alternatively, an amorphous oxide film has, for example, a completely amorphous structure and does not have a crystal part.

Note that the semiconductor layer may be a mixed film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Good. For example, the mixed film may have a single-layer structure or a stacked structure including any two or more of the above-described regions.

Hereinafter, a structure of a CAC (Cloud-Aligned Composite) -OS which is one embodiment of a non-single-crystal semiconductor layer is described.

The CAC-OS is one structure of a material in which an element included in an oxide semiconductor is unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as a mosaic or patch.

Note that the oxide semiconductor preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition, aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or One or more kinds selected from magnesium or the like may be contained.

For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). _X1 (X1 is greater real than 0) and.), or indium zinc oxide _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic _{InO X1} or _in X2 _Zn Y2 _{O Z2,} is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.

That, CAC-OS includes a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is the main component region is a composite oxide semiconductor having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

On the other hand, CAC-OS relates to a material structure of an oxide semiconductor. CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn and O, and nanoparticles mainly composed of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.

Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.

Incidentally, a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component region, in some cases clear boundary can not be observed.

In place of gallium, aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium are selected. In the case where one or a plurality of types are included, the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.

The CAC-OS can be formed by a sputtering method under a condition where the substrate is not intentionally heated, for example. In the case where a CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. For example, the flow rate ratio of the oxygen gas is 0% to less than 30%, preferably 0% to 10%. .

The CAC-OS is characterized in that no clear peak is observed when it is measured using a θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.

In addition, in the CAC-OS, in an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-shaped high luminance region and a plurality of regions in the ring region are provided. A bright spot is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

In addition, for example, in a CAC-OS in an In—Ga—Zn oxide, GaO _X3 is a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region and the region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 are unevenly distributed and mixed.

The CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO _X3 or the like is a main component and a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is a region having higher conductivity than a region containing GaO _X3 or the like as a main component. _That, In _{X2 Zn} Y2 _{O Z2} or _{InO X1,} is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Therefore, a region where In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility (μ) can be realized.

On the other hand, areas such as _{GaO X3} is the main _component, as compared to the In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component area, it is highly regions insulating. That is, a region containing GaO _X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _{X3 and the} like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act complementarily, thereby increasing the An on-current (I _on ) and high field effect mobility (μ) can be realized.

In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is suitable as a constituent material for various semiconductor devices.

The layer 1300 is provided with a transistor 43 and a transistor 44 which are Si transistors. In FIG. 10A, the transistors 43 and 44 exemplify a fin type structure, but may be a planar type as shown in FIG. Alternatively, as illustrated in FIG. 11C, a transistor including an active layer 660 of a silicon thin film may be used. The active layer 660 can be made of polycrystalline silicon or SOI (Silicon on Insulator) single crystal silicon.

A photoelectric conversion element PD using a selenium-based material has a high external quantum efficiency with respect to visible light. Further, since the selenium-based material has a high light absorption coefficient, it has an advantage that the photoelectric conversion layer 561 can be easily thinned. The photoelectric conversion element PD using a selenium-based material can be a highly sensitive sensor with large amplification by avalanche multiplication. That is, by using a selenium-based material for the photoelectric conversion layer 561, a sufficient photocurrent can be obtained even when the pixel area is reduced. Therefore, it can be said that the photoelectric conversion element PD using the selenium-based material is suitable for imaging in a low illumination environment.

As the selenium-based material, amorphous selenium or crystalline selenium which is a p-type semiconductor can be used. Crystalline selenium can be obtained, for example, by heat-treating amorphous selenium after film formation. By making the crystal grain size of crystalline selenium smaller than the pixel pitch, it is possible to reduce variation in characteristics from pixel to pixel. Crystalline selenium has higher spectral sensitivity to visible light and higher light absorption coefficient than amorphous selenium.

In FIG. 10A, the photoelectric conversion layer 561 is illustrated as a single layer; however, an n-type semiconductor such as gallium oxide, cerium oxide, or In—Ga—Zn oxide for forming a pn junction on the light-receiving surface side is illustrated. A layer is provided. These also function as a hole injection blocking layer for reducing dark current. Further, nickel oxide or antimony sulfide may be provided as an electron injection blocking layer on the electrode 566 side.

The photoelectric conversion layer 561 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, it may be a layer containing a compound of copper, indium, gallium, and selenium (CIGS). In CIS and CIGS, a photoelectric conversion element using avalanche multiplication can be formed as in the case of a single layer of selenium.

The light-transmitting conductive layer 562 can be formed using, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, or fluorine. Tin oxide containing, tin oxide containing antimony, graphene, graphene oxide, or the like can be used. The light-transmitting conductive layer 562 is not limited to a single layer and may be a stack of different films.

The photoelectric conversion element PD formed using the selenium-based material described above can be manufactured using a general semiconductor manufacturing process such as a film forming process, a lithography process, and an etching process. In addition, the selenium-based material has high resistance, and as illustrated in FIG. 10A, the photoelectric conversion layer 561 can be configured not to be separated between circuits. Therefore, it can be manufactured at a low cost with a high yield.

Alternatively, the photoelectric conversion element PD included in the layer 1100 may be a pn photodiode using a single crystal silicon substrate as shown in FIG. The photoelectric conversion element PD, ^{p +} region 620, p ^- can be configured to have a region 630, n-type region 640, ^{p +} region 650 in the single crystal silicon substrate.

In this case, it is preferable to use a method in which the layer 1200 is formed over the layer 1300 and then the separately formed layer 1100 is attached. In this case, the layer 1200 is provided with an insulating layer 81h and metal layers 402a and 403a. The layer 1100 is provided with an insulating layer 81i and metal layers 402b and 403b.

The metal layers 402a and 403a are provided to have a region embedded in the insulating layer 81h, and the metal layer 402a is electrically connected to one of the source and the drain of the transistor 41. In addition, the metal layer 403 a is electrically connected to the wiring 71. The metal layers 402b and 403b are provided so as to have a region embedded in the insulating layer 81i, and the metal layer 402b is electrically connected to the n-type region 640 of the photoelectric conversion element PD. In addition, the metal layer 403b is electrically connected to the p ⁺ region 620 through the p ⁺ region 650.

As shown in FIG. 12, the metal layer 402a and the metal layer 402b, and the metal layer 403a and the metal layer 403b are provided at positions where they are in direct contact with each other, and have connection portions 402 and 403.

Here, the metal layer 402a and the metal layer 402b are preferably composed of the same metal element as a main component. The metal layer 403a and the metal layer 403b are preferably composed of the same metal element as a main component. The insulating layer 81h and the insulating layer 81i are preferably composed of the same component.

For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used for the metal layers 402a, 402b, 403a, and 403b. From the viewpoint of ease of joining, Cu, Al, W, or Au is preferably used. For the insulating layer 81h and the insulating layer 81i, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used.

The same metal material as described above is used for each of the metal layers 402a, 402b, 403a, and 403b, and the same insulating material as described above is used for each of the insulating layer 81h and the insulating layer 81i. A bonding process can be performed at 1200. Through the bonding step, electrical connection between the metal layer 402a and the metal layer 402b and electrical connection between the metal layer 403a and the metal layer 403b can be obtained. Moreover, the connection which has the mechanical strength of the insulating layer 81h and the insulating layer 81i can be obtained.

For the bonding between the metal layers, a surface activated bonding method can be used in which an oxide film or an adsorption layer of impurities is removed by sputtering or the like, and cleaned and activated surfaces are brought into contact with each other for bonding. Alternatively, a diffusion bonding method in which the surfaces are bonded to each other using both temperature and pressure can be used. In both cases, bonding at the atomic level occurs, so that a bond with excellent electrical characteristics and mechanical strength can be obtained.

In addition, the insulating layers can be bonded to each other after high flatness is obtained by polishing or the like, and then the surfaces that have been subjected to hydrophilic treatment with oxygen plasma or the like are brought into contact with each other for temporary bonding, followed by dehydration by heat treatment to perform the main bonding. A bonding method or the like can be used. Since the bonding at the atomic level also occurs in the hydrophilic bonding method, bonding with excellent mechanical strength can be obtained.

In the case where the layer 1100 and the layer 1200 are bonded to each other, an insulating layer and a metal layer are mixed on each bonding surface. For example, a surface activated bonding method and a hydrophilic bonding method may be combined.

For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an antioxidant treatment, and then subjected to a hydrophilic treatment and bonded. Further, the surface of the metal layer may be made of a hardly oxidizable metal such as Au and subjected to a hydrophilic treatment. Note that a bonding method other than the method described above may be used.

In the bonding method, bonding is performed after a device included in each layer is completed, so that each device can be manufactured using an optimal process. Therefore, electrical characteristics and reliability of the transistor and the photoelectric conversion element can be improved.

In the imaging device of one embodiment of the present invention, a circuit different from the pixel circuit can be provided in the layer 1300. Examples of such circuits include drive circuits such as column drivers and row drivers, data conversion circuits such as A / D converters, noise reduction circuits such as CDS (Correlated Double Sampling) circuits, and control circuits for the entire imaging apparatus. .

A transistor 46 and a transistor 47 included in any of the above circuits are shown in FIGS. The transistors 46 and 47 can be formed in a region overlapping with the photoelectric conversion element PD. That is, the circuit is formed in a region overlapping with the pixel 20. Although FIG. 13 shows a configuration example of a CMOS inverter in which the transistor 46 is a p-ch type and the transistor 47 is an n-ch type, other circuit configurations may be used.

Further, as illustrated in FIG. 14, the transistor 47 may be an OS transistor provided in the layer 1200. In the structure shown in FIG. 14, the transistor 46 and the transistor 47 can be provided in a region where they overlap each other, and the circuit area can be reduced. In the case where the transistors 43 and 44 included in the pixel circuit are formed in a p-ch type, all the transistors provided in the single crystal silicon substrate 600 can be a p-ch type, and an n-ch type Si transistor is formed. The process to perform can be omitted.

13 and 14 show a stacked structure in which the transistors 46 and 47 are added to the pixel circuit shown in FIG. 10A, but the transistors 46 and 47 may be added to the pixel circuit shown in FIG. it can.

FIG. 15A is a block diagram illustrating a circuit configuration of an imaging device of one embodiment of the present invention. The imaging apparatus includes a pixel array 21 having pixels 20 arranged in a matrix, a circuit 22 (row driver) having a function of selecting a row of the pixel array 21, and a correlation double with respect to an output signal of the pixel 20. A circuit 23 (CDS circuit) for performing sampling processing, a circuit 24 (A / D conversion circuit or the like) having a function of converting analog data output from the circuit 23 into digital data, and data converted by the circuit 24 And a circuit 25 (column driver) having a function of selecting and reading out. Note that the circuit 23 may be omitted. The circuits 23 to 25 are collectively referred to as a circuit 30.

FIG. 15B is a circuit diagram of the circuit 23 connected to one column of the pixel array 21 and a block diagram of the circuit 24. The circuit 23 can include a transistor 51, a transistor 52, a capacitor C3, and a capacitor C4. Further, the circuit 24 can include a comparator circuit 27 and a counter circuit 29.

The transistor 53 functions as a current source circuit. A wiring 91 (OUT1) is electrically connected to one of a source and a drain of the transistor 53, and a power supply line is connected to the other of the source and the drain. The power supply line can be, for example, a low potential power supply line (VSS). In addition, a bias voltage is always applied to the gate of the transistor 53.

In the circuit 23, one of the source and the drain of the transistor 51 is electrically connected to one of the source and the drain of the transistor 52. One of the source and the drain of the transistor 51 is electrically connected to one electrode of the capacitor C3. The other of the source and the drain of the transistor 52 is electrically connected to one electrode of the capacitor C4. The other of the source and the drain of the transistor 52 is electrically connected to the wiring 92 (OUT2). The other of the source and the drain of the transistor 51 is electrically connected to, for example, a high potential power supply line (CDSVDD) to which a reference potential is supplied. The other electrode of the capacitive element C4 is electrically connected to, for example, a low potential power supply line (CDSVSS).

Note that the transistor 23 in which one of the source and the drain is electrically connected to the wiring 91 (OUT1) and the other of the source and the drain is electrically connected to the wiring 92 (OUT2) is turned on, so that the circuit 23 Can be bypassed. That is, an operation that does not require the circuit 23 can be performed in accordance with the operation mode of the imaging apparatus.

The imaging device of one embodiment of the present invention can have a stacked structure of the pixel array 21 and the circuit portion 35 including the circuit 30. For example, when FIG. 16A is a top view of the pixel array 21, and FIGS. 16B1 and 16B2 are top views of the circuit portion 35, the pixel array 21 shown in the perspective view of FIG. And the circuit portion 35 can be laminated. With such a structure, a transistor suitable for each element can be used, and the area of the imaging device can be reduced. Note that the circuit layout in FIGS. 16B1 and 16B2 is an example, and another layout may be used. Further, the configuration in which the control circuit 26 is provided in the circuit unit 35 is illustrated, but the control circuit 26 may be provided outside the circuit unit 35.

A circuit 22 and a circuit 30 illustrated in FIG. 16B1 are each divided into two parts and are arranged in the vicinity of the center instead of the end portions. The shift register circuits included in the circuit 22 and the circuit 30 may be operated independently in a region divided into two, or may be operated as a series of shift register circuits.

The circuit 22 and the circuit 30 illustrated in FIG. 16B2 are divided into two as in FIG. 16B1, but the circuits are arranged at an angle.

With the structure shown in FIGS. 16B1 and 16B2, the load on each wiring connected to the pixel 20 can be reduced as compared with the circuit 22 and the circuit 30 provided at the ends. Further, although the load of each wiring is not uniform, non-uniformity does not become a problem if the wiring capacitance and wiring resistance are small.

The circuit 22 and the circuit 30 are preferably manufactured using Si transistors in order to achieve both high-speed operation and a CMOS circuit configuration. For example, the circuit part 35 can be formed on a silicon substrate. The pixel array 21 is preferably manufactured using an OS transistor. Note that some of the transistors included in the circuit 22 and the circuit 30 may be formed using OS transistors.

FIG. 17A is a cross-sectional view of an example of a mode in which a color filter or the like is added to the imaging device. The cross-sectional view shows a part of a region having a pixel circuit for three pixels. An insulating layer 2500 is formed over the layer 1100 where the photoelectric conversion element PD is formed. The insulating layer 2500 can be formed using a silicon oxide film or the like that has high light-transmitting property with respect to visible light. Alternatively, a silicon nitride film may be stacked as the passivation film. Alternatively, a dielectric film such as hafnium oxide may be stacked as the antireflection film.

A light shielding layer 2510 may be formed over the insulating layer 2500. The light shielding layer 2510 has a function of preventing color mixture of light passing through the upper color filter. The light-shielding layer 2510 can have a structure in which a metal layer such as aluminum or tungsten, or a dielectric film having a function as an antireflection film is stacked with the metal layer.

An organic resin layer 2520 can be provided as a planarization film over the insulating layer 2500 and the light-blocking layer 2510. In addition, a color filter 2530 (a color filter 2530a, a color filter 2530b, and a color filter 2530c) is formed for each pixel. For example, colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) are assigned to the color filters 2530a, 2530b, and 2530c. Thus, a color image can be obtained.

An insulating layer 2560 having a light-transmitting property and the like can be provided over the color filter 2530.

In addition, as illustrated in FIG. 17B, an optical conversion layer 2550 may be used instead of the color filter 2530. With such a configuration, an imaging device capable of obtaining images in various wavelength regions can be obtained.

For example, when a filter that blocks light having a wavelength shorter than or equal to that of visible light is used for the optical conversion layer 2550, an infrared imaging device can be obtained. If a filter that blocks light having a wavelength of near infrared or shorter is used for the optical conversion layer 2550, a far infrared imaging device can be obtained. When a filter that blocks light having a wavelength longer than or equal to that of visible light is used for the optical conversion layer 2550, an ultraviolet imaging device can be obtained.

In addition, when a scintillator is used for the optical conversion layer 2550, an imaging device that can be used for an X-ray imaging device or the like to obtain an image that visualizes the intensity of radiation can be obtained. When radiation such as X-rays transmitted through the subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon. And the image data is acquired by detecting the said light with the photoelectric conversion element PD. Further, the imaging device having the configuration may be used for a radiation detector or the like.

A scintillator contains a substance that emits visible light or ultraviolet light by absorbing energy when irradiated with radiation such as X-rays or gamma rays. For example, Gd ₂ O ₂ S: Tb, Gd ₂ O ₂ S: Pr, Gd ₂ O ₂ S: Eu, BaFCl: Eu, NaI, CsI, CaF ₂ , BaF ₂ , CeF ₃ , LiF, LiI, ZnO And those dispersed in ceramics can be used.

In the photoelectric conversion element PD using a selenium-based material, radiation such as X-rays can be directly converted into electric charge, so that a scintillator can be omitted.

In addition, as illustrated in FIG. 17C, a microlens array 2540 may be provided over the color filter 2530a, the color filter 2530b, and the color filter 2530c. Light passing through the individual lenses of the microlens array 2540 passes through the color filter directly below and is irradiated onto the photoelectric conversion element PD. Alternatively, a microlens array 2540 may be provided over the optical conversion layer 2550 illustrated in FIG.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of a display panel that can be used for the display device 200 described in Embodiment 1 will be described. For example, a display panel described below can be used for each display area of the display device 200.

FIG. 18 is a top view illustrating an example of the display panel. A display panel 700 illustrated in FIG. 18 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a pixel portion 702, The sealant 712 is disposed so as to surround the source driver circuit portion 704 and the gate driver circuit portion 706, and the second substrate 705 is provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Note that although not illustrated in FIG. 18, a display element is provided between the first substrate 701 and the second substrate 705.

In addition, the display panel 700 includes a pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 that are electrically connected to regions different from the region surrounded by the sealant 712 over the first substrate 701. An FPC terminal portion 708 (FPC: Flexible printed circuit) connected to is provided. In addition, an FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. A signal line 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Various signals and the like supplied from the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.

In addition, a plurality of gate driver circuit portions 706 may be provided in the display panel 700. In addition, although an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown as the display panel 700, the present invention is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. . Note that a method for connecting a separately formed driver circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display panel 700 each include a plurality of transistors, and a transistor that is a semiconductor device of one embodiment of the present invention can be used. .

In addition, the display panel 700 can include various elements. Examples of the element include, for example, an electroluminescence (EL) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, and the like), a light-emitting transistor element (a transistor that emits light in response to current), an electron Emission element, liquid crystal element, electronic ink element, electrophoretic element, electrowetting element, plasma display panel (PDP), MEMS (micro electro mechanical system) display (for example, grating light valve (GLV), digital micromirror Devices (DMD), digital micro shutter (DMS) elements, interferometric modulation (IMOD) elements, etc.), piezoelectric ceramic displays, and the like.

An example of a display panel using an EL element is an EL display. As an example of a display panel using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display panel using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display panel using an electronic ink element or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

Note that as a display method in the display panel 700, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in a pen tile arrangement, one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display panel for color display, and can be applied to a display panel for monochrome display.

In addition, a colored layer (also referred to as a color filter) may be used to display a full color display panel using white light emission (W) in a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, or the like). Good. For example, red (R), green (G), blue (B), yellow (Y), and the like can be used in appropriate combination for the colored layer. By using the colored layer, the color reproducibility can be increased as compared with the case where the colored layer is not used. At this time, white light in a region having no colored layer may be directly used for display by arranging a region having a colored layer and a region having no colored layer. By disposing a region that does not have a colored layer in part, a decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30%. However, when a full color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from elements having respective emission colors. By using a self-luminous element, power consumption may be further reduced as compared with the case where a colored layer is used.

In addition, as a colorization method, in addition to a method (color filter method) in which part of the light emission from the white light emission described above is converted into red, green, and blue through a color filter, red, green, and blue light emission is performed. A method of using each (three-color method) or a method of converting a part of light emission from blue light emission into red or green (color conversion method, quantum dot method) may be applied.

In this embodiment, a structure in which a liquid crystal element or an EL element is used as a display element is described with reference to FIGS. Note that FIG. 19 is a cross-sectional view taken along the alternate long and short dash line QR shown in FIG. 18 and uses a liquid crystal element as a display element. FIG. 20 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 18 and has a configuration using an EL element as a display element.

First, common parts shown in FIGS. 19 and 20 will be described first, and then different parts will be described below.

<Explanation on common parts of display panel>
A display panel 700 shown in FIGS. 19 and 20 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 includes a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit portion 704 includes a transistor 752.

The structures of the transistor 750 and the transistor 752 are examples, and other transistors described in other embodiments may be used.

A transistor used for the display panel described in this embodiment is an OS transistor including an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies. The transistor can have low off-state current. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the rewrite operation can be reduced, there is an effect of suppressing power consumption.

In addition, the transistor used in this embodiment can have a relatively high field-effect mobility, and thus can be driven at high speed. For example, by using such a transistor capable of high speed driving for the display panel 700, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since a separate driving circuit can be used without using a semiconductor device formed of a silicon wafer or the like, the number of parts of the semiconductor device can be reduced. In the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

The capacitor 790 includes an oxide semiconductor film included in the transistor 750, a lower electrode formed through a step of processing the same oxide semiconductor film, a conductive film functioning as a source electrode and a drain electrode included in the transistor 750, And an upper electrode formed through a step of processing the same conductive film. Further, an insulating film formed through a step of forming the same insulating film as the third insulating film and the fourth insulating film included in the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric is sandwiched between a pair of electrodes.

19 and 20, a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.

As the planarization insulating film 770, an organic material having heat resistance such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin can be used. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed using these materials. Further, the planarization insulating film 770 may be omitted.

19 and 20 exemplify a structure in which the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 are top-gate transistors; however, the present invention is not limited to this. For example, bottom-gate transistors may be used for both the pixel portion 702 and the source driver circuit portion 704. Alternatively, a top-gate transistor and a bottom-gate transistor may be used in combination. Note that the source driver circuit portion 704 may be replaced with a gate driver circuit portion.

The signal line 710 is formed through the same process as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. Note that the signal line 710 is a conductive film formed through a different process from the source and drain electrodes of the transistors 750 and 752, for example, an oxide semiconductor formed through the same process as an oxide semiconductor film functioning as a gate electrode. A membrane may be used. For example, when a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small and display on a large screen is possible.

The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed through the same process as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.

Further, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Further, as the first substrate 701 and the second substrate 705, flexible substrates may be used. Examples of the flexible substrate include a plastic substrate.

A structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.

Further, on the second substrate 705 side, a light shielding film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light shielding film 738 and the colored film 736 are provided.

<Configuration Example of Display Panel Using Liquid Crystal Element>
A display panel 700 illustrated in FIG. 19 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. A display panel 700 illustrated in FIG. 19 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 depending on voltages applied to the conductive films 772 and 774.

The conductive film 772 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. The conductive film 772 functions as a reflective electrode. A display panel 700 shown in FIG. 19 is a so-called reflective color liquid crystal display panel that uses external light to reflect light through a conductive film 772 and display it through a colored film 736.

As the conductive film 772, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflectivity in visible light, for example, a material containing aluminum or silver is preferably used. In this embodiment, a conductive film that reflects visible light is used as the conductive film 772.

Further, in the display panel 700 illustrated in FIG. 19, unevenness is provided in part of the planarization insulating film 770 of the pixel portion 702. The unevenness can be formed, for example, by forming the planarization insulating film 770 with a resin film and providing the unevenness on the surface of the resin film. In addition, the conductive film 772 functioning as a reflective electrode is formed along the unevenness. Accordingly, when external light is incident on the conductive film 772, light can be diffusely reflected on the surface of the conductive film 772, and visibility can be improved.

Note that the display panel 700 illustrated in FIG. 19 is exemplified as a reflective color liquid crystal display panel, but is not limited thereto. For example, the conductive film 772 may be a transmissive color liquid crystal display panel by using a light-transmitting conductive film in visible light. In the case of a transmissive color liquid crystal display panel, the unevenness provided in the planarization insulating film 770 may not be provided.

Note that although not illustrated in FIG. 19, an alignment film may be provided on each of the conductive films 772 and 774 in contact with the liquid crystal layer 776. Although not shown in FIG. 19, an optical member (optical substrate) such as a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

In the case of employing a horizontal electric field method, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with several percent by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so that alignment treatment is unnecessary. In addition, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display panel during the manufacturing process can be reduced. . A liquid crystal material exhibiting a blue phase has a small viewing angle dependency.

When a liquid crystal element is used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned MicroB cell) mode, A Compensated Birefringence (FLC) mode, a FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti-Ferroelectric Liquid Crystal) mode, and the like can be used.

Alternatively, a normally black liquid crystal display panel such as a transmissive liquid crystal display panel employing a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, and the like can be used.

<Configuration Example of Display Panel Using Light-Emitting Element>
A display panel 700 illustrated in FIG. 20 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. The display panel 700 illustrated in FIG. 20 can display an image when the EL layer 786 included in the light-emitting element 782 emits light. Note that the EL layer 786 includes an organic compound or an inorganic compound such as a quantum dot.

Examples of a material that can be used for the organic compound include a fluorescent material and a phosphorescent material. Examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy type quantum dot materials, core / shell type quantum dot materials, and core type quantum dot materials. Alternatively, a material including an element group of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used. Alternatively, cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As ), A quantum dot material having an element such as aluminum (Al) may be used.

The conductive film 784 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. As the conductive film 784, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflectivity in visible light, for example, a material containing aluminum or silver is preferably used.

In the display panel 700 illustrated in FIG. 20, an insulating film 730 is provided over the planarization insulating film 770 and the conductive film 784. The insulating film 730 covers part of the conductive film 784. Note that the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786. In the present embodiment, the top emission structure is illustrated, but the present invention is not limited to this. For example, a bottom emission structure in which light is emitted to the conductive film 784 side or a dual emission structure in which light is emitted to both the conductive film 784 and the conductive film 788 can be used.

In addition, a coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at the position overlapping with the insulating film 730 in the lead wiring portion 711 and the source driver circuit portion 704. Further, the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in the display panel 700 illustrated in FIG. 20, the structure in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by separate coating, the coloring film 736 may not be provided.

FIG. 21A illustrates an example of a block diagram of a display panel that can be used in one embodiment of the present invention. The display panel includes a region having a pixel of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion (hereinafter referred to as a drive circuit portion 504) that is disposed outside the pixel portion 502 and includes a circuit for driving the pixel. ), A circuit having a function of protecting an element (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may be omitted.

A part or all of the driver circuit portion 504 is preferably formed over the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced. When part or all of the driver circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed by COG or TCP (tape carrier package). Can be implemented.

The pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driver circuit portion 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (a data signal). Hereinafter, it has a drive circuit such as a source driver 504b).

The gate driver 504a includes a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can supply another signal.

The source driver 504b includes a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. The source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can supply another signal.

The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches. Further, the source driver 504b may be configured using a shift register or the like.

Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives the data signal through one of the plurality of data lines DL to which the data signal is applied. Entered. In each of the plurality of pixel circuits 501, writing and holding of data signals are controlled by the gate driver 504a. For example, the pixel circuit 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a through the scanning line GL_m (m is a natural number equal to or less than X), and the data line DL_n (n Is a natural number less than or equal to Y), a data signal is input from the source driver 504b.

The protection circuit 506 illustrated in FIG. 21A is connected to, for example, the scanning line GL that is a wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to a data line DL that is a wiring between the source driver 504 b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507. Note that the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.

The protection circuit 506 is a circuit that brings a wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.

As shown in FIG. 21A, by providing a protection circuit 506 in each of the pixel portion 502 and the driver circuit portion 504, resistance of the display device to an overcurrent generated by ESD (Electro Static Discharge) is increased. be able to. However, the configuration of the protection circuit 506 is not limited thereto, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b may be employed. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

FIG. 21A illustrates an example in which the driver circuit portion 504 is formed using the gate driver 504a and the source driver 504b; however, the present invention is not limited to this structure. For example, only the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

In addition, the plurality of pixel circuits 501 illustrated in FIG. 21A can have a structure illustrated in FIG.

A pixel circuit 501 illustrated in FIG. 21B includes a liquid crystal element 530, a transistor 510, and a capacitor 520. Here, the transistor 510 is preferably an OS transistor.

One potential of the pair of electrodes of the liquid crystal element 530 is appropriately set according to the specification of the pixel circuit 501. The alignment state of the liquid crystal element 530 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 530 included in each of the plurality of pixel circuits 501. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 530 of the pixel circuit 501 in each row.

In the pixel circuit 501 in the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 510 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 530. The In addition, the gate electrode of the transistor 510 is electrically connected to the scan line GL_m. The transistor 510 has a function of controlling data writing of the data signal by being turned on or off.

One of the pair of electrodes of the capacitor 520 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 530. The Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitor 520 functions as a storage capacitor that stores written data.

For example, in the display device including the pixel circuit 501 in FIG. 21B, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write data.

The pixel circuit 501 in which data is written is brought into a holding state when the transistor 550 is turned off. By sequentially performing this for each row, an image can be displayed.

In addition, the plurality of pixel circuits 501 illustrated in FIG. 21A can have a structure illustrated in FIG.

A pixel circuit 501 illustrated in FIG. 21C includes transistors 512 and 514, a capacitor 522, and a light-emitting element 532. One or both of the transistor 512 and the transistor 514 are preferably OS transistors.

One of a source electrode and a drain electrode of the transistor 512 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a data line DL_n). Further, the gate electrode of the transistor 512 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).

The transistor 512 has a function of controlling data writing of the data signal by being turned on or off.

One of the pair of electrodes of the capacitor 522 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 512. Is done.

The capacitor 522 functions as a storage capacitor for storing written data.

One of a source electrode and a drain electrode of the transistor 514 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 514 is electrically connected to the other of the source electrode and the drain electrode of the transistor 512.

One of an anode and a cathode of the light-emitting element 532 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 514.

As the light-emitting element 532, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 532 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

Note that one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.

In the display panel including the pixel circuit 501 in FIG. 21C, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write.

The pixel circuit 501 in which data is written is brought into a holding state when the transistor 512 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.

22A and 22B illustrate an example of the display device 200 including the plurality of display panels described in Embodiment 1. 22A is a perspective view of a form in which a plurality of display panels are wound, and FIG. 22B is a perspective view of a state in which the plurality of display panels are developed.

A display device 200 illustrated in FIGS. 22A and 22B includes a plurality of display panels 9501, a shaft portion 9511, and a bearing portion 9512. The plurality of display panels 9501 each include a display region 9502 and a region 9503 having a light-transmitting property.

In addition, the plurality of display panels 9501 have flexibility. Further, two adjacent display panels 9501 are provided so that a part of them overlap each other. For example, a light-transmitting region 9503 of two adjacent display panels 9501 can be overlapped. By using a plurality of display panels 9501, a large-screen display device can be obtained. In addition, since the display panel 9501 can be taken up depending on the use state, a display device with excellent versatility can be obtained.

22A and 22B illustrate a state in which the display area 9502 is separated by the adjacent display panel 9501, the display areas 9502 of the adjacent display panels 9501 can be overlapped without a gap. It is preferable that the display area 9502 is apparently continuous.

Since the display panel 9501 has flexibility, the display element included in the display region 9502 is preferably an organic EL element.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, operation modes that can be performed with the display device of one embodiment of the present invention will be described with reference to FIGS.

Hereinafter, a normal operation mode (Normal mode) that operates at a normal frame frequency (typically 60 Hz to 240 Hz or less) and an idling stop (IDS) drive mode that operates at a low frame frequency will be described as examples. To do. The idling stop drive is used for the operation of extremely reducing the frequency of image rewriting described in the first embodiment.

The IDS driving mode refers to a driving method in which the rewriting of image data is stopped after the image data writing process is executed. Once the image data is written and then the interval until the next image data is written is extended, the power consumption required for writing the image data during that time can be reduced. The IDS drive mode can be set to a frame frequency of about 1/100 to 1/10 of the normal operation mode, for example. A still image has the same video signal between consecutive frames. Therefore, the IDS drive mode is particularly effective when displaying a still image. By displaying an image using IDS driving, power consumption is reduced, flickering of the screen is suppressed, and eye strain can be reduced.

23A to 23C are timing charts illustrating a pixel circuit, and a normal driving mode and an IDS driving mode. Note that FIG. 23A illustrates a first display element 591 (here, a liquid crystal element) and a pixel circuit 596 which is electrically connected to the first display element 591. In the pixel circuit 596 illustrated in FIG. 23A, the signal line SL, the gate line GL, the transistor M1 connected to the signal line SL and the gate line GL, and the capacitor Cs _LC connected to the transistor M1 Is shown.

Transistor M1 may become a leak path data _{D 1.} Therefore, the off-state current of the transistor M1 is preferably as small as possible. As the transistor M1, an OS transistor is preferably used. The OS transistor has a feature that leakage current (off-state current) in a non-conduction state is extremely lower than that of a transistor using polycrystalline silicon or the like. It can be maintained for a long time the charge on the transistor M1 is supplied to the capacitor Cs _LC by using an OS transistor.

Incidentally, in the circuit diagram shown in FIG. 23 (A), the liquid crystal element LC is the leak path of the data _{D 1.} Therefore, in order to appropriately perform IDS driving, it is preferable that the resistivity of the liquid crystal element LC is 1.0 × 10 ¹⁴ Ω · cm or more.

Note that an In—Ga—Zn oxide, an In—Zn oxide, or the like can be preferably used for the channel region of the OS transistor, for example. As the above In—Ga—Zn oxide, a composition in the vicinity of In: Ga: Zn = 4: 2: 3 [atomic ratio] can be typically used.

FIG. 23B is a timing chart showing waveforms of signals supplied to the signal line SL and the gate line GL in the normal drive mode. In the normal drive mode, it operates at a normal frame frequency (for example, 60 Hz). When one frame period is represented by periods T ₁ to T ₃ , a scanning signal is applied to the gate line GL in each frame period, and an operation of writing data D ₁ from the signal line SL to the capacitor Cs _LC is performed. This operation is the same even when writing the same data D ₁ in the period T ₁ to T ₃ or writing different data.

On the other hand, FIG. 23C is a timing chart showing waveforms of signals supplied to the signal line SL and the gate line GL in the IDS drive mode, respectively. In the IDS drive, it operates at a low frame frequency (for example, 1 Hz). Represents one frame period in the period T _1, representing the period T _W a write period of data _therein, the data retention period in the period T _RET. IDS drive mode gives a scanning signal to the gate line GL in a period _{T W,} write data _{D 1} of the signal line SL, and a gate line GL is fixed to the low level of the voltage in the period _{T RET,} nonconductive transistor M1 It performs an operation of holding temporarily the data D ₁ written as. In addition, what is necessary is just to set it as 0.1 Hz or more and less than 60 Hz as a low-speed frame frequency, for example.

Note that although examples using the liquid crystal element LC are shown in FIGS. 23A to 23C, idling stop driving can be similarly performed using a light emitting element such as an organic EL element.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 6)
In this embodiment, an example of a package containing an image sensor chip and a camera module will be described. The structure of the imaging device of one embodiment of the present invention can be used for the image sensor chip.

FIG. 24A is an external perspective view of the upper surface side of the package containing the image sensor chip. The package includes a package substrate 810 for fixing the image sensor chip 850, a cover glass 820, and an adhesive 830 for bonding the two.

FIG. 24B is an external perspective view of the lower surface side of the package. The bottom surface of the package has a BGA (Ball Grid Array) configuration with solder balls as bumps 840. In addition, not only BGA but LGA (Land grid array), PGA (Pin Grid Array), etc. may be sufficient.

FIG. 24C is a perspective view of the package shown with a part of the cover glass 820 and the adhesive 830 omitted, and FIG. 24D is a cross-sectional view of the package. An electrode pad 860 is formed on the package substrate 810, and the electrode pad 860 and the bump 840 are electrically connected through the through hole 880 and the land 885. The electrode pad 860 is electrically connected to an electrode included in the image sensor chip 850 by a wire 870.

FIG. 25A is an external perspective view of the upper surface side of the camera module in which the image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 811 for fixing the image sensor chip 851, a lens cover 821, a lens 835, and the like. Further, an IC chip 890 having functions such as a drive circuit and a signal conversion circuit of the imaging device is also provided between the package substrate 811 and the image sensor chip 851, and has a configuration as a SiP (System in package). Yes.

FIG. 25B is an external perspective view of the lower surface side of the camera module. The package substrate 811 has a QFN (Quad Flat No-Lead Package) configuration in which mounting lands 841 are provided on the lower surface and the four side surfaces. Note that this configuration is an example, and a QFP (Quad Flat Package), the above-described BGA, or the like may be used.

FIG. 25C is a perspective view of the module shown with a part of the lens cover 821 and the lens 835 omitted, and FIG. 25D is a cross-sectional view of the camera module. A part of the land 841 is used as an electrode pad 861, and the electrode pad 861 is electrically connected to electrodes included in the image sensor chip 851 and the IC chip 890 by wires 871.

By mounting the image sensor chip in a package having the above-described form, mounting on a printed board or the like is facilitated, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 7)
Games including an imaging device, a display device, and an electronic device that can use both according to one embodiment of the present invention include a display device, a personal computer, an image storage device or an image playback device including a recording medium, a mobile phone, and a portable type Cameras, portable data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, goggle type displays (head mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, Examples include printers, printer multifunction devices, automatic teller machines (ATMs), and vending machines. Specific examples of these electronic devices are shown in FIGS.

FIG. 26A illustrates a monitoring camera, which includes a housing 951, a lens 952, a support portion 953, and the like. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the monitoring camera. The surveillance camera is an idiomatic name and does not limit the application. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

FIG. 26B illustrates a video camera, which includes a first housing 971, a second housing 972, a display portion 973, operation keys 974, a lens 975, a connection portion 976, and the like. The operation key 974 and the lens 975 are provided in the first housing 971, and the display portion 973 is provided in the second housing 972. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the video camera.

FIG. 26C illustrates a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the digital camera.

FIG. 26D illustrates a wristwatch type information terminal, which includes a housing 931, a display portion 932, a wristband 933, operation buttons 935, a crown 936, a camera 939, and the like. The display unit 932 may be a touch panel. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the information terminal.

FIG. 26E illustrates an example of a specific structure of the image display system of one embodiment of the present invention illustrated in FIG. 1A, and the display device 200 including a plurality of display regions described in Embodiment 1 is implemented. 1 to 3, the camera 982 including the imaging device including the pixels, the transmitter 983 connected to the antenna 985, and the receiver 984 connected to the antenna 986 are included. The camera 982 is connected to the transmitter 983 with a cable, and the image data is transmitted to the receiver 984 wirelessly. The receiver 984 is connected to the display device 200 and can display the received image data on the display device 200.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

20 pixel 21 pixel array 21a pixel array 21p pixel array 22 circuit 23 circuit 24 circuit 25 circuit 26 control circuit 27 comparator circuit 29 counter circuit 30 circuit 32 pixel array 35 circuit unit 35a circuit unit 35p circuit unit 36 circuit unit 41 transistor 42 transistor 43 Transistor 44 Transistor 45 Transistor 46 Transistor 47 Transistor 51 Transistor 52 Transistor 53 Transistor 54 Transistor 61 Wiring 62 Wiring 63 Wiring 65 Wiring 71 Wiring 72 Wiring 73 Wiring 74 Wiring 75 Wiring 79 Wiring 80a Insulating layer 80b Insulating layer 81a Insulating layer 81h Insulating layer 81i Insulating layer 82 Conductor 83 Insulating layer 84 Conductive layer 85 Conductive layer 91 Wiring 92 Wiring 100 Imaging device 101 Sensor unit 102 Encoding device 105 Pixel device 112 pixel block 112 pixel block 113 pixel block 114 pixel block 121 pixel block 122 pixel block 123 pixel block 124 pixel block 131 pixel block 132 pixel block 133 pixel block 134 pixel block 141 pixel block 142 pixel block 143 pixel block 144 pixel Block 150 Repeater 200 Display device 201 Display unit 202 Playback device 203 Decoding device 211 Display region 212 Display region 213 Display region 214 Display region 221 Display region 222 Display region 223 Display region 224 Display region 231 Display region 232 Display region 233 Display region 234 Display area 241 Display area 242 Display area 243 Display area 244 Display area 301 Signal 302 Signal 303 Block division unit 304 Frequency division unit 305 frequency conversion unit 306 quantization unit 307 encoding unit 308 inverse quantization unit 309 inverse frequency conversion unit 310 intra-screen prediction unit 311 compensation prediction unit 312 signal 313 control unit 314 data 321 decoding unit 322 inverse quantization Unit 323 reconstruction unit 324 intra prediction unit 325 compensation prediction unit 331 block reconstruction unit 332 block reconstruction unit 351 transmission line 352 electromagnetic wave 402 connection unit 402a metal layer 402b metal layer 403 connection unit 403a metal layer 403b metal layer 501 pixel circuit 502 pixel portion 504 driving circuit portion 504a gate driver 504b source driver 506 protection circuit 507 terminal portion 510 transistor 512 transistor 514 transistor 520 capacitor element 522 capacitor element 530 liquid crystal element 532 light emitting element 550 transistor 554 transistor Gista 561 Photoelectric conversion layer 562 Translucent conductive layer 566 Electrode 567 Partition 571 Wiring 572 Light emitting element 591 Display element 596 Pixel circuit 600 Single crystal silicon substrate 620 p ⁺ region 630 p ⁻ region 640 n-type region 650 p ⁺ region 660 Active layer 700 Display panel 701 Substrate 702 Pixel portion 704 Source driver circuit portion 705 Substrate 706 Gate driver circuit portion 708 FPC terminal portion 710 Signal line 711 Wiring portion 712 Seal material 716 FPC
730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light shielding film 750 Transistor 752 Transistor 760 Connection electrode 770 Flattening insulating film 772 Conductive film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 780 Anisotropic conductive film 782 Light emitting element 784 Conductive film 786 EL layer 788 Conductive element 790 Capacitor element 810 Package substrate 811 Package substrate 820 Cover glass 821 Lens cover 830 Adhesive 835 Lens 840 Bump 841 Land 850 Image sensor chip 851 Image sensor chip 860 Electrode pad 861 Electrode pad 870 Wire 871 Wire 880 Through hole 885 Land 890 IC chip 931 Case 932 Display unit 933 Wristband 935 Button 936 Crown 939 Camera 951 Case 9 2 Lens 953 Supporting part 961 Case 962 Shutter button 963 Microphone 965 Lens 967 Light emitting part 971 Case 972 Case 973 Display part 974 Operation key 975 Lens 976 Connection part 982 Camera 983 Transmitter 984 Receiver 985 Antenna 986 Antenna 1100 Layer 1200 Layer 1300 Layer 2500 Insulating layer 2510 Light shielding layer 2520 Organic resin layer 2530 Color filter 2530a Color filter 2530b Color filter 2530c Color filter 2540 Micro lens array 2550 Optical conversion layer 2560 Insulating layer 9501 Display panel 9502 Display area 9503 Area 9511 Shaft 9512 Bearing section

Claims (8)

An image display system having an imaging device and a display device,
The imaging device includes a first pixel block, a second pixel block, an encoding device, and a storage device,
Each of the first pixel block and the second pixel block has an imaging pixel,
The encoding apparatus includes a first block dividing unit and a second block dividing unit,
The first block dividing unit has a function of dividing the first image data output from the first pixel block;
The second block dividing unit has a function of dividing the second image data output from the second pixel block;
The encoding device has a function of compressing the first and second image data output from the first block dividing unit and the second block dividing unit to create third image data,
The storage device has a function of recording the third image data output from the encoding device,
The display device includes a first display area, a second display area, a decoding device, and a playback device,
Each of the first display area and the second display area has a display pixel,
The decoding device has a first block reconstruction unit and a second block reconstruction unit,
The playback device has a function of reading the third image data;
The decoding device has a function of decompressing the third image data and outputting data to each of the first block reconstruction unit and the second block reconstruction unit,
The first block reconstruction unit has a function of reconstructing the first image data from the input data and outputting the first image data to the first display area,
The second block reconstruction unit is an image display system having a function of reconstructing the second image data from the input data and outputting the second image data to the second display area. In claim 1,
The imaging apparatus has a first mode for acquiring image data, and a second mode for detecting whether or not a subject has changed,
In the first and second pixel blocks,
A function of switching to the second mode after operating in the first mode;
A function of switching the first and / or the second pixel block that has detected a change in a subject to the first mode;
And a function of acquiring new image data with the first and / or the second pixel block switched to the first mode. In claim 1 or 2,
The display device
In the first display area and the second display area,
A function of storing the image data in each of the display pixels;
A function of displaying the acquired image data as an image on each of the display pixels;
A function of rewriting only one of the images displayed in the first and second display areas;
An image display system comprising: In any one of Claims 1 thru | or 3,
The first and second pixel blocks include the imaging pixels arranged in a matrix, a drive circuit, and a data conversion circuit,
The imaging pixel includes a photoelectric conversion element and a first transistor using an oxide semiconductor as a semiconductor,
The drive circuit includes a second transistor having silicon as an active layer or an active region,
The data conversion circuit includes a third transistor having silicon as an active layer or an active region,
The photoelectric conversion element has a region overlapping with the first transistor,
The image display system, wherein the photoelectric conversion element has a region overlapping with the second transistor or the third transistor. In any one of Claims 1 thru | or 4,
The first and second display areas include the display pixels arranged in a matrix and a drive circuit,
The display pixel includes a fourth transistor having an oxide semiconductor as a semiconductor layer. In any one of Claims 1 thru | or 5,
The image display system, wherein the display area has flexibility. In any one of Claims 4 thru | or 6,
The oxide semiconductor includes indium, zinc, and M (M is aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). . An image display system according to any one of claims 1 to 7,
A transmitter,
A receiver,
An electronic device comprising:

Images