JP2021100025A - Imaging device and driving method for imaging device - Google Patents

Abstract

To provide an imaging device with less noise.SOLUTION: An imaging device includes a photoelectric conversion device, first to fourth transistors, a capacitor, a first wire, and a second wire. One terminal of the photoelectric conversion device is electrically connected to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one electrode of the capacitor, and a gate of the third transistor. One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor. A back gate of the second transistor is electrically connected to the first wire. A back gate of the third transistor is electrically connected to the second wire to which a potential larger than the potential applied to the first wire is applied.SELECTED DRAWING: Figure 1

Description

One aspect of the present invention relates to an imaging device. Further, one aspect of the present invention relates to a method of driving an imaging device.

One aspect of the present invention is not limited to the above technical fields. The technical field of one aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter. Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, lighting devices, power storage devices, storage devices, imaging devices, and the like. The driving method or the manufacturing method thereof can be given as an example.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. Further, the storage device, the display device, the image pickup device, and the electronic device may have a semiconductor device.

Attention is being paid to a technique for constructing a transistor using an oxide semiconductor thin film formed on a substrate. For example, Patent Document 1 discloses an image pickup apparatus having an oxide semiconductor and using a transistor having an extremely small off-current in a pixel circuit.

Japanese Unexamined Patent Publication No. 2011-119711

One aspect of the present invention is to provide an image pickup apparatus with less noise. Further, one aspect of the present invention is to provide a highly productive imaging device. Further, one aspect of the present invention is to provide an image pickup device having low power consumption. Another object of one aspect of the present invention is to provide an image pickup apparatus capable of producing a high yield. Further, one aspect of the present invention is to provide a small-sized image pickup apparatus. Another object of one aspect of the present invention is to provide an image pickup apparatus capable of high-speed operation. Further, one aspect of the present invention is to provide a highly reliable imaging device. Another object of one aspect of the present invention is to provide a new imaging device. Another object of one aspect of the present invention is to provide a method for driving the image pickup apparatus. Another object of one aspect of the present invention is to provide a new semiconductor device or the like.

The description of these issues does not prevent the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. It should be noted that the problems other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the problems other than these from the description of the description, drawings, claims, etc. Is.

One aspect of the present invention includes a photoelectric conversion device, a first transistor to a fourth transistor, a capacitor, a first wiring, and a second wiring, and the second transistor is a first transistor. The third transistor has a third gate, a fourth gate, and a second semiconductor layer. Each of the first semiconductor layer and the second semiconductor layer is an oxide layer having indium, an element M (M is one or more of gallium, aluminum, yttrium, and tin), and zinc. One terminal of the photoelectric conversion device is electrically connected to one of the source or drain of the first transistor, and the other of the source or drain of the first transistor is the source or drain of the second transistor. On the other hand, it is electrically connected to one electrode of the capacitor and the third gate of the third transistor, and one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor. The second gate is electrically connected to the first wiring that is given the first potential, and the fourth gate is given a second potential that is greater than the first potential. It is an image pickup device that is electrically connected to the wiring of.

In the image pickup apparatus, the second transistor has an on / off ratio of ¹⁰⁶ or more in a state where the first potential is applied to the second gate, and the third transistor has a second to the fourth gate. It is preferable that ^{the on / off ratio is 106} or more in the state where the potential of is applied.

In the above image pickup apparatus, the second transistor applies a first potential to the second gate, sets the drain potential to 0.3 V, and sets the source potential to 0 V, and in a state where the source potential is 0 V, the potential of -3 V is applied to the first gate. to the value of the drain current at the time of applying a is the ratio of the values of the drain current when a potential is applied to + 3V to the first gate 10 ⁶ or more, the third transistor, the second to fourth gate With the potential of -3V applied to the third gate and the drain potential set to 0.3V and the source potential set to 0V, + 3V to the third gate with respect to the value of the drain current when the potential of -3V is applied to the third gate. the ratio of the value of the drain current when a potential is applied is 10 ⁶ or more, it is preferable.

Further, in the image pickup apparatus, it is preferable that the second transistor and the third transistor are formed on the same insulating layer.

Further, in the above image pickup apparatus, each of the first transistor and the fourth transistor has a metal oxide in the channel forming region, and the metal oxide is indium and the element M (M is gallium, aluminum, It is preferable to have any one or more of indium and tin) and zinc.

Another aspect of the present invention comprises a photoelectric conversion device, a first transistor to a fourth transistor, a capacitor, and a second wiring, wherein the third transistor has a third gate. It has a fourth gate and a second semiconductor layer, the second semiconductor layer containing indium and the element M (M is any one or more of gallium, aluminum, ittrium, and tin). An oxide layer with zinc, one terminal of the photoelectric conversion device is electrically connected to one of the source or drain of the first transistor, and the other of the source or drain of the first transistor is the first. One of the source or drain of the second transistor, one electrode of the capacitor, and the third gate of the third transistor are electrically connected, and one of the source or drain of the third transistor is of the fourth transistor. The fourth gate is an image pickup device that is electrically connected to either the source or the drain and is electrically connected to the second wiring that is given a potential of 0 V or more and 3 V or less.

Another aspect of the present invention comprises a photoelectric conversion device, a first transistor to a fourth transistor, a capacitor, a second wiring, and a third wiring, and the third transistor comprises. It has a third gate, a fourth gate, and a second semiconductor layer, and the second semiconductor layer is indium and element M (M is any of gallium, aluminum, yttrium, and tin). An oxide layer comprising one or more) and zinc, one terminal of the photoelectric conversion device being electrically connected to one of the source or drain of the first transistor and the source or source of the first transistor. The other of the drains is electrically connected to one of the source or drain of the second transistor, one electrode of the capacitor, and the third gate of the third transistor, and one of the source or drain of the third transistor is , One of the source or drain of the fourth transistor is electrically connected, the other terminal of the photoelectric conversion device is electrically connected to the third wiring to which the third potential is given, and the fourth gate is , An image pickup device that is electrically connected to a second wire that is given a second potential that is greater than the third potential.

In the above image pickup apparatus, it is preferable that ^{the third transistor has an on / off ratio of 106} or more in a state where the second potential is applied to the fourth gate.

In the above image pickup apparatus, the third transistor applies a second potential to the fourth gate, sets the drain potential to 0.3 V, and sets the source potential to 0 V, and in a state where the source potential is 0 V, the potential of -3 V is applied to the third gate. to the value of the drain current at the time of applying a ratio of the value of the drain current when a potential is applied to the third gate + 3V is 10 ⁶ or more, it is preferable.

Further, in the image pickup apparatus, each of the first transistor, the second transistor, and the fourth transistor has a metal oxide in the channel forming region, and the metal oxide is indium and the element M (M is , Gallium, aluminum, yttrium, and tin) and zinc.

Further, in the above imaging device, the photoelectric conversion device is preferably a photodiode having silicon in the photoelectric conversion layer.

Another aspect of the present invention includes a photoelectric conversion device, a first transistor to a fourth transistor, a capacitor, and an output line, and the second transistor has a first gate and a second. The third transistor has a third gate, a fourth gate, and a second semiconductor layer, and has a first semiconductor layer. Each of the second semiconductor layer and the second semiconductor layer is an oxide layer having indium, an element M (M is one or more of gallium, aluminum, ittrium, and tin), and zinc, and is a photoelectric conversion device. One terminal is electrically connected to one of the source or drain of the first transistor, and the other of the source or drain of the first transistor is one of the source or drain of the second transistor, one of the capacitors. Electrically connected to the electrode and the third gate of the third transistor, one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor, and the fourth The other of the source and drain of the transistor is a method of driving an imaging device that is electrically connected to the output line, and outputs imaging data corresponding to the illuminance of the light emitted to the photoelectric conversion device to the output line. It is a driving method of an image pickup apparatus in which a first potential is applied to a second gate and a second potential larger than the first potential is applied to a fourth gate during a period.

In the driving method of the image pickup apparatus, it is preferable that the second transistor and the third transistor are formed on the same insulating layer.

Further, in the driving method of the image pickup apparatus, each of the first transistor and the fourth transistor has a metal oxide in the channel forming region, and the metal oxide is indium and the element M (M is gallium). , Aluminum, yttrium, and tin) and zinc.

Further, in the driving method of the image pickup apparatus, it is preferable that the photoelectric conversion device is a photodiode having silicon in the photoelectric conversion layer.

According to one aspect of the present invention, it is possible to provide an image pickup apparatus with less noise. Moreover, according to one aspect of the present invention, it is possible to provide a highly productive imaging device. Further, according to one aspect of the present invention, it is possible to provide an image pickup device having low power consumption. Further, according to one aspect of the present invention, it is possible to provide an imaging device that can be manufactured with a high yield. Moreover, according to one aspect of the present invention, a small image pickup apparatus can be provided. Further, according to one aspect of the present invention, it is possible to provide an imaging device capable of high-speed operation. Moreover, according to one aspect of the present invention, it is possible to provide a highly reliable imaging device. Moreover, according to one aspect of the present invention, a novel imaging device can be provided. Further, according to one aspect of the present invention, it is possible to provide a method for driving the image pickup apparatus. Moreover, according to one aspect of the present invention, a novel semiconductor device or the like can be provided.

It should be noted that one aspect of the present invention is not limited to these effects. For example, one aspect of the present invention may have effects other than these effects in some cases or, depending on the circumstances. Alternatively, for example, one aspect of the present invention may not have these effects in some cases or, depending on the circumstances.

1 (A) and 1 (B) are circuit diagrams illustrating a pixel circuit of an image pickup apparatus. 2 (A) and 2 (B) are circuit diagrams illustrating a pixel circuit of the image pickup apparatus. FIG. 3A is a diagram illustrating the operation of the rolling shutter. FIG. 3B is a diagram illustrating the operation of the global shutter. 4 (A) and 4 (B) are timing charts illustrating the operation of the pixel circuit. FIG. 5 is a circuit diagram illustrating a read-out circuit. FIG. 6 is a perspective view illustrating an imaging device. 7 (A) and 7 (B) are block diagrams illustrating an image pickup apparatus. 8 (A) to 8 (E) are block diagrams and circuit diagrams for explaining the memory circuit. FIG. 9 is a cross-sectional view illustrating the pixels. 10 (A) to 10 (C) are views for explaining a Si transistor. 11 (A) to 11 (D) are diagrams for explaining the OS transistor. FIG. 12 is a cross-sectional view illustrating the pixels. FIG. 13 is a cross-sectional view illustrating the pixels. FIG. 14 is a cross-sectional view illustrating the pixels. FIG. 15 is a cross-sectional view illustrating the pixels. 16 (A) to 16 (F) are perspective views of a package and a module containing an imaging device. 17 (A) to 17 (F) are views showing electronic devices. FIG. 18 is a diagram illustrating an OS transistor. FIG. 19 is a diagram showing the electrical characteristics of the sample according to this embodiment. 20 (A) and 20 (B) are diagrams showing the results obtained by using the 1 / f noise measurement system.

The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. The hatching of the same element constituting the drawing may be omitted or changed as appropriate between different drawings.

Further, even if the element is shown as a single element on the circuit diagram, the element may be composed of a plurality of elements as long as there is no functional inconvenience. For example, a plurality of transistors operating as switches may be connected in series or in parallel. In addition, the capacitor may be divided and arranged at a plurality of positions.

In addition, one conductor may have a plurality of functions such as wiring, electrodes, and terminals, and in the present specification, a plurality of names may be used for the same element. Further, even when the elements are shown to be directly connected on the circuit diagram, the elements may actually be connected to each other via a plurality of conductors. In the book, such a configuration is also included in the category of direct connection.

In addition, the position, size, range, etc. of each configuration shown in the drawings and the like may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, the resist mask or the like may be unintentionally reduced due to a process such as etching, but it may not be reflected in the drawing for easy understanding.

Further, in the top view (also referred to as “plan view”) or the perspective view, the description of some components may be omitted in order to make the drawing easier to understand.

Further, in the present specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring" and vice versa. Further, the terms "electrode" and "wiring" include the case where a plurality of "electrodes" and "wiring" are integrally formed.

Further, in the present specification and the like, the “resistance” may determine the resistance value depending on the length of the wiring. Alternatively, the resistance also includes a case where it is formed by connecting to a conductive layer having a low efficiency different from the conductive layer used in wiring via a contact. Alternatively, the resistance value may be determined by doping the semiconductor layer with impurities.

Further, in the present specification and the like, the "terminal" in the electric circuit means a part where an input or output of an electric current, an input or output of an electric potential, or a reception or transmission of a signal is performed. Therefore, a part of the wiring or the electrode may function as a terminal.

In addition, in this specification etc., the term "upper", "upper", "lower", or "lower" does not limit the positional relationship of the components to be directly above or directly below and to be in direct contact with each other. Absent. For example, in the case of the expression "electrode B on the insulating layer A", it is not necessary that the electrode B is formed in direct contact with the insulating layer A, and another configuration is formed between the insulating layer A and the electrode B. Do not exclude those that contain elements. Further, in the expression of "the conductive layer D above the conductive layer C", it is not necessary that the conductive layer D is formed in direct contact with the conductive layer C, and between the conductive layer C and the conductive layer D. Do not exclude those that contain other components. In addition, "upper" or "lower" does not exclude cases where they are arranged diagonally.

In addition, the source and drain functions are interchanged depending on operating conditions, such as when transistors with different polarities are used or when the direction of current changes during circuit operation, so which one is the source or drain is limited. Is difficult. Therefore, in the present specification, the terms source and drain can be used interchangeably.

Further, in the present specification and the like, "electrically connected" includes a case of being directly connected and a case of being connected via "something having some electrical action". Here, the "thing having some kind of electrical action" is not particularly limited as long as it enables the exchange of electric signals between the connection targets. Therefore, even when it is expressed as "electrically connected", in an actual circuit, there is a case where there is no physical connection part and only the wiring is extended. Further, even when it is expressed as "direct connection", it includes a case where wiring is formed in different conductive layers via contacts. Therefore, there are cases where different conductive layers contain one or more same elements and cases where different conductive layers contain different elements.

In addition, in this specification and the like, when the count value and the measured value are referred to as "same", "same", "equal" or "uniform", an error of plus or minus 20% is applied unless otherwise specified. It shall include.

Further, the voltage often indicates a potential difference between a certain potential and a reference potential (for example, a ground potential or a source potential). Therefore, it is often possible to paraphrase voltage and potential. In the present specification and the like, voltage and potential can be paraphrased unless otherwise specified.

Even when the term "semiconductor" is used, for example, when the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is possible to replace "semiconductor" with "insulator". In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to make a strict distinction between the two. Therefore, the "semiconductor" and "insulator" described herein may be interchangeable.

Further, even when it is described as "semiconductor", for example, when the conductivity is sufficiently high, it has a characteristic as a "conductor". Therefore, it is also possible to replace the "semiconductor" with the "conductor". In this case, the boundary between the "semiconductor" and the "conductor" is ambiguous, and it is difficult to make a strict distinction between the two. Therefore, the "semiconductor" and "conductor" described herein may be interchangeable.

The ordinal numbers such as "first" and "second" in the present specification and the like are added to avoid confusion of the components, and do not indicate any order or order such as process order or stacking order. .. In addition, even terms that do not have ordinal numbers in the present specification and the like may have ordinal numbers within the scope of claims in order to avoid confusion of components. Further, even if the terms have ordinal numbers in the present specification and the like, different ordinal numbers may be added within the scope of claims. Further, even if the terms have ordinal numbers in the present specification and the like, the ordinal numbers may be omitted in the scope of claims.

In the present specification and the like, the "on state" of the transistor means a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as "conduction state"). Further, the "off state" of the transistor means a state in which the source and drain of the transistor can be regarded as being electrically cut off (also referred to as "non-conducting state").

Further, in the present specification and the like, the “on current” may mean a current flowing between the source and the drain when the transistor is in the on state. Further, the "off current" may mean a current flowing between the source and the drain when the transistor is in the off state. Further, the "on / off ratio" means the ratio of the on current to the off current.

Further, in the present specification and the like, the high power supply potential VDD (hereinafter, also simply referred to as “VDD”, “H potential”, or “H”) means the low power supply potential VSS (hereinafter, simply “VSS”, “L potential”). , Or also referred to as “L”). Further, VSS indicates a power supply potential having a potential lower than VDD. Further, the ground potential (hereinafter, also simply referred to as “GND” or “GND potential”) can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

Further, in the present specification and the like, the term “gate” refers to a part or all of the gate electrode and the gate wiring. The gate wiring refers to wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

Further, in the present specification and the like, the source means a part or all of a source region, a source electrode, and a source wiring. The source region refers to a region of the semiconductor layer having a resistivity of a certain value or less. The source electrode refers to a conductive layer in a portion connected to the source region. The source wiring is a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

Further, in the present specification and the like, the drain means a part or all of the drain region, the drain electrode, and the drain wiring. The drain region refers to a region of the semiconductor layer having a resistivity of a certain value or less. The drain electrode refers to a conductive layer at a portion connected to the drain region. The drain wiring refers to wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

(Embodiment 1)
In the present embodiment, the image pickup apparatus according to one aspect of the present invention will be described with reference to the drawings.

One aspect of the present invention is an imaging device having a pixel circuit. The pixel circuit has a function of converting incident light into an electric signal. The pixel circuit has at least a photoelectric conversion device and a plurality of transistors. For example, a pixel imaging device having a 4-transistor configuration has a photoelectric conversion device, a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor as a pixel circuit.

<Pixel circuit>
FIG. 1A is a circuit diagram illustrating an example of the pixel circuit 331. The pixel circuit 331 includes a photoelectric conversion device 240, a transistor 103, a transistor 104, a transistor 105, a transistor 106, and a capacitor 108. The capacitor 108 may not be provided. Each of the transistors 103 to 106 has a first gate (also simply referred to as a gate) and a second gate (also referred to as a back gate).

One electrode (cathode) of the photoelectric conversion device 240 is electrically connected to one of the source and drain of the transistor 103. The other of the source or drain of the transistor 103 is electrically connected to one of the source or drain of the transistor 104, one electrode of the capacitor 108, and the gate of the transistor 105. One of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 106.

Here, the wiring connecting the source or drain of the transistor 103, the source or drain of the transistor 104, one electrode of the capacitor 108, and the gate of the transistor 105 is referred to as a node FD. The node FD can function as a charge detector.

The other electrode (anode) of the photoelectric conversion device 240 is electrically connected to the wiring 121. The other of the source or drain of the transistor 104 is electrically connected to the wire 122. The other of the source or drain of the transistor 105 is electrically connected to the wire 123. The other of the source or drain of the transistor 106 is electrically connected to the wiring 352. The other electrode of the capacitor 108 is electrically connected to a reference potential line such as a GND wiring.

The wiring 121, the wiring 122, and the wiring 123 can have a function as a power supply line. In the configuration shown in FIG. 1A, the cathode of the photoelectric conversion device 240 is electrically connected to the transistor 103, and the node FD is reset to a high potential for operation. Therefore, the wiring 122 has a high potential ( The potential is higher than that of the wiring 121).

The gate of the transistor 103 is electrically connected to the wiring 127, and the back gate of the transistor 103 is electrically connected to the wiring 151. The gate of the transistor 104 is electrically connected to the wiring 126, and the back gate of the transistor 104 is electrically connected to the wiring 152. The back gate of the transistor 105 is electrically connected to the wiring 153. The gate of the transistor 106 is electrically connected to the wiring 128, and the back gate of the transistor 106 is electrically connected to the wiring 154.

The wiring 127, the wiring 126, and the wiring 128 can have a function as a signal line for controlling the continuity of each transistor. The wirings 151 to 154 function as wirings for applying a potential to the back gate of each transistor. The wiring 352 can have a function as an output line.

FIG. 1A shows a configuration in which the cathode of the photoelectric conversion device 240 is electrically connected to the node FD, but as shown in FIG. 1B, the anode of the photoelectric conversion device 240 is the source or drain of the transistor 103. It may be configured to be electrically connected to one of them.

In this configuration, since the node FD is reset to a low potential for operation, the wiring 122 has a low potential (a potential lower than that of the wiring 121).

The transistor 103 has a function of controlling the potential of the node FD. That is, the transistor 103 functions as a transfer transistor. The transistor 104 has a function of resetting the potential of the node FD. That is, the transistor 104 functions as a reset transistor. The transistor 105 has a function of outputting the potential of the node FD to the wiring 352 as imaging data. That is, the transistor 105 functions as a source follower transistor. The transistor 106 has a function of selecting a pixel for outputting imaging data. That is, the transistor 106 functions as a selection transistor.

If the leakage current between the source and drain of the transistor 103 and the transistor 104 connected to the node FD is large, the time that the electric charge accumulated in the node FD can be retained becomes insufficient. Further, if the leakage current between the source and drain of the transistor 105 and the transistor 106 is large, an unnecessary charge output may occur in the wiring 123 or the wiring 352.

Therefore, it is preferable to use a transistor using an oxide semiconductor (also referred to as an OS transistor) as the transistor 103 to the transistor 106. The OS transistor has a characteristic that the off-current is extremely small. Therefore, by using the OS transistor for the transistor 103 and the transistor 104, it is possible to prevent the outflow of unnecessary electric charge from the node FD, and the period during which the electric charge can be held by the node FD can be extremely extended. Further, by using the OS transistor for the transistor 105 and the transistor 106, it is possible to prevent the output of unnecessary electric charge to the wiring 123 or the wiring 352.

Noise in the image pickup device causes deterioration of image quality such as flickering of the image. Therefore, it is preferable that the noise is reduced. Noise in the image pickup apparatus includes noise caused by the components of the pixel circuit, noise caused by the circuit (including between the components), and the like. Further, noise is classified into random noise and fixed pattern noise.

In particular, if the noise caused by the source follower transistor, which is one of the components of the pixel circuit, is large, an accurate output value cannot be obtained even if the potential of the node FD is normal. Therefore, it leads to deterioration of image quality such as flickering of the image.

Therefore, it is preferable to reduce the noise caused by the transistor 105 that functions as the source follower transistor. In particular, it is preferable to reduce the noise of the drain current of the transistor 105. By reducing the noise caused by the transistor 105, a more accurate output value can be obtained. Therefore, the deterioration of the image quality is suppressed, and a clear image can be obtained.

1 / f noise can be mentioned as one of the factors of the noise of the drain current of the transistor. The 1 / f noise refers to a frequency component of current fluctuation that increases in inverse proportion to the frequency f. As a model of 1 / f noise, there are a model considered to be derived from carrier concentration fluctuation and a model considered to be derived from mobility fluctuation. In a model that is considered to be derived from carrier concentration fluctuation as the cause of 1 / f noise, it is assumed that electrons are bound to defects or emitted from defects. That is, 1 / f noise can be reduced by reducing the defect level density.

The 1 / f noise is random noise that does not depend on the amount of signal charge (also referred to as signal amount) corresponding to the illuminance of the light (incident light) applied to the photoelectric conversion device 240. 1 / f noise tends to be dominant noise when the amount of signal is small.

For example, it is preferable to apply 0 V or a positive potential to the back gate of the transistor 105 during the period in which the read operation is performed (described later). Specifically, the potential applied to the back gate of the transistor 105 is preferably 0 V or more and 3 V or less, and more preferably 0 V or more and 2 V or less. Thereby, 1 / f noise of the transistor 105 can be reduced.

By applying 0V or a positive potential to the back gate of the transistor, the carrier path extends from the vicinity of the interface between the semiconductor layer and the gate insulating film to the bulk of the semiconductor layer. Therefore, it is presumed that the influence of defects existing at the interface between the semiconductor layer and the gate insulating film and its vicinity is reduced, and 1 / f noise is reduced.

Further, the on-current can be increased by applying 0 V or a positive potential to the back gate of the transistor 105.

From the above, it is possible to obtain a clear image with less noise. Therefore, it is possible to provide an image pickup apparatus with less noise.

The period for applying 0 V or a positive potential to the back gate of the transistor 105 may not be limited to the period during which the read operation is performed. For example, when the leakage current between the source and drain of the transistor 106 is small, 0 V or a positive potential may be applied to the back gate of the transistor 105. The case where the leakage current between the source and the drain of the transistor 106 is small is, for example, the case where the transistor 106 has a normally-off characteristic. Alternatively, a negative potential is applied to the back gate of the transistor 106.

It is preferable that the transistor 103 and the transistor 104 have a normally-off characteristic (a state in which no current flows through the transistor when no potential is applied to the gate). Therefore, it is preferable to apply a negative potential to the transistor 103 and the back gate of the transistor 104. By applying a negative potential to the back gate, the threshold voltage (Vth) of the transistor 103 and the transistor 104 can be made larger and the off-current can be reduced.

The potential applied to the back gate is not limited to the above depending on the electrical characteristics of the OS transistor used as the transistor 103 to the transistor 106. For example, the potential applied to the back gate of the transistor 105 may be larger than the potential applied to the back gate of the transistor 103 and the transistor 104. At this time, the potential applied to the back gate of the transistor 105 is not limited to 0 V or positive, and may be negative.

1 (A) and 1 (B) show a configuration in which the back gate of the OS transistor (transistor 103 to transistor 106) is electrically connected to the wiring (wiring 151 to wiring 154) capable of supplying a constant potential. The threshold voltage of the transistor can be controlled.

In one aspect of the present invention, the configuration of the OS transistor that can be used for the transistor 103 to the transistor 106 is not limited to the above. FIG. 2A shows a modification of the transistor included in the pixel circuit 331 shown in FIG. 1A. The transistor 103a shown in FIG. 2A is a modification of the transistor 103 shown in FIG. 1A, and the transistor 104a shown in FIG. 2A is a modification of the transistor 104 shown in FIG. 1A. The transistor 106a shown in FIG. 2A is a modification of the transistor 106 shown in FIG. 1A.

Each of the transistor 103a, the transistor 104a, and the transistor 106a has a configuration in which a back gate is electrically connected to the gate. Thereby, the on-current of the transistor 103a, the transistor 104a, and the transistor 106a can be increased.

Further, FIG. 2B shows a modification of the transistor included in the pixel circuit 331 shown in FIG. 1A. The transistor 103b shown in FIG. 2B is a modification of the transistor 103 shown in FIG. 1A, and the transistor 106b shown in FIG. 2B is a modification of the transistor 106 shown in FIG. 1A.

Each of the transistor 103b and the transistor 106b has a configuration without a back gate. At this time, it is not necessary to provide the wiring 151 and the wiring 154. By not providing a part of the back gate and a part of the wiring, the degree of freedom in designing the image pickup apparatus can be increased. In addition, miniaturization and high integration of the imaging device become easy.

Further, the transistor may be configured so that appropriate operation can be performed by combining FIGS. 1 (A), 1 (B), 2 (A), and 2 (B).

Further, in the pixel circuit, the transistor 104, the transistor 105, the transistor 106, and the capacitor 108 may be shared by a plurality of pixel circuits. As a result, the number of transistors and wiring can be reduced, the image pickup device can be miniaturized by reducing the pixel area, and noise can be reduced by expanding the light receiving area of the photoelectric conversion device.

[Oxide semiconductor applicable to OS transistors]
As the semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more can be used. A typical example is an oxide semiconductor containing indium, and for example, CAAC-OS or CAC-OS, which will be described later, can be used. CAAC-OS is suitable for transistors and the like in which the atoms constituting the crystal are stable and reliability is important. Further, since CAC-OS exhibits high mobility characteristics, it is suitable for a transistor or the like that performs high-speed driving.

Since the OS transistor has a large energy gap in the semiconductor layer, it exhibits an extremely small off-current characteristic of several yA / μm (current value per 1 μm of channel width). Further, the OS transistor has features different from those of the Si transistor, such as impact ionization, avalanche breakdown, and short channel effect, and can form a highly reliable circuit with a high withstand voltage. In addition, variations in electrical characteristics due to crystallinity non-uniformity, which is a problem with Si transistors, are unlikely to occur with OS transistors.

The semiconductor layer of the OS transistor is an In containing, for example, indium, zinc, and element M (one or more metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It can be a film represented by −M—Zn oxide. The In-M-Zn oxide can be typically formed by a sputtering method. Alternatively, it may be formed by using an ALD (Atomic layer deposition) method.

The atomic number ratio of the metal element of the sputtering target used for forming the In—M—Zn oxide by the sputtering method preferably satisfies In ≧ M and Zn ≧ M. The atomic number ratio of the metal element of such a sputtering target is In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 1. 2, In: M: Zn = 4: 2: 3, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 3, In: M: Zn = 5: 1: 6. In: M: Zn = 5: 1: 7 and the like are preferable. The atomic number ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic number ratio of the metal element contained in the sputtering target.

As the semiconductor layer, an oxide semiconductor having a low carrier concentration is used. For example, the semiconductor layer has a carrier concentration of 1 × 10 ¹⁷ cm ^-3 or less, preferably 1 × 10 ¹⁵ cm ^-3 or less, more preferably 1 × 10 ¹³ cm ^-3 or less, and more preferably 1 × 10 ¹¹ cm ^{−. 3} or less, more preferably less than 1 × ^{10 10 cm -3,} it is possible to use an oxide semiconductor of 1 × ¹⁰ -9 ^{cm -3} or more carrier concentration. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. It can be said that the oxide semiconductor is an oxide semiconductor having a low defect level density and stable characteristics.

Not limited to these, a transistor having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Further, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the carrier concentration, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of the semiconductor layer are appropriate. ..

When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen deficiency increases and the mixture becomes n-type. Therefore, the concentration of silicon and carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry (SIMS)) is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms. / Cm ³ or less.

In addition, alkali metals and alkaline earth metals may generate carriers when combined with oxide semiconductors, which may increase the off-current of the transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by SIMS) is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier density is increased, and the n-type is easily formed. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have a normally-on characteristic. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by SIMS) is ^{preferably 5 × 10 18} atoms / cm ³ or less.

Further, when hydrogen is contained in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen deficiency, the transistor may have a normally-on characteristic. In addition, a defect containing hydrogen in an oxygen deficiency may function as a donor and generate electrons as carriers. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have a normally-on characteristic.

Defects containing hydrogen in oxygen deficiencies can function as donors for oxide semiconductors. However, it is difficult to quantitatively evaluate the defect. Therefore, in oxide semiconductors, the carrier concentration may be evaluated instead of the donor concentration. Therefore, in the present specification and the like, as a parameter of the oxide semiconductor, a carrier concentration assuming a state in which an electric field is not applied may be used instead of the donor concentration. That is, the "carrier concentration" described in the present specification and the like may be paraphrased as the "donor concentration".

Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS ^{is less than 1 × 10 20} atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , and more preferably 5 × 10 ¹⁸ atoms / cm. ^{Less than 3} , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted.

Further, the semiconductor layer may have a non-single crystal structure, for example. Non-single crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor), polycrystalline, microcrystalline, or amorphous structures with crystals oriented in the c-axis. In the non-single crystal structure, the amorphous structure has the highest defect level density, and CAAC-OS has the lowest defect level density.

An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Alternatively, the oxide film having an amorphous structure has, for example, a completely amorphous structure and has no crystal portion.

Even if the semiconductor layer is a mixed film having two or more of an amorphous structure region, a microcrystal structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Good. The mixed film may have, for example, a single-layer structure or a laminated structure including any two or more of the above-mentioned regions.

Hereinafter, the configuration of CAC (Cloud-Linked Composite) -OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

The CAC-OS is, for example, a composition of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size close thereto. In the following, in the oxide semiconductor, one or more metal elements are unevenly distributed, and the region having the metal elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. The state of being mixed with is also called a mosaic shape or a patch shape.

The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. Also, in addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from the above may be included.

For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide may be particularly referred to as CAC-IGZO in CAC-OS) is indium oxide (hereinafter, InO). _X1 (X1 is a real number greater than 0), or indium zinc oxide (hereinafter, InZn _Y2 O _Z2 (Y2 and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter, referred to as gallium oxide). , GaO _X3 (X3 is a real number larger than 0), or gallium zinc oxide (hereinafter, GaZn _Y4 O _Z4 (Y4 and Z4 are real numbers larger than 0)) and the like. Is separated to form a mosaic, and the mosaic-like InO _X1 or InZn _Y2 O _Z2 is uniformly distributed in the film (hereinafter, also referred to as cloud-like).

That is, CAC-OS is a composite oxide semiconductor having a structure in which a region _{containing GaO X3} as a main component and a region containing InZn _Y2 O _Z2 or InO _{X1 as a main component are mixed.} In the present specification, for example, the atomic number ratio of In to the element M in the first region is larger than the atomic number ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that of region 2.

In addition, IGZO is a common name, and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, it is represented by InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number). Crystalline compounds can be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented on the ab plane.

On the other hand, CAC-OS relates to the material composition of oxide semiconductors. CAC-OS is a region that is partially observed as nanoparticles containing Ga as a main component and nanoparticles containing In as a main component in a material composition containing In, Ga, Zn, and O. The regions observed in a shape refer to a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in CAC-OS, the crystal structure is a secondary element.

The CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.

In some cases, a clear boundary cannot be observed between the region _{containing GaO X3} as the main component and the region containing InZn _Y2 O _Z2 or InO _{X1 as the main component.}

Instead of gallium, select from aluminum, ittrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium. When one or more of these are contained, CAC-OS has a region that is partially observed as nanoparticles containing the metal element as a main component and a nano that contains In as a main component. The regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.

The CAC-OS can be formed by a sputtering method, for example, under the condition that the substrate is not intentionally heated. When CAC-OS is formed by a sputtering method, one or a plurality of selected gases may be used as the film forming gas: an inert gas (typically argon), an oxygen gas, and a nitrogen gas. Good. Further, the lower the flow rate ratio of the oxygen gas to the total flow rate of the film-forming gas at the time of film formation, the more preferable. ..

CAC-OS is characterized by the fact that no clear peak is observed when measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, from the X-ray diffraction measurement, it can be seen that the orientation of the measurement region in the ab plane direction and the c-axis direction is not observed.

Further, CAC-OS has a ring-shaped region with high brightness (ring region) and the ring in an electron diffraction pattern obtained by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam). Multiple bright spots are observed in the area. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

Further, for example, in CAC-OS in In-Ga-Zn oxide, GaO _X3 is the main component by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that the region and the region containing InZn _Y2 O _Z2 or InO _X1 as a main component have a structure in which they are unevenly distributed and mixed.

CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is _{phase-separated into a region containing GaO X3} or the like as a main component and a region containing InZn _Y2 O _Z2 or InO _X1 as a main component, and the region containing each element as a main component is a mosaic. It has a shaped structure.

Here, the region in which InZn _Y2 O _Z2 or InO _X1 is the main component is a region having higher conductivity than the region in which _{GaO X3 or the like is the main component.} That is, the conductivity as an oxide semiconductor is exhibited by the carrier flowing through the region where _{InZn Y2} O _Z2 or InO _{X1 is the main component.} Therefore, a high field effect mobility (μ) can be realized by distributing the region _{containing InZn Y2} O _Z2 or InO _{X1 as a main component in the oxide semiconductor in a cloud shape.}

On the other hand, _{the region containing GaO X3} or the like as the main component is a region having higher insulating properties than the region _{containing InZn Y2} O _Z2 or InO _{X1 as the main component.} That is, since _{the region containing GaO X3} or the like as the main component is distributed in the oxide semiconductor, the leakage current can be suppressed and a good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by _{GaO X3} or the like _{and the conductivity caused by InZn Y2} O _{Z2 or InO X1} act in a complementary manner to achieve a high on-current. (I _on ) and high field effect mobility (μ) can be achieved.

Further, the semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

<Operation method of imaging device>
FIG. 3 (A) is a diagram illustrating the operation method of the rolling shutter system, and FIG. 3 (B) is a diagram schematically showing the global shutter system. En represents the exposure (accumulation operation) of the nth column (n is a natural number), and Rn represents the reading operation of the nth column. In FIGS. 3A and 3B, the operations from the first row to the Mth row (M is a natural number) are shown.

The rolling shutter method is an operation method in which exposure and data reading are performed in sequence, and is a method in which the reading period of a certain line and the exposure period of another line are overlapped. Since the reading operation is performed immediately after the exposure, imaging can be performed even with a circuit configuration having a relatively short data retention period. However, since a one-frame image is composed of data that are not simultaneously captured, the image is distorted when capturing a moving object.

On the other hand, the global shutter method is an operation method in which all pixels are exposed at the same time, data is held in each pixel, and data is read out row by row. Therefore, it is possible to obtain an image without distortion even when imaging a moving object.

When a transistor having a relatively high off-current such as a Si transistor is used for the pixel circuit, the rolling shutter method is often used because the charge easily flows out from the charge detection unit. In order to realize the global shutter method using Si transistors, complicated operations such as storing data in a separate memory circuit must be performed at high speed. On the other hand, when an OS transistor is used in the pixel circuit, there is almost no outflow of data potential from the charge detection unit. Therefore, it is possible to easily realize a global shutter method in which charge accumulation operation is simultaneously performed on all pixels without complicating the circuit configuration and operation method. The imaging device according to one aspect of the present invention can also be operated by the rolling shutter method.

The pixel circuit 331 may be configured by arbitrarily combining an OS transistor and a Si transistor. By using an OS transistor for at least the transistor 103 and the transistor 104, the global shutter system can be realized.

<Operation of pixel circuit>
Next, an example of the operation of the pixel circuit shown in FIG. 1 (A) will be described with reference to the timing chart of FIG. 4 (A). In the description of the timing chart in the present specification, the high potential is represented by "H" and the low potential is represented by "L". It is assumed that "L" is always supplied to the wiring 121, and "H" is always supplied to the wiring 122 and the wiring 123.

When the potential of the wiring 126 is "H", the potential of the wiring 127 is "H", and the potential of the wiring 128 is "L" in the period T1, the transistor 103 and the transistor 104 are conducted, and the wiring 122 is connected to the node FD. The potential "H" is supplied (reset operation). That is, the period T1 is also a period for resetting the imaging data corresponding to the illuminance of the light (incident light) irradiated to the photoelectric conversion device 240.

When the potential of the wiring 126 is “L”, the potential of the wiring 127 is “H”, and the potential of the wiring 128 is “L” in the period T2, the transistor 104 becomes non-conducting and the supply of the reset potential is cut off. Further, the potential of the node FD decreases according to the operation of the photoelectric conversion device 240 (accumulation operation). That is, the period T2 corresponds to a period in which imaging data corresponding to the illuminance of the light (incident light) irradiated to the photoelectric conversion device 240 is input.

In the period T3, when the potential of the wiring 126 is “L”, the potential of the wiring 127 is “L”, and the potential of the wiring 128 is “L”, the transistor 103 becomes non-conducting, the potential of the node FD is fixed and held. (Holding operation). At this time, by using an OS transistor having a small off-current for the transistor 103 and the transistor 104 connected to the node FD, it is possible to suppress the outflow of unnecessary electric charge from the node FD and extend the data retention time. it can.

In the period T4, when the potential of the wiring 126 is "L", the potential of the wiring 127 is "L", and the potential of the wiring 128 is "H", the transistor 106 conducts, and the potential of the node FD is caused by the source follower operation of the transistor 105. Is read out to the wiring 352 (reading operation). That is, the period T4 corresponds to a period in which the potential of the node FD is output to the wiring 352 as imaging data.

During the period (period T2 to period T4) in which the potential of the wiring 126 is “L”, it is preferable to apply a negative potential to the back gates of the transistor 103 and the transistor 104. This makes it possible to increase the threshold voltage (Vth) of the transistor 103 and the transistor 104 and reduce the off-current. Therefore, it is possible to prevent the outflow of unnecessary electric charge from the node FD, and the period during which the electric charge can be retained by the node FD can be extremely extended.

Further, during the period in which the read operation is performed (period T4), it is preferable to apply 0 V or a positive potential to the back gate of the transistor 105. Thereby, 1 / f noise of the transistor 105 can be reduced. Therefore, the imaging data with less noise can be output to the wiring 352, and a clear imaging with less noise can be obtained.

That is, during the period T4, it is preferable to apply a negative potential to the back gate of the transistor 104 and to apply 0 V or a positive potential to the back gate of the transistor 105.

When the leakage current between the source and drain of the transistor 106 is small, even if 0 V or a positive potential is applied to the back gate of the transistor 105, the output of unnecessary electric charge to the wiring 352 is prevented. Therefore, even in the period T1 to the period T3, 0 V or a positive potential may be applied to the back gate of the transistor 105.

Further, when the potential given to the wiring 121 is the ground potential (0V), the potential applied to the back gate of the transistor 104 is larger than the potential given to the wiring 121.

As described above, the potential applied to the back gate is not limited to the above depending on the electrical characteristics of the transistor 104 and the OS transistor used as the transistor 105. For example, the potential applied to the back gate of the transistor 105 may be larger than the potential applied to the back gate of the transistor 103 and the transistor 104. In other words, when the potential given to the wiring 152 is the first potential and the potential given to the wiring 153 is the second potential, the second potential is preferably larger than the first potential.

It is preferable that each of the transistor 104 in the state where the first potential is applied to the back gate and the transistor 105 in the state where the second potential is applied to the back gate can obtain switching characteristics. For example, in the state of applying the first potential to the back gate of the transistor 104, the on / off ratio of the transistor 104 is preferably 10 ⁶ or more, more preferably 10 ⁹ or more, more preferably ^{10 12} or more. Further, in the state of applying the second potential to the back gate of the transistor 105, the on / off ratio of the transistor 105 is preferably 10 ⁶ or more, more preferably 10 ⁹ or more, more preferably ^{10 12} or more. As a result, the leakage current of the transistor 104 and the transistor 105 is suppressed, and good switching operation is realized.

The on / off ratio of the transistor changes depending on the potential applied to the source and / or the potential applied to the drain. For example, the more the drain potential is larger than the source potential and the larger the potential difference is, the larger the drain current of the transistor tends to be. Therefore, for example, in the transistor 104, the drain current when a potential of -3V is applied to the gate in a state where the first potential is applied to the back gate, the drain potential is 0.3V, and the source potential is 0V. for the value, the ratio of the value of the drain current when a potential is applied to the gate to + 3V is preferably 10 ⁶ or more. Further, the transistor 105 relates to the value of the drain current when a potential of -3V is applied to the gate in a state where a second potential is applied to the back gate, the drain potential is 0.3V, and the source potential is 0V. it preferably has a specific value of the drain current when a potential is applied to the gate to + 3V is 10 ⁶ or more.

The transistor used in the image pickup apparatus preferably has a threshold voltage larger than 0V and is turned on by applying a positive potential close to 0V to the gate. If the threshold voltage of the transistor is negative, a normally-on characteristic is obtained, and it becomes difficult to control the circuit composed of the transistor. Further, even if the threshold voltage is positive, in the case of a transistor having a high absolute value, the switching operation itself may not be possible due to insufficient drive voltage. That is, the potential applied to the back gate is in a range that satisfies the above. Therefore, the on / off ratio of the transistor can be calculated by applying a potential of ± 3 V to the gate of the transistor. In other words, when a potential in the range of -3V to + 3V is applied to the gate of the transistor, the potential may be applied to the back gate of the transistor so that switching characteristics (off state and on state) can be obtained.

The method for evaluating the switching characteristics of the transistor 104 and the transistor 105 is not limited to the above. For example, the potential applied to the gate when calculating the on / off ratio of the transistor 104 and the transistor 105 may be based on the threshold voltage. By using the threshold voltage as a reference, the swing width of the potential applied to the gate when calculating the on / off ratio can be reduced.

Here, the threshold voltage of the transistor 104 in the state where the first potential is applied to the back gate is Vth1, and the threshold voltage of the transistor 105 in the state where the second potential is applied to the back gate is Vth2. At this time, the transistor 104 applies (Vth1 + 2) [V] to the gate with respect to the value of the drain current when the potential of (Vth1-2) [V] is applied to the gate in a state where the first potential is applied to the back gate. the ratio of the value of the drain current when a potential is applied for (on / off ratio) is preferably 10 ⁶ or more. Further, the transistor 105 has (Vth2 + 2) [V] on the gate with respect to the value of the drain current when the potential of (Vth2-2) [V] is applied to the gate in a state where the second potential is applied to the back gate. the ratio of the value of the drain current when a potential is applied (oN / oFF ratio) is preferably 10 ⁶ or more.

The above is an example of the operation of the pixel circuit shown in FIG. 1 (A).

The pixel circuit shown in FIG. 1 (B) can be operated according to the timing chart of FIG. 4 (B). It is assumed that "H" is always supplied to the wiring 121 and 123, and "L" is always supplied to the wiring 122. The basic operation is the same as the description of the timing chart of FIG. 4 (A) above.

<Read circuit>
FIG. 5 is a diagram illustrating an example of a read circuit 311 connected to the pixel circuit 331, and shows a circuit diagram of the CDS circuit 400 and a block diagram of the A / D converter 410 electrically connected to the CDS circuit 400. Shown. The CDS circuit 400 and the A / D converter 410 shown in FIG. 5 are examples, and may have other configurations.

The CDS circuit 400 includes a resistance 401 for voltage conversion, a capacitor 402 for capacitance coupling _{, a transistor 403 for supplying potential V 0} , a transistor 404 for holding the potential supplied to the A / D converter 410, and a capacitor 405 for holding the potential. Can be configured to have. In the CDS circuit 400, the input is electrically connected to the pixel circuit 331 and the output is electrically connected to the comparator circuit (COMP) of the A / D converter 410.

When the potential of the wiring 352 is V _res (the pixel circuit 331 is in the reset state), the potential of the node N (the connection point of the transistor 403, the transistor 404, and the capacitor 402) is set to V ₀ . Then, when the potential of the wiring 352 becomes V _data (the pixel circuit 331 outputs the imaging data) with _{the node N floating, the potential of the node N becomes V 0} + V _data −V _res . Therefore, in the CDS circuit 400, the potential in the reset state can be subtracted from the potential of the imaging data output by the pixel circuit 331, and the noise component can be reduced.

The analog-to-digital converter 410 can be configured to include a comparator circuit (COMP) and a counter circuit (COUNTER). In the A / D converter 410, the signal potential input from the CDS circuit 400 to the comparator circuit (COMP) and the sweeped reference potential (RAMP) are compared. Then, the counter circuit (COUNTER) operates according to the output of the comparator circuit (COMP), and a digital signal is output to the plurality of wirings 353.

<Laminate structure>
FIG. 6 is a cross-sectional perspective view illustrating an imaging device according to an aspect of the present invention. The image pickup apparatus has a layer 201, a layer 202, a layer 203, a layer 204, and a layer 205.

In the present embodiment, the imaging device is divided into the above five layers for clarification of the description, but the type, quantity, and position of the elements included in each layer are limited to the description of the present embodiment. Not done. For example, elements such as an insulating layer, wiring, and a plug near the boundary between layers may belong to a layer different from the description of the present embodiment. Alternatively, elements different from these may be included.

The layer 201 may be provided with, for example, a pixel circuit read-out circuit, a memory circuit drive circuit, and the like.

A memory circuit or the like can be provided on the layer 202, for example.

The layer 203 may be provided with, for example, a pixel circuit (excluding photoelectric conversion devices) and a drive circuit for the pixel circuit.

A photoelectric conversion device can be provided on the layer 204. For the photoelectric conversion device, for example, a photodiode or the like can be used. The photoelectric conversion device is an element of a pixel circuit.

An optical conversion layer can be provided on the layer 205. For example, a color filter or the like can be used for the optical conversion layer. Layer 205 can also have a microlens array 255.

As described above, the image pickup apparatus of one aspect of the present invention is provided in the photoelectric conversion device provided in the layer 204, the pixel circuit provided in the layer 203, the drive circuit of the pixel circuit, the memory circuit provided in the layer 202, and the layer 201. It has a read circuit of a pixel circuit and a drive circuit of a memory circuit.

The photoelectric conversion device preferably has sensitivity to visible light. For example, a Si photodiode that uses silicon for the photoelectric conversion layer can be used as the photoelectric conversion device.

It is preferable to use a transistor (hereinafter, OS transistor) in which a metal oxide is used in the channel forming region for a component such as a pixel circuit and a drive circuit of the pixel circuit. The OS transistor has an extremely small off current, and can suppress unnecessary outflow of data from the pixel circuit. Therefore, it is possible to perform a global shutter operation in which data is acquired all at once by a plurality of pixel circuits and sequentially read out with a simple circuit configuration. Further, the pixel drive circuit can be formed by a process common to that of the pixel circuit.

It is preferable to use an OS transistor for the memory circuit as well. By using an OS transistor for the cell transistor of the memory circuit, unnecessary outflow of data can be suppressed and the frequency of refreshing can be suppressed. Therefore, power consumption can be suppressed.

Since high-speed operation is required for the reading circuit of the pixel circuit, the driving circuit of the memory circuit, and the like, it is preferable to use a transistor having high mobility. For example, it is preferable to use a transistor using silicon (hereinafter, Si transistor) in the channel forming region. Examples of the Si transistor include a transistor having amorphous silicon, a transistor having crystalline silicon (microcrystalline silicon, low temperature polysilicon, single crystal silicon), and the like. The drive circuit of the pixel circuit may be formed of a Si transistor.

When a plurality of Si devices are laminated, a polishing step and a bonding step are required a plurality of times. Therefore, there are problems such as a large number of processes, a need for a dedicated device, a low yield, and a high manufacturing cost. In one aspect of the present invention, the polishing step and the bonding step can be reduced by forming a circuit using an OS transistor on the Si device. Therefore, the yield can be improved. In addition, the productivity of the imaging device can be increased.

The OS transistor can be formed on a Si device (Si transistor, Si photodiode) via an insulating layer without using complicated processes such as bonding and bump bonding.

Therefore, in one aspect of the present invention, the layer 201 is a layer including a silicon substrate, and a circuit having a Si transistor in the layer 201 is formed. Then, the layer 202 is formed on the layer 201. A circuit having an OS transistor is formed on the layer 202.

Further, the layer 204 is a layer including a silicon substrate, and a Si photodiode is formed on the layer 204 as a photoelectric conversion device. Then, the layer 203 is formed on the surface on which the Si photodiode of the layer 204 is formed. A circuit having an OS transistor is formed on the layer 203.

Then, by laminating the surface of the layer 202 on the side opposite to the layer 201 and the surface of the layer 203 on the side opposite to the layer 204, a laminated structure in which the layers 201 to 204 overlap can be produced. FIG. 6 shows a configuration in which a layer 205 is further provided on the layer 204 of the laminated body in which the layers 201 to 204 are overlapped.

In the case of laminating Si devices, in the case of laminating four layers, a polishing step and a laminating step are required at least three times each, but in one aspect of the present invention, the polishing step is laminating once or twice. The matching process can be performed once.

By forming the image pickup device in a laminated structure, a small image pickup device can be formed. Further, by stacking each circuit, wiring delay and the like can be suppressed, and high-speed operation can be performed.

<Circuit>
FIG. 7A is a simple block diagram illustrating the electrical connection of the elements included in the layers 201 to 203. The photoelectric conversion device 240 included in the layer 204 is included in the pixel circuit 331 (PIX) on the circuit, and is not shown here.

The pixel circuits 331 are arranged side by side in a matrix and are electrically connected to the drive circuit 332 (Driver) via the wiring 351. The drive circuit 332 can control the data acquisition operation and the selection operation of the pixel circuit 331. For the drive circuit 332, for example, a shift register or the like can be used.

Further, the pixel circuit 331 is electrically connected to the read circuit 311 (RC) via the wiring 352. The readout circuit 311 includes a correlated double sampling circuit (CDS circuit) that reduces noise and an A / D converter that converts analog data into digital data.

The read circuit 311 is electrically connected to the memory circuit 321 (MEM) via the wiring 353. The memory circuit 321 can hold the digital data output from the read circuit 311. Alternatively, digital data can be output from the read circuit 311 to the outside without going through the memory circuit 321.

The memory circuit 321 is electrically connected to the low driver 312 (RD) via the wiring 354. Further, the memory circuit 321 is electrically connected to the column driver 313 (CD) via the wiring 355. The low driver 312 is a drive circuit of the memory circuit 321 and can control the writing and reading of data. The column driver 313 is a drive circuit of the memory circuit 321 and can control the reading of data.

The details of the connection relationship between the pixel circuit 331, the read circuit 311 and the memory circuit 321 will be described with reference to the block diagram of FIG. 7B. The number of read circuits 311 is the same as that of the pixel circuits 331, and one read circuit 311 is electrically connected to each pixel circuit 331 via the wiring 352. Further, the read circuit 311 is connected to a plurality of wirings 353, and each of the wirings 353 is electrically connected to one memory cell 321a. A data holding circuit may be provided between the read circuit 311 and the memory circuit 321.

The A / D converter included in the read circuit 311 outputs binary data corresponding to a predetermined number of bits in parallel. Therefore, the A / D converter is connected to the memory cells 321a for the number of bits. For example, when the output of the A / D converter is 8 bits, it is connected to eight memory cells 321a.

With the above configuration, in the image pickup apparatus of one aspect of the present invention, A / D conversion of analog data acquired by all pixel circuits 331 can be performed in parallel, and the converted digital data can be directly sent to the memory circuit 321. Can be written. That is, it is possible to perform from imaging to storage in the memory circuit at high speed. It is also possible to perform the imaging operation, the A / D conversion operation, and the reading operation in parallel. Therefore, it is possible to provide an imaging device capable of high-speed operation.

<Memory circuit>
FIG. 8A is a diagram showing a connection relationship between the memory cell 321a included in the memory circuit 321, the low driver 312, and the column driver 313. An OS transistor can be used as the transistor constituting the memory cell 321a.

The memory circuit 321 has m (m is an integer of 1 or more) in a column, n (n is an integer of 1 or more) in a row, and a total of m × n memory cells 321a, and the memory cells 321a have a matrix shape. Is located in. In FIG. 8A, the address of the memory cell 321a is also shown. For example, [1,1] indicates a memory cell 321a located at the address of the first row and the first column, and [i, j] (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less). Indicates a memory cell 321a located at the address of the i-th row and the j-th column. The number of wires connecting the memory circuit 321 and the low driver 312 is determined by the configuration of the memory cells 321a, the number of the memory cells 321a included in the row, and the like. The number of wires connecting the memory circuit 321 and the column driver 313 is determined by the configuration of the memory cells 321a, the number of memory cells 321a included in one line, and the like.

8 (B) to 8 (E) are diagrams illustrating memory cells 321aA to memory cells 321aD that can be applied to memory cells 321a. In the following description, the bit wires can be connected to the column driver 313. In addition, the word wires can be connected to the low driver 312. The bit wires are also electrically connected to the read circuit 311 but are not shown here.

For the low driver 312 and the column driver 313, for example, a decoder or a shift register can be used. A plurality of low drivers 312 and column drivers 313 may be provided.

[DOSRAM]
FIG. 8B shows a circuit configuration example of the DRAM type memory cell 321aA. In the present specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 321aA has a transistor M11 and a capacitor Cs.

The first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is. , Is connected to the wiring BGL. The second terminal of the capacitor Cs is connected to the wiring GNDL. Wiring GNDL is wiring that gives a low level potential (reference potential).

The wiring BIL functions as a bit line. The wiring WL functions as a word line. The wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M11. The threshold voltage of the transistor M11 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

Data writing and reading is performed by applying a high level potential to the wiring WL, making the transistor M11 conductive, and electrically connecting the wiring BIL and the first terminal of the capacitor Cs.

It is preferable to use an OS transistor for the transistor M11. Further, as the semiconductor layer of the OS transistor, an oxide semiconductor having any one or more of indium, element M (element M is one or more of aluminum, gallium, yttrium, or tin) and zinc can be used. preferable. In particular, it is preferable to use an oxide semiconductor having indium, gallium, and zinc.

An OS transistor to which an oxide semiconductor containing indium, gallium, and zinc is applied has a characteristic that the off-current is extremely small. By using an OS transistor as the transistor M11, the leakage current of the transistor M11 can be made very small. That is, since the written data can be held by the transistor M11 for a long time, the frequency of refreshing the memory cells can be reduced. Alternatively, the memory cell refresh operation can be eliminated.

[NOSRAM]
FIG. 8C shows a circuit configuration example of a gain cell type (also referred to as “2Tr1C type”) memory cell 321aB having two transistors and one capacitor. The memory cell 321aB includes a transistor M11, a transistor M3, and a capacitor Cs.

The first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, the second terminal of the transistor M11 is connected to the wiring WBL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is. , Is connected to the wiring BGL. The second terminal of the capacitor Cs is connected to the wiring RL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor Cs.

The wiring WBL functions as a write bit line. The wiring RBL functions as a read bit line. The wiring WL functions as a word line. The wiring RL functions as wiring for applying a predetermined potential to the second terminal of the capacitor Cs. It is preferable to apply a reference potential to the wiring RL during data writing and data retention.

The wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M11. The threshold voltage of the transistor M11 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

Data is written by applying a high level potential to the wiring WL, making the transistor M11 conductive, and electrically connecting the wiring WBL and the first terminal of the capacitor Cs. Specifically, when the transistor M11 is in a conductive state, a potential corresponding to the information recorded in the wiring WBL is applied, and the potential is written to the first terminal of the capacitor Cs and the gate of the transistor M3. After that, a low level potential is applied to the wiring WL to bring the transistor M11 into a non-conducting state, thereby holding the potential of the first terminal of the capacitor Cs and the potential of the gate of the transistor M3.

Data is read out by applying a predetermined potential to the wiring RL and the wiring SL. Since the current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, they are connected to the first terminal of the transistor M3. By reading out the potential of the wiring RBL, the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M3) can be read out. That is, the information written in the memory cell can be read from the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M3). Alternatively, it is possible to know whether or not there is information written in this memory cell.

Further, as shown in FIG. 8D, the wiring WBL and the wiring RBL may be combined into one wiring BIL. In the memory cell 321aC shown in FIG. 8D, the wiring WBL and the wiring RBL of the memory cell 321aB are used as one wiring BIL, and the second terminal of the transistor M11 and the first terminal of the transistor M3 are connected to the wiring BIL. The configuration is as follows. That is, the memory cell 321aC has a configuration in which the write bit line and the read bit line operate as one wiring BIL.

Also in the memory cells 321aB and the memory cells 321aC, it is preferable to use an OS transistor for the transistor M11. A storage device using an OS transistor for the transistor M11 and using a 2Tr1C type memory cell such as a memory cell 321aB and a memory cell 321aC is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).

Further, FIG. 8E shows a circuit configuration example of a gain cell type (also referred to as “3Tr1C type”) memory cell 321aD of a 3-transistor 1-capacitor. The memory cell 321aD includes a transistor M11, a transistor M5, a transistor M6, and a capacitor Cs.

The first terminal of the transistor M11 is connected to the first terminal of the capacitor Cs, the second terminal of the transistor M11 is connected to the wiring BIL, the gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is. , Is electrically connected to the wiring BGL. The second terminal of the capacitor Cs is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor Cs. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RL.

The wiring BIL functions as a bit line, the wiring WL functions as a write word line, and the wiring RL functions as a read word line.

The wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M11. The threshold voltage of the transistor M11 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

Data is written by applying a high level potential to the wiring WL, making the transistor M11 conductive, and connecting the wiring BIL and the first terminal of the capacitor Cs. Specifically, when the transistor M11 is in a conductive state, a potential corresponding to the information recorded in the wiring BIL is applied, and the potential is written to the first terminal of the capacitor Cs and the gate of the transistor M5. After that, a low level potential is applied to the wiring WL to bring the transistor M11 into a non-conducting state, thereby holding the potential of the first terminal of the capacitor Cs and the potential of the gate of the transistor M5.

Data is read out by precharging the wiring BIL with a predetermined potential, then electrically suspending the wiring BIL, and applying a high level potential to the wiring RL. Since the wiring RL has a high level potential, the transistor M6 is in a conductive state, and the wiring BIL and the second terminal of the transistor M5 are in an electrically connected state. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, but the transistor M5 depends on the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M5). The potential of the second terminal and the potential of the wiring BIL change. Here, by reading out the potential of the wiring BIL, the potential held in the first terminal (or the gate of the transistor M5) of the capacitor Cs can be read out. That is, the information written in the memory cell can be read from the potential held in the first terminal of the capacitor Cs (or the gate of the transistor M5). Alternatively, it is possible to know whether or not there is information written in this memory cell.

Also in the memory cell 321aD, it is preferable to use an OS transistor for the transistor M11. The 3Tr1C type memory cell 321aD to which the OS transistor is applied as the transistor M11 is one aspect of the NOSRAM described above. The configuration of the circuit of the memory cell can be changed as appropriate.

<Laminate structure 1>
Next, the laminated structure of the image pickup apparatus will be described with reference to a cross-sectional view.

FIG. 9 is an example of a cross-sectional view of a laminated body having layers 201 to 205 and having a bonding surface between the layers 202 and 203.

<Layer 201>
The layer 201 has a read circuit 311 provided on the silicon substrate 211, a low driver 312, and a column driver 313. Here, as a part of the above circuit, the capacitor 402 and the transistor 403 included in the CDS circuit of the read circuit 311, the transistor 115 included in the A / D converter of the read circuit 311 and the transistor 116 included in the low driver 312 are shown. One electrode of the capacitor 402 and one of the source or drain of the transistor 403 are electrically connected.

The layer 201 is provided with an insulating layer 212, an insulating layer 213, an insulating layer 214, an insulating layer 215, an insulating layer 216, an insulating layer 217, and an insulating layer 218. The insulating layer 212 has a function as a protective film. The insulating layer 212, the insulating layer 213, the insulating layer 214, and the insulating layer 217 have functions as an interlayer insulating film and a flattening film. The insulating layer 216 has a function as a dielectric layer of the capacitor 402. The insulating layer 218 has a function as a blocking film.

As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used. As the interlayer insulating film and the flattening film, for example, an inorganic insulating film such as a silicon oxide film or an organic insulating film such as an acrylic resin or a polyimide resin can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used. As the blocking film, it is preferable to use a film having a function of preventing the diffusion of hydrogen.

In Si devices, hydrogen is required to terminate dangling bonds, but hydrogen in the vicinity of the OS transistor becomes one of the factors that generate carriers in the oxide semiconductor layer, which reduces reliability. .. Therefore, it is preferable to provide a hydrogen blocking film between the layer on which the Si device is formed and the layer on which the OS transistor is formed.

As the blocking film, for example, aluminum oxide, aluminum nitride, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide, yttria-stabilized zirconia (YSZ) and the like can be used.

The Si transistor shown in FIG. 9 is a fin type having a channel forming region on the silicon substrate 211. A cross section of the Si transistor in the channel width direction (cross section corresponding to the portion indicated by the alternate long and short dash line in A1-A2 in FIG. 9) is shown in FIG. 10 (A).

The Si transistor may be a planar type as shown in FIG. 10 (B). Alternatively, as shown in FIG. 10C, it may be a transistor having a semiconductor layer 545 of a silicon thin film. The semiconductor layer 545 can be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on the insulating layer 546 on the silicon substrate 211.

Conductors that can be used as wiring, electrodes, and plugs for electrical connections between devices include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, and hafnium. , Vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc. Etc. may be appropriately selected and used. The conductor is not limited to a single layer, and may be a plurality of layers made of different materials.

<Layer 202>
The layer 202 is formed on the layer 201. Layer 202 has a memory circuit 321 with an OS transistor. Here, the transistor 111 and the capacitor 112 included in the memory cell 321a are shown as a part of the memory circuit 321.

The layer 202 is provided with an insulating layer 221, an insulating layer 222, an insulating layer 223, an insulating layer 224, an insulating layer 225, an insulating layer 226, an insulating layer 227, an insulating layer 228, and an insulating layer 229. Further, the conductive layer 131 is provided.

The insulating layer 221, the insulating layer 224, the insulating layer 225, the insulating layer 227, and the insulating layer 228 have functions as an interlayer insulating film and a flattening film. The insulating layer 222 has a function as a gate insulating film. The insulating layer 223 has a function as a protective film. The insulating layer 226 has a function as a dielectric layer of the capacitor. The insulating layer 229 and the conductive layer 131 have a function as a bonding layer.

As the gate insulating film, a silicon oxide film or the like can be used. The bonding layer will be described later.

The conductive layer 131 is electrically connected to the other electrode of the capacitor 402 of the layer 201. One of the source or drain of transistor 111 is electrically connected to one of the source or drain of transistor 115 of layer 201. The gate of transistor 111 is electrically connected to either the source or drain of transistor 116 in layer 201. The other of the source or drain of the transistor 111 is electrically connected to one electrode of the capacitor 112.

FIG. 11A shows the details of the transistor 111. The transistor 111 shown in FIG. 11A is provided with an insulating layer on a laminate of an oxide semiconductor layer and a conductive layer, and a conductor 705 and a drain that function as source electrodes by providing an opening reaching the oxide semiconductor layer. It is a self-aligned configuration that forms a conductor 706 that functions as an electrode.

The transistor 111 is configured to include a channel forming region, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, a conductor 701 that functions as a gate electrode, and an insulator 702 that functions as a gate insulating film. Can be done. At least an insulator 702 and a conductor 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.

In one aspect of the present invention, the configuration of the transistor 111 is not limited to the above. The transistor 111a shown in FIG. 11B is a modification of the transistor 111 shown in FIG. 11A. The transistor 111a is a self-aligned transistor that forms a source region 703 and a drain region 704 in the semiconductor layer using the conductor 701 as a mask.

Further, the transistor 111b shown in FIG. 11C is a modification of the transistor 111 shown in FIG. 11A. The transistor 111b is a non-self-aligned top-gate transistor having a region in which the conductor 705 or the conductor 706 and the conductor 701 overlap.

Further, the conductor 535 is conductive as shown in the cross-sectional view of the transistor 111 shown in FIG. 11 (D) in the channel width direction (cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of B1-B2 in FIG. 11 (A)). It may be electrically connected to the top gate of the transistor 111 provided so as to face the body 535. Note that FIG. 11 (D) shows the transistor of FIG. 11 (A) as an example, but the same applies to transistors having other structures. Alternatively, the conductor 535 may be configured to be able to supply a fixed potential different from that of the top gate.

Although the transistor 111 shows a structure having a conductor 535 that functions as a back gate, it may have a structure that does not have a back gate.

<Layer 203>
The layer 203 is formed on the surface on which the Si photodiode of the layer 204 is formed. Layer 203 has a pixel circuit 331 with an OS transistor. Here, the transistor 103, the transistor 104, and the transistor 105 are shown as a part of the pixel circuit 331.

The layer 203 is provided with an insulating layer 231, an insulating layer 232, an insulating layer 233, an insulating layer 234, an insulating layer 235, an insulating layer 236, and an insulating layer 237. Further, the conductive layer 132 is provided.

The insulating layer 231 and the conductive layer 132 have a function as a bonding layer. The insulating layer 232, the insulating layer 233, the insulating layer 234, and the insulating layer 237 have functions as an interlayer insulating film and a flattening film. The insulating layer 235 has a function as a protective film. The insulating layer 236 has a function as a gate insulating film.

The conductive layer 132 is electrically connected to the wiring 352 that functions as an output line of the pixel circuit 331.

Each of the transistors 103 to 106 has the same configuration as any one of the transistors 111 shown in FIGS. 11A to 11C.

<Layer 204>
The layer 204 has a photoelectric conversion device 240, an insulating layer 241 and an insulating layer 242, and an insulating layer 245.

The photoelectric conversion device 240 is a pn junction type photodiode formed on a silicon substrate, and has a p-type region 243 and an n-type region 244. The photoelectric conversion device 240 is an embedded photodiode, and a thin p-type region 243 provided on the surface side (current extraction side) of the n-type region 244 can suppress dark current and reduce noise.

The insulating layer 241 has a function as a blocking layer. The insulating layer 242 has a function as an element separation layer. The insulating layer 245 has a function of suppressing the outflow of carriers.

The silicon substrate is provided with a groove for separating pixels, and the insulating layer 245 is provided on the surface of the silicon substrate on the layer 205 side and the groove. By providing the insulating layer 245, it is possible to prevent the carriers generated in the photoelectric conversion device 240 from flowing out to the adjacent pixels. The insulating layer 245 also has a function of suppressing the intrusion of stray light. Therefore, the insulating layer 245 can suppress color mixing. An antireflection film may be provided between the surface of the silicon substrate on the layer 205 side and the insulating layer 245.

The device separation layer can be formed by using a LOCOS (LOCOxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like. As the insulating layer 245, for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as a polyimide resin or an acrylic resin can be used. The insulating layer 245 may have a multi-layer structure.

The n-type region 244 (corresponding to the cathode) of the photoelectric conversion device 240 is electrically connected to one of the source and drain of the transistor 103 of the layer 203 via a thin p-type region. The p-type region 243 (anode) is electrically connected to the wiring 121 of the layer 203 that functions as a power supply line.

In the laminated structure 1 shown in FIG. 9, the transistors 103 to 105 provided in the layer 203 are formed on the insulating layer 241 provided in the layer 204.

<Layer 205>
Layer 205 is formed on layer 204. The layer 205 has a light-shielding layer 251, an optical conversion layer 250, and a microlens array 255.

The light-shielding layer 251 can suppress the inflow of light to adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 251. Further, the metal layer and a dielectric film having a function as an antireflection film may be laminated.

A color filter can be used for the optical conversion layer 250. A color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter for each pixel.

Further, if a wavelength cut filter is used for the optical conversion layer 250, the image pickup device can obtain images in various wavelength regions.

For example, if the optical conversion layer 250 uses a filter that blocks light having a wavelength equal to or lower than that of visible light, it can be used as an infrared imaging device. Further, if the optical conversion layer 250 uses a filter that blocks light having a wavelength of near infrared rays or less, a far infrared ray imaging device can be obtained. Further, if the optical conversion layer 250 uses a filter that blocks light having a wavelength equal to or higher than that of visible light, it can be used as an ultraviolet imaging device.

Further, if a scintillator is used for the optical conversion layer 250, the image pickup device can obtain an image that visualizes the intensity of radiation used in an X-ray image pickup device or the like. When radiation such as X-rays transmitted through a subject is incident on a scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon. Then, the imaging data is acquired by detecting the light with the photoelectric conversion device 240. Further, an image pickup device having the above configuration may be used as a radiation detector or the like.

The scintillator contains a substance that absorbs the energy and emits visible light or ultraviolet light when irradiated with radiation such as X-rays and gamma rays. For example, Gd ₂ O ₂ S: Tb, Gd ₂ O ₂ S: Pr, Gd ₂ O ₂ S: Eu, BaFCl: Eu, NaI, CsI, CaF ₂ , BaF ₂ , CeF ₃ , LiF, LiI, ZnO, etc. Those dispersed in resin or ceramics can be used.

A microlens array 255 is provided on the optical conversion layer 250. Light passing through the individual lenses of the microlens array 255 passes through the optical conversion layer 250 directly below and is irradiated to the photoelectric conversion device 240. By providing the microlens array 255, the focused light can be incident on the photoelectric conversion device 240, so that photoelectric conversion can be performed efficiently. The microlens array 255 is preferably formed of a resin or glass having high translucency with respect to visible light.

<Lasting>
Next, the bonding of the layer 202 and the layer 203 will be described.

The layer 202 is provided with an insulating layer 229 and a conductive layer 131. The conductive layer 131 has a region embedded in the insulating layer 229. Further, the surfaces of the insulating layer 229 and the conductive layer 131 are flattened so that their heights match.

The layer 203 is provided with an insulating layer 231 and a conductive layer 132. The conductive layer 132 has a region embedded in the insulating layer 231. Further, the surfaces of the insulating layer 231 and the conductive layer 132 are flattened so that their heights match.

Here, it is preferable that the conductive layer 131 and the conductive layer 132 are metal elements having the same main components. Further, it is preferable that the insulating layer 229 and the insulating layer 231 are composed of the same components.

For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au and the like can be used for the conductive layer 131 and the conductive layer 132. Cu, Al, W, or Au is preferably used because of the ease of joining. Further, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, titanium nitride and the like can be used for the insulating layer 229 and the insulating layer 231.

That is, it is preferable to use the same metal material shown above for each of the conductive layer 131 and the conductive layer 132. Further, it is preferable to use the same insulating material shown above for each of the insulating layer 229 and the insulating layer 231. With this configuration, bonding can be performed with the boundary between the layer 202 and the layer 203 as the joining position.

The conductive layer 131 and the conductive layer 132 may have a multi-layer structure of a plurality of layers, and in that case, the surface layer (bonding surface) may be the same metal material. Further, the insulating layer 229 and the insulating layer 231 may also have a multi-layer structure of a plurality of layers, in which case, the insulating materials having the same surface layer (bonding surface) may be used.

By the bonding, an electrical connection between the conductive layer 131 and the conductive layer 132 can be obtained. Further, it is possible to obtain a connection having mechanical strength of the insulating layer 229 and the insulating layer 231.

For bonding between metal layers, a surface-activated bonding method can be used in which the oxide film on the surface and the adsorption layer of impurities are removed by sputtering or the like, and the cleaned and activated surfaces are brought into contact with each other for bonding. .. Alternatively, a diffusion bonding method or the like in which surfaces are bonded to each other by using both temperature and pressure can be used. In both cases, bonding at the atomic level occurs, so that excellent bonding can be obtained not only electrically but also mechanically.

Further, in order to bond the insulating layers to each other, after obtaining high flatness by polishing or the like, the surfaces treated with hydrophilicity such as oxygen plasma are brought into contact with each other for temporary bonding, and then main bonding is performed by dehydration by heat treatment. A joining method or the like can be used. Since the hydrophilic bonding method also causes bonding at the atomic level, it is possible to obtain mechanically excellent bonding.

When the layer 202 and the layer 203 are bonded together, an insulating layer and a metal layer are mixed on the respective bonding surfaces. Therefore, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.

For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an antioxidant treatment, and then a hydrophilic treatment is performed to join the metal layer. Further, the surface of the metal layer may be made of a refractory metal such as Au and subjected to hydrophilic treatment. A joining method other than the above-mentioned method may be used.

By the above bonding, the pixel circuit 331 of the layer 203 and the readout circuit 311 of the layer 201 can be electrically connected.

<Modification example 1 of laminated structure 1>
FIG. 12 shows a modified example of the laminated structure 1 shown in FIG. The laminated structure shown in FIG. 12 is different from the laminated structure 1 shown in FIG. 9 in the configurations of the layers 203 and 204. Modification 1 shown in FIG. 12 has a configuration in which the transistor 103 included in the pixel circuit 331 is provided on the layer 204. In layer 204, the transistor 103 is made of Si transistors. One of the source or drain of the transistor 103 is directly connected to the photoelectric conversion device 240, and the other of the source or drain acts as a node FD.

In this case, the layer 203 is provided with the transistors excluding the transistor 103 among the transistors constituting the pixel circuit 331. In FIG. 12, the transistor 104 and the transistor 105 are illustrated.

In the first modification shown in FIG. 12, the transistor 104 and the transistor 105 provided in the layer 203 are formed on the insulating layer 246 provided in the layer 204.

<Modification 2 of laminated structure 1>
FIG. 13 shows a modified example of the laminated structure 1 shown in FIG. The laminated structure shown in FIG. 13 is different from the laminated structure 1 shown in FIG. 9 in the configurations of the layers 201 and 203. The second modification shown in FIG. 13 is a configuration in which the CDS circuit 400, which is a component of the read circuit 311 is provided on the layer 203. Although FIG. 13 shows a configuration in which the CDS circuit 400 is laminated on the pixel circuit 331, the CDS circuit 400 may be provided on the same surface as the pixel circuit 331.

In the case of the above configuration, the layer 201 is provided with an A / D converter 410, which is another component of the readout circuit 311. FIG. 13 illustrates a transistor 117 that functions as an input transistor of the A / D converter 410. The gate of the transistor 117 is electrically connected to the conductive layer 131 of the layer 202.

Layer 203 has a CDS circuit 400 in addition to the pixel circuit 331. Here, the capacitor 402, the transistor 403, and the transistor 404, which are the elements of the CDS circuit 400, are illustrated. The transistor 403 and the transistor 404 can be formed of an OS transistor. Further, the layer 203 is provided with an insulating layer 421, an insulating layer 422, an insulating layer 423, an insulating layer 424, an insulating layer 425, an insulating layer 426, and an insulating layer 427.

The insulating layer 421, the insulating layer 423, the insulating layer 424, and the insulating layer 427 have functions as an interlayer insulating film and a flattening film. The insulating layer 422 has a function as a dielectric layer of the capacitor 402. The insulating layer 425 has a function as a protective film. The insulating layer 426 has a function as a gate insulating film.

The other electrode of the capacitor 402 is electrically connected to the wiring 352 to which the pixel circuit 331 is connected, and one electrode of the capacitor 402 is one of the source or drain of the transistor 403 and one of the source or drain of the transistor 404. Is electrically connected to. Then, the other side of the source or drain of the transistor 404 is connected to the conductive layer 132. By laminating the conductive layer 132 and the conductive layer 131 of the layer 202, the CDS circuit 400 and the A / D converter 410 can be electrically connected.

In the second modification shown in FIG. 13, the transistors 103 to 105 provided in the layer 203 are formed on the insulating layer 241 provided in the layer 204.

<Laminate structure 2>
In the laminated structure 1 and its modified example, the structure in which the layer 202 and the layer 203 are bonded to each other is shown, but the layers may be bonded to each other. The laminated structure 2 shown in FIG. 14 has a structure having a bonded surface between the layer 203 and the layer 204.

In this case, the layer 203 is provided with a conductive layer 135 that is electrically connected to either the source or the drain of the transistor 103. Further, a conductive layer 136 that is electrically connected to the wiring 121 is provided. The conductive layer 135 and the conductive layer 136 have a region embedded in the insulating layer 231. Further, the surfaces of the insulating layer 231 and the conductive layer 135, and the conductive layer 136 are flattened so that their heights match.

The layer 204 is provided with a conductive layer 133 that is electrically connected to the n-type region 244 (corresponding to the cathode) of the photoelectric conversion device 240. In addition, a conductive layer 134 that is electrically connected to the p-type region 243 (anode) is provided. Further, an insulating layer 249 is provided on the insulating layer 246. The conductive layer 133 and the conductive layer 134 have a region embedded in the insulating layer 249. Further, the surfaces of the insulating layer 249, the conductive layer 133, and the conductive layer 134 are flattened so that their heights match.

Here, the conductive layer 133, the conductive layer 134, the conductive layer 135, and the conductive layer 136 are the same bonded layers as the above-mentioned conductive layer 131 and the conductive layer 132. Further, the insulating layer 249 is the same bonded layer as the above-mentioned insulating layer 229 and the insulating layer 231.

Therefore, by laminating the conductive layer 133 and the conductive layer 135, one of the source or drain of the transistor 103 can be electrically connected to the n-type region 244 (corresponding to the cathode) of the photoelectric conversion device. Further, by laminating the conductive layer 134 and the conductive layer 136, the p-type region 243 (corresponding to the anode) of the photoelectric conversion device and the wiring 121 can be electrically connected. Further, by laminating the insulating layer 231 and the insulating layer 249, the layer 203 and the layer 204 can be electrically and mechanically bonded.

In the laminated structure 2 shown in FIG. 14, the transistors 103 to 105 provided in the layer 203 are formed on the insulating layer 228 provided in the layer 202.

<Laminate structure 3>
The laminated structure 3 shown in FIG. 15 has a structure in which a bonding surface is provided between the layer 201 and the layer 202.

In this case, the layer 201 is provided with a conductive layer 141 that is electrically connected to the other electrode of the capacitor 402. In addition, a conductive layer 142 that is electrically connected to one of the source and drain of the transistor 115 is provided. Further, the conductive layer 143 that is electrically connected to one of the source and drain of the transistor 116 is electrically connected. Further, an insulating layer 219 is provided on the insulating layer 218. The conductive layer 141, the conductive layer 142, and the conductive layer 143 have a region embedded in the insulating layer 219. Further, the surfaces of the insulating layer 219, the conductive layer 141, the conductive layer 142, and the conductive layer 143 are flattened so that their heights match.

The layer 202 is provided with a conductive layer 137 that is electrically connected to the wiring 352 of the layer 203. Further, a conductive layer 138 is provided which is electrically connected to one of the source and drain of the transistor 111 included in the layer 202. Further, a conductive layer 139 that is electrically connected to the gate of the transistor 111 is provided. The conductive layer 137, the conductive layer 138, and the conductive layer 139 have a region embedded in the insulating layer 229. Further, the surfaces of the insulating layer 229, the conductive layer 137, the conductive layer 138, and the conductive layer 139 are flattened so that their heights match.

Here, the conductive layer 137, the conductive layer 138, the conductive layer 139, the conductive layer 141, the conductive layer 142, and the conductive layer 143 are the same bonded layers as the above-mentioned conductive layer 131 and the conductive layer 132. Further, the insulating layer 219 is the same bonded layer as the above-mentioned insulating layer 229 and the insulating layer 231.

Therefore, by laminating the conductive layer 137 and the conductive layer 141, the readout circuit 311 and the pixel circuit 331 can be electrically connected. Further, by laminating the conductive layer 138 and the conductive layer 142, the read circuit 311 and the memory circuit 321 can be electrically connected. Further, by laminating the conductive layer 139 and the conductive layer 143, the low driver 312 and the memory circuit 321 can be electrically connected.

In the laminated structure 3 shown in FIG. 15, the transistors 103 to 105 provided in the layer 203 are formed on the insulating layer 241 provided in the layer 204.

In the present embodiment, the configuration in which the pixel circuit read circuit and the memory circuit drive circuit are provided on the layer 201 and the memory circuit is provided on the layer 202 has been described, but the present invention is not limited to this. For example, a pixel circuit drive circuit, a neural network, a communication circuit, a CPU, and the like may be provided on the layer 201 or the layer 202.

A normally-off CPU (also referred to as "Noff-CPU") can be realized by using an OS transistor and a Si transistor. The Nonf-CPU is an integrated circuit including a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.

The Noff-CPU can stop the power supply to the unnecessary circuit in the Noff-CPU and put the circuit in the standby state. No power is consumed in the circuit where the power supply is stopped and the circuit is in the standby state. Therefore, the Nonf-CPU can minimize the amount of power used. Further, the Nonf-CPU can retain information necessary for operation such as setting conditions for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to restart the power supply to the circuit, and it is not necessary to rewrite the setting conditions and the like. That is, high-speed recovery from the standby state is possible. In this way, the Nonf-CPU can reduce the power consumption without significantly reducing the operating speed.

This embodiment can be appropriately combined with the description of other embodiments or examples.

(Embodiment 2)
In this embodiment, an example of a package containing an image sensor chip and a camera module will be described. For the image sensor chip, the configuration of the imaging device according to one aspect of the present invention can be used.

FIG. 16A is an external perspective view of the upper surface side of the package containing the image sensor chip. The package has a package substrate 610 for fixing the image sensor chip 650 (see FIG. 16C), a cover glass 620, an adhesive 630 for adhering both, and the like.

FIG. 16B is an external perspective view of the lower surface side of the package. On the lower surface of the package, there is a BGA (Ball grid array) in which solder balls are bumps 640. In addition to BGA, it may have LGA (Land grid array), PGA (Pin grid array), or the like.

FIG. 16C is a perspective view of the package shown by omitting a part of the cover glass 620 and the adhesive 630. An electrode pad 660 is formed on the package substrate 610, and the electrode pad 660 and the bump 640 are electrically connected via a through hole. The electrode pad 660 is electrically connected to the image sensor chip 650 by a wire 670.

Further, FIG. 16D is an external perspective view of the upper surface side of the camera module in which the image sensor chip is housed in a lens-integrated package. The camera module has a package substrate 611 for fixing an image sensor chip 651 (see FIG. 16F), a lens cover 621, a lens 635, and the like. Further, an IC chip 690 (see FIG. 16F) having functions such as a drive circuit for an image pickup device and a signal conversion circuit is also provided between the package substrate 611 and the image sensor chip 651, and SiP (System in package) is provided. ).

FIG. 16E is an external perspective view of the lower surface side of the camera module. The lower surface and the side surface of the package substrate 611 have a QFN (Quad flat no-lead package) configuration in which a land 641 for mounting is provided. The configuration is an example, and a QFP (Quad flat package) or the above-mentioned BGA may be provided.

FIG. 16F is a perspective view of the module shown by omitting a part of the lens cover 621 and the lens 635. The land 641 is electrically connected to the electrode pad 661, and the electrode pad 661 is electrically connected to the image sensor chip 651 or the IC chip 690 by a wire 671.

By housing the image sensor chip in a package having the above-mentioned form, it can be easily mounted on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

This embodiment can be appropriately combined with the description of other embodiments or examples.

(Embodiment 3)
Electronic devices that can use the imaging device according to one aspect of the present invention include a display device, a personal computer, an image storage device or image reproduction device provided with a recording medium, a mobile phone, a game machine including a portable type, and a portable data terminal. , Electronic book terminals, video cameras, cameras such as digital still cameras, goggles type displays (head mount displays), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers , Automatic cash deposit / payment machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIGS. 17 (A) to 17 (F).

FIG. 17A is an example of a mobile phone, which includes a housing 981, a display unit 982, an operation button 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor on the display unit 982. All operations such as making a phone call or inputting characters can be performed by touching the display unit 982 with a finger or a stylus. An image pickup device according to an aspect of the present invention and an operation method thereof can be applied to an element for image acquisition in the mobile phone.

FIG. 17B is a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, and the like. Information can be input and output by the touch panel function of the display unit 912. In addition, characters and the like can be recognized from the image acquired by the camera 919, and the characters can be output as voice by the speaker 913. An imaging device according to an aspect of the present invention and an operation method thereof can be applied to an element for image acquisition in the portable data terminal.

FIG. 17C is a surveillance camera, which has a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism or the like, and by installing it on the ceiling, it is possible to take an image of the entire surroundings. An image pickup apparatus according to an aspect of the present invention and an operation method thereof can be applied to an element for image acquisition in the camera unit. The surveillance camera is an idiomatic name and does not limit its use. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

FIG. 17D is a video camera, which includes a first housing 971, a second housing 972, a display unit 973, an operation key 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, and the like. The operation key 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. An image pickup apparatus according to an aspect of the present invention and an operation method thereof can be applied to an element for image acquisition in the video camera.

FIG. 17E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light emitting unit 967, a lens 965, and the like. An image pickup apparatus according to an aspect of the present invention and an operation method thereof can be applied to an element for image acquisition in the digital camera.

FIG. 17F is a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, a camera 939, and the like. The display unit 932 includes a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 have flexibility and are excellent in wearability to the body. An image pickup apparatus according to an aspect of the present invention and an operation method thereof can be applied to an element for image acquisition in the information terminal.

This embodiment can be appropriately combined with the description of other embodiments or examples.

In this embodiment, the relationship between the potential applied to the back gate of the OS transistor and the electrical characteristics of the OS transistor will be described. Specifically, as the electrical characteristics of the OS transistor, the drain current (Id) -gate voltage (Vg) characteristic of the OS transistor and the noise of the drain current of the OS transistor were evaluated. A semiconductor device analyzer manufactured by Keysight Technology was used to measure the Id-Vg characteristics.

The noise of the drain current of the OS transistor is a value obtained by _{standardizing the spectral density S Id} of the noise power of the drain current with the drain current Id _{obtained by using the 1 / f noise measurement system (S Id} / Id ² ). Can be evaluated by.

In this embodiment, a 1 / f noise measurement system manufactured by Keysight Technology Co., Ltd. was used to measure the noise of the drain current of the transistor. Keysight Technology B1500A was used for the semiconductor device analyzer, and Keysight Technology E5052B was used for the signal source analyzer. As the prober, SUMMIT 11000B-M manufactured by Cascade Microtech (with temperature control function (from 213K to 473K)) was used. The measurement was performed in a dark environment. The measurement range was within the voltage and current specification range (200V / 1A or 100V / 100mA) of the measuring device and the frequency measurement range (1Hz to 100kHz).

Next, the sample evaluated using the semiconductor parameter analyzer and the 1 / f noise measurement system will be described.

As the above sample, a sample having an OS transistor was prepared. A cross-sectional view of the OS transistor included in the sample is shown in FIG. The OS transistor can be applied to the transistor 105 described in the previous embodiment.

The transistor 111A shown in FIG. 18 is a modification of the transistor 111 shown in FIG. 11 (A). In the transistor 111A, the same reference numerals are added to the structures having the same functions as the structures constituting the transistor 111. Also in this item, as the constituent material of the transistor 111A, the material described in detail in the previous embodiment can be used.

The transistor 111A is different from the transistor 111 in that it does not have the oxide semiconductor layer 707. Further, it is different that the insulator 713 is provided on the conductor 705 and the insulator 714 is provided on the conductor 706. Further, it is different that the oxide layer 711 is provided under the conductor 705 and the oxide layer 712 is provided under the conductor 706. Further, the insulator on the conductor 535 has a laminated structure of the insulator 708 and the insulator 709.

In the transistor 111A, the semiconductor layer 710 is an oxide semiconductor layer having a region in which a channel is formed. Further, the insulator 708 and the insulator 709 function as a gate insulating film. Further, the insulator 713 and the insulator 714 preferably function as a barrier layer that suppresses the permeation of oxygen. Further, the oxide layer 711 and the oxide layer 712 preferably have a function of suppressing the permeation of oxygen.

In this embodiment, a laminated structure of titanium nitride, tungsten, and titanium nitride was used as the conductor 535. Further, hafnium oxide was used as the insulator 708, and silicon oxide was used as the insulator 709.

Further, as the semiconductor layer 710, a two-layer laminated structure was used. Metal oxidation formed with a film thickness of 5 nm using an oxide target of In: Ga: Zn = 1: 3: 4 [atomic number ratio] as the layer on the insulator 709 side of the semiconductor layer 710 by a sputtering method. I used a thing. As the oxide layer 711 side and the oxide layer 712 side of the semiconductor layer 710, an oxide target of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio] was used by a sputtering method at 15 nm. A metal oxide formed with the same thickness as the above was used.

Further, as the oxide layer 711 and the oxide layer 712, In-Ga-Zn oxide formed by a sputtering method was used. Further, as the conductor 705 and the conductor 706, tantalum nitride formed by the sputtering method was used. Further, as the insulator 713 and the insulator 714, a laminated structure of silicon nitride and silicon oxide was used.

Further, as the insulator 702, silicon oxide formed by the CVD method was used. Further, as the conductor 701, a laminated structure of titanium nitride and tungsten was used.

The design value of the channel length L and the design value of the channel width W of the OS transistor included in the sample are L / W = 360 nm / 360 nm.

The above is the description of the sample prepared in this example.

The Id-Vg characteristics of the OS transistor contained in the prepared sample were measured. For the measurement of Id-Vg characteristics, the drain potential Vd is 0.3V, the source potential Vs is 0V, the bottom gate potential Vbg is variable (in 1V increments from -2V to 3V), and the top gate potential Vg is -4. It was swept from 0V to 4.0V in 0.04V steps.

FIG. 19 shows the measurement results of the Id-Vg characteristics of the OS transistor of the sample. In FIG. 19, the horizontal axis is the top gate potential Vg [V]. The vertical axis is the drain current Id [A].

As shown in FIG. 19, when Vbg is in the range of -2V to 3V, the ratio of the value of the drain current when the potential of + 3V is applied to the gate to the value of the drain current when the potential of -3V is applied to the gate. The (on / off ratio) was ¹⁰⁶ or more.

Here, the threshold voltage when the potential of X [V] is applied to Vbg is expressed _{as Vth Vbg = X.} As shown in FIG. 19, when Vbg was in the range of -2V to 3V, Vth _{Vbg = X} was a value in the range of 1.69V to -1.62V. At this time, _{the drain current when the potential of (Vth Vbg = X} + 2) [V] is applied to the gate with respect to the value of the drain current when the potential _{of (Vth Vbg = X-2) [V] is applied to the gate.} the ratio of the value (on / off ratio) was 10 ⁶ or more. _{Further, the drain current value when the potential of (Vth Vbg = X} +1) [V] is applied to the gate with respect to the value of the drain current when the potential of (Vth _{Vbg = X -1) [V] is applied to the gate.} the ratio of the value (on / off ratio) was 10 ⁶ or more.

Therefore, it was confirmed that in the OS transistor of the sample of this example, the on / off ratio can be secured in the range of Vbg of -2V to 3V, and normal switching characteristics can be obtained.

Next, the result of evaluating the noise of the drain current of the OS transistor of the sample using the 1 / f noise measurement system will be described.

20 (A) and 20 (B) show the results obtained by using the 1 / f noise measurement system in the OS transistor included in the sample. When using the 1 / f noise measurement system, Vbg was set to -2V, -1V, 0V, 1V, 2V, or 3V.

In FIG. 20A, the horizontal axis is the noise frequency f (Frequency) [Hz], and the range of the noise frequency f is 10 Hz or more and 1000 Hz or less. _{The vertical axis is a value SId} / Id ² [/ Hz] obtained by normalizing the spectral density of the noise power of the drain current with the drain current.

In FIG. 20B, the horizontal axis is the voltage Vbg [V] applied to the back gate. _{The vertical axis is a value SId} / Id ² [/ Hz] obtained by normalizing the spectral density of the noise power of the drain current with the drain current when the noise frequency f is 100 Hz.

From FIG. 20A, it can be seen that the frequency dependence of noise is approximately proportional to 1 / f at frequencies in the range of 10 Hz to 1000 Hz.

From FIGS. 20 (A) and 20 (B), when Vbg is 0 V and its vicinity, the larger the Vbg, the more the spectral density of the noise power of the drain current is normalized by the drain current (S _Id / Id ² ). Tended to be smaller. _{Further, the value (S Id} / Id ² ) obtained by normalizing the spectral density of the noise power of the drain current when a potential of 0 V or more is applied to Vbg is higher than that when a negative potential is applied to Vbg. It was suggested that it was small.

The OS transistor described in this embodiment can reduce 1 / f noise by controlling the potential applied to the back gate.

This embodiment can be carried out in appropriate combination with the configurations described in other embodiments and examples.

103 Conductor 103a Transistor 103b Transistor 104 Transistor 104a Transistor 105 Transistor 106 Transistor 106a Transistor 106b Transistor 108 Capsule 111 Transistor 111a Transistor 111b Transistor 111A Transistor 112 Capitol 115 Transistor 116 Transistor 117 Transit 121 Wiring 122 Wiring 123 Wiring 126 Wiring 127 Wiring 128 Wiring 131 Conductive Layer 132 Conductive layer 133 Conductive layer 134 Conductive layer 135 Conductive layer 136 Conductive layer 137 Conductive layer 138 Conductive layer 139 Conductive layer 141 Conductive layer 142 Conductive layer 143 Conductive layer 151 Wiring 152 Wiring 153 Wiring 154 Wiring 201 Layer 202 Layer 203 Layer 204 205 Layer 211 Silicon substrate 212 Insulation layer 213 Insulation layer 214 Insulation layer 215 Insulation layer 216 Insulation layer 217 Insulation layer 218 Insulation layer 219 Insulation layer 221 Insulation layer 222 Insulation layer 223 Insulation layer 224 Insulation layer 225 Insulation layer 226 Insulation layer 227 Insulation layer 227 228 Insulation layer 229 Insulation layer 231 Insulation layer 232 Insulation layer 233 Insulation layer 234 Insulation layer 235 Insulation layer 236 Insulation layer 237 Insulation layer 240 Photoelectric conversion device 241 Insulation layer 242 Insulation layer 243 P-type region 244 n-type region 245 Insulation layer 246 Insulation Layer 249 Insulation layer 250 Optical conversion layer 251 Light-shielding layer 255 Microlens array 311 Read circuit 312 Low driver 313 Column driver 321 Memory circuit 321a Memory cell 321aA Memory cell 321aB Memory cell 321aC Memory cell 321aD Memory cell 331 Pixel circuit 332 Drive circuit 351 Wiring 352 Wiring 353 Wiring 354 Wiring 355 Wiring 400 CDS Circuit 401 Resistance 402 Capsirator 403 Transistor 404 Transistor 405 Capitol 410 A / D Converter 421 Insulation layer 422 Insulation layer 423 Insulation layer 424 Insulation layer 425 Insulation layer 426 Insulation layer 427 Insulation layer 535 Conductor 545 Semiconductor layer 546 Insulation layer 610 Package substrate 611 Package substrate 620 Cover glass 621 Lens cover 630 Adhesive 635 Lens 640 Bump 641 Land 650 Image sensor chip 651 Image sensor chip 660 Electrode Pad 661 Electrode Pad 670 Wire 671 Wire 690 IC Chip 701 Conductor 702 Insulator 703 Source Region 704 Drain Region 705 Conductor 706 Conductor 707 Oxide Semiconductor Layer 708 Insulator 709 Insulator 710 Semiconductor Layer 711 Oxide Layer 712 Oxide layer 713 Insulation 714 Insulation 911 Housing 912 Display 913 Speaker 919 Camera 932 Display 933 Housing and wristband 939 Camera 951 Support 952 Camera unit 953 Protective cover 961 Housing 962 Shutter button 963 Microphone 965 Lens 967 Light emitting part 971 Housing 972 Housing 973 Display unit 974 Operation key 975 Lens 976 Connection part 977 Speaker 978 Microphone 981 Housing 982 Display unit 983 Operation button 984 External connection port 985 Speaker 986 Microphone 987 Camera

Claims (15)

It has a photoelectric conversion device, a first transistor to a fourth transistor, a capacitor, a first wiring, and a second wiring.
The second transistor has a first gate, a second gate, and a first semiconductor layer.
The third transistor has a third gate, a fourth gate, and a second semiconductor layer.
Each of the first semiconductor layer and the second semiconductor layer is an oxidation having indium, the element M (M is one or more of gallium, aluminum, yttrium, and tin), and zinc. It is a layer of material,
One terminal of the photoelectric conversion device is electrically connected to one of the source and drain of the first transistor.
The other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one electrode of the capacitor, and the third gate of the third transistor. ,
One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor.
The second gate is electrically connected to the first wire to which the first potential is applied.
The fourth gate is electrically connected to the second wire to which a second potential larger than the first potential is given.
Imaging device. In claim 1,
^{The second transistor has an on / off ratio of 106} or more in a state where the first potential is applied to the second gate.
^{The third transistor has an on / off ratio of 106} or more in a state where the second potential is applied to the fourth gate.
Imaging device. In claim 1,
The second transistor applies a potential of -3V to the first gate in a state where the first potential is applied to the second gate, the drain potential is 0.3V, and the source potential is 0V. to the value of the drain current at the time of applying, the ratio of the value of the drain current when a potential is applied to the first gate + 3V is 10 ⁶ or more,
The third transistor applies a potential of -3V to the third gate in a state where the second potential is applied to the fourth gate, the drain potential is 0.3V, and the source potential is 0V. to the value of the drain current at the time of applying, the ratio of the value of the drain current when a potential is applied to the third gate + 3V is 10 ⁶ or more,
Imaging device. In any one of claims 1 to 3,
The second transistor and the third transistor are formed on the same insulating layer.
Imaging device. In any one of claims 1 to 4,
Each of the first transistor and the fourth transistor has a metal oxide in the channel forming region.
The metal oxide has indium, the element M (where M is one or more of gallium, aluminum, yttrium, and tin), and zinc.
Imaging device. It has a photoelectric conversion device, a first transistor to a fourth transistor, a capacitor, and a second wiring.
The third transistor has a third gate, a fourth gate, and a second semiconductor layer.
The second semiconductor layer is an oxide layer having indium, the element M (M is one or more of gallium, aluminum, yttrium, and tin), and zinc.
One terminal of the photoelectric conversion device is electrically connected to one of the source and drain of the first transistor.
The other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one electrode of the capacitor, and the third gate of the third transistor. ,
One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor.
The fourth gate is electrically connected to the second wiring to which a potential of 0 V or more and 3 V or less is applied.
Imaging device. It has a photoelectric conversion device, a first transistor to a fourth transistor, a capacitor, a second wiring, and a third wiring.
The third transistor has a third gate, a fourth gate, and a second semiconductor layer.
The second semiconductor layer is an oxide layer having indium, the element M (M is one or more of gallium, aluminum, yttrium, and tin), and zinc.
One terminal of the photoelectric conversion device is electrically connected to one of the source and drain of the first transistor.
The other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one electrode of the capacitor, and the third gate of the third transistor. ,
One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor.
The other terminal of the photoelectric conversion device is electrically connected to the third wiring to which a third potential is applied.
The fourth gate is electrically connected to the second wire to which a second potential larger than the third potential is given.
Imaging device. In claim 7,
^{The third transistor has an on / off ratio of 106} or more in a state where the second potential is applied to the fourth gate.
Imaging device. In claim 7,
The third transistor applies a potential of -3V to the third gate in a state where the second potential is applied to the fourth gate, the drain potential is 0.3V, and the source potential is 0V. to the value of the drain current at the time of applying, the ratio of the value of the drain current when a potential is applied to the third gate + 3V is 10 ⁶ or more,
Imaging device. In any one of claims 6 to 9,
Each of the first transistor, the second transistor, and the fourth transistor has a metal oxide in the channel forming region.
The metal oxide has indium, the element M (where M is one or more of gallium, aluminum, yttrium, and tin), and zinc.
Imaging device. In any one of claims 1 to 10.
The photoelectric conversion device is a photodiode having silicon in the photoelectric conversion layer.
Imaging device. It has a photoelectric conversion device, a first transistor to a fourth transistor, a capacitor, and an output line.
The second transistor has a first gate, a second gate, and a first semiconductor layer.
The third transistor has a third gate, a fourth gate, and a second semiconductor layer.
Each of the first semiconductor layer and the second semiconductor layer is an oxidation having indium, the element M (M is one or more of gallium, aluminum, yttrium, and tin), and zinc. It is a layer of material,
One terminal of the photoelectric conversion device is electrically connected to one of the source and drain of the first transistor.
The other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one electrode of the capacitor, and the third gate of the third transistor. ,
One of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor.
The other of the source and drain of the fourth transistor is a method of driving an image pickup apparatus electrically connected to the output line.
During the period of outputting the imaging data corresponding to the illuminance of the light applied to the photoelectric conversion device to the output line, the first potential is applied to the second gate, and the second potential is larger than the first potential. Apply the potential of
How to drive the image pickup device. In claim 12,
The second transistor and the third transistor are formed on the same insulating layer.
How to drive the image pickup device. In claim 12 or 13,
Each of the first transistor and the fourth transistor has a metal oxide in the channel forming region.
The metal oxide has indium, the element M (where M is one or more of gallium, aluminum, yttrium, and tin), and zinc.
How to drive the image pickup device. In any one of claims 12 to 14,
The photoelectric conversion device is a photodiode having silicon in the photoelectric conversion layer.
How to drive the image pickup device.

Images