JP7273611B2 - Imaging device - Google Patents

Description

One aspect of the present invention relates to an imaging method or an imaging device. One aspect of the present invention relates to a microscope having an imaging function.

Note that one embodiment of the present invention is not limited to the above technical field. Technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input/output devices, and driving methods thereof. , or methods for producing them, can be mentioned as an example. A semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

An optical microscope is known as means for observing an object by enlarging it. An optical microscope generally includes a slide glass on which an object is placed, a light-emitting device for illuminating the object, an optical system for forming an observation image, and the like.

For example, Patent Literature 1 discloses a microscope having a stage, an imaging optical system, and a surface emitting illumination device.

JP-A-2002-221664

A conventional optical microscope has a mechanism for forming an image using an optical system such as a lens, so there is a problem that increasing the resolution results in a narrower field of view. Further, since the optical microscope uses an optical system, image distortion occurs due to lens aberration. In addition, when observing at a different magnification, it is necessary to use an optical system with a zoom function or switch to a lens with a different magnification.

An object of one embodiment of the present invention is to provide an imaging method or an imaging device that achieves both high resolution and a wide field of view. Another object is to provide an imaging device with a simplified device configuration. Another object is to provide an imaging device that can be realized at low cost. Another object is to provide a novel imaging method, an imaging device, or a microscope.

The description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from descriptions in the specification, drawings, claims, and the like.

One aspect of the present invention is a method for imaging an object to be observed disposed between a light-emitting surface and a light-receiving surface, wherein the light-emitting surface, the light-receiving surface, and the object to be observed are shielded from external light, The surface has a plurality of light-emitting regions arranged in a matrix, and the plurality of light-emitting regions are sequentially caused to emit light, and in synchronization with the light emission of the light-emitting regions, data on the amount of light received by the light-receiving surface is sequentially obtained. be.

Another aspect of the present invention is a method for imaging an object to be observed disposed between a light-emitting surface and a light-receiving surface, wherein the light-emitting surface, the light-receiving surface, and the object to be observed are shielded from external light. The light-emitting surface has a plurality of light-emitting regions arranged in a matrix, and the plurality of light-emitting regions are sequentially caused to emit light. data is mapped based on the arrangement of a plurality of light emitting regions to generate a captured image.

Another embodiment of the present invention is an imaging device including a planar light emitting device, a photoelectric conversion device, a light shielding member, and a stage. A planar light-emitting device has a plurality of light-emitting elements arranged in a matrix. A photoelectric conversion device has a light receiving surface. The stage is translucent and has a function of supporting an object to be observed. A light-emitting surface and a light-receiving surface of the planar light-emitting device are provided facing each other with a stage interposed therebetween. A light shielding member is provided to cover the light receiving surface, the light emitting surface, and the stage. A planar light emitting device has a function of individually causing a plurality of light emitting elements to emit light. A photoelectric conversion device has a function of outputting data on the amount of light received by a light-receiving surface in synchronization with light emission of a light-emitting element.

Another embodiment of the present invention is an imaging device that includes a planar light emitting device, a photoelectric conversion device, a light shielding member, a stage, and a controller. A planar light-emitting device has a plurality of light-emitting elements arranged in a matrix. A photoelectric conversion device has a light receiving surface. The stage is translucent and has a function of supporting an object to be observed. A light-emitting surface and a light-receiving surface of the planar light-emitting device are provided facing each other with a stage interposed therebetween. A light shielding member is provided to cover the light receiving surface, the light emitting surface, and the stage. The control unit has a function of controlling the planar light emitting device to sequentially emit light from the plurality of light emitting elements, and a photoelectric conversion device to output data on the amount of light received by the light receiving surface in synchronization with the light emission of the light emitting elements. and a function of generating a captured image by mapping the data based on the arrangement of the light emitting elements.

Moreover, in the above, it is preferable to have an image display device. At this time, the control unit preferably has a function of outputting the captured image to the image display device. Also, the image display device preferably has a function of displaying the captured image.

Moreover, in the above, the light-emitting element is preferably an organic EL element, an inorganic EL element, or a light-emitting diode.

Moreover, in the above, the photoelectric conversion device is preferably an illuminometer or a luminance meter.

Moreover, in the above, the arrangement interval of the plurality of light emitting elements is preferably 0.1 μm or more and 100 μm or less.

Moreover, in the above, it is preferable that the surface of the planar light emitting device also serves as a stage.

Moreover, in the above, it is preferable to have a position adjusting mechanism. The position adjustment mechanism preferably has a function of relatively moving the planar light emitting device and the stage in a direction parallel to the light emitting surface with a positional accuracy smaller than the arrangement interval of the plurality of light emitting elements.

According to one aspect of the present invention, it is possible to provide an imaging method or imaging apparatus that achieves both high resolution and a wide field of view. Alternatively, an imaging device with a simplified device configuration can be provided. Alternatively, an imaging device that can be realized at low cost can be provided. Alternatively, a novel imaging method, imaging device, or microscope can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from descriptions in the specification, drawings, claims, and the like.

1A and 1B are diagrams for explaining an imaging device and an imaging method; FIG. A configuration example of an imaging device. 1A and 1B are diagrams for explaining an imaging device and an imaging method; FIG. A configuration example of a planar light emitting device. A configuration example of a planar light emitting device. The figure explaining the imaging method. The figure explaining the imaging method. A configuration example of a planar light emitting device. A configuration example of a display device. A configuration example of a display device. A configuration example of a display device. A configuration example of a display device. A configuration example of a display device. 4 is a captured image according to Example 1. FIG. 4 is a captured image according to Example 1. FIG. (A) A microscope image of an object to be observed, and (B) a captured image according to Example 2. FIG. (A) A schematic diagram of an observed object, (B) a microscope image of an observed object, and (C) a captured image according to Example 2. FIG.

Hereinafter, embodiments will be described with reference to the drawings. Those skilled in the art will readily appreciate, however, that the embodiments can be embodied in many different forms and that various changes in form and detail can be made without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

In the configuration of the invention to be described below, the same reference numerals are used in common for the same parts or parts having similar functions in different drawings, and repeated description thereof will be omitted. Moreover, when referring to similar functions, the hatch patterns may be the same and no particular reference numerals may be attached.

In each drawing described in this specification, the size of each component, the thickness of layers, or regions may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

Note that ordinal numbers such as “first” and “second” in this specification and the like are used to avoid confusion of constituent elements, and are not numerically limited.

A transistor is a type of semiconductor element, and can achieve current or voltage amplification, switching operation for controlling conduction or non-conduction, and the like. A transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

(Embodiment 1)
In this embodiment, an imaging method and an imaging device of one embodiment of the present invention will be described. The imaging method and imaging apparatus exemplified below can be used as a microscope.

One embodiment of the present invention includes a planar light-emitting device having a planar light-emitting surface and a photoelectric conversion device having a light-receiving surface. The light-emitting surface and the light-receiving surface are provided to face each other with an object to be observed (including an object to be observed, a sample, a specimen, etc.) interposed therebetween. At least the light receiving surface, the light emitting surface, and the object to be observed are covered with a light shielding member (light shielding member) or the like so as to be shielded from external light.

A planar light-emitting device has a plurality of light-emitting regions arranged in a matrix, and the plurality of light-emitting regions constitute a light-emitting surface. A planar light-emitting device can drive each light-emitting region individually. In particular, it is preferable that driving (also referred to as dot-sequential driving) in which a plurality of light-emitting regions sequentially emit light is possible.

A photoelectric conversion device can convert light captured by a light receiving surface into an electric signal and output the electric signal. The photoelectric conversion device preferably has a function of outputting data on the amount of light corresponding to the amount of light captured by the light receiving surface.

An imaging method will be described. With the object to be observed placed between the light-emitting surface and the light-receiving surface, first, one of the plurality of light-emitting regions of the light-emitting surface is caused to emit light (turn on), and the light-receiving surface captures the light in synchronization with this. Get the data of the amount of light. Subsequently, a different light-emitting region is caused to emit light, and light amount data is obtained in the same manner as described above. This series of operations is performed for all light-emitting regions provided in the observation area. An observation image can be obtained by mapping the obtained light quantity data based on the arrangement of the corresponding light emitting regions.

Here, when there is no object to be observed on the optical path of the light from the light emitting region, the light directly enters the light receiving surface from the light emitting region. On the other hand, when an object to be observed exists on the optical path of the light from the light emitting region, the light transmitted through the object to be observed enters the light receiving surface. When the object to be observed is light-shielding, almost no light enters the light-receiving surface.

Thus, according to one aspect of the present invention, a transmission image or contour image of an object to be observed can be observed.

The light-emitting region of the planar light-emitting device can take at least two states, a light-emitting state and a non-light-emitting state. Further, the light-emitting region may be configured so that the light-emitting brightness can be adjusted. In addition, it is preferable that the contrast ratio between the luminous state and the non-luminous state of the luminous region is as high as possible.

One or more light-emitting elements are preferably provided in one light-emitting region. As the light-emitting element, it is preferable to use a self-luminous electroluminescence element such as an organic EL (Electro Luminescence) element, an inorganic EL element, or a light-emitting diode. Such a light-emitting element can reduce the luminance as much as possible when no electric field is applied. Therefore, when one light-emitting region is caused to emit light, the influence of light leaking from other light-emitting regions in the non-light-emitting state can be extremely reduced, so that a high-contrast observation image can be obtained.

The element provided in the light-emitting region is not limited to the light-emitting element described above, and an optical element capable of controlling the light-emitting state and the non-light-emitting state by controlling the reflectance and transmittance of light can also be used. For example, a liquid crystal element or a shutter type MEMS (Micro Electro Mechanical Systems) element may be used.

Alternatively, the planar light-emitting device may be configured by using the light-emitting surface (one end surface) of the optical fiber as the light-emitting region and arranging them in a matrix. In this case, the planar light-emitting device may include a plurality of optical fibers and a light-emitting device that sequentially irradiates light onto the other end surfaces of the plurality of optical fibers.

The higher the density of the light-emitting regions arranged in a matrix, the higher the resolution of the observed image. For example, the arrangement interval (also referred to as the arrangement pitch) of the light emitting regions is 0.1 μm or more and 1 mm or less, preferably 0.1 μm or more and 500 μm or less, more preferably 0.1 μm or more and 100 μm or less, further preferably 0.1 μm or more and 50 μm or less. can be The fineness of the light-emitting surface can be set according to the size of the object to be observed, the width of the observation area (observation field of view), and the like. For example, the array pitch of the light-emitting regions is 1/30 or less, preferably 1/50 or less, more preferably 1/100 or less with respect to the size (diagonal length) of the region to be observed, It can be 1/10000 or more.

A display panel having pixels arranged in a matrix may be used as the planar light emitting device. A pixel can be configured to include one or more of the light-emitting elements or optical elements described above. As the display panel, a passive matrix display panel or an active matrix display panel can be applied. An active matrix display panel has a selection transistor in a pixel. In particular, it is preferable to use a transistor including an oxide semiconductor as the selection transistor because leakage current in a non-selected state can be significantly reduced and contrast can be improved.

As the photoelectric conversion device, a photometer (also referred to as a photometer) capable of converting photons captured by a light receiving surface into an electric signal by utilizing the photoelectric effect can be used. For example, it is preferable to use a photometer having a photodiode, a photoresistor, or the like, because the size of the device can be easily reduced. As the photometer, an illuminometer (also referred to as a photometer) capable of measuring illuminance can be preferably used. As the illuminometer, an illuminometer that can measure the spectrum and color of light, such as a spectral irradiance meter, a color illuminometer, and a color rendering illuminometer, may be used. Alternatively, a luminance meter for measuring luminance may be used as the photometer. As a luminance meter, a spectral radiance meter, a color luminance meter, or the like may be used.

Further, a stage for placing an object to be observed may be provided between the light receiving surface and the light emitting surface. The stage is made of a member having translucency. For example, it is preferable to use glass or the like because it has excellent translucency and chemical resistance and is less likely to be scratched. Since an observed image with higher resolution can be obtained as the distance between the object to be observed and the light emitting surface is smaller, it is preferable to reduce the thickness of the stage and provide it closer to or in contact with the light emitting surface. Alternatively, the surface (that is, the light-emitting surface) of the planar light-emitting device may also serve as a stage, and the object to be observed may be placed on the surface.

A more specific example will be described below with reference to the drawings.

[Configuration example 1 of imaging device]
FIG. 1A is a schematic diagram of the imaging device 10. FIG. The imaging device 10 has a planar light emitting device 11 , a photoelectric conversion device 12 , a light blocking member 13 and a stage 14 .

The planar light emitting device 11 has a plurality of light emitting regions 21 arranged in a matrix. The light emitting region 21 can emit light toward the photoelectric conversion device 12 side. Therefore, the surface of the planar light emitting device 11 on the photoelectric conversion device 12 side corresponds to the light emitting surface 11a.

The photoelectric conversion device 12 has a light receiving surface 12a. The photoelectric conversion device 12 is provided so that the light receiving surface 12a faces the light emitting surface 11a.

The stage 14 is arranged between the light emitting surface 11a and the light receiving surface 12a. FIG. 1A shows an example in which an object 30 to be observed is arranged on the stage 14 . The stage 14 has translucency to at least the light emitted from the light emitting region 21 . The smaller the distance between the light emitting surface 11a and the object 30 to be observed, the higher the resolution of the observed image. It is preferable to provide the stage 14 so that the In particular, the smaller the distance between the stage 14 and the light-emitting surface 11a side, the better. Alternatively, they may be in contact with each other. Further, the thinner the stage 14, the better. For example, it can be 2 mm or less, preferably 1 mm or less.

The upper surface of the planar light emitting device 11 (that is, the light emitting surface 11 a ) may also serve as the stage 14 . That is, a configuration may be adopted in which the observed object 30 is arranged in contact with the surface of the planar light emitting device 11 without providing the stage 14 .

The light shielding member 13 is provided so as to cover the planar light emitting device 11 , the photoelectric conversion device 12 and the stage 14 . Since external light is blocked by the light shielding member 13, the photoelectric conversion device 12 can receive only the light caused by the light emission of the light emitting region 21, and a captured image in which noise caused by the external light is reduced can be obtained. can be done.

The inner wall of the light shielding member 13 may be a black member that does not reflect light, or may be a member that isotropically diffuses light. When the inner wall of the light shielding member 13 is black, the light receiving surface 12a and the light emitting surface 11a are arranged parallel to each other as shown in FIG. , the light-receiving sensitivity can be made constant. Further, at this time, it is more preferable to make the area of the light receiving surface 12a larger than the area of the light emitting surface 11a. On the other hand, when the inner wall of the light shielding member 13 is a member that isotropically diffuses light, the inner wall of the light shielding member 13 can function as an integrating sphere. etc. are not limited, and the light receiving surface 12a may be arranged anywhere as long as it is inside surrounded by the light shielding member 13 .

FIG. 1A schematically shows direct light 31 and transmitted light 32 . When the observed object 30 is not positioned between the light emitting region 21 and the light receiving surface 12a, the light emitted from the light emitting region 21 reaches the light receiving surface 12a directly as light 31. FIG. On the other hand, when the observed object 30 is positioned between them, the transmitted light 32 transmitted through the observed object 30 reaches the light receiving surface 12a. In addition, when the observed object 30 has light blocking properties, the light from the light emitting region 21 is blocked by the observed object 30 and does not reach the light receiving surface 12a.

The light received by the light-receiving surface 12a is mainly the direct light 31 or the transmitted light 32, but in addition to this, for example, diffused light from the observed object 30, reflected light from the inside or surface of the observed object 30, or , secondary reflected light in which these diffused light and reflected light are reflected on the surface of the stage 14 and the planar light emitting device 11, and the like. If the sharpness of the observed image is reduced due to these effects, the observed image may be subjected to image correction to remove background noise.

[Example of imaging method]
Next, an example of an imaging method is described with reference to FIGS. 1B1 to 1B4 and 1C.

FIG. 1B1 schematically shows a state in which a columnar observed object 30 is arranged on the light emitting surface 11a.

The light emitting surface 11a has m×n light emitting regions 21 arranged in a matrix, m in the X direction and n in the Y direction (m and n are independently integers of 2 or more). Here, in FIG. 1B1 and the like, in order to distinguish each light emitting region, the light emitting region 21 (i, j) (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less) is described. .

Imaging is performed by sequentially causing the light emitting regions 21 (i, j) to emit light and acquiring data of the amount of light received by the light receiving surface 12a in synchronization with the light emission (hereinafter also referred to as light amount data). One captured image can be obtained when the acquisition of the light amount data is completed for all the light emitting regions 21(i, j) within the observation range.

For example, the light quantity data is acquired when the light emitting region 21 (1, 1) located at the upper leftmost position of the light emitting surface 11a in FIG. 1B1 is caused to emit light. Subsequently, as shown in FIG. 1(B2), light amount data when the adjacent light emitting region 21 (2, 1) is caused to emit light is acquired. Since neither the light emitting region (1, 1) nor the light emitting region (2, 1) overlaps the observed object 30, the direct light 31 is mainly received.

FIG. 1(B3) shows a case where the light emitting region 21 (x, y) overlapping the observed object 30 is caused to emit light. Light emitted from the light emitting region 21 (x, y) passes through the observed object 30 and is received as transmitted light 32 .

FIG. 1B4 shows the case where the light emitting region 21(m,n) diagonally opposite to the light emitting region 21(1,1) is caused to emit light.

The order in which the light-emitting regions 21 (i, j) are made to emit light is not particularly limited, but the light-emitting regions (for example, light-emitting region (1, 1)) positioned at the end of the row positioned at the end of the observation range are sequentially emitted. is preferred.

In this way, it is possible to obtain m×n pieces of light amount data corresponding to each light emitting region 21 . A captured image can be generated by mapping and visualizing the m×n light amount data based on the arrangement of the light emitting regions 21 . More specifically, two-dimensional image data can be generated by replacing the data values of the light intensity data with gradation values.

FIG. 1C shows an example of a captured image obtained by the imaging method of one embodiment of the present invention. The captured image 40 has m×n pieces of pixel data 22 (pixel data 22(1,1) to pixel data 22(m,n)). Here, one pixel data 22 (i, j) corresponds to one light emitting area 21 (i, j) of the planar light emitting device 11 .

In FIG. 1C, the outline of the observed object 30 is indicated by a dashed line at the corresponding position on the captured image 40 . A pixel having a larger area overlapping with the observed object 30 is shown to be darker (with a denser hatching pattern).

In the captured image 40 , one pixel data 22 corresponds to one light emitting area 21 , so length measurement can be performed using the captured image 40 . For example, the length of the range indicated by the arrows in FIG. 1(C) corresponds to 10 pieces of pixel data 22, so it can be easily understood that it corresponds to 10 times the length of the arrangement interval of the light emitting regions 21. . Similarly, not only the length but also the area can be easily calculated from the number of pixel data 22 present in a predetermined range.

In addition, although the method of causing one light-emitting region 21 to emit light in order is shown here, a plurality of light-emitting regions 21 may emit light at the same time. For example, when the definition of the light emitting surface 11a is too high for the size of the object 30 to be observed, or when a high-resolution observation image is not required, a method of simultaneously emitting light from a plurality of adjacent light emitting regions may be used. At this time, by making the number of pixels in the X direction and the Y direction the same, such as 2×2, 3×3, etc., it is possible to prevent the observed image from being distorted.

Also, when it is desired to obtain a moving image instead of a still image, the moving image can be obtained by repeating the series of operations described above.

In addition, it is not necessary to sequentially emit light from all the light-emitting regions 21 of the planar light-emitting device 11, and it is sufficient to sequentially light-emit only the light-emitting regions 21 positioned within the desired observation range to obtain light amount data. For example, only the light-emitting region 21 in the range including at least part of the observed object 30 can be caused to emit light.

[Configuration example 2 of imaging device]
A more specific configuration example of the imaging apparatus will be described below.

FIG. 2A is a block diagram of the imaging device 10A. The imaging device 10A has a planar light emitting device 11, a photoelectric conversion device 12, a light blocking member 13, a control section 51, a timing control section 52, an AD conversion section 53, and the like.

The timing control unit 52 has a function of generating a drive signal for synchronously driving the planar light emitting device 11 and the photoelectric conversion device 12 and outputting it to the planar light emitting device 11 and the photoelectric conversion device 12 .

The AD conversion unit 53 has a function of converting an analog signal output from the photoelectric conversion device 12 into a digital signal including light amount data and outputting the digital signal to the control unit 51 .

The control section 51 has a function of controlling the operation of the timing control section 52 . The control unit 51 also has a function of generating a captured image by mapping a plurality of light amount data input from the AD conversion unit 53 based on the arrangement of the light emitting areas of the planar light emitting device 11 as well. A computer can be preferably used as the control unit 51 .

Also, the control unit 51 may have a storage unit 54 . The control unit 51 can write data of the generated captured image to the storage unit 54 and read the data from the storage unit 54 .

FIG. 2B shows a configuration example of an imaging device 10B including a display device 55. As shown in FIG. The display device 55 can display video data including captured images output from the control unit 51 .

Here, a configuration example of the planar light emitting device 11 is shown in FIG. 2(C). The planar light-emitting device 11 has a light-emitting portion 61 , a drive circuit 62 , a drive circuit 63 , a plurality of pixels 65 , a plurality of wirings 66 and a plurality of wirings 67 .

Driving signals are supplied to the driving circuit 62 and the driving circuit 63 from the timing control section 52, respectively. For example, the drive circuit 62 functions as a source line drive circuit, and the drive circuit 63 functions as a gate line drive circuit.

A plurality of wirings 66 are electrically connected to the drive circuit 62 and function as source lines. A plurality of wirings 67 are electrically connected to the drive circuit 63 and function as gate lines. Pixel 65 is electrically connected to one wiring 66 and one wiring 67 .

With such a configuration, the pixels 65 can be driven individually. For example, when the pixels 65 have light-emitting elements, the planar light-emitting device 11 can be driven so that the light-emitting elements sequentially emit light.

[Modification]
A configuration example of an imaging apparatus that is partially different from the above will be described below.

FIG. 3A shows a configuration example of the imaging device 10a. The imaging device 10a differs from the imaging device 10 mainly in that it has a position adjustment mechanism 16. As shown in FIG.

The position adjustment mechanism 16 has a function of relatively moving the planar light emitting device 11 and the stage 14 in a direction parallel to the light emitting surface 11a.

The planar light emitting device 11 is fixed on the upper surface of the position adjusting mechanism 16 . In FIG. 3A, the position adjustment mechanism 16 has a dial 16a for adjusting the position in the X direction and a dial 16b for adjusting the position in the Y direction. Note that the position adjustment mechanism 16 may have a function of adjusting the position in the height direction. Moreover, although an example having the dials 16a and 16b is shown here, a configuration in which a motor, a drive circuit, etc. are provided and electrical control is possible may be employed.

Here, it is preferable that the position adjusting mechanism 16 can control the relative positions of the planar light emitting device 11 and the stage 14 with positional accuracy smaller than the arrangement interval of the plurality of light emitting regions 21 of the planar light emitting device 11 .

An example of an imaging method using the imaging apparatus 10a will be described below with reference to FIGS. 3B1 to 3B4 and 3C.

FIG. 3B1 schematically shows the relative positions of the stage 14 and the plurality of light emitting regions 21. As shown in FIG. Also, the object to be observed 30 placed on the stage 14 is indicated by a dashed line. Here, for the sake of clarity, the number of light emitting regions 21 is clearly shown as five in both the X direction and the Y direction.

First, in the state shown in FIG. 3B1, the first imaging is performed in the same manner as in the imaging method example described above.

Subsequently, as shown in FIG. 3B2, the position adjustment mechanism 16 is used to shift the light emitting area of the planar light emitting device 11 in the Y direction, and the second imaging is performed. Here, when the arrangement interval of the light-emitting regions 21 is p, imaging is performed in a state shifted by half the distance (distance p/2).

Subsequently, as shown in FIG. 3(B3), the third imaging is performed by shifting the distance p/2 in the X direction from the initial state (the state of FIG. 3(B1)). Finally, as shown in FIG. 3B4, the fourth imaging is performed by shifting p/2 in each of the X and Y directions from the initial state.

As described above, four captured images can be obtained. These four captured images are captured images in a state shifted by half the array interval p of the light emitting regions 21 . Therefore, by calculating the difference between these four captured images, it is possible to generate a captured image with twice the resolution.

FIG. 3C shows an example of a captured image 40a obtained by the imaging method illustrated here. The captured image 40a has 2m×2n pieces of pixel data (pixel data 22(1,1) to pixel data (2m,2n)). That is, the captured image 40a is an image whose resolution is doubled while the imaging range remains the same as compared with the captured image 40 shown in FIG. 1(C). Further, this also doubles the resolution, so that the accuracy of the length and area that can be calculated from the number of pixel data 22 can be improved.

The above is the description of the modification.

[Configuration Example of Planar Light Emitting Device]
A configuration example of a planar light emitting device that can be used for an imaging device will be described below. Here, in particular, a configuration example of a pixel to which a light-emitting element is applied will be described.

[Configuration example 1]
FIG. 4A shows a configuration example of a pixel 65a that can be applied to the pixel 65 of the planar light emitting device 11 illustrated in FIG. 2C.

The pixel 65 a has a light emitting element 71 . The light emitting element 71 has an anode electrically connected to the wiring 66 and a cathode electrically connected to the wiring 67 . By arranging the pixels 65a in a matrix, a so-called passive matrix light emitting device can be realized. With such a structure, an extremely high-definition light-emitting device can be realized.

[Configuration example 2]
A pixel 65 b illustrated in FIG. 4B includes a light-emitting element 71 and a transistor 72 . The transistor 72 has a gate electrically connected to the wiring 67 , one of its source and drain electrically connected to the wiring 66 , and the other electrically connected to the anode of the light emitting element 71 . The cathode of the light emitting element 71 is electrically connected to a wiring to which a fixed potential is applied.

Transistor 72 functions as a select transistor. By arranging the pixels 65b in a matrix, a so-called active matrix light emitting device can be realized. With the structure shown in FIG. 4B, an extremely high-definition light-emitting device can be realized.

Since active matrix light-emitting devices are used in various electronic devices such as monitor devices, tablet terminals, and smartphones, they can also be used as planar light-emitting devices. For example, as an imaging device, an electronic device such as a tablet terminal or a smartphone can be attached so that its display surface faces the light receiving surface of the photoelectric conversion device, thereby realizing a simpler imaging device. .

[Configuration example 3]
A pixel 65 c illustrated in FIG. 4C includes a light-emitting element 71 , a transistor 72 , a transistor 73 , and a capacitor 74 . The transistor 72 has a gate electrically connected to the wiring 67 , one of the source and the drain electrically connected to the wiring 66 , and the other electrically connected to one electrode of the capacitor 74 and the gate of the transistor 73 . It is The transistor 73 has one of its source and drain electrically connected to the power supply line and the other electrically connected to the anode of the light emitting element 71 . The other electrode of the capacitor 74 and the cathode of the light emitting element 71 are electrically connected to wirings to which fixed potentials are applied.

Transistor 72 functions as a select transistor. The transistor 73 also functions as a driving transistor that controls the current flowing through the light emitting element 71 . The capacitive element 74 functions as a holding capacitor. By arranging the pixels 65c in a matrix, a so-called active matrix light emitting device can be realized.

Note that as shown in FIG. 4D, a structure in which the capacitor 74 is not provided can also be employed.

4B, 4C, and 4D, a semiconductor layer in which a channel is formed in at least one of the transistor 72 and the transistor 73 is formed with an oxide film. A transistor to which a semiconductor is applied is preferably used. A transistor including an oxide semiconductor can have much lower leakage current (off current) in a non-conducting state (off state) than a transistor including silicon or the like. It is possible to suitably prevent a decrease in contrast due to light emission.

Note that a transistor whose semiconductor layer is made of silicon (single crystal silicon, polycrystalline silicon, or amorphous silicon) can also be used as the transistor 72 or the transistor 73 . Further, in the case of a pixel including two or more transistors, a transistor using an oxide semiconductor and a transistor using silicon may be mixed.

Further, in FIGS. 4B, 4C, and 4D, an example in which an n-channel transistor is used is shown, but a p-channel transistor may be used. In the case of a pixel having two or more transistors, a structure in which an n-type transistor and a p-type transistor are mixed may be used.

Note that the structure of the pixel is not limited to the above, and the pixel may have enhanced functionality by adding a transistor, a capacitor, a resistor, a wiring, or the like as appropriate.

[Example of driving method]
An example of a method for driving the imaging device will be described below.

Here, as shown in FIG. 5, a planar light-emitting device in which 4×4 pixels 65 are arranged in a matrix will be described as an example.

Four wirings (wirings S1 to S4) functioning as source lines are connected to the driver circuit 62, and four wirings (wirings G1 to G4) functioning as gate lines are connected to the driver circuit 63. It is

Each pixel 65 is electrically connected to one of the wirings S1 to S4 and one of the wirings G1 to G4. For the pixel 65, the pixels 65a to 65d described above, or the like can be applied.

[Driving method example 1]
FIG. 6A is a timing chart relating to a driving method when the pixel 65a illustrated in FIG. 4A is applied to the pixel 65. FIG. The timing chart in FIG. 5A shows the wiring G1, the wiring G2, the wiring G3, the wiring G4, the wiring S1, the wiring S2, the wiring S3, the wiring S4, and the sampling SA from the top. Two types of potentials, a high potential and a low potential, are applied to each wiring. The width of the sampling SA in FIG. 6A corresponds to the sampling period of the data of the amount of light received by the photoelectric conversion device 12 .

First, in a period T1, a low potential is applied to the wiring G1, a high potential is applied to the wirings G2 to G4, and a high potential is sequentially applied to the wirings S1 to S4. A potential difference between the low potential applied to the wiring G1 and the high potential applied to the wiring S1 corresponds to the voltage for causing the light emitting element 71 to emit light. Accordingly, in the period T1, the four pixels 65 connected to the wiring G1 can emit light.

The sampling SA is performed in synchronization with signals supplied to the wirings S1 to S4. That is, one sampling is performed while one pixel 65 emits light.

Subsequently, in a period T2, a high potential is applied to the wiring G1, a low potential is applied to the wiring G2, and a high potential is applied to the wirings S1 to S4 in order in the same manner as described above, whereby four pixels connected to the wiring G2 are obtained. 65 can be illuminated in sequence. Also, sampling is performed in synchronization with light emission of the pixel 65 .

Similarly, in the period T3 and the period T4, the pixels 65 can be sequentially caused to emit light, and sampling can be performed in synchronization with the emission.

Sampling of all the pixels 65 is thus completed.

[Driving method example 2]
FIG. 6B is a timing chart of a driving method that can be used when the pixel 65b, the pixel 65c, or the pixel 65d illustrated in FIGS. . 6B is different from the case of FIG. 6A in that the signals supplied to the wirings G1 to G4 are signals in which the high potential and the low potential are switched.

In the period T1, four pixels 65 connected to the wiring G1 are selected by applying a high potential to the wiring G1. A high potential is sequentially applied to the wirings S1 to S4 in this state, so that the four pixels sequentially emit light.

[Driving method example 3]
FIG. 7A is a timing chart of a driving method that can be used when the pixel 65c or the pixel 65d illustrated in FIGS.

The example shown in FIG. 7A is an example in which one pixel emits light in one frame period (that is, period T1 to period T4).

In the period T1, a high potential is applied to the wirings G1 and S1, and a low potential is applied to the other wirings. Accordingly, the pixels 65 connected to the wiring G1 and the wiring S1 emit light.

In periods after the period T2, a low potential is applied to the wiring G1, a low potential is applied to the wiring S1, and a high potential is sequentially applied to the wirings G2 to G4. At this time, since data is held in the pixel 65, the pixel 65 is kept emitting light. Sampling is performed from period T1 to period T4.

As a result, the sampling period (exposure period) can be lengthened, so that a captured image with higher sensitivity can be obtained.

[Driving method example 4]
FIG. 7B is a timing chart of a driving method that can be used when the pixel 65 is the pixel 65b, the pixel 65c, or the pixel 65d illustrated in FIGS. .

FIG. 7B shows an example in which four pixels 65 connected to the wiring S1 are caused to emit light during one frame period.

Here, each of the periods T1 to T4 is divided into two periods (for example, a period T11 and a period T12).

In the period T11, a high potential is applied to the wiring G1 and a high potential is applied to the wiring S1, so that the pixel 65 connected to the wirings G1 and S1 emits light. Sampling SA is performed in this period T11.

Subsequently, in a period T12, the wiring G1 is kept at a high potential, and the wiring S1 is supplied with a low potential. As a result, the pixel 65 is brought into a state of not emitting light.

Subsequently, in a period T21, a low potential is applied to the wiring G1, a high potential is applied to the wiring G2, and a high potential is applied to the wiring S1, so that the pixels 65 connected to the wirings G2 and S1 emit light, and sampling is performed. conduct. After that, in a period T2, a low potential is applied to the wiring S1 to stop the pixel 65 from emitting light. After that, driving is performed in the same manner in periods T3 and T4.

Such a method can shorten the time to obtain one captured image as compared with FIG. 7(A).

The above is the description of the example of the driving method.

[Configuration example of drive circuit]
In the case of an active-matrix display panel, it is necessary to input video data of different potentials to the pixels according to the image to be displayed. becomes. On the other hand, in the case of the planar light-emitting device used for the imaging device of one embodiment of the present invention, the potential of the signal applied to the pixel does not necessarily have to be different for each pixel; therefore, the configuration of the source line driver circuit can be simplified.

FIG. 8A shows a configuration example of the driving circuit 62. As shown in FIG. The drive circuit 62 has a shift register composed of a plurality of flip-flop circuits (hereinafter referred to as FF circuits 81). A wiring to which the clock signal CLK is input and a wiring to which the pulse signal _VSP is applied are connected to the drive circuit 62 .

The output terminal of one FF circuit 81 is electrically connected to the input terminal of the adjacent FF circuit 81 and one source line (wiring S1 or the like). A clock signal CLK is also input to the FF circuit 81 . A pulse signal _VSP is input to the FF circuit 81 positioned closest to the input side of the drive circuit 62 .

The driver circuit 62 can output the output potential of the FF circuit 81 to the wirings S1 to S4 and the like based on the clock signal CLK. With such a configuration, an extremely simplified drive circuit 62 can be realized.

FIG. 8B shows an example in which a plurality of selector circuits 82 are further provided.

A pulse signal _VSP is input to the FF circuit 81 . A wiring to which the potential VH is applied and a wiring to which the potential VL is applied are electrically connected to the input terminal of one selector circuit 82, and one source line (the wiring S1 or the like) is electrically connected to the output terminal. The selector circuit 82 can output either the potential VH or the potential VL to the source line according to the input from the FF circuit 81 .

The driver circuit 62 illustrated in FIG. 8B can sequentially output the potential VH to the wirings S1 to S4 and the like based on the clock signal CLK, and at the same time, can output the potential VL to other wirings. As a result, the FF circuit 81 can be driven at a lower voltage than in FIG. 8A, so that it can be driven at a higher speed.

The above is the description of the configuration example of the drive circuit.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 2)
In this embodiment, a display panel that can be used for a planar light-emitting device that can be applied to an imaging method and an imaging device of one embodiment of the present invention will be described.

[Configuration example]
FIG. 9 shows a top view of the display panel 700. As shown in FIG. The display panel 700 has a pixel portion 702 provided over a substrate 745 . A source driver circuit portion 704 , a pair of gate driver circuit portions 706 , wirings 710 and the like are provided over the substrate 745 . A plurality of display elements are provided in the pixel portion 702 .

A pair of gate driver circuit portions 706 are provided on both sides of the pixel portion 702 . Note that the gate driver circuit portion 706 and the source driver circuit portion 704 may not be provided over the substrate 745 . For example, each may be in the form of an IC chip, which can be mounted on the display panel 700 . The IC chip can be mounted on substrate 745 or FPC 716 .

Also, an IC 717 is mounted on the substrate 745 . The IC 717 functions as, for example, a source driver circuit. At this time, the source driver circuit portion 704 in the display panel 700 can have a structure including at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, and the like.

Further, an FPC terminal portion 708 to which an FPC 716 (FPC: flexible printed circuit) is connected is provided on a part of the substrate 745 . The FPC 716 supplies various signals and the like to the pixel portion 702 , the source driver circuit portion 704 , the gate driver circuit portion 706 , and the IC 717 through the FPC terminal portion 708 and the wiring 710 .

A transistor including an oxide semiconductor is preferably used as the transistor included in the pixel portion 702 , the source driver circuit portion 704 , and the gate driver circuit portion 706 . A transistor including an oxide semiconductor may also be used as a transistor included in the IC 717 .

A light-emitting element or the like can be used as a display element provided in the pixel portion 702 . Light-emitting elements include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), QLEDs (Quantum-dot LEDs), and semiconductor lasers.

Organic EL elements (OLED) include a bottom emission type that emits light to the surface to be formed, a top emission type that emits light to the side opposite to the surface to be formed, and a dual emission type that emits light to both sides. and either can be used. In particular, it is preferable to use a top-emission light-emitting element because the aperture ratio can be increased, so that high definition can be easily achieved and the luminance of the light-emitting element can be increased.

Light-emitting diodes (LEDs) include macro LEDs (also referred to as giant LEDs), mini LEDs, micro LEDs, and the like. Here, an LED chip with a side dimension exceeding 1 mm is called a macro LED, an LED chip with a side dimension of more than 100 μm and 1 mm or less is called a mini LED, and an LED chip with a side dimension of 100 μm or less is called a micro LED. As LEDs applied to the pixel portion 702, it is particularly preferable to use mini-LEDs or micro-LEDs. A very high-definition display device can be realized by using micro LEDs.

As the display element, a liquid crystal element such as a transmissive liquid crystal element, a reflective liquid crystal element, or a transflective liquid crystal element can be used. In addition, a shutter type or optical interference type MEMS (Micro Electro Mechanical Systems) element, a display element to which a microcapsule type, an electrophoresis type, an electrowetting type, an electronic liquid powder (registered trademark) type, or the like is applied is used. can also

[Cross-sectional configuration example]
A configuration using an organic EL as a display element will be described below with reference to FIGS. 10 and 11. FIG. 10 and 11 are schematic cross-sectional views of the display panel 700 shown in FIG. 9 taken along the dashed-dotted line ST.

First, common parts of the display panels shown in FIGS. 10 and 11 will be described.

10 and 11 show cross sections including a pixel portion 702, a gate driver circuit portion 706, and an FPC terminal portion 708. FIG. A pixel portion 702 includes a transistor 750 and a capacitor 790 . The gate driver circuitry 706 has a transistor 752 .

The transistors 750 and 752 are transistors in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. Note that the semiconductor layer is not limited to this, and a transistor using silicon (amorphous silicon, polycrystalline silicon, or single crystal silicon) or an organic semiconductor can also be used for the semiconductor layer.

The transistor used in this embodiment includes a highly purified oxide semiconductor film in which formation of oxygen vacancies is suppressed. The transistor can have a significantly low off current. Therefore, in a pixel to which such a transistor is applied, an electric signal such as an image signal can be held for a long time, and an image signal can be written at a long interval. Therefore, the frequency of refresh operation can be reduced, so that power consumption can be reduced.

In addition, since the transistor used in this embodiment mode has relatively high field-effect mobility, it can be driven at high speed. For example, by using such a transistor capable of high-speed driving in a display panel, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. That is, it is possible to adopt a configuration in which a driver circuit formed of a silicon wafer or the like is not applied, and the number of parts of the display device can be reduced. Also in the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

The capacitor 790 includes a lower electrode formed by processing the same film as the first gate electrode included in the transistor 750 and an upper electrode formed by processing the same metal oxide film as the semiconductor layer. have. The top electrode is made low resistance, as are the source and drain regions of transistor 750 . In addition, part of an insulating film functioning as a first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitive element 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. A wiring obtained by processing the same film as the source and drain electrodes of the transistor 750 is connected to the upper electrode.

An insulating layer 770 functioning as a planarization film is provided over the transistors 750 , 752 , and the capacitor 790 .

The transistor 750 included in the pixel portion 702 and the transistor 752 included in the gate driver circuit portion 706 may have different structures. For example, a top-gate transistor may be applied to one of them, and a bottom-gate transistor may be applied to the other. Note that the source driver circuit section 704 is similar to the gate driver circuit section 706 .

The FPC terminal section 708 has a wiring 760, an anisotropic conductive film 780, and an FPC 716, some of which function as connection electrodes. The wiring 760 is electrically connected to terminals of the FPC 716 through an anisotropic conductive film 780 . Here, the wiring 760 is formed using the same conductive film as the source and drain electrodes of the transistor 750 and the like.

Next, the display panel 700 shown in FIG. 10 will be described.

A display panel 700 shown in FIG. 10 has a substrate 745 and a substrate 740 . As the substrates 745 and 740, a flexible substrate such as a glass substrate or a plastic substrate can be used.

A transistor 750 , a transistor 752 , a capacitor 790 , and the like are provided over a substrate 745 .

The display panel 700 also includes a light-emitting element 782, a colored layer 736, a light-blocking layer 738, and the like.

The light-emitting element 782 has a conductive layer 772 , an EL layer 786 , and a conductive layer 788 . A conductive layer 772 is electrically connected to a source or drain electrode of the transistor 750 . A conductive layer 772 is provided over the insulating layer 770 and functions as a pixel electrode. An insulating layer 730 is provided to cover an end portion of the conductive layer 772 , and an EL layer 786 and a conductive layer 788 are stacked over the insulating layer 730 and the conductive layer 772 .

A material that reflects visible light can be used for the conductive layer 772 . For example, materials containing aluminum, silver, etc. can be used. For the conductive layer 788, a material that transmits visible light can be used. For example, an oxide material containing indium, zinc, tin, or the like may be used. Therefore, the light-emitting element 782 is a top-emission light-emitting element that emits light to the side opposite to the formation surface (the substrate 740 side).

The EL layer 786 has an organic compound or an inorganic compound such as quantum dots. EL layer 786 includes a light-emitting material that emits light when an electric current is passed through it.

A fluorescent material, a phosphorescent material, a thermally activated delayed fluorescence (TADF) material, an inorganic compound (quantum dot material, etc.), or the like can be used as the light-emitting material. Materials that can be used for quantum dots include colloidal quantum dot materials, alloy quantum dot materials, core-shell quantum dot materials, core quantum dot materials, and the like.

A light shielding layer 738 and a colored layer 736 are provided on one surface of the substrate 740 . The colored layer 736 is provided so as to overlap with the light emitting element 782 . In addition, the light shielding layer 738 is provided in a region that does not overlap with the light emitting element 782 in the pixel portion 702 . The light shielding layer 738 may also be provided so as to overlap the gate driver circuit portion 706 and the like.

The substrates 740 and 745 are bonded together by a sealing layer 732 .

Here, a light-emitting material that emits white light is used for the EL layer 786 included in the light-emitting element 782 . White light emitted by the light emitting element 782 is colored by the coloring layer 736 and emitted to the outside. An EL layer 786 is provided over pixels exhibiting different colors. The display panel 700 has a full-color display by arranging pixels provided with a coloring layer 736 that transmits any one of red (R), green (G), and blue (B) in a matrix in the pixel portion. can be displayed.

Note that when the display panel 700 does not need to perform full-color display and only white light or single-color light such as red (R), green (G), and blue (B) can be used for display, the colored layer 736 may be omitted.

Alternatively, a semi-transmissive and semi-reflective conductive film may be used as the conductive layer 788 . At this time, a structure in which a microresonator (microcavity) structure is realized between the conductive layer 772 and the conductive layer 788 to intensify and emit light of a specific wavelength can be employed. Further, at this time, an optical adjustment layer for adjusting the optical distance is arranged between the conductive layer 772 and the conductive layer 788, and the thickness of the optical adjustment layer is made different between the pixels of different colors. The configuration may be such that the color purity of the light emitted from the pixel is increased.

Note that when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel row, that is, when the EL layer 786 is formed by separate coloring, the structure may be such that the colored layer 736 and the optical adjustment layer described above are not provided.

Here, substrates with low moisture permeability are preferably used for the substrates 745 and 740, respectively. With such a structure in which the light-emitting element 782, the transistor 750, and the like are sandwiched between the substrates 745 and 740, their deterioration is suppressed, and a highly reliable display panel can be realized.

A display panel 700A shown in FIG. 11 has a protective layer 479 functioning as a protective film instead of the substrate 740 shown in FIG.

The protective layer 749 is attached to the sealing layer 732 . As the protective layer 749, a glass substrate, a resin film, or the like can be used. As the protective layer 749, an optical member such as a polarizing plate (including a circularly polarizing plate) or a scattering plate may be used. Alternatively, a configuration in which two or more of these are laminated may be applied.

An EL layer 786 included in the light-emitting element 782 is provided in an island shape over the insulating layer 730 and the conductive layer 772 . Color display can be realized without using the coloring layer 736 by separately forming the EL layer 786 so that each subpixel emits light in a different color.

A protective layer 741 is provided to cover the light emitting element 782 . The protective layer 741 has a function of preventing impurities such as water from diffusing into the light emitting element 782 . The protective layer 741 has a layered structure in which an insulating layer 741a, an insulating layer 741b, and an insulating layer 741c are stacked in this order from the conductive layer 788 side. At this time, it is preferable to use an inorganic insulating film with a high barrier property against impurities such as water for the insulating layers 741a and 741c, and an organic insulating film functioning as a planarizing film for the insulating layer 741b. . In addition, it is preferable that the protective layer 741 is provided so as to extend to the gate driver circuit portion 706 as well.

Further, it is preferable that an island-shaped organic insulating film covering the transistors 750 and 752 and the like be formed inside the sealing layer 732 . In other words, the edge of the organic insulating film is preferably positioned inside the sealing layer 732 or in a region overlapping with the edge of the sealing layer 732 . FIG. 11 shows an example in which the insulating layer 770, the insulating layer 730, and the insulating layer 741b are processed into an island shape. For example, in a portion overlapping with the sealing layer 732, the insulating layer 741c and the insulating layer 741a are provided in contact with each other. In this way, the surface of the organic insulating film covering the transistor 750 and the transistor 752 is not exposed to the outside beyond the sealing layer 732, thereby preventing water from entering the transistor 750 and the transistor 752 from the outside through the organic insulating film. and hydrogen can be suitably prevented from diffusing. As a result, variation in electrical characteristics of the transistor can be suppressed, and a display device with extremely high reliability can be realized.

[About the components]
Components such as a transistor that can be applied to a display device are described below.

[transistor]
A transistor includes a conductive layer functioning as a gate electrode, a semiconductor layer, a conductive layer functioning as a source electrode, a conductive layer functioning as a drain electrode, and an insulating layer functioning as a gate insulating layer.

Note that there is no particular limitation on the structure of the transistor included in the display device of one embodiment of the present invention. For example, a planar transistor, a staggered transistor, or an inverted staggered transistor may be used. Further, the transistor structure may be either a top-gate type or a bottom-gate type. Alternatively, gate electrodes may be provided above and below the channel.

There is no particular limitation on the crystallinity of a semiconductor material used for a transistor, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having a crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystal region in part) can be used. semiconductor) may be used. A single crystal semiconductor or a crystalline semiconductor is preferably used because deterioration in transistor characteristics can be suppressed.

A transistor using a metal oxide film as a semiconductor layer in which a channel is formed will be described below.

As a semiconductor material used for a transistor, a metal oxide with an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is a metal oxide containing indium, and for example, CAC-OS, which will be described later, can be used.

A transistor including a metal oxide, which has a wider bandgap and a lower carrier concentration than silicon, can hold charge accumulated in a capacitor connected in series with the transistor for a long time due to its low off-state current. is possible.

The semiconductor layer is represented by an In--M--Zn oxide containing, for example, indium, zinc and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium). It can be a membrane.

When the metal oxide forming the semiconductor layer is an In--M--Zn oxide, the atomic ratio of the metal elements in the sputtering target used for forming the In--M--Zn oxide is In≧M, Zn It is preferable to satisfy ≧M. The atomic ratios of the metal elements in such a sputtering target are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1: 2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1: 7, In:M:Zn=5:1:8, etc. are preferable. It should be noted that the atomic ratio of the semiconductor layers to be deposited includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.

A metal oxide film with a low carrier concentration is used as the semiconductor layer. For example, the semiconductor layer has a carrier concentration of 1×10 ¹⁷ cm ⁻³ or less, preferably 1×10 ¹⁵ cm ⁻³ or less, more preferably 1×10 ¹³ cm ⁻³ or less, more preferably 1×10 ¹¹ cm −3 or less ^. A metal oxide having a carrier concentration of ³ or less, more preferably less than 1×10 ¹⁰ cm ⁻³ and 1×10 ⁻⁹ cm ⁻³ or more can be used. Such metal oxides are referred to as highly pure or substantially highly pure intrinsic metal oxides. The oxide semiconductor can be said to be a metal oxide with a low defect state density and stable characteristics.

Note that the oxide semiconductor is not limited to these, and an oxide semiconductor having an appropriate composition may be used according to required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of the transistor. In addition, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the semiconductor layer has appropriate carrier concentration, impurity concentration, defect density, atomic ratio of metal elements and oxygen, interatomic distance, density, and the like. .

If silicon or carbon, which is one of Group 14 elements, is contained in the metal oxide forming the semiconductor layer, oxygen vacancies increase in the semiconductor layer and the semiconductor layer becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁷ atoms/cm ³ or less.

Further, alkali metals and alkaline earth metals may generate carriers when combined with metal oxides, which may increase the off-state current of the transistor. Therefore, the concentration of alkali metals or alkaline earth metals obtained by secondary ion mass spectrometry in the semiconductor layer is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

Further, when the metal oxide forming the semiconductor layer contains nitrogen, electrons as carriers are generated, the carrier concentration increases, and the semiconductor layer tends to become n-type. As a result, a transistor using a metal oxide containing nitrogen tends to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer obtained by secondary ion mass spectrometry is preferably 5×10 ¹⁸ atoms/cm ³ or less.

Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudo-amorphous oxide semiconductor (a-like OS). : amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

A CAC-OS (cloud-aligned composite oxide semiconductor) may be used for the semiconductor layer of the transistor disclosed in one embodiment of the present invention.

Note that the above non-single-crystal oxide semiconductor or CAC-OS can be preferably used for a semiconductor layer of the transistor disclosed in one embodiment of the present invention. As a non-single-crystal oxide semiconductor, an nc-OS or a CAAC-OS can be preferably used.

Note that in one embodiment of the present invention, a CAC-OS is preferably used for the semiconductor layer of the transistor. By using a CAC-OS, a transistor can have high electrical characteristics or high reliability.

Note that the semiconductor layer includes two or more of a CAAC-OS region, a polycrystalline oxide semiconductor region, an nc-OS region, a pseudo-amorphous oxide semiconductor region, and an amorphous oxide semiconductor region. It may be a mixed film having The mixed film may have, for example, a single-layer structure or a laminated structure containing two or more of the above-described regions.

<Configuration of CAC-OS>
A structure of a CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

A CAC-OS is, for example, one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following description, one or more metal elements are unevenly distributed in the metal oxide, and the region containing the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. The mixed state is also called mosaic or patch.

Note that the metal oxide preferably contains at least indium. Indium and zinc are particularly preferred. Also, in addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. may contain one or more selected from

For example, CAC-OS in In—Ga—Zn oxide (In—Ga—Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is indium oxide (hereinafter, InO _X1 (X1 is a real number greater than 0), or indium zinc oxide (hereinafter referred to as In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers greater than 0); ) and the like, and the material is separated into a mosaic shape, and the mosaic InO _X1 or In _X2 Zn _Y2 O _Z2 is uniformly distributed in the film (hereinafter also referred to as a cloud shape). be.

That is, CAC-OS is a composite metal oxide having a structure in which a region containing GaO _{2 X3} as a main component and a region containing In _{2 X2} Zn _Y2 O _Z2 or InO _{2 X1} as a main component are mixed. In this specification, for example, the first region means that the atomic ratio of In to the element M in the first region is greater than the atomic ratio of In to the element M in the second region. Assume that the concentration of In is higher than that of the region No. 2.

Note that IGZO is a common name, and may refer to one compound of In, Ga, Zn, and O. Representative examples are represented by InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _(1+x0) Ga _(1−x0) O ₃ (ZnO) _m0 (−1≦x0≦1, m0 is an arbitrary number). Crystalline compounds are mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

CAC-OS, on the other hand, relates to the material composition of metal oxides. CAC-OS is a material composition containing In, Ga, Zn, and O, in which a region observed in the form of nanoparticles whose main component is Ga in part and nanoparticles whose main component is In in part. The regions observed in a pattern refer to a configuration in which the regions are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS the crystal structure is a secondary factor.

Note that CAC-OS does not include a stacked structure of two or more films with different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.

In some cases, a clear boundary cannot be observed between a region containing GaO _X3 as a main component and a region containing In _{X2 ZnY2} O _Z2 or InO _X1 as a main component.

Instead of gallium, aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. CAC-OS contains one or more of the above metal elements, part of which is observed in the form of nanoparticles containing the metal element as the main component, and part of which contains nanoparticles containing In as the main component. The regions observed as particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.

CAC-OS can be formed, for example, by a sputtering method under the condition that the substrate is not intentionally heated. Further, when the CAC-OS is formed by a sputtering method, any one or more selected from inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the film forming gas. good. Further, the flow rate ratio of oxygen gas to the total flow rate of film formation gas during film formation is preferably as low as possible. .

CAC-OS is characterized by the fact that no clear peak is observed when measured using θ/2θ scanning by the Out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. have. That is, it can be seen from the X-ray diffraction measurement that no orientations in the ab plane direction and the c-axis direction of the measurement region are observed.

In addition, CAC-OS has an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam). A plurality of bright spots are observed in . Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure with no orientation in the planar direction and the cross-sectional direction.

Further, for example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) reveals a region in which GaO _X3 is the main component. , and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are unevenly distributed and mixed.

CAC-OS has a structure different from IGZO compounds in which metal elements are uniformly distributed, and has properties different from those of IGZO compounds. That is, the CAC-OS is phase-separated into a region containing GaO _{2 X3} or the like as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _{2 X1} as a main component, and a region containing each element as a main component. has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as the main component has higher conductivity than the region containing GaO _X3 or the like as the main component. That is, when carriers flow through a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component, conductivity as a metal oxide is developed. Therefore, a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is distributed in the metal oxide in a cloud shape, so that a high field effect mobility (μ) can be realized.

On the other hand, a region containing GaO _{2 X3} or the like as a main component has higher insulating properties than a region containing In _X2 Zn _Y2 O _Z2 or InO _{2 X1} as a main component. In other words, by distributing the region mainly composed of GaO _{2 X3} or the like in the metal oxide, it is possible to suppress leakage current and realize good switching operation.

Therefore, when CAC-OS is used for a semiconductor element, the insulation properties caused by GaO _X3 and the like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act in a complementary manner. On-current (I _on ) and high field effect mobility (μ) can be achieved.

In addition, a semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices including displays.

Further, since a transistor including CAC-OS in a semiconductor layer has high field-effect mobility and high driving capability, the transistor can be used in a driver circuit, typically a scanning line driver circuit that generates a gate signal. , a display device with a narrow frame width (also referred to as a narrow frame) can be provided. By using the transistor in a signal line driver circuit included in the display device (in particular, a demultiplexer connected to an output terminal of a shift register included in the signal line driver circuit), the number of wirings connected to the display device is reduced. A display device can be provided.

A transistor having a CAC-OS in a semiconductor layer does not require a laser crystallization process unlike a transistor using low-temperature polysilicon. Therefore, the manufacturing cost can be reduced even for a display device using a large-sized substrate. In addition, semiconductors are used in high-resolution and large display devices such as ultra high-definition (“4K resolution”, “4K2K”, “4K”) and super high-definition (“8K resolution”, “8K4K”, “8K”). By using a transistor including a CAC-OS in a layer for a driver circuit and a display portion, writing can be performed in a short time and display defects can be reduced, which is preferable.

Alternatively, silicon may be used for a semiconductor in which a channel of a transistor is formed. Although amorphous silicon may be used as silicon, it is particularly preferable to use crystalline silicon. For example, microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like is preferably used. In particular, polycrystalline silicon can be formed at a lower temperature than monocrystalline silicon, and has higher field effect mobility and higher reliability than amorphous silicon.

[Conductive layer]
In addition to the gate, source and drain of transistors, materials that can be used for conductive layers such as various wirings and electrodes constituting display devices include aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, A metal such as tantalum or tungsten, or an alloy containing this as a main component can be used. Also, a film containing these materials can be used as a single layer or as a laminated structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is stacked over a titanium film, a two-layer structure in which an aluminum film is stacked over a tungsten film, and a copper film over a copper-magnesium-aluminum alloy film. A two-layer structure, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and an aluminum film or a copper film overlaid thereon and further a titanium film or a titanium nitride film is formed thereon, a molybdenum film or a molybdenum nitride film is laminated thereon, an aluminum film or a copper film is laminated thereon, and a molybdenum film or a There is a three-layer structure that forms a molybdenum nitride film, and the like. Note that an oxide such as indium oxide, tin oxide, or zinc oxide may be used. Further, it is preferable to use copper containing manganese because the controllability of the shape by etching is increased.

[Insulating layer]
Examples of insulating materials that can be used for each insulating layer include resins such as acrylic and epoxy, resins having a siloxane bond, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide. Materials can also be used.

Further, the light-emitting element is preferably provided between a pair of insulating films with low water permeability. As a result, it is possible to prevent impurities such as water from entering the light-emitting element, and to prevent deterioration of the reliability of the device.

Examples of the insulating film with low water permeability include a film containing nitrogen and silicon such as a silicon nitride film and a silicon nitride oxide film, a film containing nitrogen and aluminum such as an aluminum nitride film, and the like. Alternatively, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like may be used.

For example, the water vapor permeation amount of an insulating film with low water permeability is 1×10 ⁻⁵ [g/(m ² ·day)] or less, preferably 1×10 ⁻⁶ [g/(m ² ·day)] or less, It is more preferably 1×10 ⁻⁷ [g/(m ² ·day)] or less, still more preferably 1×10 ⁻⁸ [g/(m ² ·day)] or less.

The above is the description of the constituent elements.

At least part of the structural examples and the drawings corresponding to them in this embodiment can be combined with other structural examples, the drawings, and the like as appropriate.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 3)
In this embodiment, a configuration example of a display device capable of realizing extremely high definition will be described. A display device exemplified below can be applied to the planar light-emitting device in the imaging method and imaging device of one embodiment of the present invention.

FIG. 12A is a cross-sectional view showing a configuration example of the display device 100. FIG. The display device 100 has a substrate 101 and a substrate 105 , and the substrates 101 and 105 are attached to each other with a sealing material 112 .

As the substrate 101, a single crystal semiconductor substrate such as a single crystal silicon substrate can be used. Note that a semiconductor substrate other than a single crystal semiconductor substrate may be used as the substrate 101 .

A transistor 441 and a transistor 601 are provided over the substrate 101 . The transistor 441 can be a transistor provided in a driver circuit or the like. The transistor 601 can be a transistor provided in a pixel, a transistor provided in a gate driver circuit, or a transistor provided in a source driver circuit.

The transistor 441 includes a conductive layer 443 functioning as a gate electrode, an insulating layer 445 functioning as a gate insulating layer, and part of the substrate 101 . A semiconductor region 447 including a channel formation region, a low-resistance region 449a functioning as one of a source region and a drain region, and a low-resistance region 449b functioning as the other are formed in part of the substrate 101 . Transistor 441 may be either p-channel or n-channel.

A transistor 441 is electrically isolated from other transistors by an element isolation layer 403 . FIG. 12A shows the case where the element isolation layer 403 electrically isolates the transistor 441 from the transistor 601 . The element isolation layer 403 can be formed using a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

Here, in the transistor 441 illustrated in FIG. 12A, the semiconductor region 447 has a convex shape. In addition, the conductive layer 443 is provided so as to cover the side surface and the top surface of the semiconductor region 447 with the insulating layer 445 interposed therebetween. Note that FIG. 12A does not show how the conductive layer 443 covers the side surface of the semiconductor region 447 . A material that adjusts the work function can be used for the conductive layer 443 .

A transistor in which a semiconductor region has a convex shape, such as the transistor 441, can be called a fin transistor because it uses a convex portion of a semiconductor substrate. In addition, an insulating layer that functions as a mask for forming the protrusion may be provided in contact with the upper portion of the protrusion. In addition, although FIG. 12A shows a structure in which part of the substrate 101 is processed to form a convex portion, a semiconductor having a convex shape may be formed by processing an SOI substrate.

Note that the structure of the transistor 441 illustrated in FIG. 12A is an example, and the structure is not limited to that structure, and an appropriate structure may be employed depending on the circuit structure, the operation method of the circuit, or the like. For example, transistor 441 may be a planar transistor.

The transistor 601 can have a structure similar to that of the transistor 441 .

In addition to the element isolation layer 403 and the transistors 441 and 601 , the insulating layer 405 , the insulating layer 407 , the insulating layer 409 , and the insulating layer 411 are provided over the substrate 101 . A conductive layer 451 is embedded in the insulating layer 405 , the insulating layer 407 , the insulating layer 409 , and the insulating layer 411 . Here, the height of the top surface of the conductive layer 451 and the height of the top surface of the insulating layer 411 can be made approximately the same.

An insulating layer 413 and an insulating layer 415 are provided over the conductive layer 451 and the insulating layer 411 . A conductive layer 457 is embedded in the insulating layers 413 and 415 . The height of the top surface of the conductive layer 457 and the height of the top surface of the insulating layer 415 can be approximately the same.

An insulating layer 417 and an insulating layer 419 are provided over the conductive layer 457 and the insulating layer 415 . A conductive layer 459 is embedded in the insulating layers 417 and 419 . The height of the top surface of the conductive layer 459 and the height of the top surface of the insulating layer 419 can be approximately the same.

An insulating layer 421 and an insulating layer 214 are provided over the conductive layer 459 and the insulating layer 419 . A conductive layer 453 is embedded in the insulating layer 421 and the insulating layer 214 . The height of the top surface of the conductive layer 453 and the height of the top surface of the insulating layer 214 can be made approximately the same.

An insulating layer 216 is provided over the conductive layer 453 and the insulating layer 214 . A conductive layer 455 is embedded in the insulating layer 216 . The height of the top surface of the conductive layer 455 and the height of the top surface of the insulating layer 216 can be approximately the same.

An insulating layer 222 , an insulating layer 224 , an insulating layer 254 , an insulating layer 280 , an insulating layer 274 , and an insulating layer 281 are provided over the conductive layer 455 and the insulating layer 216 . A conductive layer 305 is embedded in the insulating layer 222 , the insulating layer 224 , the insulating layer 254 , the insulating layer 280 , the insulating layer 274 , and the insulating layer 281 . The height of the upper surface of the conductive layer 305 and the height of the upper surface of the insulating layer 281 can be made approximately the same.

An insulating layer 361 is provided over the conductive layer 305 and the insulating layer 281 . A conductive layer 317 and a conductive layer 337 are embedded in the insulating layer 361 . The height of the top surface of the conductive layer 337 and the height of the top surface of the insulating layer 361 can be made approximately the same.

An insulating layer 363 is provided over the conductive layer 337 and the insulating layer 361 . A conductive layer 347 , a conductive layer 353 , a conductive layer 355 , and a conductive layer 357 are embedded in the insulating layer 363 . The height of the top surfaces of the conductive layers 353, 355, and 357 and the top surface of the insulating layer 363 can be approximately the same.

A connection electrode 160 is provided over the conductive layer 353 , the conductive layer 355 , the conductive layer 357 , and the insulating layer 363 . Also, an anisotropic conductive layer 180 is provided so as to be electrically connected to the connection electrode 160 , and an FPC (Flexible Printed Circuit) 116 is provided so as to be electrically connected to the anisotropic conductive layer 180 . Various signals and the like are supplied to the display device 100 from the outside of the display device 100 by the FPC 116 .

As shown in FIG. 12A, the low-resistance region 449b functioning as the other of the source region and the drain region of the transistor 441 includes a conductive layer 451, a conductive layer 457, a conductive layer 459, a conductive layer 453, and a conductive layer 455. , the conductive layer 305 , the conductive layer 317 , the conductive layer 337 , the conductive layer 347 , the conductive layer 353 , the conductive layer 355 , the conductive layer 357 , the connection electrode 160 , and the anisotropic conductive layer 180 are electrically connected to the FPC 116 . It is Here, FIG. 12A shows three conductive layers, ie, a conductive layer 353, a conductive layer 355, and a conductive layer 357 as conductive layers having a function of electrically connecting the connection electrode 160 and the conductive layer 347; One aspect of the invention is not limited to this. The number of conductive layers having a function of electrically connecting the connection electrode 160 and the conductive layer 347 may be one, two, or four or more. By providing a plurality of conductive layers having a function of electrically connecting the connection electrode 160 and the conductive layer 347, contact resistance can be reduced.

A transistor 150 is provided over the insulating layer 214 . The transistor 150 can be a transistor provided in a pixel. A transistor including an oxide semiconductor can be used as the transistor 150 . Such a transistor is characterized by an extremely low off current. Therefore, since the holding time of an image signal or the like can be lengthened, the frequency of refresh operations can be reduced. Therefore, power consumption of the display device 100 can be reduced.

A conductive layer 301 a and a conductive layer 301 b are embedded in the insulating layers 254 , 280 , 274 , and 281 . The conductive layer 301 a is electrically connected to one of the source and drain of the transistor 150 , and the conductive layer 301 b is electrically connected to the other of the source and drain of the transistor 150 . Here, the top surface of the conductive layers 301a and 301b and the top surface of the insulating layer 281 can be almost the same height.

A conductive layer 311 , a conductive layer 313 , a conductive layer 331 , a capacitor 190 , a conductive layer 333 , and a conductive layer 335 are embedded in the insulating layer 361 . The conductive layers 311 and 313 are electrically connected to the transistor 150 and function as wirings. The conductive layers 333 and 335 are electrically connected to the capacitor 190 . The height of the top surfaces of the conductive layers 331, 333, and 335 and the top surface of the insulating layer 361 can be approximately the same.

A conductive layer 341 , a conductive layer 343 , and a conductive layer 351 are embedded in the insulating layer 363 . The height of the top surface of the conductive layer 351 and the height of the top surface of the insulating layer 363 can be made approximately the same.

Insulating layer 405, insulating layer 407, insulating layer 409, insulating layer 411, insulating layer 413, insulating layer 415, insulating layer 417, insulating layer 419, insulating layer 421, insulating layer 214, insulating layer 280, insulating layer 274, insulating layer 281, the insulating layer 361, and the insulating layer 363 have a function as an interlayer film, and may have a function as a planarization film covering the uneven shape below each. For example, the upper surface of the insulating layer 363 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like in order to improve planarity.

As shown in FIG. 12A, the capacitor 190 has a lower electrode 321 and an upper electrode 325 . An insulating layer 323 is provided between the lower electrode 321 and the upper electrode 325 . That is, the capacitive element 190 has a laminated structure in which the insulating layer 323 functioning as a dielectric is sandwiched between a pair of electrodes. Although FIG. 12A shows an example in which the capacitor 190 is provided over the insulating layer 281, the capacitor 190 may be provided over an insulating layer different from the insulating layer 281. FIG.

FIG. 12B shows an enlarged view of the transistor 150. FIG.

The transistor 150 includes a conductive layer 161, a semiconductor layer 151, a semiconductor layer 152, a semiconductor layer 153, a pair of conductive layers 154, an insulating layer 155, a conductive layer 156, a conductive layer 157, and the like.

The conductive layer 161 functions as a first gate electrode, and the conductive layers 156 and 157 function as second gate electrodes. A pair of conductive layers 154 function as a source electrode and a drain electrode, respectively.

The semiconductor layer 153 , the insulating layer 155 , the conductive layer 156 , and the conductive layer 157 are provided in order so as to fill the concave portion provided in the insulating layer 280 .

With such a structure, a transistor occupying an extremely small area can be realized. For example, a transistor with a channel length of 100 nm or less, 80 nm or less, 60 nm or less, or even 40 nm or less can be realized. Therefore, an extremely high-definition display device can be realized.

A display device 100 illustrated in FIG. 12A includes a light-emitting element 182 . The light emitting element 182 has a conductive layer 172 , an EL layer 186 and a conductive layer 188 . The EL layer 186 has an organic compound or an inorganic compound such as quantum dots. In addition, the conductive layer 172 is electrically connected to the other of the source and the drain of the transistor 150 through the conductive layers 351, 341, 331, 313, and 301b. The conductive layer 172 is formed over the insulating layer 363 and functions as a pixel electrode.

The insulating layer 130 is provided over the insulating layer 363 in the display device 100 illustrated in FIG. Here, the insulating layer 130 can be configured to cover part of the conductive layer 172 . The light-emitting element 182 includes a light-transmitting conductive layer 188 and is a top-emission light-emitting element.

The light emitting element 182 can have a microcavity structure. Accordingly, light of predetermined colors (for example, RGB) can be extracted without providing a colored layer, and the display device 100 can perform color display. Absorption of light by the colored layer can be suppressed by adopting a structure in which the colored layer is not provided. As a result, the display device 100 can display a high-brightness image, and the power consumption of the display device 100 can be reduced. Note that even when the EL layer 186 is formed in an island shape for each pixel or in a striped shape for each pixel row, that is, in the case where the EL layer 186 is formed by coloring separately, a structure in which a colored layer is not provided can be employed.

Note that the light shielding layer 138 is provided so as to have a region overlapping with the insulating layer 130 . Also, the light shielding layer 138 is covered with the insulating layer 134 . A sealing layer 132 is filled between the light emitting element 182 and the insulating layer 134 .

Further, structure 178 is provided between insulating layer 130 and EL layer 186 . Also, the structure 178 is provided between the insulating layer 130 and the insulating layer 134 .

In FIG. 12A, the transistor 441 and the transistor 601 are provided so that a channel formation region is formed inside the substrate 101, and stacked over the transistor 441 and the transistor 601 to use an oxide semiconductor. is shown, one embodiment of the present invention is not limited to this. FIG. 13 shows a modification of FIG. 12(A). The display device 100 illustrated in FIG. 13 is different from the structure illustrated in FIG. 12A in that the transistor 150 is stacked over the transistors 602 and 603 to which an oxide semiconductor is applied. In other words, the display device 100 illustrated in FIG. 13 includes stacked transistors each including an oxide semiconductor.

An insulating layer 613 and an insulating layer 614 are provided over the substrate 101 , and the transistors 602 and 603 are provided over the insulating layer 614 . Note that a transistor or the like may be provided between the substrate 101 and the insulating layer 613 . For example, a transistor having a structure similar to that of the transistor 441 and the transistor 601 illustrated in FIG. 12A may be provided between the substrate 101 and the insulating layer 613 .

The transistor 602 can be a transistor provided in the driver circuit. The transistor 603 can be a transistor provided in a gate driver or a transistor provided in a source driver.

The transistors 602 and 603 can be transistors with structures similar to the transistor 150 . Note that the transistors 602 and 603 may have different structures from the transistor 150 .

Over the insulating layer 614, in addition to the transistors 602 and 603, an insulating layer 616, an insulating layer 622, an insulating layer 624, an insulating layer 654, an insulating layer 680, an insulating layer 674, and an insulating layer 681 are provided. A conductive layer 461 is embedded in the insulating layer 654 , the insulating layer 680 , the insulating layer 674 , and the insulating layer 681 . The height of the top surface of the conductive layer 461 and the height of the top surface of the insulating layer 681 can be made approximately the same.

An insulating layer 501 is provided over the conductive layer 461 and the insulating layer 681 . A conductive layer 463 is embedded in the insulating layer 501 . The height of the top surface of the conductive layer 463 and the height of the top surface of the insulating layer 501 can be made approximately the same.

An insulating layer 503 is provided over the conductive layer 463 and the insulating layer 501 . A conductive layer 465 is embedded in the insulating layer 503 . The height of the top surface of the conductive layer 465 and the height of the top surface of the insulating layer 503 can be made approximately the same.

An insulating layer 505 is provided over the conductive layer 465 and the insulating layer 503 . A conductive layer 467 is embedded in the insulating layer 505 . The height of the top surface of the conductive layer 467 and the height of the top surface of the insulating layer 505 can be made approximately the same.

An insulating layer 507 is provided over the conductive layer 467 and the insulating layer 505 . A conductive layer 469 is embedded in the insulating layer 507 . The height of the top surface of the conductive layer 469 and the height of the top surface of the insulating layer 507 can be made approximately the same.

An insulating layer 509 is provided over the conductive layer 469 and the insulating layer 507 . A conductive layer 471 is embedded in the insulating layer 509 . The height of the top surface of the conductive layer 471 and the height of the top surface of the insulating layer 509 can be made approximately the same.

An insulating layer 421 and an insulating layer 214 are provided over the conductive layer 471 and the insulating layer 509 . A conductive layer 453 is embedded in the insulating layer 421 and the insulating layer 214 . The height of the top surface of the conductive layer 453 and the height of the top surface of the insulating layer 214 can be made approximately the same.

As shown in FIG. 13, one of the source or drain of transistor 602 is connected to conductive layer 461, conductive layer 463, conductive layer 465, conductive layer 467, conductive layer 469, conductive layer 471, conductive layer 453, conductive layer 455, conductive layer It is electrically connected to FPC 116 via layer 305 , conductive layer 317 , conductive layer 337 , conductive layer 347 , conductive layer 353 , conductive layer 355 , conductive layer 357 , connection electrode 160 , and anisotropic conductive layer 180 . there is

The insulating layers 613, 614, 680, 674, 681, 501, 503, 505, 507, and 509 function as interlayer films. , may have a function as a planarizing film covering the uneven shape below each.

When the display device 100 has the structure illustrated in FIG. 13, the display device 100 can have a narrow frame and a small size, and all the transistors included in the display device 100 can be transistors using an oxide semiconductor. Accordingly, manufacturing cost of the display device 100 can be reduced because it is not necessary to manufacture different types of transistors.

Although the structure in which two transistors are stacked is described above, a structure in which three or more layers are stacked may be employed. For example, a stacked structure in which two or more transistors using an oxide semiconductor are stacked over a transistor using silicon can be employed.

Moreover, although the structure in which the transistors are stacked has been described above, the structure is not limited to this. In the case where a transistor can be manufactured sufficiently finely so that a required pixel interval can be realized, manufacturing cost can be reduced by forming a display device without stacking transistors. For example, a transistor including any of the above oxide semiconductors may be provided over a single crystal substrate.

At least part of the structural examples and the drawings corresponding to them in this embodiment can be combined with other structural examples, the drawings, and the like as appropriate.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

Example 1 In this example, results of imaging using an imaging method of one embodiment of the present invention will be described.

A display panel using an organic EL element as a light emitting element was used as the planar light emitting device. Further, the organic EL panel was a display panel to which an oxide semiconductor was applied as a transistor forming a pixel. Table 1 shows specifications of the display panel.

A luminance meter was used as a photoelectric conversion device used for imaging. As a luminance meter, a color luminance meter BM-5AS manufactured by Topcon Technohouse Co., Ltd. was used.

For imaging, first, the display panel was arranged in a dark room, and a luminance meter was fixed at a position approximately 70 cm above the display area of the display panel. Then, while the object to be observed was placed directly on the screen of the display panel, the brightness was repeatedly measured when each pixel was caused to emit white light. Here, a ruler with a transparent base material was used as the object to be observed.

After that, based on the minimum and maximum values of the plurality of luminance data obtained, 8-bit gradation image data was generated by assigning a gradation value to each data.

FIG. 14 shows an image obtained by the above imaging. The image shown in FIG. 14 is an image consisting of 80×80 pixel data. As shown in FIG. 14, it can be seen that a clear image is obtained with a high contrast ratio.

Also, from the image shown in FIG. 14, when an attempt was made to measure the memory interval of the ruler, it was found to be 0.987 [0.005] mm, and it was found that the length could be measured with high accuracy.

Subsequently, a comparison was made between the case of using an organic EL panel as a planar light emitting device and the case of using a liquid crystal panel.

As the liquid crystal panel, a commercially available monitor device having a pixel density of 86 ppi and a pixel pitch of 0.295 mm×0.295 mm was used.

Also, in order to make the pixel pitch closer, the organic EL panel was imaged every 3×3 pixels.

FIG. 15A1 shows an image captured using an organic EL panel, and FIG. 15B1 shows an image captured using a liquid crystal panel. Each image has 75×75 pixels. In any image, it can be seen that the ruler's memory and numbers can be clearly imaged. Also, it can be seen that an image with a higher contrast is obtained by using the organic EL panel than by using the liquid crystal panel.

FIG. 15A2 shows gradation values corresponding to one row of image data indicated by the dashed line in FIG. 15A1. FIG. 15(B2) shows tone values corresponding to one row of image data indicated by the dashed line in FIG. 15(B1). In FIGS. 15A2 and 15B2, the horizontal axis indicates the address of the pixel data, and the vertical axis indicates the gradation value of the image data normalized with the maximum value of 1 being the gradation value.

When an organic EL panel is used, there is a large difference in gradation value between bright and dark portions, and high contrast is obtained. On the other hand, when the liquid crystal panel is used, the difference in gradation value between the bright portion and the dark portion is small, and the contrast is low.

When a liquid crystal panel is used, some of the light from the backlight is emitted even from pixels that do not emit light. end up On the other hand, since the organic EL elements included in the organic EL panel are self-luminous, pixels that do not emit light do not emit light, so that high contrast can be achieved. Furthermore, since an oxide semiconductor with remarkably low leakage current in an off state is used for a transistor forming a pixel, leakage current between adjacent pixels is suppressed, and higher contrast is achieved.

Note that although the imaging range is a 75×75 pixel area here, it can be expanded to an imaging range corresponding to the resolution of the display panel.

From the above, it has been confirmed that an imaging apparatus that can be used as a microscope and that achieves both high resolution and a wide field of view can be realized with an extremely simple configuration without using a lens.

In this example, a display panel having a much higher definition than the display panel used in Example 1 is applied to a planar light-emitting device, and the result of imaging will be described.

The display panel used in this embodiment has a definition (pixel density) of 5291 ppi and a resolution (number of effective pixels) of 1280×720, which is extremely high definition. The size of the display area is 6.14 mm×3.46 mm. A top emission type organic EL element was used as the light emitting element. A single-crystal substrate was used as a substrate of the display panel, and a transistor using an oxide semiconductor and a light-emitting element were sequentially formed over the substrate. An oxide semiconductor was applied to transistors forming a pixel and a gate line driver circuit, and an IC was applied to a source line driver circuit.

As for the imaging method, the description of the first embodiment can be used. Here, the operation of measuring the brightness while emitting white light was repeated for every 3×3 pixels, and an image composed of 105×105 pixel data was obtained.

A glass substrate provided with a metal thin film having a character pattern was used as an object to be observed. FIG. 16A shows an optical microscope image of the object to be observed. The characters "TEG2" are applied to the imaging area of the object to be observed. The size of one character is approximately 300 μm×300 μm, and the line width of the character portion is approximately 60 μm. Further, as shown in FIG. 16A, a wiring pattern having a line width of about 5 μm is also applied to the object to be observed in addition to the characters.

FIG. 16B shows an image obtained by imaging. The image shown in FIG. 16B is an 8-bit gradation image composed of 105×105 pixel data. As shown in FIG. 16B, the portion shielded by the metal thin film is displayed dark, and the other portion is displayed bright, so that the characters "TEG2" can be clearly read. Also, it can be seen that part of the wiring pattern positioned above and below the character is also imaged.

Subsequently, as an object to be observed, an image was taken using a laminate of two glass substrates provided with metal thin films having different character patterns. The thickness of the glass substrates is 0.7 mm each.

FIG. 17A shows a schematic diagram of an object to be observed. A character pattern of "TEG2" is applied to the surface of the lower glass substrate, and a character pattern of "TEG1" is applied to the surface of the upper glass substrate. As shown in FIG. 17A, an object to be observed was obtained by stacking two glass substrates so that two characters do not overlap each other.

FIG. 17B shows an optical microscope image of the object to be observed. Here, the image was taken with the surface of the glass substrate located on the lower side (that is, the letters "TEG2") in focus. As shown in FIG. 17B, since the depth of field of the optical microscope is shallow, the characters "TEG1" applied to the surface of the upper glass substrate may be out of focus and blurred. I can confirm.

FIG. 17C shows an image captured by the imaging method of one embodiment of the present invention. As shown in FIG. 17C, it can be confirmed that two character patterns arranged with a thickness of about 0.7 mm apart can be clearly observed. From this, it was confirmed that an in-focus image could be captured over the entire thickness direction of the object to be observed.

From the above, it was confirmed that even an extremely minute object can be imaged by using a high-definition display panel in the imaging method of one embodiment of the present invention. Furthermore, since the depth of field is extremely deep and there is no need to adjust the focus with a lens, even with a thick object to be observed, a single image can be captured to obtain a clear image in focus over the entire thickness direction. It was confirmed that images could be captured.

10, 10a, 10A, 10B: imaging device, 11: planar light emitting device, 11a: light emitting surface, 12: photoelectric conversion device, 12a: light receiving surface, 13: light shielding member, 14: stage, 16: position adjustment mechanism, 16a , b: dial, 21: light emitting area, 22: pixel data, 30: object to be observed, 31: direct light, 32: transmitted light, 40, 40a: captured image, 51: control unit, 52: timing control unit, 53 : A-D converter, 54: storage unit, 55: display device, 61: light emitting unit, 62, 63: drive circuit, 65, 65a to d: pixels, 66, 67: wiring, 71: light emitting element, 72, 73: transistor, 74: capacitive element, 81: FF circuit, 82: selector circuit

Claims (3)

An imaging device having a planar light emitting device, a photoelectric conversion device, a light shielding member, and a stage,
The planar light emitting device has a plurality of light emitting elements arranged in a matrix,
The photoelectric conversion device has a light receiving surface,
The stage has translucency and has a function of supporting an object to be observed,
the light-emitting surface and the light-receiving surface of the planar light-emitting device are provided to face each other with the stage interposed therebetween,
The light shielding member is provided to cover the light receiving surface, the light emitting surface, and the stage,
The planar light emitting device has a function of individually causing the plurality of light emitting elements to emit light,
The photoelectric conversion device has a function of outputting data on the amount of light received by the light receiving surface in synchronization with light emission of the light emitting element,
An imaging device that does not have a lens . An imaging device having a planar light emitting device, a photoelectric conversion device, a light shielding member, and a stage,
The planar light emitting device has a plurality of light emitting elements arranged in a matrix,
The photoelectric conversion device has a light receiving surface,
The stage has translucency and has a function of supporting an object to be observed,
the light-emitting surface and the light-receiving surface of the planar light-emitting device are provided to face each other with the stage interposed therebetween,
The light shielding member is provided to cover the light receiving surface, the light emitting surface, and the stage,
The planar light emitting device has a function of individually causing the plurality of light emitting elements to emit light,
The photoelectric conversion device has a function of outputting data on the amount of light received by the light receiving surface in synchronization with light emission of the light emitting element,
An imaging device having no lens between the object to be observed and the light emitting surface. An imaging device having a planar light emitting device, a photoelectric conversion device, a light shielding member, and a stage,
The planar light emitting device has a plurality of light emitting elements arranged in a matrix,
The photoelectric conversion device has a light receiving surface,
The stage has translucency and has a function of supporting an object to be observed,
the light-emitting surface and the light-receiving surface of the planar light-emitting device are provided to face each other with the stage interposed therebetween,
The light shielding member is provided to cover the light receiving surface, the light emitting surface, and the stage,
The planar light emitting device has a function of individually causing the plurality of light emitting elements to emit light,
The photoelectric conversion device has a function of outputting data on the amount of light received by the light receiving surface in synchronization with light emission of the light emitting element,
An imaging apparatus having no lens between the observed object and the light-emitting surface and no lens between the observed object and the light-receiving surface.

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