JP2018133038A - Information processing device, control device, control method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically determine whether to change the number of ways when the number of ways is changeable.SOLUTION: An information processing device comprises: a storage part for storing data in a set associative system; a use history flag indicating whether or not the data are stored in at least one region among storage regions included in each line of the set associative system; a replacement flag indicating whether or not the removal of the data has been performed in each line; a way extension instruction part for determining whether to increase the number of ways in the set associative system on the basis of the value of the use history flag and the value of the replacement flag; and a way extension part for increasing the number of ways when the way extension instruction part determines to increase the number of ways.SELECTED DRAWING: Figure 5

Description

  The present invention relates to an information processing device, a control device, a control method, and a program.

Several techniques have been proposed in connection with cache memory control.
For example, Patent Document 1 discloses a store control device that makes it easy to control store data from a store buffer unit. The store control device receives store data in units of blocks from the processor, stores the data in the store buffer unit, and drives store data from the store buffer unit to the main storage device in units of lines that are a plurality of continuous blocks. When expelling store data, the store control device expells store data with priority given to ways in which all blocks in the line exist in the store buffer unit.

It is more preferable that such a store control apparatus can cope with a case where the number of ways is insufficient.
In this regard, Patent Document 2 discloses a cache system that can change the number of sets and the number of ways by a set associative method. This cache system includes i sets of m ways and n sets of cache arrays, and changes the number of sets and the number of ways by controlling selection of sets and selection of ways. i, m, and n may all be multipliers of 2.

JP 2014-052754 A JP-A-2005-293300

  More preferably, when the number of ways can be changed as in the cache system described in Patent Document 2, it is possible to automatically determine whether to change the number of ways.

  An object of the present invention is to provide an information processing apparatus, a control apparatus, a control method, and a program that can solve the above-described problems.

  According to the first aspect of the present invention, an information processing device stores in at least one area of a storage unit that stores data by a set associative method and a storage area included in the row for each row of the set associative method. Based on a use history flag indicating whether data has been stored, a replace flag indicating whether data has been evicted in each row for each row, a value of the use history flag, and a value of the replace flag A way extension instruction unit that determines whether or not to increase the number of ways in the set associative method, and a way extension that increases the number of ways when the way extension instruction unit determines to increase the number of ways. A section.

  According to the second aspect of the present invention, the control device stores data in at least one of the storage areas included in the row for each row of the set associative method of the storage unit that stores data in the set associative method. Of the way in the set associative method based on the value of the use history flag indicating whether or not the data has been stored and the value of the replace flag indicating whether or not data has been evicted in the row for each row. A way expansion instructing unit that determines whether or not to increase the number, and a way expansion unit that increases the number of ways when the way expansion instructing unit determines to increase the number of ways.

  According to the third aspect of the present invention, the control method includes data stored in at least one of the storage areas included in the row for each row of the set associative method of the storage unit that stores data by the set associative method. Of the way in the set associative method based on the value of the use history flag indicating whether or not the data has been stored and the value of the replace flag indicating whether or not data has been evicted in the row for each row. It is determined whether or not to increase the number, and when it is determined to increase the number of ways, the method includes increasing the number of ways.

  According to the fourth aspect of the present invention, there is provided a program for controlling a storage unit that stores data by a set associative method, to store at least one of storage areas included in the row for each row of the set associative method. The set associative based on a value of a use history flag indicating whether data is stored in one area and a value of a replace flag indicating whether data is evicted in the row for each row. This is a program for determining whether to increase the number of ways in the system and increasing the number of ways when it is determined to increase the number of ways.

  According to the present invention, when the number of ways can be changed, it is possible to automatically determine whether or not to change the number of ways.

It is a schematic block diagram which shows the structural example of the information processing apparatus which concerns on embodiment of this invention. It is a figure which shows the example of the data structure of the request which the central processing unit which concerns on the same embodiment outputs. It is a schematic block diagram which shows the structural example of the merge circuit which concerns on the same embodiment. It is a figure which shows the example of the store data by which the merge process which concerns on the same embodiment was carried out. It is a schematic block diagram which shows the structural example of the store buffer which concerns on the embodiment. It is a figure which shows the example of the data structure of the data which the address array which concerns on the same embodiment memorize | stores. It is a figure which shows the structural example of the entry full detection circuit based on the embodiment. It is a figure which shows the example of the production | generation rule at the time of the eviction control circuit concerning the same embodiment producing | generating an eviction instruction signal. It is a figure which shows the 1st example of operation | movement of the information processing apparatus at the time of the load which concerns on the embodiment. It is a figure showing the 2nd example of operation of an information processor at the time of loading concerning the embodiment. It is a figure which shows the example of the process sequence of the information processing apparatus in case the store buffer which concerns on the embodiment memorize | stores store data. It is a figure which shows the example of the process sequence of information processing apparatus in case the store buffer which concerns on the embodiment performs the eviction process of a store request. It is a figure which shows the example of the process sequence which the store buffer based on the embodiment expands the way of an address array and a data array. It is a figure which shows the 1st example of the value of the use log | history flag which concerns on the embodiment, and a replacement flag. It is a figure which shows the 1st example of a structure of the address array after way expansion concerning the embodiment. It is a figure which shows the 2nd example of the value of a use log | history flag and a replacement flag which concerns on the embodiment. It is a figure which shows the 2nd example of a structure of the address array after way expansion concerning the embodiment. It is a figure which shows the example of the minimum structure of the information processing apparatus which concerns on this invention. It is a figure which shows the example of the minimum structure of the control apparatus which concerns on this invention.

Hereinafter, although embodiment of this invention is described, the following embodiment does not limit the invention concerning a claim. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.
FIG. 1 is a schematic configuration diagram illustrating a configuration example of an information processing apparatus according to an embodiment of the present invention. As shown in FIG. 1, the information processing apparatus 10 includes a central processing unit 1, a merge circuit 2, a store buffer 3, an entry full detection circuit 4, an eviction control circuit 5, and a main storage device. 6.

The central processing unit 1 is connected to the merge circuit 2 and the main storage device 6. The central processing unit 1 outputs a store request and store data to the merge circuit 2. The store request is an instruction for requesting writing of store data to the main storage device 6.
Further, the central processing unit 1 outputs a load request to the main storage device 6 via the merge circuit 2 and receives load data from the main storage device 6. The load request is an instruction for requesting reading of data from the main storage device 6. The load data is data read from the main storage device 6 in response to the load request.
Hereinafter, store requests and load requests are collectively referred to as requests.

The data length of the store data that the central processing unit 1 outputs in response to the store request is shorter than the data length of the load data that the main storage device 6 outputs in response to the load request. In the following, an example will be described in which the data length of the store data output from the central processing unit 1 is 8 bytes (B) and the data length of the load data output from the main storage device 6 is 128 bytes. However, neither the data length of the store data output from the central processing unit 1 nor the data length of the load data output from the main storage device 6 is limited to a specific data length. The data length of the store data output from the central processing unit 1 only needs to be shorter than the data length of the load data output from the main storage device 6. Furthermore, it is preferable that the data length of the load data output from the main storage device 6 is an integral multiple of the data length of the store data output from the central processing unit 1, but the present invention is not limited to this.
Hereinafter, data whose data length is the data length of the load data output from the main storage device 6 is referred to as a line. The data length of the line is referred to as the line length.

FIG. 2 is a diagram illustrating an example of a data structure of requests (store request and load request) output from the central processing unit 1. As shown in FIG. 2, the request output from the central processing unit 1 includes a command and an address.
The command indicates an operation instructed to the main storage device 6. Specifically, the command indicates a load or store operation instruction.

The address indicates an address in the main storage device 6. In the case of a load request, an address indicating a position where the main storage device 6 should read the load data is stored in the address column. In the case of store data, an address indicating a position where the main storage device 6 should store the store data is stored in the address column.
The request address can be divided into an upper address, a middle address, and a lower address.

As will be described later, the store buffer 3 stores store data by the set associative method, and the intermediate address is used as an index in the set associative. That is, the intermediate address is associated with the row in the set associative one-on-one.
The upper address is used as a tag in the set associative. That is, the upper address is used for distinguishing storage areas that are included in the number of ways in one row by set associative.

A position in the storage area of the main storage device 6 can be designated in units of lines by a combination of the upper address and the middle address, and the lower address indicates a position in the line.
Since the store buffer 3 and the main storage device 6 process the data in units of lines, the lower address is ignored. On the other hand, as described above, the central processing unit 1 outputs store data in units smaller than a line. The merge circuit 2 uses the lower address to align the store data on the line when the store data output from the central processing unit 1 is merged into the line.

The merge circuit 2 is connected to the central processing unit 1 and the store buffer 3. The merge circuit 2 outputs the request output from the central processing unit 1 to the store buffer 3.
When the central processing unit 1 outputs a store request, the merge circuit 2 merges the store data with the data stored in the store buffer 3.
Here, the store buffer 3 and the main storage device 6 input / output data in line units, whereas the store data is shorter than the line length as described above. Therefore, when the store buffer 3 stores a line including the address where the store data is to be stored, the merge circuit 2 reads this line from the store buffer 3. Then, the merge circuit 2 writes the store data at the position specified by the address of the store request in the read line. The merge circuit 2 outputs the line in which the store data has been written by a store request to the store buffer 3, and the store buffer 3 replaces (overwrites) the line read to the merge circuit 2 with the line output by the merge circuit 2. .

FIG. 3 is a schematic configuration diagram showing a configuration example of the merge circuit 2. In the example of FIG. 3, the merge circuit 2 includes a shifter 201 and a merger 202.
The shifter 201 shifts store data according to a lower address indicating an address in the line. As a result, the shifter 201 performs alignment on the line of the store data output from the central processing unit 1.

The merger 202 updates the data in the corresponding area in the store data for each line. That is, the merger 202 merges the store data output from the central processing unit 1 with the store data in units of lines stored in the store buffer 3 based on the alignment by the shifter 201.
The merger 202 outputs the merged line-unit store data to the store buffer 3. The store buffer 3 overwrites the store data in units of lines output from the merger 202 in the storage area from which the store data is read before merging.

FIG. 4 is a diagram illustrating an example of store data that has undergone merge processing. In the example of FIG. 4, the central processing unit 1 outputs 8-byte store data together with the store request. On the other hand, the main storage device 6 uses a line obtained by dividing the storage area of the main storage device 6 every 128 bytes as a unit for data input / output.
When the central processing unit 1 requests the main storage device 6 to store 24 bytes of data, the central processing unit 1 uses the 24 bytes of data as 8 stored data 1, 2 and 3 in FIG. Divide into bytes and output 3 store requests. The store data 1, 2 and 3 are originally continuous data and are data to be stored in the same line in the main storage device 6.

If, every time the store buffer 3 receives a store request from the central processing unit 1, data is read from the main storage device 6 in units of lines, and data in units of lines reflecting the store request is written back, the main storage device 6 Data reading and data writing to the main memory 6 must be performed three times.
On the other hand, the store buffer 3 reads the data from the main storage device 6 in line units, and generates and generates data reflecting all three store requests from the central processing unit 1 as shown in FIG. If data is written back, data reading from the main storage device 6 and data writing to the main storage device 6 are each performed once. Therefore, the store buffer 3 reflects the store request from the central processing unit 1 on the data read from the main storage device 6 and then immediately outputs the store request to the store buffer 3 itself without outputting the store request to the main storage device 6. store. In the case of stores on the same line, the merge circuit 2 performs a merge process. The store buffer 3 outputs a store request to the main storage device 6 when an event that causes eviction occurs.

The store buffer 3 is connected to the merge circuit 2, the entry full detection circuit 4, the eviction control circuit 5, and the main storage device 6. The store buffer 3 functions as a cache memory of the main storage device 6 and stores store data to the main storage device 6 by a set associative method.
When the load request is acquired, the store buffer 3 performs address comparison between the load request and the store request in the store buffer 3. If the addresses match, the store buffer 3 reads the store data at the matched address and outputs it to the main storage device 6 together with the store request. Further, the store buffer 3 reads the store data and outputs it to the merge circuit 2, and stores the merged store data that is the output of the merge circuit 2 in the original storage location of the store buffer 3. Further, the store buffer 3 outputs entry information indicating the data storage status in the store buffer 3 to the entry full detection circuit 4. Further, the store buffer 3 outputs store data to the main storage device 6 in accordance with an instruction from the eviction control circuit 5.

  FIG. 5 is a schematic configuration diagram illustrating a configuration example of the store buffer 3. In FIG. 5, the store buffer 3 includes an address array 301, a data array 302, an address replacement circuit 303, an address selection circuit 304, a register 305, an entry selection circuit 306, array control circuits 307 and 308, A use history flag register 309, a replace flag register 310, and a way expansion instruction circuit 311 are provided.

The combination of the address array 301 and the data array 302 constitutes a set associative storage device, and temporarily stores store requests and store data. The address array 301 and the data array 302 correspond to examples of storage units.
The address array 301 stores the address of the store request and the merge state of the store data.

FIG. 6 is a diagram illustrating an example of a data structure of data stored in the address array 301. As shown in FIG. 6, the address array 301 stores data in the format of address + valid byte information.
Here, the valid byte information is information indicating the position of the merged portion of the store data in units of lines in units of 8 bytes. Here, 8 bytes is an example of the data length of the store data from the central processing unit 1.

For example, when the merge circuit 2 merges the 128-byte store data in the store buffer 3 in units of 8 bytes, the merged 8 bytes are set to “1” using 16 (= 128 ÷ 8) bits as valid byte information. It shows with. 128 bytes here is an example of a line length.
When the valid byte information is “1” for all 16 bits, it indicates completion of line merging. When the merging of the lines is completed, the lines can be stored in the main storage device 6 without performing a process such as masking.

The storage area of the address array 301 is divided into areas of m rows × n columns (m and n are positive integers), and one address is stored in one area. Each row of the address array 301 is associated with the intermediate address value in the store request on a one-to-one basis, and the address of the store request is stored in the storage area of the row corresponding to the intermediate address value. Since each row has n address storage areas, the address array 301 can store up to n addresses having the same intermediate address value and different upper addresses.
Hereinafter, each row of the address array 301 and each row of the data array 302 are referred to as entries.

  In the area of the address array 301, a value that can be distinguished from the address value is stored in an area in which a valid address value is not stored. As a value that can be distinguished from the address value, for example, a negative integer value can be used, but is not limited thereto. A value distinguishable from the address value indicates that the area is a free area. The empty area here is an area where new data can be written.

  The store buffer 3 writes and reads data in units of lines in accordance with the lines of the main storage device 6. For this reason, the store buffer 3 ignores the lower address of the store request. That is, if the upper address value and the middle address value are the same, the store buffer 3 treats the same address value even if the lower address value is different, and performs processing such as data reading.

The data array 302 stores store data.
Similarly to the address array 301, the storage area of the data array 302 is also divided into areas of m rows × n columns. Each row of the data array 302 has a one-to-one correspondence with each row of the address array 301, and each column of the data array 302 has a one-to-one correspondence with each column of the address array. As a result, the address array 301 and the data array 302 constitute an n-way set associative storage device.

When the address replacement circuit 303 receives the eviction instruction signal output from the eviction control circuit 5, the address replacement circuit 303 replaces the address indicated in the request with the address indicated in the eviction instruction signal.
The address selection circuit 304 selects one of the address values output by the address array 301 for each way based on the address indicated in the request. The address selection circuit 304 generates a store request for the main storage device 6 based on the selected address and outputs it to the main storage device 6.

The register 305 temporarily stores the load request. When an entry having the same address as the load request is evicted from the address array 301, the register 305 temporarily waits for the load request to prevent the load request from overtaking the store request.
The entry selection circuit 306 controls each part of the store buffer 3 in response to the request output from the merge circuit 2 and the eviction instruction signal output from the eviction control circuit 5.

Array control circuits 307 and 308 control reading and writing of store requests (address values and store data) to the address array 301 and the data array 302, respectively.
Specifically, the array control circuit 307 reads the address value included in the request or eviction instruction signal, and selects the corresponding row of the address array 301 based on the intermediate address value. The array control circuit 308 reads the address value included in the request or eviction instruction signal, and selects the corresponding row of the data array 302 based on the intermediate address value.

When reading a store request, the array control circuit 307 controls the address array 301 to output the address value of each area of the selected row. Further, the array control circuit 308 controls the data array 302 so as to output store data of each area of the selected row.
When writing a store request, the array control circuit 307 selects a free area from the selected row area and writes the data shown in FIG. 6 in the selected free area. In addition, the array control circuit 308 writes the store data output from the merge circuit 2 in the same row and the same column area as the address array 301 area in which the address is written in the data array 302 area.

  The array control circuit 307 counts the number of stored addresses for each row of the address array 301, and generates entry information including the count result and an address value indicating the row. The array control circuit 307 outputs the generated entry information to the entry full detection circuit 4. The array control circuit 307 generates entry information, for example, at predetermined intervals and outputs the entry information to the entry full detection circuit 4.

The array control circuits 307 and 308 control the configuration of the storage areas of the address array 301 and the data array 302. Specifically, the array control circuits 307 and 308 determine the usage state of the address array 301 and the data array 302 based on the information in the usage history flag register 309 and the replacement flag register 310. The array control circuits 307 and 308 change the number of rows and the number of columns in the set associative memory based on the determination result. For example, the array control circuits 307 and 308 replace the storage area of m rows × n columns with (m / 2) rows × 2n columns. Thereby, each array can be handled as a storage area having an area of m / 2 rows in 2n ways.
The array control circuits 307 and 308 correspond to an example of a way expansion unit and increase the number of ways. Specifically, the array control circuits 307 and 308 increase the number of ways by replacing a way in one row with a way that follows an existing way in another row.

  The usage history flag register 309 has a 1-bit register for each row of the address array 301. The usage history flag register 309 sets the value of the corresponding register to “1” when data is stored in any of the n storage areas of one row of the address array 301. On the other hand, when none of the n storage areas in one row of the address array 301 is used, the usage history flag register 309 sets the value of the corresponding register to “0”.

  The replace flag register 310 has a 1-bit register for each row of the address array 301. The replace flag register 310 corresponds to a case where a store request is output from the central processing unit 1 and entry eviction occurs in a state where n storage areas of one row of the address array 301 are all filled with entries. Set the register value to "1". In other cases, the replace flag register 310 sets the value of the register to “0”.

The way expansion instruction circuit 311 receives the flags of the use history flag register 309 and the replace flag register 310 as input, generates a way expansion instruction signal, and sends it to the array control circuits 307 and 308. The way expansion instruction circuit 311 corresponds to an example of a way expansion instruction unit.
When the array control circuits 307 and 308 receive the way expansion instruction signal from the way expansion instruction circuit 311, the storage areas of the address array 301 and the data array 302 are replaced with the preset number of rows and columns to control each entry. For example, the array control circuits 307 and 308 replace the memory area of m rows × n columns with (m / 2) rows × 2n columns as described above.
Each unit that controls the address array 301 and the data array 302 may be configured as a control device and incorporated in the information processing apparatus 10. In particular, the way expansion instruction circuit 311 and the array control circuits 307 and 308 may be included in the control device.

The entry full detection circuit 4 is connected to the store buffer 3 and the eviction control circuit 5. The entry full detection circuit 4 receives entry information from the store buffer 3 and determines entry full. If it is determined that the entry is full, the entry full detection circuit 4 outputs entry full information to the eviction control circuit 5.
As will be described later, the entry here is a row of a set associative storage device included in the store buffer 3. The entry information here is information indicating the number of addresses stored in one row of the set associative storage device. The number of addresses here indicates the number of store data in units of lines stored in one row. The entry full here means that data is stored in any of the storage areas corresponding to the number of ways included in one row.

FIG. 7 is a diagram illustrating a configuration example of the entry full detection circuit 4. In the example of FIG. 7, the entry full detection circuit 4 includes a register 401 and a comparison circuit 402.
The register 401 stores in advance the number of ways in the store buffer 3 (the number of columns in the address array 301).
The comparison circuit 402 compares the number of addresses (store request number) stored in each row of the address array 301 indicated by the entry information output from the store buffer 3 with the number of ways stored in the register 401. When a line having more addresses than the number of ways is detected, the comparison circuit 402 outputs “1” indicating entry full and an address value indicating the line as an entry full signal.

The eviction control circuit 5 is connected to the store buffer 3 and the entry full detection circuit 4. The eviction control circuit 5 performs store data eviction determination based on the entry full information output by the entry full detection circuit 4. The eviction determination here is a determination as to whether or not it is necessary to output data from the store buffer 3 to the main storage device 6. When the central processing unit 1 further outputs a store request while the entry of the store buffer 3 is full, it is necessary to make a space for storing the store request in the store buffer 3. The output of data from the store buffer 3 to the main storage device 6 to create this empty space is called data eviction. The determination of whether or not it is necessary to perform the eviction is referred to as an eviction determination.
When it is determined that eviction is necessary, the eviction control circuit 5 outputs an eviction instruction signal to the store buffer 3.

FIG. 8 is a diagram illustrating an example of a generation rule when the eviction control circuit 5 generates an eviction instruction signal. In the example of FIG. 8, when the acquired entry full information indicates entry full, the eviction control circuit 5 sets the value of the eviction instruction signal to “1” + address value. This value “1” indicates that eviction is necessary. The address value indicates data to be evicted.
On the other hand, when the acquired entry full information indicates that the entry is not full, the eviction control circuit 5 sets the value of the eviction instruction signal to “0”. The value “0” of the eviction instruction signal indicates that eviction is unnecessary.

The main storage device 6 is connected to the central processing unit 1 and the store buffer 3. The main storage device 6 inputs and outputs data according to the request output from the store buffer 3.
When the store buffer 3 outputs a load request, the main storage device 6 reads the load data according to the address information in the request and outputs it to the central processing unit 1. When the store buffer 3 outputs a store request, the main storage device 6 holds store data according to the address information in the request. Specifically, the main storage device 6 stores the store data in the storage area indicated by the address information in the request among the storage areas of the main storage apparatus 6 itself.

Next, the operation of the information processing apparatus 10 will be described.
FIG. 9 is a diagram illustrating a first example of the operation of the information processing apparatus 10 during loading. FIG. 9 shows an example where the store buffer 3 does not store data corresponding to the address indicated by the load request.
In the process of FIG. 9, the central processing unit 1 outputs a load request, and the merge circuit 2 transfers this load request as it is to the store buffer 3 (sequence S111).

The store buffer 3 that has acquired the load request compares the address of the load request with the address of the store request in the store buffer, and determines whether or not the store data needs to be evicted (sequence S112).
As described with reference to FIG. 5, the store buffer 3 has an n-way (n is an integer such as 1, 2, 4, 8, etc.) set associative cache configuration. When determining whether or not the eviction is necessary, the store buffer 3 refers to the middle address in the load request, identifies the row of the address array 301, and reads the store request from each way. The store buffer 3 determines whether or not the read store request address matches the upper address in the load request. In the example of FIG. 9, the store buffer 3 determines that the addresses do not match and eviction is unnecessary.

The store buffer 3 determined not to be purged sends the load request to the main storage device 6 as it is (sequence S113).
The main storage device 6 reads out the load data corresponding to the address in the received load request and outputs it to the central processing unit 1 (sequence S114).
After the sequence S114, the process of FIG. 9 ends.

FIG. 10 is a diagram illustrating a second example of the operation of the information processing apparatus 10 during loading. FIG. 10 shows an example in which the store buffer 3 stores data corresponding to the address indicated by the load request.
The sequence S121 in FIG. 10 is the same as the sequence S111 in FIG.

The store buffer 3 that has acquired the load request determines whether or not the store data should be evicted (sequence S122), as in the case of the sequence S112 in FIG.
In the example of FIG. 10, the store buffer 3 determines that the addresses match and needs to be evicted.

  The store buffer 3 that has been determined to be evicted saves the load request in the register 305 (sequence S123). Then, the store buffer 3 reads out the store request and store data at the address determined to match in the sequence S122 and outputs them to the main storage device 6 (sequence S124). The main storage device 6 stores the store data according to the store request (sequence S125).

Thereafter, store buffer 3 transfers the saved load request to main storage device 6 (sequence S126). The main storage device 6 reads the load data in accordance with the load request and outputs it to the central processing unit 1 (sequence S127).
In this way, the store buffer 3 outputs a store request to the main storage device 6 to execute the store, and then outputs the load request to the main storage device 6 to prevent the subsequent load request from overtaking the store request. can do.
After the sequence S127, the process of FIG.

FIG. 11 is a diagram illustrating an example of a processing procedure of the information processing apparatus 10 when the store buffer 3 stores store data.
In the process of FIG. 11, the central processing unit 1 outputs a store request to the merge circuit 2 (sequence S211).
The merge circuit 2 that has acquired the store request reads out store data in units of lines corresponding to the address indicated by the store request from the store buffer 3 (sequence S212).

Then, the merge circuit 2 merges the store data of the store request with the store data in units of lines read from the store buffer 3 (sequence S213).
The merge circuit 2 outputs a store request that combines the merged line-unit store data and address to the store buffer 3 (sequence S214). The store buffer 3 overwrites the store request from the merge circuit 2 with the store request from which the store data has been read in sequence S212 (sequence S215).
Further, the store buffer 3 sets the value of the use history flag corresponding to the area where the data is written to “1” (sequence S216).
After sequence S216, the process in FIG. 11 is terminated.

  If the store buffer 3 does not store store data that can be merged, the merge circuit 2 shapes the store data from the central processing unit 1 into store data in units of lines. The merge circuit 2 stores in the store buffer 3 a store request that combines the shaped store data and the address. Then, the store buffer 3 sets the value of the use history flag corresponding to the area where the data is written to “1”.

FIG. 12 is a diagram illustrating an example of a processing procedure of the information processing apparatus 10 when the store buffer 3 performs a store request eviction process.
In the example of FIG. 12, the store buffer 3 outputs entry information to the entry full detection circuit 4 (sequence S221). The entry full detection circuit 4 determines whether the entry is full based on the entry information from the store buffer 3 (sequence S222). In the example of FIG. 12, the entry full detection circuit 4 detects entry full. That is, the entry full detection circuit 4 determines that the entry is full.

The entry full detection circuit 4 determined to be entry full outputs an entry full signal to the eviction control circuit 5 (sequence S223).
The eviction control circuit 5 that has acquired the entry full signal performs the eviction determination (sequence S224). In the example of FIG. 12, the eviction control circuit 5 determines that eviction is necessary. The eviction control circuit 5 that has determined that eviction is necessary outputs an eviction instruction signal to the store buffer 3 (sequence S225).

The store buffer 3 evoke store data in accordance with the eviction instruction signal (sequence S226). The store buffer 3 stores store data in units of lines, and outputs the store data in units of lines to the main storage device 6 in accordance with the eviction instruction signal.
Specifically, the row of the address array 301 is specified by referring to the middle address in the store buffer 3 and the store request. The store buffer 3 compares whether the address read from each way in the specified row matches the upper address in the store request. The store buffer 3 outputs the data corresponding to the matched address among the line-unit store data read from the data array 302. Normally, the store buffer 3 reads store data corresponding to the middle address and the upper address indicated in the store request. On the other hand, when the eviction instruction signal is acquired, the address replacement circuit 303 of the store buffer 3 replaces the address indicated by the eviction instruction signal. The store buffer 3 reads store data corresponding to the replaced address.

The store buffer 3 that has purged store data sets the value of the replace flag corresponding to the area from which data has been purged to “1” (sequence S227).
The main storage device 6 that has acquired the store request evicted from the store buffer 3 stores the store data in units of rows in the area corresponding to the address in the acquired store request (sequence S228).
After the sequence S228, the process of FIG.

  Various existing methods can be used as a method for selecting a store request to be expelled by the store buffer 3. For example, the store buffer 3 may evict store requests by FIFO (First-In First-Out). In this case, the store buffer 3 that has received the eviction instruction signal expels the oldest store request among the store requests stored in the row indicated by the eviction instruction signal. The store buffer 3 stores a subsequent store request in an empty area from which the store request has been evicted.

FIG. 13 is a diagram illustrating an example of a processing procedure in which the store buffer 3 extends the way of the address array 301 and the data array 302.
In the process of FIG. 13, the way extension instruction circuit 311 reads the use history flag from the use history flag register 309 (sequence S231), and reads the replace flag from the replace flag register 310 (sequence S232).

  Then, the way extension instruction circuit 311 determines whether or not to extend the way based on the use history flag and the replace flag (sequence S233). The way expansion here is to increase the number of ways. The number of ways here corresponds to the number of columns in the set associative, and the number of columns increases when the way is expanded. In the example of FIG. 13, the way expansion instruction circuit 311 has decided to expand the way.

The way extension instruction circuit 311 that has decided to extend the way outputs a way extension instruction to each of the array control circuits 307 and 308.
Upon receiving the way expansion instruction, the array control circuits 307 and 308 extend the way of the address array and the data array (sequence S235).
After sequence S235, the process of FIG.

  FIG. 14 is a diagram illustrating a first example of values of the use history flag and the replace flag. In the example of FIG. 14, the address array 301 is in a state before way expansion. In the example of FIG. 14, the number of rows (number of indexes) of the address array 301 is 8, and the number of columns (number of ways) is 4. Since the number of rows and columns of the data array 302 are set to be the same as the number of rows and columns of the address array 301, the data array 302 is also in a state before the way expansion.

  In the example of FIG. 14, the value of the replace flag in each row included in the area A11 is “1”. The value “1” of the replace flag indicates that the store request storage area (empty way) is insufficient in the corresponding row and the eviction is performed. On the other hand, the value of the use history flag of each row included in the area A12 is “0”. The use history flag value “0” indicates that the storage area of the corresponding row is not used.

As described above, the storage area for the store request is insufficient in each row included in the area A11, and the storage area for the store request remains unused in each line included in the area A12.
Therefore, the store buffer 3 collects the row of the area A11 and the row of the area A12.
For example, when detecting the state of the use history flag and the replace flag shown in FIG. 14, the way expansion instruction circuit 311 generates a way expansion instruction signal and outputs it to the array control circuits 307 and 308. When the array control circuits 307 and 308 obtain the way expansion instruction signal from the way expansion instruction circuit 311, the number of rows (number of indexes) of the address array 301 and the data array 302 is set to 4, and the number of columns (number of ways) is set to 8. To do. Therefore, the array control circuits 307 and 308 treat the ways 0 to 3 of each row in the area A12 as the ways 4 to 7 of each row of the area A11.

FIG. 15 is a diagram illustrating a first example of the configuration of the address array 301 after way expansion.
In the address array 301 shown in FIG. 15, one row of the area A11 and one row of the area A12 are combined (combined into one row), and the number of ways is doubled. In particular, a line whose replace flag value is “1” and a line whose use history flag value is “0” are combined. The store buffer 3 changes the configuration of the data array 302 in the same manner as the address array.
As the number of ways increases, the address array 301 in the example of FIG. 15 can increase the number of store request storage areas per row, and the number of store request evictions is expected to decrease. .

For example, when the number of rows whose replace flag value is “1” is equal to or greater than a predetermined threshold and the number of rows whose use history flag value is “0” is equal to or greater than a predetermined threshold, the store buffer 3 Change the number of rows to half and the number of columns to double. As a changing method, for example, a known method such as a method disclosed in JP-A-2005-293300 can be used.
For example, the store buffer 3 includes the first bit of the middle address in the upper address, thereby halving the number of rows in the array and doubling the number of columns.
As described above, the information processing apparatus 10 can improve the use efficiency of the store buffer 3 by reducing the number of ways by using the usage history flag and the replace flag to reduce the number of ways. By improving the use efficiency of the store buffer, the store data can be efficiently compressed, and the access efficiency to the main storage device 6 can be improved.

  FIG. 16 is a diagram illustrating a second example of values of the use history flag and the replace flag. In the example of FIG. 16, the address array 301 is in a state before way expansion. In the example of FIG. 16, the address array 301 has 8 rows and 4 columns. Since the number of rows and columns of the data array 302 are set to be the same as the number of rows and columns of the address array 301, the data array 302 is also in a state before the way expansion.

In the example of FIG. 16, the value of the replace flag in the row included in the area A21 is “1”. On the other hand, the value of the use history flag of the row included in the area A22 is “0”.
From the values of the replacement flag and the usage history flag, the storage area for the store request is insufficient in the line included in the area A21, and the storage area for the store request remains unused in the line included in the area A22.
Therefore, the store buffer 3 collects the row of the area A21 and the row of the area A22.

FIG. 17 is a diagram illustrating a second example of the configuration of the address array 301 after way expansion.
The example of FIG. 17 is different from the case of FIG. 15 in that way extension is performed for only one certain row (Index).
In order to change the state of the address array 301 from the state of FIG. 16 to the state of FIG. 17, for example, the determination condition of the way expansion instruction circuit 311 is (1) “1” and
(2) Assume that all other ways in a row are empty. The way expansion instruction circuit 311 outputs a way expansion instruction signal when this condition is satisfied.

The way expansion instruction circuit 311 outputs the way expansion instruction signal and the target index number to the array control circuits 307 and 308. The array control circuits 307 and 308 change the way only for the target index.
In this way, by performing way expansion on only one certain index, the information processing apparatus 10 also has a case where there are a shortage of ways in only some rows and a case where there is a vacancy in only some rows. Way expansion can be performed to improve the utilization efficiency of the store buffer 3. In addition, the number of ways remains other than the lines combined into one line, and the load for searching the area in the line can be relatively small.

As described above, the usage history flag of the usage history flag register 309 stores data in at least one of the storage areas included in the row for each row of the set associative method in the address array 301 and the data array 302. Indicates whether or not Further, the replace flag in the replace flag register 310 indicates whether or not data has been evicted in each row. The way expansion instruction circuit 311 determines whether to increase the number of ways in the set associative method based on the value of the use history flag and the value of the replace flag. The array control circuits 307 and 308 increase the number of ways when the way expansion instruction circuit 311 determines to increase the number of ways.
Thus, the information processing apparatus 10 can automatically determine whether or not to increase the number of ways with reference to the use history flag and the replace flag. In addition, the information processing apparatus 10 includes the use history flag and the replace flag, so that it is possible to detect a line where the area is insufficient and a line where the area is not used. By combining the lines with insufficient area and the lines where the area is not used into one line, it is possible to increase the hit rate and reduce the number of times data is expelled. Further, the memory access efficiency can be improved by combining the lines having insufficient areas and the lines in which the areas are not used into one line.

  Further, the array control circuits 307 and 308 halve the number of set associative rows (number of indexes) and double the number of ways (number of columns). Thereby, the number of ways per line can be kept the same. Since the number of ways per row is the same, the array control circuits 307 and 308 can control the address array 301 and the data array 302 with a relatively simple process.

In addition, the array control circuits 307 and 308 indicate that the use history flag in the set associative line indicates that the data is stored in the area, and the replace flag indicates that the data has been evicted. Combine lines into a single line.
By performing way expansion on only one index in this way, the information processing apparatus 10 can also execute ways even when there are insufficient ways in only some rows and when there are vacancies in only some rows. The use efficiency of the store buffer 3 can be improved by expanding. In addition, the number of ways remains except for one line, so that the load for searching for an area in the line can be relatively small.

Next, the minimum configuration of the present invention will be described with reference to FIGS.
FIG. 18 is a diagram showing an example of the minimum configuration of the information processing apparatus according to the present invention. The information processing apparatus 20 illustrated in FIG. 18 includes a storage unit 21, a use history flag 22, a replace flag 23, a way expansion instruction unit 24, and a way expansion unit 25.
With this configuration, the storage unit 21 stores data using the set associative method. The usage history flag 22 indicates whether data is stored in at least one of the storage areas included in the row for each set associative method. The replace flag 23 indicates whether or not data has been evicted in each row. The way expansion instruction unit 24 determines whether to increase the number of ways in the set associative method based on the value of the usage history flag 22 and the value of the replace flag 23. The way expansion unit 25 increases the number of ways when the way expansion instruction unit 24 determines to increase the number of ways.

  Thereby, the information processing apparatus 20 can automatically determine whether or not to increase the number of ways with reference to the use history flag 22 and the replace flag 23. Further, since the information processing apparatus 20 includes the use history flag 22 and the replace flag 23, it is possible to detect a line where the area is insufficient and a line where the area is not used. By combining the lines with insufficient area and the lines where the area is not used into one line, it is possible to increase the hit rate and reduce the number of times data is expelled. Further, the memory access efficiency can be improved by combining the lines having insufficient areas and the lines in which the areas are not used into one line.

FIG. 19 is a diagram showing an example of the minimum configuration of the control device according to the present invention. The control device 30 illustrated in FIG. 19 includes a way expansion instruction unit 31 and a way expansion unit 32.
With this configuration, the way extension instruction unit 31 stores data in at least one of the storage areas included in the row for each row of the set associative method in the storage unit that stores data in the set associative method. Whether or not to increase the number of ways in the set associative method based on the value of the usage history flag indicating whether or not and the value of the replace flag indicating whether or not data has been evicted in each row. To decide. When the way expansion instruction unit 31 determines to increase the number of ways, the way expansion unit 32 increases the number of ways.

  Thereby, the control device 30 can automatically determine whether or not to increase the number of ways with reference to the use history flag and the replace flag 23. In addition, the control device 30 can detect a line where the area is insufficient and a line where the area is not used by referring to the use history flag and the replace flag. By combining the lines with insufficient area and the lines where the area is not used into one line, it is possible to increase the hit rate and reduce the number of times data is expelled. Further, the memory access efficiency can be improved by combining the lines having insufficient areas and the lines in which the areas are not used into one line.

Note that a program for realizing all or part of the information processing devices 10 and 20 and the control device 30 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system. The processing of each unit may be performed by executing. Here, the “computer system” includes an OS and hardware such as peripheral devices.
The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. The program may be a program for realizing a part of the functions described above, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 Central processing unit 2 Merge circuit 3 Store buffer 4 Entry full detection circuit 5 Ejection control circuit 6 Main memory device 10 Information processing device 201 Shifter 202 Merger 301 Address array 302 Data array 303 Address replacement circuit 304 Address selection circuit 305 Register 306 Entry Selection circuit 307, 308 Array control circuit 309 Usage history flag register 310 Replace flag register 311 Way expansion instruction circuit 401 Register 402 Comparison circuit

Claims (6)

A storage unit for storing data in a set associative manner;
A usage history flag indicating whether data is stored in at least one of the storage areas included in the row for each row of the set associative method;
A replace flag indicating whether or not data has been evicted in the row for each row;
A way expansion instruction unit for determining whether to increase the number of ways in the set associative method based on the value of the use history flag and the value of the replace flag;
If the way extension instruction unit decides to increase the number of ways, a way extension unit that increases the number of ways;
An information processing apparatus comprising:   The information processing apparatus according to claim 1, wherein the way extension unit halves the number of rows in the set associative method and doubles the number of ways. In the set associative method line, the way extension unit indicates that the use history flag indicates that data has been stored in the area, and the replace flag indicates that the data has been evicted. Combine the lines shown in one line
The information processing apparatus according to claim 1 or 2. For each row of the set associative method of the storage unit that stores data in the set associative method, a value of a use history flag indicating whether or not data is stored in at least one of the storage areas included in the row; A way expansion instruction unit that determines whether or not to increase the number of ways in the set associative method based on the value of a replacement flag indicating whether or not data has been evicted in the row for each row;
If the way extension instruction unit decides to increase the number of ways, a way extension unit that increases the number of ways;
A control device comprising: For each row of the set associative method of the storage unit that stores data in the set associative method, a value of a use history flag indicating whether or not data is stored in at least one of the storage areas included in the row; For each row, based on the value of a replacement flag indicating whether or not data has been evicted in the row, determine whether to increase the number of ways in the set associative method,
If you decide to increase the number of ways, increase the number of ways,
Control method. To the computer that controls the storage unit that stores data in the set associative method,
For each row of the set associative method, a value of a use history flag indicating whether or not data is stored in at least one of the storage areas included in the row, and data is expelled in the row for each row. And whether to increase the number of ways in the set associative method based on the value of the replacement flag indicating whether or not
If you decide to increase the number of ways, increase the number of ways,
Program for.

Images