JPH04315235A - Cache data replace method and cache data replace device for cache memory - Google Patents

Abstract

PURPOSE:To improve the throughput of a multiprocessor system using a cache memory by reducing the waiting time of a processor by decreasing the number of times for transferring data between the cache memory and a main storage device at this system. CONSTITUTION:Replace memories 24 and 25 are provided to store history data for each block as a unit in the case of replacing cache data, and the respective replace memories store data showing the history of update and replace. Further, the data in this replace memory are reloaded even by an access state from another processor as well. In the case of replacing the cache data, the bit of the history data is discriminated, the block not updated, replaced or accessed from the other processor is preferentially replaced.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a cache memory replacement method for operating a processor at high speed using a shared memory shared bus type multiprocessor configuration, and in particular to an N (N≧2) way set associative write back type method. The present invention relates to a method and device for replacing data blocks in a cache memory.

0002

[Background Art] In order to make a processor operate at high speed,
It is common practice to arrange a cache memory, which has a small capacity but can operate at high speed, between a processor and a main storage device. The storage area of the main storage device is divided into a plurality of blocks, and some of the storage data of the plurality of blocks is loaded into the cache memory. The processor first accesses the cache memory, and if data at the accessed address exists on the cache memory, that is, when there is a cache hit, the processor directly accesses the data on the cache memory and reads or writes it. . Furthermore, when there is no data at the corresponding address on the cache memory, that is, when a cache miss occurs, a new block is read from the main memory and replaced with any old block already on the cache memory. This replacement is generally called a replacement. At this time, the method for determining which block to replace is called a replacement algorithm. This replacement algorithm uses the LRU (Least
FIFO (First In First O) method, which targets the block most recently read into the cache memory
t) method etc. are known.

[0003]Also, data on the cache memory may be updated by write access from the processor, but when replacing, all data in a certain block on the cache memory is written to the main memory at once. The method is called a write-back method. Note that write-back
) method is sometimes called a copy-back method. When the processor accesses the cache memory that can operate at high speed, the overall processing speed becomes faster.

[0004] In conventional cache memory, the above-mentioned LRU method and FI
The FO method is used, but these methods only focus on the frequency of data use and the order in which it was input, and check whether or not the data in the block to be replaced has changed, that is,
Replacement was performed by write-back regardless of whether writing was performed or not.

[0005]

[Problems to be Solved by the Invention] However, when data in the cache memory is unconditionally written back to the main memory during replacement, it takes time to write to the main memory, so the wait time of the processor increases. There was a problem that the system throughput decreased due to the increase in the amount of data. Furthermore, the LRU method and FIFO method have a problem in that the configuration becomes complicated.

In view of the above-mentioned problems, the present invention provides a data replacement method for a cache memory in a multiprocessor configuration by reducing the number of write-backs from a cache memory block in which data has been changed to the main storage device. The purpose is to reduce the number of data transfers between the processor and the main memory, thereby reducing processor latency and improving system throughput. A further object of the present invention is to increase the idle time of the shared bus, thereby reducing the cache response waiting time of the processor and the waiting time of the shared bus, thereby improving system throughput.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the method of replacing cache data in a cache memory of the present invention is such that a plurality of processors are provided for a common main storage device, and a cache memory is provided for each processor. In a cache data replacement method for a cache memory, the write operation to the cache memory is performed on blocks divided into a plurality of blocks, and the cache data of the written block is written to the main storage device at the time of replacement, A history data memory is provided for storing history data consisting of a plurality of bits corresponding to each block, and the bits of the history data are set to a first state in an initial state, and the cache data in the cache memory is changed, or , sets the bit corresponding to the block in the second state when it is replaced, and when data having the same address in the cache memory is updated by another processor, the bit corresponding to the block in the history data memory is set to the second state. The bit is set to the second state, and when replacing cache data, the cache data of the block whose history data bit is set to the first state is preferentially replaced.

[0008] Furthermore, the present invention provides a common main storage device with a plurality of processors, a cache memory for each processor, and write operations to the cache memory for blocks divided into a plurality of blocks. In a cache data replacement method for a cache memory in which cache data of a block that has been written is written to the main memory at the time of replacement or every time a write is made to the cache memory, history data consisting of multiple bits corresponding to each block is used. A history data memory is provided for storing the block, in which the bits of the history data are set to a first state in the initial state, the bits corresponding to the block are set to the second state by writing by the processor, and the bits of the history data are set to the second state by writing by the processor. When data having the same address in the cache memory is updated by the processor, the corresponding bit of the history data memory is set to the first state, and when replacing the cache data, the bit of the history data is set to the first state. The method is characterized in that the cache data of the block set to the first state is preferentially replaced.

Further, in the cache data replacement device for a cache memory of the present invention, a plurality of processors are provided for a common main storage device, a cache memory is provided for each processor, and a plurality of write operations to the cache memory are performed. In a cache data replacement device for a cache memory, in which cache data of a block that has been written to a block divided into blocks is written to the main storage device at the time of replacement,
A history data memory for storing history data consisting of multiple bits corresponding to each block, in which history data bits are set to a first state in an initial state, and a cache in a cache memory. means for detecting a signal indicating a data change or a signal indicating a data replacement and setting a bit corresponding to the block in the history data memory to a second state; means for detecting a signal indicating that data stored in the history data memory has been updated and setting a corresponding bit in the history data memory to a second state; and means for determining the contents of the history data memory when replacing cache data; The present invention is characterized in that it includes means for determining a block to preferentially replace cache data based on a bit in a state of 1.

[0010]Furthermore, in the present invention, a plurality of processors are provided for a common main storage device, a cache memory is provided for each processor, and a write operation to the cache memory is performed for a block divided into a plurality of blocks. History data consisting of multiple bits corresponding to each block is used in a cache data replacement device for a cache memory in which writing of the cache data of a block that has been written to the main memory is performed at the time of replacement or each time the cache data is written to the cache memory. a history data memory for storing history data, in which bits of the history data are set to a first state in an initial state;
means for detecting a signal indicative of a write by the processor and setting a bit of historical data corresponding to the block of the historical data memory to a second state; and having the same address in the cache memory by another processor. means for detecting a signal indicating that data has been updated and setting a corresponding bit in the history data memory to a first state; and means for determining the contents of the history data memory when replacing cache data; The present invention is characterized by providing means for determining a block to preferentially replace cache data based on the bits in the state.

[0011]

According to the present invention, in the initial state, the bits of the history data stored in the history data memory are set to, for example, "0". Then, when the cache data in the cache memory is changed or replaced, the corresponding bit is set to "1", for example. Also, when data having the same address in the cache memory is updated by another processor, the corresponding bit in the history data memory is set to "1", for example. When replacing cache data due to a cache miss, for example, a block that is set to "0",
That is, cache data in blocks that have not changed are replaced preferentially. The data in the block whose contents have been changed by the processor will eventually need to be replaced, but replacement requires writing back from the cache memory to the main memory, and this write back takes time. It takes. Therefore, in the present invention,
By preferentially replacing blocks whose cache data has not been changed, that is, blocks that do not require write-back, the rate at which blocks that require write-back are evicted from the cache memory is reduced. This reduces the number of write-backs and improves system throughput. Furthermore, since the latency time of the shared bus is reduced, system throughput is improved in a multiprocessor system with a shared memory shared bus.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, features of the present invention will be specifically explained based on embodiments with reference to the drawings.

FIG. 1 shows a schematic diagram of a cache memory to which the present invention is applied. In this embodiment, a 4-way set associative cache memory will be described as an example. The set associative method is a method for determining where on the cache memory the data on the main storage device should be associated, and the storage area of the cache memory and main storage device is divided into four blocks. The correspondence is made in units of blocks. Regarding the set associative method itself, for example,
Muraki, Kuroda, Shindo, "Cache Memory Methods and Trade-offs," Complete Guide to 32-Bit Microprocessors, Nikkei McGraw-Hill Publishing, pp. 242-265. In the set associative system, the cache memory is composed of a matrix with E rows and S columns, each of which has blocks as elements. E is called the number of elements, S is called the number of sets,
A method in which the number of elements is N is called an N-way set associative method. Note that E, S, and N are integers of 1 or more.

In FIG. 1, numeral 1 is a processor address section schematically showing real address information from a processor (not shown), and this processor address section 1 includes a tag address 2, a set address 3, and a word address 4. ing. The set address 3 from the processor address section 1 is supplied to the replacement circuit 5, the tag memory 6, the valid memory 7, and the memory main body 8a of the data memory 8. Further, the word address 4 is supplied to the selector 8b of the data memory 8.

The tag address 2 from the processor address unit 1 is compared with the tag data 13 from the tag memory 6 in a comparator 9, and when the two match, a cache hit signal 31 is output. This cache hit signal 31 is supplied to the sequencer 11, and the sequencer 1
1 outputs a data selection signal 12. This data selection signal 12 is supplied to the selector 8c of the data memory 8, and target cache data 14 is output from the data memory 8 based on the set address 3 and word address 4.

This embodiment has a multiprocessor configuration, and processor addresses 102 and 105 from different processors are sent to the address selector 1.
5, and the selected address 16 is set in the processor address section 1.

In the cache memory described above, when a cache miss occurs, the replacement circuit 5 reads a new block from the main memory and replaces it with any old block already on the cache memory. Hereinafter, the replacement circuit 5 will be explained in detail with reference to FIG. 2.

The replace circuit 5 includes an update history data replace memory 24 that stores a block of cache data accessed by the set address 3 from the processor address unit 1 shown in FIG. 1 and whose data has been updated; A replacement memory 25 for replacement history data that stores blocks of , a replacement determination circuit 28 that determines a block to be replaced in the event of a cache miss based on update history data 26 from the replacement memory 24 and replacement history data 27 from the replacement memory 25, etc. has been done. Replace data 29 is output from the replace determination circuit 28, and this replace data 29 is
5 as data, and is also supplied to the tag memory 6 and valid memory 7 (see FIG. 1).

[0019] Also, a replace signal (indicated by RP in the figure) 30 indicating that it is a replacement period, a cache hit signal (indicated by C-H in the figure) 31 indicating a hit in cache access, and a processor write signal (indicated by C-H in the figure). A replace update signal (indicated by R-wr in the figure) 33 is generated by an AND circuit 22 from a signal (indicated by P-wr in the figure) 21 . This replace update signal 33 is supplied to an OR circuit 37 together with a cache update signal (indicated by C-U in the figure) 36, and the output of the OR circuit 37 is supplied to the replace memory 24. The cache update signal 36 is a signal indicating that the cache memory has data at the same address as the address broadcast on the memory address bus 120 from another processor. In addition, a replace signal 30 and a cache miss signal (C-
A replace update signal (indicated by M) 32 to the replace memory 25 by an AND circuit 23
) 34 is generated.

The processor write signal 21 is output from the processor when the processor writes, and the replace signal 30 is output from the sequencer when cache data needs to be replaced (when there is a cache miss and the cache memory is full of valid data). It is output from 11. Further, the cache hit signal 31 is output from the sequencer 11 when there is a cache hit (when the cache hit signal 31 becomes valid), and the cache miss signal 32 is output from the sequencer 11 when there is a cache miss (when the cache hit signal 31 becomes valid).
output from the sequencer 11).

The bit width of the update history data 26, replacement history data 27, and replacement data 29 is the same as the number of sets, that is, the number of ways, and is 2 bits for 2-way and 4 bits for 4-way. In this embodiment, a 4-way case is explained.

The contents of the replace memory 24 are updated by broadcasting when the cache receives a write hit and when data is updated from other cache memories. Further, the contents of the replace memory 25 are updated when a data block is replaced due to a cache miss.

The replacement operation in the above-mentioned 4-way set associative cache memory will be explained below for each case. In this embodiment, the operation will be described when the present invention is applied to a shared memory shared bus type multiprocessor system as shown in FIG.

In FIG. 3, CPUs (central processing units) 101 and 111 and cache memory 104, respectively.
, 114, the plurality of processors 109, 119 have
memory address bus 120, memory data bus 121,
It is commonly connected to the control signal line 122. In addition, the plurality of processors 109 are connected to these buses, etc.
, 119 is connected.

In each processor 109, 119,
Each CPU 101, 111 and each cache memory 104,
114 refers to processor address buses 102, 112,
They are connected via processor data buses 103 and 113 and processor control signal lines 107 and 117. Also,
Each cache memory 104, 114 and each bus 120, 1
21, 122 are cache address buses 105, 11
5, cache data buses 106 and 116, and memory control buses 108 and 118.

For example, when processor 101 accesses cache memory 104, processor address 102 is input to replace circuit 5, tag memory 6, and data memory 8 by address selector 15 (see FIG. 1). It should be noted that here, in order to simplify the explanation, the address bus and the addresses on this address bus are indicated by the same reference numerals. When the processor 101 accesses the cache memory 104, the cache update signal 36 is never asserted.

[0027] Each operation when the cache memory hits or misses will be explained below.

(1) When the cache memory has a read hit (cache hit signal 31 is asserted).

This means that the type of access from the processor is read, and that the data at the accessed address is on the cache memory. In this case, since there is no need to update or replace data blocks in the cache memory, no operations are performed on the replacement memories 24 and 25.

(2) When there is a read miss in the cache memory (the cache miss signal 32 is asserted).

This means that the type of access from the processor is read, and that the data at the accessed address is not on the cache memory. In this case, since it is necessary to transfer the missed data from the main storage device 110 to the cache memory 104, the replacement determining circuit 28 selects the transfer destination block in the cache memory from among the four sets specified by the set address 3. Decide on one thing. Now processor address 10
The replacement history data of the set accessed by the set address 3 of 2 is the update history data 2 of FIG. 4(a).
6. Assume that the state is as shown in the replacement history data 27. Note that ■ to ■ in the figure indicate the numbers of each block. In FIG. 4(a), update history data 2 of “0010”
6 indicates that the data of block (2) has been changed in the past, and the replacement history data 27 of "0001" indicates that block (2) has been replaced. The replacement determining circuit 28 determines the location of the block to be replaced based on these two pieces of data. In this example, since the flags of block (2) and block (2) are set, block (2) or block (2) can be selected as the replacement block. For example, if block (2) is selected, the bit of block (2) is asserted as indicated by the replace data 29. Then, the cache-missed data is loaded into block ■. It is to be noted that the selection of blocks (2) and (2) is arbitrary; for example, it may be determined at random or in ascending order of block numbers.

When the replacement of block (2) is completed, the contents of the replace memory 25 are changed to the state shown in FIG.
It is updated as in b). That is, the bit corresponding to block (2) of the replacement history data 27 becomes "1".

(3) When the cache memory has a write hit (cache hit signal 31 and processor write signal 21 are asserted).

This means that the type of access from the processor is write, and that the data at the accessed address is on the cache memory. Here, it is assumed that block (2) of the set specified by set address 3 has been write-hit (see FIG. 5). With set address 3, data 26 and 27 are output from replace memories 24 and 25. The replace decision circuit 28 outputs replace data 29 based on these two data in the same manner as in the case of a read error (see FIG. 5(a)).
. Then, by asserting the replace signal 30, cache hit signal 31, and processor write signal 21, the contents of the replace memory 24 are changed to the data 26 in FIG. 5(b).
will be updated as follows. Note that at this time, no data is loaded into the cache memory 104.

(4) When a write miss occurs in the cache memory (cache miss signal 32 and processor write signal 21 are asserted).

This is the same as when there is a read error. However, since the data is updated by writing, the data 27 of the contents of the replace memory 25 is changed from FIG. 6(a) to FIG. 6(b).
will be updated as follows.

Next, the operation when another processor (in this case, the processor 111) writes data to the cache memory 114 that is shared with the cache memory 104 will be described.

When shared data is output to the memory address bus 120, memory data bus 121, and control signal line 122, the selector 15 outputs the data from the memory address bus 120 to the replace circuit 5, tag memory 6, and data memory 8. A processor address 105 is input. If the cache memory is hit at this time, the cache update signal 36 is asserted. Note that here, a hit in the cache memory means that data is shared, and at this time, the cache hit signal 31 is asserted. By asserting the cache update signal 36, it is known that the data stored in the cache memory has been updated by another processor, and the updated block of data is written back to the main memory as much as possible. In order to prevent this, the contents of the replace memory 24 are set to "1". Figure 7
(a) and (b) show an example in which block (2) of the update history data 26 is set to "1".

(5) History data of any block is “1”
If it becomes.

As replacements and data updates are performed, which block's history data (update history data 26,
The replacement history data 27) may also become "1" (see FIG. 8(a)). At this time, the replacement determination circuit 2
8 is at the end of data replacement or after data update,
Output “0000” to the replacement data 29. At the same time as the output, a clear signal (indicated by CLR in the figure) 35 is asserted, and "0" is written in the replacement memories 24 and 25, returning to the initial state (see FIG. 8(b)).

In the explanation of the above embodiment, a block in which neither of the replace memories 24 and 25 is "1" is replaced, but this condition can also be changed as follows.

First, the replacement memories 24 and 25 whose outputs are both "0" are replaced. When “0” is no longer present in both outputs, replace the block whose data is “0” in the replace memory 24, and when all the outputs of the replace memory 24 are “1”, the output of the replace memory 25 is “0”. Replace block.

Then, when they all become "1", the contents of the replacement memories 24 and 25 are set to "0". Or, conversely, the replace memory 25 first replaces the block with "0", and when the output of the replace memory 25 becomes all "1", the replace memory 24 replaces the block with "0", and all the blocks are "1". When this happens, the replace memories 24 and 25 are cleared to "0". In this way,
Replacement memory 24 by processor write signal 21
The order of the blocks to be replaced is determined by weighting the updates of the blocks and the updates of the replace memory 25 due to replacement. By weighting in this way,
It becomes possible to change the order of replacement, and performance can be improved depending on the type of application program.

In the embodiment shown in FIG. 2, the update history data 26 and the replacement history data 27 are stored in separate replacement memories 24 and 25, but as shown in FIG. Replace memory 3
8 can also be integrated. Incidentally, members and the like corresponding to those in the embodiment shown in FIG. 2 are given the same reference numerals, and explanations thereof will be omitted.

In the embodiment shown in FIG. 9, the replace update signals 33 and 34 are supplied together with the cache update signal 36 to the replace memory 38 via an OR circuit 39. Further, the tag address 2 is supplied as an address signal from the processor address section 1 shown in FIG. 40 is the replacement determination circuit 2
8.

[0046] In the above embodiment, the bit of the history data in the initial state is set to "0", and the bit of the updated or replaced block is set to "1". “0” may be inverted.

In the above embodiment, when data stored in the cache memory is updated by another processor in a shared memory shared bus multiprocessor system, the updated data block is prevented from being written back as much as possible. However, it is also possible to proactively use the free space that occurs when shared data is invalidated.

In this case, in the block diagram shown in FIG. 2, a cache invalidation signal is used in place of the cache update signal 36. This cache invalidation signal is a signal indicating that the cache memory has data at the same address as the address broadcast on the memory address bus 120 from another processor.

The contents of the replace memory 24 are updated when the cache memory has a write hit, and the contents of the replace memory 25 are updated when a data block is replaced due to a cache miss and when data from another cache memory is invalidated. Updated by broadcast in time.

In case of read hit, in case of read miss,
In both cases of write hit and write miss, the operation is the same as that when using the cache update signal 36, so a description thereof will be omitted.

[0051] Also, when another processor writes data in the cache memory 114 that is shared with the cache memory 104, the cache update signal 3
The operation is almost the same as that when using the memory card 6, but the write operation to the replacement memory 25 is different. That is, when the cache memory is hit, the cache invalidation signal is asserted, and with this assertion, it is learned that the data stored in the cache memory has been invalidated by another processor, and the cache invalidation signal is actively used to access the invalidated block. In order to load data, the contents of the replace memory 24 are cleared to "0".

In this way, the bits of the blocks of data invalidated by other processors are set to "0",
The cache memory can be used efficiently by loading new data into invalidated blocks preferentially compared to blocks with "1" bits.

[0053] Also, the history data of any block is "1".
The operation when the cache update signal 36 is used is the same as the operation when the cache update signal 36 is used.

[0054] In the above-described embodiment, the bits of blocks of data invalidated by other processors are set to "0", and the bits of blocks of data invalidated by other processors are prioritized compared to blocks with bits of "1". Although new data is loaded into the block, the bits "1" and "0" may be reversed.

[0055]

As described above, in the present invention, when the cache data in the cache memory is changed, the bit corresponding to the changed block of history data is set to "1", for example, When replacing cache data, for example, by preferentially replacing cache data in blocks that are set to "0", the ratio of data in blocks modified by the processor to be evicted from the cache memory will be lowered. . This reduces the number of write-backs, reduces cache misses and processor wait times for accesses via the shared bus, and improves system throughput. In addition, cache memory can be used efficiently by actively loading data into blocks that have been invalidated by other processors. Furthermore, in the present invention, since it is only necessary to provide a memory for storing the state of bits of history data, the circuit configuration is simpler than when a replacement method using LRU or FIFO is adopted.

[Brief explanation of the drawing]

FIG. 1 shows a schematic diagram of a cache memory to which the present invention is applied.

2 is a block diagram showing an example of the configuration of a replacement circuit used in the cache memory of FIG. 1. FIG.

FIG. 3 is a block diagram showing the overall configuration of a shared memory shared bus multiprocessor system to which the present invention is applied.

FIG. 4 is a diagram showing the transition of data in a replacement memory when a read miss occurs.

FIG. 5 is a diagram showing the transition of data in the replace memory when a write hit occurs.

FIG. 6 is a transition diagram of data in a replacement memory when a write error occurs.

FIG. 7 is a transition diagram of data in a replacement memory when shared data is updated.

FIG. 8 is a data transition diagram of the replacement memory when all data is “1”.

FIG. 9 is a block diagram showing another configuration example of a replacement circuit.

FIG. 10 is a transition diagram of data in a replacement memory when shared data is invalidated.

[Explanation of symbols]

1 Processor address section, 2 Tag address, 3
Set address, 4 word address, 5 replacement circuit, 6 tag memory, 7 valid memory, 8 data memory, 8a memory body, 8b, 8c
Selector, 9 Comparator, 11 Sequencer, 12 Data selection signal, 13 Tag data, 1
4 cache data, 15 address selector,
16 address, 21 processor write signal, 2
2, 23 AND circuit, 24 Replace memory for update history data, 25 Replace memory for replace history data, 26 Update history data, 27 Replace history data, 28 Replace determination circuit, 29
Replace data, 30 Replace signal, 31
cache hit signal, 32 cache miss signal,
33, 34 Replace update signal, 35 Clear signal, 36 Cache update signal, 37 OR circuit,
38 replacement memory, 39 OR circuit, 40 replacement history data, 101 CPU, 102 processor address bus, 103 processor data bus,
104 cache memory, 105 cache address bus, 106 cache data bus, 107
Processor control signal line, 108 Memory control bus, 109 Processor, 110 Main storage device, 11
1 CPU, 112 Processor address bus, 113
processor data bus, 114 cache memory, 115 cache address bus, 116 cache data bus, 117 processor control signal line, 118 memory control bus, 119 processor,
120 memory address bus, 121 memory data bus, 122 control signal line

Claims (4)

[Claims] Claim 1: A plurality of processors are provided for a common main storage device, a cache memory is provided for each processor, and a write operation to the cache memory is performed to blocks divided into a plurality of blocks. In a cache data replacement method for a cache memory in which the cache data of the previous block is written to the main memory at the time of replacement, a history data memory is provided to store history data consisting of multiple bits corresponding to each block, and the initial In the state, bits of history data are set to the first state, and when cache data in the cache memory is changed or replaced, the bit corresponding to the block is set to the second state, and the other bits are set to the first state. When data with the same address in the cache memory is updated by the processor,
The corresponding bit of the history data memory is set to a second state, and when replacing cache data, the cache data of the block whose history data bit is set to the first state is preferentially replaced. A cache data replacement method in a cache memory, characterized in that: 2. A plurality of processors are provided for a common main storage device, a cache memory is provided for each processor, and write operations to the cache memory are performed to blocks divided into a plurality of blocks. To store history data consisting of multiple bits corresponding to each block in a cache data replacement method of a cache memory in which writing of cache data of a block to the main storage device is performed at the time of replacement or every time writing to the cache memory A history data memory is provided, in which the bits of the history data are set to a first state in the initial state, the bits corresponding to the block are set to the second state by writing by the processor, and the bits of the history data are set to the second state by writing by the processor, and the cache is When data having the same address in memory is updated, the corresponding bit in the history data memory is set to the first state, and when replacing cache data, the history data bit is set to the first state. A cache data replacement method in a cache memory, characterized in that cache data of a block set in a state is replaced preferentially. 3. A plurality of processors are provided for a common main storage device, a cache memory is provided for each processor, and a write operation to the cache memory is performed to blocks divided into a plurality of blocks. In a cache data replacement device for a cache memory in which the cache data of the previous block is written to the main storage device at the time of replacement, this is a history data memory for storing history data consisting of multiple bits corresponding to each block. In the state, a history data memory in which bits of history data are set to the first state, and a signal indicating a change in cache data in the cache memory or a signal indicating replacement are detected and the corresponding block of the history data memory is set to the first state. means for setting a corresponding bit to a second state; and means for detecting a signal indicating that data having the same address in the cache memory has been updated by another processor and setting the corresponding bit in the history data memory. means for determining the contents of the history data memory when replacing cache data, and determining a block to preferentially replace cache data based on the bits in the first state; A cache data replacement device in a cache memory, characterized in that it is provided with a cache data replacement device. 4. A plurality of processors are provided for a common main storage device, a cache memory is provided for each processor, and a write operation to the cache memory is performed to blocks divided into a plurality of blocks. To store history data consisting of multiple bits corresponding to each block in a cache data replacement device for a cache memory in which writing of cache data of a block to the main storage device is performed at the time of replacement or every time writing to the cache memory. a history data memory in which bits of the history data are set to a first state in an initial state, and a signal indicating writing by the processor is detected to correspond to the corresponding block of the history data memory. means for setting a bit of historical data to a second state; and means for detecting a signal indicating that data having the same address in the cache memory has been updated by another processor to update a bit of the historical data in the corresponding historical data memory. means for setting bits to a first state; and determining a block to replace cache data preferentially based on the bits in the first state by determining the contents of the history data memory when replacing cache data. 1. A cache data replacement device in a cache memory, characterized in that a cache data replacement device is provided in a cache memory.