JP5453500B2 - Store control device, information processing device, and store control method - Google Patents

Description

  The present invention relates to a store control device, an information processing device, and a store control method.

  An example of a technique related to the control of the store buffer is described in Patent Document 1. This technique is provided with a timer, a circuit indicating the number of data stored in the write buffer, and the like for controlling the storage data to be purged from the store buffer.

JP 2012-43202 A

  The technique described in Patent Document 1 described above has a problem that the control for expelling store data from the write buffer is complicated because a timer and a circuit indicating the number of data stored in the write buffer are provided.

  The objective of this invention is providing the store control apparatus, information processing apparatus, and store control method which solved the said subject.

  The store control device of the present invention receives a store request accompanied by block-unit store data, stores a store buffer unit including a plurality of ways for storing store data in units of lines including a plurality of blocks, and a line in the store buffer unit. All blocks include a store buffer control unit that performs control for expelling store data in preference to the way existing in the store buffer unit.

  The store control method of the present invention receives a store request accompanied by block-unit store data, and stores all the blocks in a line with respect to a store buffer unit including a plurality of ways for storing store data in units of lines including a plurality of blocks. The store data is expelled giving priority to the way existing in the store buffer section.

  The effect of the present invention is that the control for expelling store data from the write buffer is simplified.

It is a block diagram which shows the structure of the 1st Embodiment of this invention. It is a flowchart which shows the operation | movement of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of a store buffer part. It is a block diagram which shows the structure of a store buffer part. It is explanatory drawing which shows the content of entry information. It is a block diagram which shows the structure of an entry full detection circuit. It is a block diagram which shows the structure of a eviction control circuit. It is explanatory drawing which shows the logic of a eviction control circuit. It is a block diagram which shows the structure of a merge circuit. It is explanatory drawing which shows the content of a request. It is a schematic flowchart which shows the operation | movement of the 2nd Embodiment of this invention. It is explanatory drawing which shows an example of eviction operation. It is a block diagram which shows the structure of the 3rd Embodiment of this invention. It is explanatory drawing which shows the content of a request. It is explanatory drawing which shows the content of entry information. It is a block diagram which shows the structure of a store buffer part. It is a block diagram which shows the structure of a store buffer part.

  Next, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment. Referring to FIG. 1, the store control apparatus 100 according to the first embodiment includes a store buffer unit 101 and a store buffer control unit 102.

  The store buffer control unit 102 is connected to the processor and the store buffer unit 101. The store buffer control unit 102 controls the store buffer unit 101. The store buffer unit 101 is connected to the store buffer control unit 102 and the main storage device. The store buffer unit 101 temporarily stores store data stored (written) in the main memory from the processor.

  The store buffer control unit 102 receives store data in units of blocks (a plurality of consecutive bytes) in response to a request from the processor, and stores it in the store buffer unit 101. Further, the store buffer control unit 102 takes out (purges) store data in units of lines (a plurality of continuous blocks) from the store buffer unit 101 and outputs the stored data to the main storage device.

  Further, when at least one block exists in a line of the store buffer unit 101, when store data (block unit) corresponding to the line is received from the processor by a request, the data is merged and stored. Also, if merging occurs at least once, the line is called merging. If all the blocks of a line exist, the line is called merge complete.

  As a store buffer system, a system having a plurality of ways (for example, a set associative system) is applied. Here, the unit of information stored in each way is referred to as an entry.

  Next, the operation of the first embodiment will be described with reference to the drawings. FIG. 2 is a flowchart showing the operation of the first embodiment. Referring to FIG. 2, when an opportunity to drive store data to the main storage device occurs (step S1 / Y), the store buffer control unit 102 indicates that all blocks in the line exist in the store buffer unit 101 (that is, An instruction for expelling the store data with priority given to the way of merge completion is output (step S2).

  Here, the trigger is, for example, that store data is stored in all the way entries (lines) corresponding to the address (middle) of the request in the store buffer unit 101, and the new store data is stored in any way. This is the case of storing in the entry (line).

  Next, the store buffer unit 101 evicts the store data and outputs it to the main storage device according to the instruction from the store buffer control unit 102 (step S3).

  Next, the effect of the first embodiment will be described.

  In the first embodiment, store data is expelled preferentially from a way in which all blocks in a line exist in the store buffer unit 101 (merge completion).

  Therefore, the first embodiment has an effect that, for example, the timer of the technique described in Patent Document 1 and a circuit indicating the number of data stored in the write buffer are unnecessary, and the control of the eviction is simplified. .

  Therefore, the first embodiment has an effect that the amount of hardware is reduced as compared with, for example, a configuration using LRU (Least Recently Used) for the eviction algorithm.

  Further, the first embodiment has an effect that the number of accesses to the main storage device 114 can be reduced and the store buffer unit 101 can be used efficiently.

  The reason is that the merge completion line has a low probability that a new merge will occur, so the merge completion line is expelled and a line with a high probability of merge is stored in the store buffer unit 101. is there.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 3 is a block diagram showing the configuration of the second embodiment. Referring to FIG. 3, the information processing apparatus 110 according to the second embodiment includes a processor 111, a store control apparatus 100, and a main storage device 114.

  The store control apparatus 100 is an example of the store control apparatus 100 according to the first embodiment, and includes a store buffer unit 101 and a store buffer control unit 102. Store buffer control unit 102 includes merge circuit 112, entry full detection circuit 115, and eviction control circuit 116.

  The processor 111 is connected to the merge circuit 112 and the main storage device 114. The processor 111 outputs a request (load, store) and store data to be written to the main storage device 114 to the merge circuit 112. Further, the processor 111 receives load data (read data) from the main storage device 114.

  The merge circuit 112 is connected to the processor 111 and the store buffer unit 101. The merge circuit 112 outputs a request from the processor 111 and store data to the store buffer unit 101. In addition, the merge circuit 112 performs a merge process on the store data in units of lines from the store buffer unit 101 and the store data from the processor 111 and outputs the merged data to the store buffer unit 101.

  The store buffer unit 101 is connected to the merge circuit 112, the main storage device 114, the entry full detection circuit 115, and the eviction control circuit 116. The store buffer unit 101 compares the address of the load request with the address of the store request in the store buffer unit 101. If they match, the store buffer unit 101 evicts (reads) the corresponding store data and sends it to the main storage device 114 together with the store request. Output.

  Further, the store buffer unit 101 reads out the store data, outputs it to the merge circuit 112, and stores the merged store data, which is the output of the merge circuit 112, in the original storage location (original entry).

  Further, the store buffer unit 101 outputs a part of entry information (information in the entry) and the latest way number to the entry full detection circuit 115, and stores the store data in accordance with an instruction from the eviction control circuit 116. Output to.

  The main storage device 114 is connected to the processor 111 and the store buffer unit 101. The main storage device 114 reads (loads) and writes (stores) data in accordance with a request from the store buffer unit 101. The main storage device 114 outputs the read data to the processor 111 as load data.

  The entry full detection circuit 115 is connected to the store buffer unit 101 and the eviction control circuit 116. The entry full detection circuit 115 receives part of the entry information from the store buffer unit 101, determines entry full, and outputs the entry full information, part of the entry information, and the latest way number to the eviction control circuit 116. .

  The eviction control circuit 116 is connected to the store buffer unit 101 and the entry full detection circuit 115. The eviction control circuit 116 performs store data eviction determination based on the entry full information from the entry full detection circuit 115 and part of the entry information, and outputs a eviction instruction and an eviction way number to the store buffer unit 101.

  Next, a detailed configuration of the store buffer unit 101 will be described. 4 and 5 are block diagrams showing the configuration of the store buffer unit 101. FIG. 4 and 5, the same numeral portions surrounded by a circle are connected.

  4 and 5, the store buffer unit 101 includes an address array 301, a data array 302, an entry selection circuit 303, an entry information update circuit 304, a register 305, a selector 306, a selector 307, a selector 308, a comparison circuit 309, An address array control circuit 310 and a data array control circuit 311 are included.

  The store buffer unit 101 receives a request and store data from the merge circuit 112, and a eviction instruction and eviction way number from the eviction control circuit 116.

  The address array 301 stores entry information. FIG. 6 is an explanatory diagram showing the contents of entry information. Referring to FIG. 6, the entry information includes entry valid information, merge completion information, merging information, an address (upper order), and valid block information.

  The entry valid information indicates whether the entry is valid, that is, whether valid store data exists in the entry of the data array 302. The valid block information indicates a valid block among the lines of the data array 302.

  When the merge information is set, it indicates that merge has occurred in the store data in the data array 302 of the entry. The merge completion information, when set, indicates that all blocks in the line in the data array 302 of the entry are valid. That is, merge completion information is set when the valid block information of the entry indicates the validity of all blocks.

  In the following description, for the sake of clarity, when the entry valid information, merge completion information, and merging information are set to “1”, the entry is valid, the merge is completed, and the merge is performed. Let's say that it is in the middle.

  The address array 301 stores the latest way number for each address (middle) (hereinafter referred to as an index) included in the request. Further, the address array 301 outputs a part of the entry information of all the ways corresponding to the index and the latest way number to the entry full detection circuit 115. The latest way number indicates the way that was recently accessed (registered, stored with eviction, merged).

  In addition, the address array 301 outputs all way entry information corresponding to the index to the entry selection circuit 303. Further, the address array 301 outputs addresses (upper ranks) and entry valid information in the entry information of all ways corresponding to the index to the comparison circuit 309.

  The data array 302 stores store data in a storage position (entry) corresponding to the entry of the address array 301. Further, the data array 302 outputs all way store data corresponding to the index to the selector 307 and the selector 308.

  The comparison circuit 309 compares the address (upper order) in the entry information of all the ways corresponding to the index and the higher address order included in the request, and outputs a comparison result indicating whether or not they match. Note that the comparison circuit 309 determines that the comparison results do not match unless the entry valid information in the entry information indicates validity.

  The selector 307 selects store data under the control of the entry information update circuit 304 and outputs it to the main storage device 114. The selector 308 selects way store data indicating a match according to the comparison result from the comparison circuit 309, and outputs it to the merge circuit 112.

  In the case of a load request, the entry selection circuit 303 selects way entry information to be expelled according to the comparison result of the comparison circuit 309. Further, in the case of a store request, the entry selection circuit 303 selects entry information of the way to be ejected according to the eviction instruction from the eviction control circuit 116 and the eviction way number. Further, the entry selection circuit 303 outputs entry information, an eviction instruction, an eviction way number, and the like to the entry information update circuit 304.

  In the case of a load request, the entry information update circuit 304 updates the entry information of the entry to be evicted from the entry selection circuit 303, and generates a selection signal for the selector 307. In the case of a store request, the entry information update circuit 304 determines entry registration, merging, or eviction according to the comparison result from the comparison circuit 309, the entry information from the entry selection circuit 303, and the eviction instruction. And update the entry information and the latest way number. The entry information update circuit 304 generates a selection signal for the selector 307.

  The address array control circuit 310 stores the updated (or new) entry information and the updated latest way number for the way specified by the entry information update circuit 304 of the address array 301. The data array control circuit 311 stores or updates the store data in the entry of the designated way according to the output of the entry information update circuit 304.

  The register 305 temporarily saves (stores) the load request. The selector 306 selects entry information to be evicted and outputs it to the main storage device 114 when the egress by the load request occurs, and further outputs the load request saved from the register 305 to the main storage device 114. .

  Next, a detailed configuration of the entry full detection circuit 115 will be described. FIG. 7 is a block diagram showing a configuration of the entry full detection circuit 115. Referring to FIG. 7, the entry full detection circuit 115 receives, from the address array 301 of the store buffer unit 101, entry valid information, merge completion information, and merging information in all way entry information corresponding to indexes. Further, the entry full detection circuit 115 receives the latest way number corresponding to the index from the address array 301 of the store buffer unit 101.

  The entry full detection circuit 115 uses the logical product circuit 401 to generate entry full information indicating that all pieces of entry valid information are valid and outputs the entry full information to the eviction control circuit 116. Further, the entry full detection circuit 115 outputs merge completion information, merging information, and latest way number in the received entry information of all ways to the eviction control circuit 116.

  Next, a detailed configuration of the eviction control circuit 116 will be described. FIG. 8 is a block diagram showing a configuration of the eviction control circuit 116. FIG. 9 is an explanatory diagram showing the logic of the eviction control circuit 116. In FIG. 9, “−” indicates that either “0” or “1” may be used.

  8 and 9, the eviction control circuit 116 receives entry full information, merge completion information (for all ways), merging information (for all ways), and the latest way number from the entry full detection circuit 115. . The eviction control circuit 116 includes an encoding circuit 601, an encoding circuit 602, an encoding circuit 603, and a selector 604.

  The encoding circuit 601 generates the way number of the way whose merge completion information is “1”. However, when there are a plurality of merge completion information of “1”, the search is sequentially performed from the next way number of the latest way number, and the way number of the way whose merge completion information is “1” is generated. The next way number is a number obtained by adding 1 to the latest way number. However, if the latest way number is the maximum way number (= N), the next way number is the minimum way number (= 0).

  The encoding circuit 602 generates the way number of the way whose merge information is “1”. However, when there are a plurality of information being merged with ‘1’, the search is sequentially performed from the way number next to the latest way number, and a way number with the ‘1’ being merged is generated.

  The encoding circuit 603 generates a way number next to the latest way number.

  The selector 604 selects the way number from the encoding circuit 601 as the eviction way number if there is even one merge completion information of “1”. The selector 604 selects the way number from the encoding circuit 602 as the eviction way number if there is no merge completion information of “1” and there is at least one merged information of “1”. . The selector 604 selects the way number from the encoding circuit 603 as the eviction way number when neither the merge completion information “1” nor the merging information “1” exists.

  The eviction control circuit 116 outputs the eviction way number from the selector 604 to the store buffer unit 101, and outputs the entry full information from the entry full detection circuit 115 as an eviction instruction.

  Next, a detailed configuration of the merge circuit 112 will be described. FIG. 10 is a block diagram showing a configuration of the merge circuit 112. Referring to FIG. 10, the merge circuit 112 receives a request and block-unit store data from the processor 111, and receives line-unit store data from the store buffer unit 101.

  The merge circuit 112 includes a decode circuit 510, a block-unit selector 500, a selector 501,..., And a selector 50N.

  The number of selectors 500 to 50N is indicated by the address (lower order) in the request. For example, if the address (lower order) is 4 bits, there are 16 selectors in block units.

  The decode circuit 510 selects store data from the processor 111 only for the block specified by the address (lower order) in the request, and generates a selection signal for selecting store data from the store buffer unit 101 for the other blocks. .

  The selectors 500 to 50N select store data according to the selection signal. For example, if the address (lower order) = '0001', only the first (0 origin) selector 501 out of 16 selects store data from the processor 111.

  Then, the merge circuit 112 outputs the selected line-unit store data and the request from the processor 111 to the store buffer unit 101.

  Next, the operation of the second exemplary embodiment of the present invention will be described with reference to the drawings. In order to make the explanation easy to understand, suppose that one line is 128 [B] (bytes) and one block is 8 [B] (bytes). That is, 1 line = 16 blocks. In the following description, the presence of a line in the store buffer unit 101 means that there is at least one block of store data belonging to the line.

  The store buffer unit 101 will be described as having an N + 1 way set associative cache configuration having, for example, way-0 to way-N (N is an integer such as 1, 3, 7, etc.).

  Here, the details of the request will be described. FIG. 11 is an explanatory diagram showing the contents of a request. Referring to FIG. 11, the request includes a command, an address (upper order), an address (middle order), an address (lower order), and priority designation information.

  The command indicates a type such as a load request or a store request. The address (upper order) becomes a part of the entry information of the address array 301 of the store buffer unit 101. The address (middle level) is an index that indexes the address array 301 and the data array 302.

  The address (lower order) is a unit of 8 [B] and indicates which block in the line the load / store data corresponds to. The priority designation information instructs to preferentially evict the entry designated by the address in the request. When the priority designation information of the store request is ON, the store control apparatus 100 sets the entry full information to “1” regardless of whether all the blocks in the line exist.

  FIG. 12 is a schematic flowchart showing the operation of the second embodiment. Referring to FIG. 12, upon receiving a load request (step S11 / load), the store control apparatus 100 checks whether a line corresponding to the address in the request exists in the store buffer unit 101 (step S12). This checks for the existence of line units, not block units.

  When the line exists (step S12 / Y), the store control device 100 outputs the store data of the line in the store buffer unit 101 to the main storage device 114 (evicts), and deletes the entry (step S13). ). Next, the store control device 100 outputs the received load request to the main storage device 114 (step S14).

  If the line does not exist (step S12 / N), the store control device 100 outputs the received load request to the main storage device 114 (step S14).

  Upon receiving the store request (step S11 / store), the store control apparatus 100 checks whether or not a line corresponding to the address in the request exists in the store buffer unit 101 (step S15).

  When the line exists (step S15 / Y), the store control apparatus 100 merges the store data accompanying the store request with the store data of the line and stores it in the store buffer unit 101 (step S16).

  When the line does not exist (step S15 / N), the store control apparatus 100 checks whether or not the line exists in all ways corresponding to the address (index) in the request (that is, entry is full) (step S15 / N). S17).

  If the entry is not full (step S17 / N), the store control apparatus 100 stores (registers) the store data in an empty way entry (step S18).

  If the entry is full (step S17 / Y), the store control device 100 stores the store data (in line units) of one way entry into the main storage device 114 together with the store request based on the logic of the eviction control circuit 116. Output (purge) (step S19). Next, the store control apparatus 100 stores the store data accompanying the received request in the entry to be evicted (step S20).

  Next, the operation for the load request will be described in more detail.

  A load request from the processor 111 is received by the store buffer unit 101 via the merge circuit 112. The merge circuit 112 outputs the load request to the store buffer unit 101 as it is.

  The store buffer unit 101 indexes the address array 301 by an address (index) in the load request, and reads entry information from corresponding entries of all ways. Next, the store buffer unit 101 uses the comparison circuit 309 to compare whether the address (upper) in the read entry information matches the address (upper) in the load request.

  If the addresses (upper ranks) do not match, the store buffer unit 101 outputs the load request via the selector 306 to the main storage device 114 as it is.

  If the addresses (upper ranks) match and the entry valid information indicates valid, the store buffer unit 101 stores (saves) the load request in the register 305.

  Next, the store buffer unit 101 uses the entry selection circuit 303 to select the entry information of the way whose match is detected by the comparison circuit 309.

  Further, the store buffer unit 101 indexes the data array 302 by the address (middle) (index) in the load request, and reads the store data from the corresponding entries of all ways. Then, the store buffer unit 101 uses the selector 307 to select the store data of the way whose match is detected by the comparison circuit 309.

  Next, the store buffer unit 101 generates a store command. The store buffer unit 101 uses the store command, the address (upper) in the entry information from the entry selection circuit 303, the valid block information, and the address (middle) from the load request as a store request via the selector 306 to the main storage device. To 114. At that time, the store buffer unit 101 outputs the store data (128 [B]) from the selector 307 to the main storage device 114.

  Next, the store buffer unit 101 uses the entry information update circuit 304 to delete the entry information output to the main storage device 114. That is, the entry information update circuit 304 resets the entry valid information of the entry information of the entry so as to indicate invalidity. The entry becomes empty. At this time, the entry information update circuit 304 does not update the latest way number. Further, the entry information update circuit 304 sets the valid block information to a value indicating that all blocks are invalid.

  Further, the store buffer unit 101 outputs the load request stored in the register 305 to the main storage device 114 via the selector 306. The main storage device 114 reads the load data (128 [B]) corresponding to the address in the received load request and outputs it to the processor 111.

  Next, the operation for the store request will be described in more detail.

  First, a case where the store data of the line specified by the request does not exist in the entry and the entry indicated by the index has a vacancy will be described. In this case, no eviction or merging is performed.

  The merge circuit 112 of the store buffer control unit 102 outputs the store request as it is. In addition, the merge circuit 112 selects store data from the processor 111 only for the block designated by the address (lower order) in the request, and selects store data from the store buffer unit 101 for other blocks. B].

  The store buffer unit 101 indexes the address array 301 by an address (index) in the store request and reads entry information from corresponding entries of all ways. Next, the store buffer unit 101 uses the comparison circuit 309 to compare whether the address (upper order) in the read entry information matches the address (upper order) in the store request.

  In this case, since the addresses (upper ranks) do not match, the entry selection circuit 303 of the store buffer unit 101 checks whether or not the eviction instruction from the eviction control circuit 116 indicates eviction. In this case, the eviction instruction does not indicate eviction (that is, there is an empty entry). Therefore, the entry information update circuit 304 refers to the entry valid information of each way from the entry selection circuit 303 and generates a storage way number (empty) indicating the way to store (register) the store data.

  Further, the entry information update circuit 304 sets the entry valid information to a value (“1”) indicating validity, the merge completion information to a value that is not merge completion (“0”), and the information that is being merged to a value that is not being merged (“ 0 '). The entry information update circuit 304 generates valid block information from the address (lower order) from the request, and sets the storage way number as the latest way number.

  Then, the entry information update circuit 304 outputs the address (upper order), the storage way number, the entry valid information, the merge completion information, the merging information, the valid block information, and the latest way number from the request.

  The address array control circuit 310 updates the latest way number corresponding to the index of the address array 301 in accordance with the output of the entry information update circuit 304. The address array control circuit 310 registers entry information for the way entry corresponding to the index of the address array 301 and designated by the storage way number.

  Further, the data array control circuit 311 stores the store data from the merge circuit 112 for the entry of the way corresponding to the index of the address array 301 and designated by the storage way number in accordance with the output of the entry information update circuit 304. Registration (storage).

  When registering a store request, if the priority designation information in the request is a value ('1') that designates priority, the merge completion information is set to '1' and the merge in progress information is set to '0'. To do. As a result, this entry is preferentially evicted during the evicting operation.

  Next, a case where the store data of the line specified by the store request exists in the entry will be described. In this case, eviction is not performed and merging is performed.

  The store buffer unit 101 of the store buffer control unit 102 indexes the address array 301 according to the address (middle) (index) in the store request, and reads the entry information from the corresponding entries of all ways. Next, the store buffer unit 101 uses the comparison circuit 309 to compare whether the address (upper order) in the read entry information matches the address (upper order) in the store request.

  In this case, the addresses (upper order) match. In accordance with the output of the comparison circuit 309, the selector 308 selects the store data from the way in which the coincidence of the data array 302 is detected, and outputs it to the merge circuit 112.

  The merge circuit 112 outputs the store request as it is. Further, the merge circuit 112 selects store data from the processor 111 only for the block designated by the address (lower order) in the request, and selects store data from the selector 308 for other blocks, and 128 [B]. Output as.

  Further, the entry information update circuit 304 generates, as the storage way number, the number of the way whose address (upper order) matches according to the output of the comparison circuit 309. Store data is stored (merged) in the way indicated by the storage way number.

  Further, the entry information update circuit 304 sets the entry valid information as it is ('1'), and sets the merging information to the merging value ('1'). The entry information update circuit 304 merges the valid block information generated from the address (lower order) from the request with the valid block information so far.

  Further, the entry information update circuit 304 sets the merge completion information to the merge completion value ('1') when the merged effective block information indicates the validity of all the blocks. Further, the entry information update circuit 304 sets the storage way number as the latest way number.

  Then, the entry information update circuit 304 outputs the address (upper order), the storage way number, the entry valid information, the merge completion information, the merging information, the valid block information, and the latest way number from the request.

  The address array control circuit 310 stores (updates) entry information for the entry of the way corresponding to the index of the address array 301 and designated by the storage way number in accordance with the output of the entry information update circuit 304, and The latest way number is updated.

  Further, the data array control circuit 311 stores the store data from the merge circuit 112 for the entry of the way corresponding to the index of the address array 301 and designated by the storage way number in accordance with the output of the entry information update circuit 304. Is stored (updated).

  If the priority designation information in the request is a value (“1”) that designates priority, the merge completion information is registered as “1” and the information being merged is left as it is. As a result, this entry is preferentially evicted during the evicting operation.

  Next, a case where the store data of the line specified by the store request does not exist in the entry and the entry indicated by the index has no space will be described. In this case, eviction is performed and merging is not performed.

  The store buffer unit 101 indexes the address array 301 by an address (index) in the store request, and reads and outputs entry information from corresponding entries of all ways.

  The entry full detection circuit 115 of the store buffer control unit 102 generates and outputs entry full information based on entry valid information from the address array 301 of the store buffer unit 101. In this case, since the entry valid information of all ways indicates validity, the entry full information indicates entry full. The entry full detection circuit 115 outputs merge completion information, merging information, and the latest way number.

  Next, the eviction control circuit 116 of the store buffer control unit 102 generates and outputs an eviction way number based on the merge completion information, the merging information, and the latest way number. The logic for generating the eviction way number is as described above with reference to FIGS.

  Here, an example of the eviction operation will be described in detail with reference to the drawings. FIG. 13 is an explanatory diagram showing an example of the eviction operation. In the figure, “unmerged” indicates that merging is neither completed nor merged.

  Referring to FIG. 13, for the entry with index = “00”, the merge completion information is “1” only in way-0. Therefore, the entry of way-0 is an entry to be evicted.

  Further, for the entry with index = “01”, there is no entry whose merge completion information is “1”. There are multiple entries whose information during merge is ‘1’ such as way-0, way-1, way-3, way-4, way-5, and way-6. The latest way number is '1', indicating way-1. Therefore, the search is sequentially performed in the way-2 and way-3 next to the way-1, and the entry of the way-3 whose merge information is “1” becomes an entry to be evicted.

  Further, when the entry full information indicates entry full, the eviction control circuit 116 outputs an eviction instruction for instructing eviction.

  Further, the store buffer unit 101 uses the comparison circuit 309 to compare whether the address (upper order) in the read entry information matches the address (upper order) in the store request.

  In this case, since the addresses (upper ranks) do not match, the entry selection circuit 303 of the store buffer unit 101 checks whether or not the eviction instruction from the eviction control circuit 116 indicates eviction. In this case, the eviction instruction indicates eviction (that is, there is no empty entry).

  Then, the entry selection circuit 303 selects the entry information of the way specified by the eviction way number from the eviction control circuit 116.

  Further, the store buffer unit 101 indexes the data array 302 by the address (middle) (index) in the load request, and reads the store data from the corresponding entries of all ways. Then, the store buffer unit 101 uses the selector 307 to select the store data of the way specified by the eviction way number. The eviction way number generated by the eviction control circuit 116 is received by the entry information update circuit 304 via the entry selection circuit 303. In this case, the entry information update circuit 304 generates a selection signal for the selector 307 based on the eviction way number.

  Next, the store buffer unit 101 generates a store command. Then, the store buffer unit 101 uses the store command, the address (upper) in the entry information from the entry selection circuit 303, the valid block information, and the address (middle) from the store request as a store request via the selector 306. The data is output to the storage device 114. At that time, the store buffer unit 101 outputs the store data (128 [B]) from the selector 307 to the main storage device 114.

  Next, the entry information update circuit 304 generates the eviction way number from the entry selection circuit 303 as a storage way number. Further, the entry information update circuit 304 sets the entry valid information to a value (“1”) indicating validity, the merge completion information to a value that is not merge completion (“0”), and the information that is being merged to a value that is not being merged (“ 0 '). The entry information update circuit 304 generates valid block information from the address (lower order) from the request, and sets the storage way number as the latest way number.

  Then, the entry information update circuit 304 outputs the address (upper order), the storage way number, the entry valid information, the merge completion information, the merging information, the valid block information, and the latest way number from the request.

  The address array control circuit 310 stores the entry information for the way entry corresponding to the index of the address array 301 and designated by the storage way number, and the latest way according to the output of the entry information update circuit 304. Update the number.

  Further, the data array control circuit 311 stores the store data from the merge circuit 112 for the entry of the way corresponding to the index of the address array 301 and designated by the storage way number in accordance with the output of the entry information update circuit 304. Store.

  If the priority designation information in the request is a value ('1') that designates priority, the merge completion information is stored as '1' and the information being merged is stored as '0'.

  In the second embodiment, a configuration corresponding to a pipeline stage for storing information can be appropriately provided for pipeline control. Further, a configuration in which a cache is provided between the store control device 100 and the main storage device 114 is possible.

  Next, the effect of the second embodiment will be described.

  The second embodiment includes the store control device 100 of the first embodiment, and is configured to determine the eviction way from the merge completion information, the merging information, and the latest way number. Therefore, it has the same effect as the first embodiment.

  In the second embodiment, when there are a plurality of ways in which merge completion information or merge completion information is set, the search is sequentially performed from the next way number of the latest way number, and merge completion information or In this configuration, the way in which the merging information is set is set as the evacuation target way. Therefore, a way that has been accessed recently is not a target for eviction. Therefore, the second embodiment has the effect that the possibility of merging by subsequent requests is improved, the store operation for the main storage device 114 is reduced, and the performance is improved.

  Next, a third embodiment of the present invention will be described in detail with reference to the drawings. FIG. 14 is a block diagram illustrating a configuration of the third embodiment.

  Referring to FIG. 14, the processor 111 outputs core failure information to the store control device 100. The store buffer unit 101 of the store control apparatus 100 receives core failure information. FIG. 15 is an explanatory diagram showing the contents of a request. Referring to FIG. 15, in the request of the third embodiment, a core number is added to the request of the second embodiment.

  FIG. 16 is an explanatory diagram showing the contents of entry information. Referring to FIG. 16, in the entry information of the third embodiment, a core number is added to the entry information of the second embodiment. 17 and 18 are block diagrams illustrating the configuration of the store buffer unit 101 according to the third embodiment. In FIG. 17 and FIG. 18, the same numeral portions surrounded by circles are connected. Referring to FIGS. 17 and 18, a purge instruction replacement circuit 320 is added to the second embodiment.

  Hereinafter, an operation different from that of the second embodiment will be described.

  The processor 111 is composed of a plurality of cores, and each core outputs a request. Each core outputs a core number unique to the request.

  The store control device 100 includes the core number in the request in the entry information and stores it in the address array 301 of the store buffer unit 101.

  When a failure occurs in the core, the processor 111 outputs the core failure information including the core number indicating the core in which the failure has occurred. When eviction occurs due to a store request, the store buffer unit 101 preferentially selects an entry including the core number indicated by the core failure information as a eviction target.

  Specifically, the eviction instruction replacement circuit 320 receives the core number in the entry information of all ways from the address array 301 and the core fault information from the processor 111. Upon receiving the eviction instruction and the eviction way number from the eviction control circuit 116, the eviction instruction replacement circuit 320 compares the core number indicated by the core failure information with the core number in the entry information.

  If they match in the comparison, the eviction instruction replacement circuit 320 sets the number indicating the way storing the entry information including the matched core number as the eviction way number. If they do not match in the comparison, the eviction instruction replacement circuit 320 sets the eviction way number from the eviction control circuit 116 as the eviction way number as it is.

  The eviction instruction replacement circuit 320 outputs the eviction instruction and the eviction way number to the entry selection circuit 303. Subsequent operations are the same as those in the second embodiment.

  Next, the effect of the third embodiment will be described.

  Since the third embodiment includes the configuration of the second embodiment, the third embodiment has the same effect as the second embodiment.

  In the third embodiment, store data corresponding to a failed core is preferentially driven out. Therefore, the entry information and store data of the failed core are not stored in the store buffer unit 101 for a long time, and the store buffer unit 101 can be used efficiently.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

[Appendix 1]
A store buffer unit including a plurality of ways for receiving a store request with store data in units of blocks and storing the store data in units of lines including a plurality of blocks;
A store buffer control unit for controlling all blocks in the line of the store buffer unit to expel store data in preference to the way existing in the store buffer unit;
A store control device comprising:

[Appendix 2]
When there are a plurality of ways in which all the blocks in the line of the store buffer section exist, search is performed sequentially from the way number next to the latest way number, and the store data giving priority to the way in which all the blocks in the line exist The store control device according to appendix 1, further comprising the store buffer control unit that performs control to drive out the data.

[Appendix 3]
Including the store buffer control unit that performs control to expel store data in preference to the way in which the merged block exists when all the blocks in the line of the store buffer unit do not exist. The store control device according to supplementary note 2, which is characterized.

[Appendix 4]
If there is no way in which all the blocks in the line of the store buffer part exist and there are multiple ways in which a merged block exists, the search is sequentially performed from the way number next to the latest way number and merged. The store control apparatus according to appendix 3, including the store buffer control unit that performs control for expelling store data with priority given to a way in which a block in which the block is implemented exists.

[Appendix 5]
Upon receiving a store request including priority specification information, store data is stored in the store buffer unit, and control is performed so that all the blocks in the line storing the store data exist in the store buffer unit. The store control device according to appendix 4, wherein the store control device includes a section.

[Appendix 6]
When a request including a core number is received, the core number is stored in the store buffer unit, and when core failure information is received, a match between the core number included in the core failure information and the core number in the store buffer unit is checked and matched. The store control apparatus according to appendix 5, wherein the store control of the way including the core number is preferentially driven out.

[Appendix 7]
Additional store controller according to appendix 1, 2, 3, 4, 5 or 6;
A processor that outputs a store request with store data in units of blocks to the store controller;
A main storage device for storing store data evicted from the store control device;
An information processing apparatus comprising:

[Appendix 8]
A store buffer unit that receives a store request with store data in units of blocks and stores the store data in units of lines including a plurality of blocks, and a store buffer unit that includes a plurality of ways, all the blocks in the line exist in the store buffer unit Store control method characterized by expelling store data in preference to

[Appendix 9]
When there are a plurality of ways in which all the blocks in the line of the store buffer section exist, search is performed sequentially from the way number next to the latest way number, and the store data giving priority to the way in which all the blocks in the line exist The store control method according to appendix 8, wherein the store control method is performed.

[Appendix 10]
The store control method according to appendix 9, wherein when there is no way in which all the blocks in the line of the store buffer unit exist, store data is expelled in preference to the way in which the merged block exists.

[Appendix 11]
If there is no way in which all the blocks in the line of the store buffer part exist and there are multiple ways in which a merged block exists, the search is sequentially performed from the way number next to the latest way number and merged. The store control method according to appendix 10, wherein the store data is expelled preferentially to the way in which the block in which the block is executed exists.

[Appendix 12]
When a store request including priority designation information is received, store data is stored in the store buffer unit, and all blocks in a line storing the store data are processed as existing in the store buffer unit. The store control method according to attachment 11.

[Appendix 13]
When a request including a core number is received, the core number is stored in the store buffer unit, and when core failure information is received, a match between the core number included in the core failure information and the core number in the store buffer unit is checked and matched. The store control method according to appendix 12, wherein the way store data including the core number is preferentially driven out.

DESCRIPTION OF SYMBOLS 100 Store control apparatus 101 Store buffer part 102 Store buffer control part 110 Information processing apparatus 111 Processor 112 Merge circuit 114 Main memory 115 Entry full detection circuit 116 Ejection control circuit 301 Address array 302 Data array 303 Entry selection circuit 304 Entry information update circuit 305 register 306 selector 307 selector 308 selector 309 comparison circuit 310 address array control circuit 311 data array control circuit 320 eviction instruction replacement circuit 401 logical product circuit 500 selector 501 selector 50N selector 510 decode circuit 601 encode circuit 602 encode circuit 603 encode circuit 604 selector

Claims (10)

A store buffer unit including a plurality of ways for receiving a store request with store data in units of blocks and storing the store data in units of lines including a plurality of blocks;
A store buffer control unit for controlling all blocks in the line of the store buffer unit to expel store data in preference to the way existing in the store buffer unit;
A store control device comprising:   When there are a plurality of ways in which all the blocks in the line of the store buffer section exist, search is performed sequentially from the way number next to the latest way number, and the store data giving priority to the way in which all the blocks in the line exist The store control device according to claim 1, further comprising the store buffer control unit that performs control to drive out the data.   Including the store buffer control unit that performs control to expel store data in preference to the way in which the merged block exists when all the blocks in the line of the store buffer unit do not exist. The store control device according to claim 2, wherein   If there is no way in which all the blocks in the line of the store buffer part exist and there are multiple ways in which a merged block exists, the search is sequentially performed from the way number next to the latest way number and merged. 4. The store control apparatus according to claim 3, further comprising: the store buffer control unit that performs control for expelling store data in preference to a way in which a block in which the block is executed is present.   Upon receiving a store request including priority specification information, store data is stored in the store buffer unit, and control is performed so that all the blocks in the line storing the store data exist in the store buffer unit. The store control device according to claim 4, further comprising a storage unit.   When a request including a core number is received, the core number is stored in the store buffer unit, and when core failure information is received, a match between the core number included in the core failure information and the core number in the store buffer unit is checked and matched. 6. The store control apparatus according to claim 5, wherein control is performed to preferentially expel way store data including the core number. The store control device according to claim 1, 2, 3, 4, 5, or 6,
A processor that outputs a store request with store data in units of blocks to the store controller;
A main storage device for storing store data evicted from the store control device;
An information processing apparatus comprising:   A store buffer unit that receives a store request with store data in units of blocks and stores the store data in units of lines including a plurality of blocks, and a store buffer unit that includes a plurality of ways, all the blocks in the line exist in the store buffer unit Store control method characterized by expelling store data in preference to   When there are a plurality of ways in which all the blocks in the line of the store buffer section exist, search is performed sequentially from the way number next to the latest way number, and the store data giving priority to the way in which all the blocks in the line exist The store control method according to claim 8, wherein the store control method is performed.   10. The store control method according to claim 9, wherein when there is no way in which all the blocks in the line of the store buffer unit exist, store data is expelled in preference to the way in which the merged block exists. .

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