JP2018129549A - Plasma processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for plasma processing, which can suppress the occurrence of the potential difference between a wafer and the inner wall face of a process chamber and reduce the deposition of electrically charged contaminations to the wafer during suspension of plasma discharge accompanying the switching of a process.SOLUTION: A plasma processing device comprises: a plasma processing chamber; a radio frequency power source; a sample holder to place a sample on; an electrode disposed in the sample holder for electrostatically attracting the sample; a DC power source for applying a DC voltage to the electrode; and a controller which controls an output voltage of the DC power source so as to reduce the potential difference between the potential of the sample and the potential of the inner wall of the plasma processing chamber to a potential difference within a predetermined range in the event of suspension of plasma discharge.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a technique for manufacturing a semiconductor device. The present invention also relates to a plasma processing apparatus suitable for manufacturing a semiconductor device.

  One of plasma processing methods in the manufacture of semiconductor devices is plasma etching. Plasma etching forms a fine circuit pattern on a wafer by exposing a laminated film of a wafer, which is a semiconductor substrate carried on a mounting table in a plasma processing chamber, to plasma. At this time, various conditions of the plasma processing, that is, gas type, pressure, power value for generating plasma, and the like vary depending on the type of the film to be subjected to plasma processing. Therefore, after the processing of a certain film is completed, it is necessary to switch the plasma processing conditions for the processing of the next film. Since this plasma processing condition and the corresponding processing switching are not stable, it is common to interrupt the plasma discharge in order to prevent unintended etching progress.

  Regarding the plasma processing and the switching of conditions with the interruption of the plasma discharge, it has been pointed out that dust in the processing chamber adheres to the wafer due to the disappearance of the plasma. Hereinafter, dust is referred to as foreign matter. In particular, when a potential is applied to the wafer, foreign matter may be attracted and attached to the wafer by Coulomb force. If foreign matter adheres to the wafer, the foreign matter inhibits etching, leading to a decrease in yield.

  The following are examples of prior art relating to the reduction of foreign matter adhering to the wafer in the plasma treatment.

  In Japanese Patent Laid-Open No. 2001-15581 (Patent Document 1), it is assumed that most of the foreign matters inside the plasma processing chamber are negatively charged, and the wafer is adsorbed to a holding table in the processing chamber using a monopolar adsorption electrode. In this case, it is disclosed that a negative potential is applied to the wafer by applying a negative potential to the electrode for adsorption.

  On the other hand, Japanese Patent Laid-Open No. 2003-100720 (Patent Document 2) discloses that a foreign substance is adsorbed by a foreign substance removing electrode to which a negative potential is applied, assuming that the foreign substance is positively charged.

  Japanese Patent Laid-Open No. 2002-270576 (Patent Document 3) discloses that foreign matter can be obtained by shutting off the power output of the unipolar adsorption electrode and applying no potential to the wafer while plasma processing is not performed. Is disclosed to prevent the wafer from being attracted to the wafer.

JP 2001-15581 A JP 2003-100720 A JP 2002-270576 A

  The techniques of Patent Document 1 and Patent Document 2 assume a situation in which most of the foreign matter is charged positively or negatively. Therefore, when both positive and negative foreign substances exist in the processing chamber, the effect of reducing the adhesion of the foreign substances to the wafer cannot be expected.

  The technique of Patent Document 3 does not take into account the potential of the inner wall surface of the processing chamber that is a foreign material source. Since the inner wall surface of the processing chamber in which the plasma processing is performed is exposed to the plasma, it may be charged by the inflow of charged particles from the plasma and have a potential. When the inner wall surface of the processing chamber has a potential, a potential difference is generated between the wafer and the inner wall surface, so that charged foreign substances may be attracted to the wafer.

  Furthermore, as a factor that causes an unintended potential difference between the wafer and the inner wall surface of the processing chamber, there are a structure of an electrostatic adsorption electrode that is an electrode for adsorbing the wafer onto the mounting table, and aging deterioration. The operation of the electrostatic chucking electrode has a great influence on the adhesion of foreign matter to the wafer due to the Coulomb force.

  An object of the present invention is to suppress the occurrence of an unintended potential difference between the wafer and the inner wall surface of the processing chamber during the interruption of the plasma discharge associated with the switching of the processing and conditions in the plasma processing, and charged foreign matter It is to provide a technique capable of reducing the adhesion of the wafer to the wafer.

  A typical embodiment of the present invention is a plasma processing apparatus having the following configuration.

  In one embodiment, a plasma processing apparatus includes: a plasma processing chamber in which a sample is plasma-processed using plasma; a high-frequency power supply that supplies high-frequency power for generating the plasma; and the sample disposed in the plasma processing chamber A sample stage, an electrode disposed inside the sample stage for electrostatically adsorbing the sample, a direct current power source for applying a direct current voltage to the electrode, and when the plasma is absent, And a control device that controls the DC power supply so as to apply a value obtained as a value of the DC voltage that reduces the potential difference between the potential of the sample and the potential of the inner wall of the plasma processing chamber to the electrode.

  In one embodiment, a plasma processing apparatus includes: a plasma processing chamber in which a sample is plasma-processed using plasma; a high-frequency power supply that supplies high-frequency power for generating the plasma; and the sample disposed in the plasma processing chamber A sample stage, an electrode disposed inside the sample stage for electrostatically adsorbing the sample, a direct current power source for applying a direct current voltage to the electrode, the plasma being absent and the plasma And a control device that controls the DC power supply so that a value obtained as a value of the DC voltage for reducing the potential of the sample when the potential of the inner wall of the processing chamber is substantially 0 is applied to the electrode.

  In the plasma processing apparatus of one embodiment, the electrode has a first electrode to which a positive DC voltage is applied and a second electrode to which a negative DC voltage is applied, and the DC power source is , A first DC power source for applying a DC voltage to the first electrode, and a second DC power source for applying a DC voltage to the second electrode.

  In the plasma processing apparatus of one embodiment, the predetermined range is ± 10V.

  According to a typical embodiment of the present invention, an unintended potential difference is suppressed between the wafer and the processing chamber wall surface during the plasma discharge interruption due to the process switching. The adhesion of charged foreign matter to the wafer can be reduced.

It is a figure which shows the structure of the principal part cross section of the plasma processing apparatus of Embodiment 1 of this invention. 3 is a diagram illustrating an equivalent circuit that models a variable DC power supply, an electrostatic chucking electrode, a dielectric layer, and a wafer in the first embodiment. FIG. It is a time chart which shows the mode of the process in the plasma processing apparatus of one Embodiment. 6 is a time chart showing a state of processing in the plasma processing apparatuses of the first embodiment, the second embodiment, and the third embodiment. 6 is a graph showing a calculation result of an estimate for a reduction effect of adhesion of foreign matters to a wafer in the plasma processing apparatus of the first embodiment. 6 is a graph of a result of a wafer potential test against an output voltage of a variable DC power supply in the plasma processing apparatus of the second embodiment. 6 is a graph showing a change in the number of foreign matters attached to a wafer when an output voltage of a variable DC power supply is changed during discharge interruption in the plasma processing apparatus of the second embodiment. It is a figure which shows the structure of the principal part cross section of the plasma processing apparatus of Embodiment 3. FIG. FIG. 10 is a diagram showing an equivalent circuit that models a variable DC power supply, an electrostatic adsorption electrode, a dielectric layer, a wafer, a test plasma, and a processing chamber in the plasma processing apparatus of the third embodiment. It is a figure which shows the structure of the principal part cross section of the plasma processing apparatus of Embodiment 4. FIG. 6 is a time chart showing a state of processing in the plasma processing apparatus of the fourth embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In the description of each embodiment, “discharge” and “plasma” are mixed, but “discharge” and “plasma” are used as synonyms.

<Summary>
An outline of the present embodiment and the like will be described while supplementally explaining background technology and problems. Conventionally, for plasma processing and switching of conditions, for example, it takes several seconds to tens of seconds. In the case of switching the gas to be used, time is required for exhausting the gas used in the pretreatment from the processing chamber and filling the processing chamber with the gas used in the next processing.

  The electrostatic adsorption electrode and the wafer in the processing chamber are electrically connected with a finite resistance value and a capacitance value by a dielectric layer existing between them. The electrostatic adsorption electrode adsorbs the wafer by Coulomb force. The electrostatic adsorption electrode includes a monopolar type and a multipolar type. Among the multipolar type, those having two electrodes are particularly described as a bipolar type.

  In a monopolar electrode, the potential applied to the electrode affects the potential of the wafer. For example, when a positive potential is applied to a monopolar electrode and the wafer is attracted, a positive potential appears on the wafer when plasma discharge is not performed.

  On the other hand, the bipolar electrode attracts the wafer by applying a potential of opposite polarity to each electrode. At that time, the potential of the wafer is ideally designed to be an average value of potentials applied to both electrodes in many cases. For example, when a potential of +500 V is applied to one electrode and −500 V is applied to the other electrode, the potential of the wafer is 0 V. When a potential of +600 V is applied to one electrode and −400 V is applied to the other electrode, the potential of the wafer is +100 V.

  Factors that cause an unintended potential difference between the wafer and the inner wall surface of the processing chamber include structural problems of the electrostatic chucking electrode and deterioration over time. For example, in the case of adsorption with a bipolar electrode, the resistance value between each of the two electrodes and the wafer when the areas of the two electrodes are different or when foreign matter adheres on the wafer mounting table. There may be differences. In these cases, even if the average value of the potential applied to the two electrostatic adsorption electrodes is set to 0 V, a potential may be generated on the wafer due to the non-uniformity of the mutual electrode state.

  Due to the influence including the electrostatic adsorption electrode, a potential difference larger than a certain level is generated between the wafer and the inner wall surface of the processing chamber during the interruption of the plasma discharge. As a result, charged foreign matter in the processing chamber may be attracted and adhered to the wafer by Coulomb force.

  The plasma processing apparatus according to the embodiment of the present invention is not intended between the wafer and the inner wall surface of the processing chamber due to the influence including the electrostatic adsorption electrode during the interruption of the plasma discharge accompanying the plasma processing and switching of conditions. It has a mechanism to suppress the occurrence of potential difference. Thereby, the charged foreign matter in the processing chamber is reduced from being attracted to and attached to the wafer by the Coulomb force.

<Embodiment 1>
The plasma processing apparatus according to the first embodiment of the present invention will be described with reference to FIGS.

[Plasma processing equipment]
FIG. 1 shows a cross-sectional configuration of the main part of the plasma processing apparatus of the first embodiment. The plasma processing apparatus of the first embodiment shown in FIG. 1 is an electron cyclotron resonance type etching apparatus. Hereinafter, electron cyclotron resonance is referred to as ECR. The plasma processing apparatus according to the present invention is not limited to an ECR type etching apparatus and can be applied.

  The plasma processing apparatus which is the ECR type etching apparatus of FIG. 1 has a wafer 103 which is a semiconductor substrate serving as a sample mounted on a mounting table 102 which is a sample stage inside a processing chamber 101 which is a vacuum processing chamber. Plasma is generated inside the chamber 101.

  The plasma processing apparatus supplies power from the high frequency power source 105 to the high frequency electrode 104 installed inside the mounting table 102 after the plasma is generated. By the supply of the electric power, a negative potential called a self bias is generated on the wafer 103. By drawing ions into the wafer 103 by this negative potential, so-called reactive ion etching occurs, and the etching process proceeds.

  The inner wall base material of the processing chamber 101 includes a grounded conductor. In Embodiment 1, the conductor inner wall base material that is the inner wall base material including the grounded conductor may be exposed to plasma. The conductor inner wall base material may have a thin dielectric film so that the inner wall surface quickly becomes approximately 0 V after the plasma disappears. 101a shows the inner wall surface of the process chamber 101, and the said conductor inner wall base material. 101b shows the grounding regarding the inner wall surface 101a.

  The plasma processing apparatus includes a μ-wave oscillation source 106 and a solenoid coil 107 as a mechanism for generating plasma. The μ wave generated by the μ wave oscillation source 106 is introduced into the processing chamber 101 through the waveguide 108. The μ wave gives energy to electrons by ECR in a magnetic field generated by the solenoid coil 107. The electrons ionize a gas supplied from a gas supply source (not shown) to generate plasma.

  During the plasma treatment, a cooling gas for adjusting the temperature of the wafer 103 is supplied to the back surface of the wafer 103. In order to prevent the wafer 103 from being displaced by the cooling gas, the wafer 103 is adsorbed onto the mounting table 102 by bipolar electrostatic adsorption electrodes 109 and 110. The electrostatic adsorption electrodes 109 and 110 are concentrically arranged such that one of the electrostatic adsorption electrodes 109 is disposed on the inner side and the other electrode is disposed on the outer side. A dielectric layer 111 exists between the electrostatic adsorption electrodes 109 and 110 and the wafer 103. The electrostatic chucking electrodes 109 and 110 and the wafer 103 are electrically connected with a finite resistance and capacitance.

  The electrostatic attraction electrodes 109 and 110 are connected to variable DC power sources 112 and 113 which are independent DC power sources, respectively. One variable DC power source 112 is connected to the inner electrostatic attracting electrode 109, and the other variable DC power source 113 is connected to the outer electrostatic attracting electrode 110.

  A reverse polarity potential is applied to the electrostatic chucking electrodes 109 and 110 by respective power sources. For example, a potential of +500 V is applied to the inner electrostatic chucking electrode 109 by the variable DC power supply 112, and a potential of −500 V is applied to the outer electrostatic chucking electrode 110 from the variable DC power supply 113.

  Further, the plasma processing apparatus of the first embodiment includes a control device 115 and a storage device 114 for controlling the output voltage values of the variable DC power sources 112 and 113. The variable DC power sources 112 and 113 are connected to the control device 115, and the output voltage value is controlled from the control device 115.

  In the first embodiment, the dielectric layer 111 between the electrostatic adsorption electrodes 109 and 110 and the wafer 103 has a resistivity such that a certain amount of leakage current flows. For example, when the dielectric layer 111 is a sprayed film for performing adsorption by the Johnson-Rahbek effect, the above leakage current flows. Note that the Johnson-Rahbek effect is a phenomenon in which an adsorption force is generated by applying a potential difference between a metal surface and a semiconductor surface, and is often used as a method of electrostatic adsorption.

[Equivalent circuit]
FIG. 2 shows an equivalent circuit in which the variable DC power sources 112 and 113, the electrostatic adsorption electrodes 109 and 110, the dielectric layer 111, and the wafer 103 are simply modeled in the plasma processing apparatus of the first embodiment. In this equivalent circuit, the resistance of the wafer 103 is assumed to be negligibly small. In the equivalent circuit of FIG. 2, V ₁ is the voltage of the variable DC power source 112, and V ₂ is the voltage of the variable DC power source 113. R ₁ and R ₂ are resistances of the dielectric layer 111, and C ₁ and C ₂ are capacitances of the dielectric layer 111. R ₁ and C ₁ are the resistance and capacitance on the one electrostatic adsorption electrode 109 side, and R ₂ and C ₂ are the resistance and capacitance on the other electrostatic adsorption electrode 110 side.

_Vwaf , which is the potential of the wafer 103 in a steady state when plasma discharge is not performed, is _expressed by the following formula 1. In Equation 1, R ₁ and R ₂ are resistance values of the resistance of the dielectric layer 111, and V ₁ and V ₂ are output voltage values of the variable DC power sources 112 and 113.

Therefore, when R ₁ = R ₂ in Equation 1, the potential of the wafer 103 is an average value of V ₁ and V ₂ which are output voltage values of the variable DC power sources 112 and 113 which are both power sources.

On the other hand, if the resistance value shifts for some reason and R ₁ ≠ R _{2 in} Equation 1, the potential of the wafer 103 does not become the average value of the output voltage values of both power supplies, and the wafer 103 has no intention. A potential to be applied is applied. When an unintended potential is applied to the wafer 103, there is a possibility that foreign matter charged by the potential difference between the wafer 103 and the inner wall surface 101 a of the processing chamber 101 is attracted to the wafer 103. The inner wall surface 101a of the processing chamber 101 is one of the generation sources of foreign matters.

In order not to generate an unintended potential on the wafer 103, the plasma processing apparatus of the first embodiment has the values of R ₁ and R ₂ that are the resistance values so that the potential applied to the wafer 103 becomes a desired value. Accordingly, the output voltage values V ₁ and V ₂ of the variable DC power sources 112 and 113 are controlled.

  In the first embodiment, the base material of the inner wall surface 101a of the processing chamber 101 is a grounded conductor, and the ground resistance value and ground capacitance on the surface are sufficiently small. Therefore, the potential of the inner wall surface 101a of the processing chamber 101 during the interruption of the plasma discharge becomes approximately 0 V relatively quickly after the end of the discharge. Therefore, in order not to generate a potential difference between the wafer 103 and the inner wall surface 101a of the processing chamber 101, the potential of the wafer 103 may be set to about 0V.

  The ratio of the output voltages of the variable DC power supply 112 and the variable DC power supply 113 at which the potential of the wafer 103 becomes 0V is expressed by the following Expression 2 from Expression 1.

The plasma processing apparatus of the first embodiment is configured to output V ₁ , which are output voltages of the variable DC power sources 112 and 113 connected to the electrostatic chucking electrodes 109 and 110 during interruption of plasma discharge accompanying plasma processing and switching of conditions. V ₂ is changed so as to satisfy Equation 2 above. As a result, the plasma processing apparatus of the first embodiment sets the potential of the wafer 103 to 0 V so as not to generate a potential difference between the wafer 103 and the inner wall surface 101 a of the processing chamber 101.

[Processing time chart]
FIG. 3 is a time chart showing the state of conventional processing including plasma processing in the plasma processing apparatus. In this plasma processing apparatus, the configuration of the processing chamber 101 is the same as that shown in FIG. This is the case of a configuration that does not have

FIG. 3A shows the μ wave incident power, which is the μ wave power from the μ wave oscillation source 106. (B) shows the high frequency bias incident power, which is the power from the high frequency power source 105 to the high frequency electrode 104. (C) shows the variable DC power supply output voltage. A solid line 301 indicates an output voltage of the variable DC power supply 112 to the inner electrostatic adsorption electrode 109, and a broken line 302 indicates an output voltage of the variable DC power supply 113 to the outer electrostatic adsorption electrode 110. In this embodiment, the output voltage is constant without variable control. (D) shows the wafer potential and the inner wall potential. A solid line 311 indicates the potential of the wafer 103, and a broken line 312 indicates the potential of the inner wall surface 101 a of the processing chamber 101. A time T1 from time t0 to t1 indicates a time during plasma discharge. A time T2 from time t1 to t2 indicates a time during which the plasma discharge is interrupted.

  In the case of the processing in the conventional form of FIG. 3, a potential difference as shown by 313 occurs between the wafer potential 311a and the inner wall surface potential 312a at the time T2 during the discharge interruption of (d). . Due to this potential difference, foreign matter may be attracted and attached to the wafer 103.

  FIG. 4 is a time chart showing the state of the processing including the plasma processing in the plasma processing apparatus of the first embodiment, similar to FIG. FIG. 4A shows the μ wave incident power, which is the μ wave power from the μ wave oscillation source 106. (B) shows the high frequency bias incident power, which is the power from the high frequency power source 105 to the high frequency electrode 104. (C) shows the variable DC power supply output voltage. A solid line 401 indicates an output voltage of the variable DC power supply 112 to the inner electrostatic adsorption electrode 109, and a broken line 402 indicates an output voltage of the variable DC power supply 113 to the outer electrostatic adsorption electrode 110. In the first embodiment, the output voltage is variably controlled. (D) shows the wafer potential and the inner wall potential. A solid line 411 indicates the potential of the wafer 103, and a broken line 412 indicates the potential of the inner wall surface 101 a of the processing chamber 101.

  In the plasma processing apparatus of the first embodiment, after the wafer 103 is mounted on the mounting table 102 which is a sample table, the variable DC power source 112 and the variable DC power source 113 are controlled by the control from the control device 115. A predetermined voltage for 103 is output. Thereafter, the plasma processing apparatus prepares for processing such as pressure adjustment inside the processing chamber 101. The illustration of the preparation is omitted.

  After the preparation is completed, a predetermined μ-wave power for plasma generation is applied from time t0 as shown in (a). Thus, after the plasma is generated, at time T1 during discharge, as shown in (b), a high frequency bias is applied to perform an etching process. When the desired etching process is completed, the high frequency bias incident power is first cut off in (b). By the interruption, as shown at time t1 in (d), the potential 411 of the wafer 103 and the potential 412 of the inner wall surface 101a become substantially the same.

  Thereafter, in (a), at the time T2 during the interruption of the discharge, the supply of the μ wave incident power is stopped, and the plasma discharge is interrupted in preparation for the next processing.

  At the moment of the end of the plasma discharge indicated at time t1, the inner wall surface 101a of the processing chamber 101 is charged by the inflow of electrons from the plasma, and has a certain potential as indicated by 412 in (d). This potential changes in accordance with a time constant at which the charge accumulated on the inner wall surface 101a of the processing chamber 101 is released to the ground. In the first embodiment, this time constant is short, and the potential of the inner wall surface 101a of the processing chamber 101 is assumed to be 0 V relatively quickly as indicated by 412a.

  Further, at time t1, a certain amount of leakage current also flows with respect to the potential of the wafer 103. Therefore, the potential generated by charging due to the inflow of charged particles from the plasma disappears relatively quickly, and individual electrodes appear due to the difference in resistance value between inside and outside. It becomes the electric potential according to the characteristic.

For this reason, for example, in the case of R ₁ ≠ R ₂ described above, in the case of the processing of the plasma processing apparatus of the embodiment of FIG. 3, as shown in FIG. The potential of the inner wall surface 101a becomes 0V as in 312a, but the potential of the wafer 103 does not become 0V as in 311a. That is, a potential difference 313 is generated between the wafer 103 and the inner wall surface 101a.

  On the other hand, in the processing of the plasma processing apparatus of the first embodiment in FIG. 4, the control device 115 performs variable control of the output voltages of the variable DC power source 112 and the variable DC power source 113 in (c). 400 of (c) shows the change of the output voltage of this variable DC power supply 112 and the variable DC power supply 113 and its time.

  The control device 115 changes the potential of the wafer 103 as shown in (d) by controlling the output voltage in (c). That is, in (d), the control device 115 sets the output voltage so that the potential 411 of the wafer 103 at time T1 during discharge becomes 0 V as at 411a at time T2 during discharge interruption. Change to satisfy Equation 2.

  In (c), at time T1 during discharge, 401 which is the output voltage of the variable DC power source 112 is a predetermined positive voltage, and 402 which is the output voltage of the variable DC power source 113 is a predetermined negative voltage. is there. The control device 115 performs control to maintain the respective predetermined output voltage values for 400 times at the time T2 when the discharge is interrupted. In other words, the control device 115 changes the output voltage 401 of the variable DC power source 112 so as to increase by a predetermined voltage for 400 time, and maintains the voltage state of 401a. Similarly, the control device 115 changes the output voltage 402 of the variable DC power supply 113 so as to increase by a predetermined voltage at a time of 400, and maintains the voltage state of 402a. Accordingly, in (d), at time 400, the potential 411a of the wafer 103 approaches 0 V, similar to 412a which is the potential of the inner wall surface 101a.

  In the plasma processing apparatus of the first embodiment, the change in the output voltage value of the variable DC power sources 112 and 113 to the electrostatic adsorption electrodes 109 and 110 is achieved as follows. That is, the storage device 114 stores the output voltage values of the variable DC power sources 112 and 113 to be output at the time T2 when the plasma discharge is interrupted. The control device 115 variably controls the output voltage values of the variable DC power sources 112 and 113 so that the output voltage value stored in the storage device 114 becomes the output voltage value stored in the storage device 114 at the time T2 when the discharge is interrupted.

  The plasma processing apparatus may include a user interface for setting the output voltage value of the control in the storage device 114 based on a user operation.

  The plasma processing apparatus of the first embodiment eliminates the potential difference between the wafer 103 and the inner wall surface 101a at the time T2 during the discharge interruption by the operation including the above control. In 400 of (d), the potential difference is substantially 0 V as in 411a and 412a. This prevents foreign matter from being attracted and attached to the wafer 103.

  The plasma processing apparatus prepares for the next discharge process such as pressure adjustment in the processing chamber 101 while maintaining a predetermined output voltage at time T2 400 under the control of the control apparatus 115. After the preparation is completed, the plasma processing apparatus stops the control at 400 by the control apparatus 115. Thereby, the variable DC power sources 112 and 113 output a predetermined voltage for the next discharge process, that is, the same voltage as 401 and 402. Thereafter, supply of μ wave incident power is started from time t2, and the next discharge process is performed.

  The plasma processing apparatus repeats the control including the plasma discharge process and the discharge interruption as described above until the final discharge process is completed, and after the final discharge process is completed, the variable DC power supply is passed through a predetermined wafer neutralization sequence. The voltages of 112 and 113 are cut off.

[Effects]
In order to eliminate the potential difference between the wafer 103 and the inner wall surface 101a of the processing chamber 101 while the plasma discharge is interrupted, how much the potential difference should be reduced is sufficient to obtain the effect of reducing the adhesion of foreign matter. We examined as follows.

  FIG. 5 is a graph showing a result obtained by estimating the effect of reducing the adhesion of charged foreign matter to the wafer 103 in the plasma processing apparatus of the first embodiment by calculation. The horizontal axis of the graph represents the potential difference [V] between the wafer 103 and the inner wall surface 101 a of the processing chamber 101. The vertical axis of the graph represents the adhesion rate [%] of foreign matter to the wafer 103.

This estimate was calculated under the following conditions. It was assumed that the pressure in the processing chamber 101 was 0.6 Pa, and that there was a gas flow toward the exhaust port at an average of about 3 m / s in the processing chamber 101. It is assumed that 1000 foreign matters are generated from the side surface of the inner wall surface 101 a of the vacuum processing chamber 101. The occurrence position of the foreign matter is specified within a rough range, and the occurrence location of each of the 1000 individual foreign matters is randomly determined within the specified range. As the particle size of the foreign matter, a value of 15 nm or more and 120 nm or less was randomly given for each of 1000 foreign matters. Regarding the initial speed of the foreign matter, a value of 5 m / s or less was randomly given for each of the 1000 foreign matters. In this calculation, in order to estimate the effect of attracting the charged foreign matter to the wafer 103, the charge of the foreign matter was set to −1.6 × 10 ⁻¹⁹ [C] for all 1000 foreign matters.

  The adhesion rate of foreign matter to the wafer 103 was calculated under the above conditions. As a result, as shown in FIG. 5, when the potential difference between the wafer 103 and the inner wall surface 101a of the processing chamber 101 is +10 V, the foreign matter adhering to the wafer 103 is about 2%. This adhesion rate is not so different from the adhesion rate when the potential difference is 0V. However, when the potential difference between the wafer 103 and the inner wall surface 101a of the processing chamber 101 is +20 V, the result is that the adhesion rate increases to about 8%.

  From the above results, in the plasma processing apparatus of the first embodiment, the potential difference between the wafer 103 and the inner wall surface 101a during the plasma discharge interruption, which can sufficiently reduce the adhesion of foreign matter, is set within ± 10V. In FIG. 4D, the potential difference at the time T2 during the interruption of the discharge is shown as 0V. However, if the potential difference is within ± 10V, a correspondingly sufficient effect can be obtained.

  As described above, according to the plasma processing apparatus and the plasma processing method of the first embodiment, during the interruption of the plasma discharge accompanying the plasma processing and the switching of the conditions, the gap between the wafer 103 and the inner wall surface 101a of the processing chamber 101 is obtained. It is possible to suppress the occurrence of an unintended potential difference, and to reduce the adhesion of charged foreign matter to the wafer 103.

<Embodiment 2>
A plasma processing apparatus according to the second embodiment of the present invention will be described with reference to FIGS. In the following, the configuration of the second embodiment different from that of the first embodiment will be described. In the plasma processing apparatus of the second embodiment, the output voltage of the variable DC power sources 112 and 113 during the interruption of discharge in the plasma processing apparatus of the first embodiment is obtained by dividing the potential of the wafer 103 and the output voltages of the variable DC power sources 112 and 113. Decide based on measurements to understand the relationship between them.

  In the first embodiment, the configuration in which the potential of the wafer 103 is determined based on the resistance value of the dielectric layer 111 between the wafer 103 and the electrostatic chucking electrodes 109 and 110 has been described. However, when the resistance value cannot be accurately grasped or when an unintended potential is generated due to other factors, the configuration of the first embodiment cannot be applied.

In that case, it is effective to apply the configuration of the second embodiment. In the second embodiment, the relationship between V _waf that is the potential of the wafer 103 and V ₁ and V ₂ that are the output voltage values of the variable DC power sources 112 and 113 is grasped by measurement. Thereby, it is possible to perform control to reduce the potential difference between the wafer 103 and the inner wall surface 101a of the processing chamber 101 while the plasma discharge is interrupted. The work including grasping by the above measurement is hereinafter referred to as a test.

  The plasma processing apparatus according to the second embodiment includes a mechanism including an experimental apparatus as means for performing the above-described test in addition to the same components as those of the plasma processing apparatus according to the first embodiment. In the plasma processing method in the plasma processing apparatus of the second embodiment, the above test is first performed in the same plasma processing apparatus configuration as that of the first embodiment.

  The above assay is realized by the following means and procedures, for example. The plasma processing apparatus of the second embodiment is provided with a mechanism that can measure the potential of the wafer 103. This mechanism is realized by, for example, attaching the potential measurement probe to the wafer 103 by opening the processing chamber 101 to the atmosphere. The plasma processing apparatus of the second embodiment uses this measurement mechanism to measure the potential of the wafer 103 when the output voltage of the variable DC power sources 112 and 113 is variously changed by the control device 115.

[Test]
FIG. 6 shows a calibration of the potential of the wafer 103 and the output voltages of the variable DC power sources 112 and 113 using the test means including the experimental apparatus and the measurement mechanism in the plasma processing apparatus of the second embodiment. The graph which is an example of the result is shown. The horizontal axis of the graph represents the average value [V] of the output voltages of the variable DC power supplies 112 and 113. The vertical axis of the graph represents the potential [V] of the wafer 103. In addition, this test was performed without generating plasma.

  In this test, the following conditions were used. The output voltage was based on + 500V for the variable DC power supply 112 of the inner electrostatic adsorption electrode 109 and -500V for the variable DC power supply 113 of the outer electrostatic adsorption electrode 110. The change in the output voltage is changed by an equal amount in both the variable DC power supply 112 and the variable DC power supply 113. For example, when the average value of the output voltage of the variable DC power supply on the horizontal axis in FIG. 6 is changed by + 10V, the output voltages of both the variable DC power supply 112 and the variable DC power supply 113 are changed by + 10V. In this case, the output voltage of the variable DC power source 112 is + 510V, and the output voltage of the variable DC power source 113 is −490V.

  In the plasma processing apparatus of the second embodiment, when the average value of the output voltages of the variable DC power sources 112 and 113 is 0V as shown in FIG. Had been granted. When the average value of the output voltage was changed, the potential of the wafer 103 was changed by almost the same amount as the change amount of the average value. The average value of the output voltage at which the potential of the wafer 103 becomes 0V was about + 40V.

In the plasma processing apparatus of the second embodiment, as in the first embodiment, the potential of the inner wall surface 101a of the processing chamber 101 during the interruption of the plasma discharge becomes approximately 0 V relatively quickly after the end of the discharge. Therefore, in the plasma processing apparatus of the second embodiment, the control device 115 sets the average value of the output voltages of the variable DC power sources 112 and 113 to +40 V during the discharge interruption. Thereby, as shown in FIG. 4D, the potential difference between the wafer 103 and the inner wall surface 101a can be eliminated.

The output voltage values of the variable DC power sources 112 and 113 during the plasma discharge interruption determined by the above test are V _1ctrl and V _2ctrl . In FIG. 4, 401a corresponds to V _1ctrl and 402a corresponds to V _2ctrl . The storage device 114 stores the values of V _1ctrl and V _2ctrl . As in FIG. 4C, the plasma processing apparatus sets the output voltage values of the variable DC power sources 112 and 113 to V _1ctrl , V at 400 time by the control device 115 at time T2 during plasma discharge interruption. _Control to be 2 _ctrl .

[Effects]
FIG. 7 shows the foreign matter adhering to the wafer 103 when the output voltages of the variable DC power sources 112 and 113 are changed variously during the interruption of discharge as an effect of reducing the adhesion of foreign matter in the plasma processing apparatus of the second embodiment. It is a graph showing the change of a number. The horizontal axis of the graph indicates the average value [V] of the output voltages of the variable DC power supplies 112 and 113 and the potential [V] of the wafer 103 associated therewith. The vertical axis of the graph indicates the number of foreign matters attached to the wafer 103. The number of foreign objects indicates a value normalized by the number of foreign objects when the average value of the output voltages of the variable DC power sources 112 and 113 is 0V.

  As shown in FIG. 7, when the average value of the output voltages of the variable DC power sources 112 and 113 is around +40 V, that is, when the potential of the wafer 103 is around 0 V, the variable DC power sources 112 and 113 which are conventional normal operations are used. Compared with the case where the average value of the output voltage of 0V is 0V, the foreign matter reduction effect of about 40% was obtained. In addition, when the potential of the wafer 103 is negative, the number of foreign matters attached to the wafer 103 increases as the absolute value of the potential of the wafer 103 increases. On the other hand, when the potential of the wafer 103 is positive, even if the absolute value of the potential of the wafer 103 is increased, the number of foreign matters attached to the wafer 103 does not change greatly.

  From the above results, the following two points are estimated. One point is that most of the charged foreign matter in the processing chamber 101 is positively charged. The increase in adhering foreign matter when the potential of the wafer 103 is negative is considered to be a result of attracting the positively charged foreign matter to the potential of the wafer 103.

  Another point is that the effect of the technique of applying a potential having the same polarity as the charge of the foreign matter to the wafer 103 and repelling the charged foreign matter flying to the wafer 103 to reduce the foreign matter is small. This is judged from the fact that, although the presence of the positively charged foreign matter is suggested from the above-mentioned results, the effect of reducing the foreign matter was not obtained even when a positive potential was applied to the wafer 103. The In this regard, the foreign matter generated during the interruption of discharge has a sufficiently small initial velocity when it is generated from the inner wall surface 101a of the processing chamber 101, and if there is no potential difference between the wafer 103 and the inner wall surface 101a, the wafer 103 This can be explained by thinking that there are few foreign objects that can fly. Therefore, it can be said that it is important to control the potential so that charged foreign matters are not attracted to the wafer 103 unnecessarily during discharge interruption.

  The plasma processing apparatus of the second embodiment takes the above two points into consideration, and controls the variable DC power sources 112 and 113 by the controller 115 so that charged foreign matter is not unnecessarily attracted to the wafer 103 during discharge interruption. The potential of the wafer 103 is controlled by controlling the output voltage.

  From the above results, according to the plasma processing apparatus of the second embodiment, charging was suppressed by suppressing the occurrence of an unintended potential difference between the wafer 103 and the inner wall surface 101a of the processing chamber 101 during discharge interruption. It was confirmed that adhesion of foreign matter to the wafer 103 can be reduced.

<Embodiment 3>
A plasma processing apparatus according to the third embodiment of the present invention will be described with reference to FIGS. Hereinafter, a part of the third embodiment having a configuration different from that of the first and second embodiments will be described.

[Plasma processing equipment]
FIG. 8 shows a cross-sectional configuration of the main part of the plasma processing apparatus of the third embodiment. The plasma processing apparatus of Embodiment 3 in FIG. 8 is also an ECR type etching apparatus, but is not limited to the ECR type and can be applied. In addition to the constituent elements of the plasma processing apparatuses of the first embodiment and the second embodiment, the plasma processing apparatus of the third embodiment includes an examination means different from that of the second embodiment. The means for verification in the third embodiment includes a mechanism for performing verification of the plasma processing apparatus without opening the processing chamber 101 to the atmosphere. The plasma processing method in the plasma processing apparatus of the third embodiment includes a procedure for performing an assay using the assay means.

  In FIG. 8, the plasma processing apparatus of the third embodiment includes ammeters 801 and 802 and a control device 803 as components of the above-described verification means. The ammeters 801 and 802 are ammeters that measure the current flowing from the variable DC power sources 112 and 113 to the wafer 103, and are connected to the control device 803. The control device 803 is provided in place of the above-described control device 115, and includes a function for controlling the test. The control device 803 controls the output voltage values of the variable DC power sources 112 and 113 so that the currents measured by the ammeters 801 and 802 are equal to each other.

  In particular, the ammeters 801 and 802 may be ammeters that detect current flowing from the electrostatic adsorption electrodes 109 and 110 on the mounting table 102 to the wafer 103 via the dielectric layer 111.

  The plasma processing apparatus of the third embodiment generates a verification plasma 804 that is a plasma for verification in the processing chamber 101 when performing the verification. Hereinafter, the plasma discharge of the test plasma 804 is referred to as test discharge.

[Equivalent circuit]
FIG. 9 shows variable DC power sources 112 and 113, electrostatic adsorption electrodes 109 and 110, dielectric layer 111, wafer 103, verification plasma 804, and vacuum during verification discharge in the plasma processing apparatus of the third embodiment. An equivalent circuit in which the processing chamber 101 is simply modeled is shown. I ₁ is the current of the ammeter 801, and I ₂ is the current of the ammeter 802. I ₃ is the current from the wafer 103 to the verification plasma 804. R ₃ is the resistance value of the test plasma 804, and C ₃ is the capacitance value of the test plasma 804. R ₄ is the ground resistance of the inner wall surface 101 a of the processing chamber 101, and C ₄ is the ground capacitance of the inner wall surface 101 a of the processing chamber 101.

During the verification discharge, the wafer 103 and the inner wall surface 101a of the processing chamber 101 are electrically connected by the verification plasma 804. At this time, the resistance value R ₃ and the capacitance value C ₃ through the plasma between the wafer 103 and the inner wall surface 101 a of the processing chamber 101 are the resistance between the wafer 103 and the electrostatic adsorption electrodes 109 and 110. The values R ₁ and R ₂ are sufficiently smaller than the capacitance values C ₁ and C ₂ , respectively.

In the plasma processing apparatus of the third embodiment, the ground resistance R ₄ and the ground capacitance C ₄ of the inner wall surface 101 a of the processing chamber 101 are also the resistance values R ₁ and R ₂ and the capacitance values C ₁ and C. Small enough compared to ₂ . Therefore, the potential of the wafer 103 is approximately 0 V during the verification discharge.

In addition, when the current I ₃ flows through the verification plasma 804, different currents I ₁ and I ₂ flow through the ammeter 801 and the ammeter 802. In the plasma processing apparatus of the third embodiment, the control device 803 sets the output voltage values V ₁ and V ₂ so that the values of these two currents are equal. With this setting, the current I ₃ does not flow in the verification plasma 804. That is, the state is equivalent to an equivalent circuit when there is no plasma discharge. The output voltage values V ₁ and V ₂ of the variable DC power sources 112 and 113 determined as described above are V _1ctrl and V _2ctrl which are output voltages such that the potential of the wafer 103 becomes 0V even when there is no plasma discharge. Become.

  The plasma processing apparatus according to the third embodiment performs a test discharge in a necessary unit and timing such as for each wafer processing or for each lot. During the calibration discharge, first, the wafer 103 is carried into the mounting table 102 in the vacuum processing chamber 101. The wafer 103 is attracted to the mounting table 102 by electrostatic attracting electrodes 109 and 110. The adsorption voltage at this time is set to a value generally used when processing a product wafer.

Thereafter, the plasma processing apparatus makes preparations for verification discharge such as pressure adjustment in the processing chamber 101. After the preparation is completed, the plasma processing apparatus generates plasma by applying predetermined μ-wave power for generating plasma. After plasma generation, current is measured by ammeters 801 and 802. The control device 803 monitors the current values I ₁ and I ₂ of the ammeters 801 and 802. The control device 803 outputs the output voltages of the variable DC power sources 112 and 113 so that the difference between the current values I ₁ and I ₂ is within ± 1% with respect to the sum of the absolute values of the current values. V ₁ and V ₂ are controlled. In addition, the change of the output voltage of the said variable DC power supply 112,113 shall be changed by the same quantity similarly to the above-mentioned.

In the above control, when the difference between the current values is within ± 1% of the sum of the absolute values of the current values, the control device 803 stops the control of the output voltages of the variable DC power sources 112 and 113. The values of V ₁ and V ₂ , which are output voltage values, are stored in the storage device 114. The values of V ₁ and V ₂ stored here are the above-described V _1ctrl and V _2ctrl .

  The difference between the current values, which is a condition for stopping the control of the output voltage of the variable DC power sources 112 and 113 during the verification discharge, should not be within ± 1% of the sum of the absolute values of the current values. It doesn't matter. However, as described above, it is desirable that the potential difference between the wafer 103 and the inner wall surface 101a can be made sufficiently small so as to obtain a foreign matter reducing effect.

In the third embodiment, the reason for stopping the control is that the difference between the current values is within ± 1% of the sum of the absolute values of the current values for the following reason. The potential difference between the electrostatic chucking electrode 109 and the electrostatic chucking electrode 110 in the first embodiment is 1000V. With respect to the potential difference of 1000 V, the allowable potential difference between the wafer 103 and the inner wall surface 101 a from which the effect of reducing foreign matter is obtained is ± 10 V. The allowable potential difference of ± 10 V is ± 1% of 1000 V that is the potential difference between the electrostatic adsorption electrode 109 and the electrostatic adsorption electrode 110. Therefore, as a condition for stopping the control, the difference between the current values is within ± 1% of the sum of absolute values of the current values.

The plasma processing apparatus processes the product wafer after the verification. In the processing of the product wafer, the plasma processing apparatus controls the output voltage values of the variable DC power sources 112 and 113 by the control device 803 while the plasma discharge is interrupted, as in FIG. _4C , V _1ctrl , _Control to be V 2 _ctrl .

[Effects]
As described above, according to the plasma processing method of the plasma processing apparatus of the third embodiment, the verification is performed without opening the processing chamber 101 to the atmosphere. Then, according to the present plasma processing method, an unintended potential difference is suppressed from occurring between the wafer 103 and the inner wall surface 101a of the processing chamber 101 during plasma discharge interruption during processing of the product wafer. Thereby, adhesion of charged foreign matter to the wafer 103 can be reduced.

<Embodiment 4>
A plasma processing apparatus according to the fourth embodiment of the present invention will be described with reference to FIGS. Hereafter, the part of the configuration different from the above-described embodiment in Embodiment 4 will be described.

[Plasma processing equipment]
FIG. 10 shows a cross-sectional configuration of the main part of the plasma processing apparatus of the fourth embodiment. The plasma processing apparatus of the fourth embodiment shown in FIG. 10 is also an ECR type etching apparatus, but is not limited to an ECR type etching apparatus and can be applied. The plasma processing apparatus of the fourth embodiment includes a wafer potential measurement probe 1001, an inner wall surface potential measurement probe 1002, and a control device 1003 in addition to the above-described components.

  The wafer potential measurement probe 1001 is a probe that measures the potential of the wafer 103 in the processing chamber 101. The inner wall potential measurement probe 1002 is a probe that measures the potential of the inner wall surface 101 a of the processing chamber 101.

  The control device 1003 is provided in place of the control device 115 and monitors the potential measurement results of the wafer potential measurement probe 1001 and the inner wall potential measurement probe 1002 which are both probes, and the variable DC power sources 112 and 113 based on the results. It has a function to control the output voltage.

  In the fourth embodiment, the base material of the inner wall surface 101a of the processing chamber 101 is, for example, a grounded conductor as described above. However, the present invention is not limited to this, and the fourth embodiment can be suitably applied to the case where the base material of the inner wall surface 101a is not grounded or the material of the base material is not a conductor.

  The base material of the inner wall surface 101a may be exposed to plasma. When the base material is grounded, there may be a thin dielectric film whose surface of the inner wall surface 101a quickly becomes approximately 0 V after the plasma disappears. Furthermore, the fourth embodiment can be suitably applied even when the dielectric film of the base material of the inner wall surface 101a is thick and the time constant of potential change ranges from several seconds to several tens of seconds or longer. .

In the fourth embodiment, the dielectric layer 111 between the electrostatic chucking electrodes 109 and 110 and the wafer 103 may have a resistivity such that a certain amount of leakage current flows, or almost no leakage current flows. It may be such a resistivity. For example, the dielectric layer 111 may be a sprayed film for performing adsorption by the above-mentioned Johnson-Rahbek effect, or a sintered body whose resistivity is about 10 ⁵ to 10 ⁶ times higher than that. Also good.

  In the plasma processing method in the plasma processing apparatus of the fourth embodiment, the measurement of the potential of the wafer 103 and the potential of the inner wall surface 101a is performed using the wafer potential measuring probe 1001 and the inner wall surface potential measuring probe 1002 while the plasma discharge is interrupted. Done. The control device 1003 monitors the measurement results of both these probes. The control device 1003 controls the output voltages of the variable DC power sources 112 and 113 so that the potential difference between the wafer 103 and the inner wall surface 101a becomes small based on the potential of the wafer 103 and the potential of the inner wall surface 101a as the measurement results. . In the fourth embodiment, the output voltage of the variable DC power sources 112 and 113 is changed by the same amount as described above.

  The plasma processing apparatus of the fourth embodiment eliminates the potential difference between the wafer 103 and the inner wall surface 101a of the processing chamber 101 while the plasma discharge is interrupted by performing the above-described control by the control device 1003. Thereby, the charged foreign matter is prevented from being attracted and attached to the wafer 103.

[Processing time chart]
FIG. 11 shows a time chart of processing including plasma processing in the plasma processing apparatus of the fourth embodiment in the same manner as described above. The processing of FIG. 11 differs from the above-described FIG. 4 in the forms of (c) and (d) at time T2 during the interruption of plasma discharge.

  In the variable DC power supply output voltage of (c), 1101 is a predetermined positive voltage as a reference as the output voltage of the variable DC power supply 112 to the inner electrostatic adsorption electrode 109. Reference numeral 1102 denotes a predetermined negative voltage as a reference as an output voltage of the variable DC power supply 113 to the outer electrostatic adsorption electrode 110. Reference numeral 1100 denotes a change in the output voltage and its time under the control of the control device 1003 at time T2 during discharge interruption. The control device 1003 performs control to change the output voltage values of the variable DC power supply 112 and the variable DC power supply 113 at time 1100.

  At time 1100, 1101 which is the output voltage of the variable DC power supply 112 changes as 1101a, and 1102 which is the output voltage of the variable DC power supply 113 changes as 1102a. 1101a changes from a state where the predetermined voltage is lower than the voltage value of 1101 to a state where the potential gradually increases and reaches a state where the predetermined voltage is higher than the voltage value of 1101. Similarly, 1102a changes from a state where the voltage is lower than the voltage value of 1102 to a state where the potential is gradually increased and is higher than the voltage value of 1102.

  In (d), the wafer potential and the inner wall surface potential, 1111 indicates the potential of the wafer 103, and 1112 indicates the potential of the inner wall surface 101a. At time t1 when the discharge ends at time T1, 1111 and 1112 have the same potential as described above. At time T2, the potential 1111 of the wafer 103 changes as 1111a. 1111a is a form in which the potential gradually decreases to 0 V after the potential once decreases slightly at 1100 time. Similarly, 1112 which is the electric potential of the inner wall surface 101a changes like 1112a. 1112a gradually approaches 0V at 1100 time. Immediately after time t1, there is a potential difference between 1111 and 1112. Thereafter, the potential difference becomes approximately 0V. In the time of 1100, the potential difference between 1111a and 1112a is almost 0V.

  In the plasma processing apparatus of the fourth embodiment, the pressure in the processing chamber 101 is controlled in the same manner as described above while controlling the output voltage of the variable DC power sources 112 and 113 by the control device 1003 at the time T2 during the interruption of the discharge. Prepare for the next discharge treatment, such as adjustment. After the preparation is completed, the plasma processing apparatus stops the control such as 1100 by the control apparatus 1003. Thereby, the variable DC power sources 112 and 113 output a predetermined voltage for the next discharge process. Thereafter, the supply of μ-wave power is started, and the next discharge process is similarly performed.

  The plasma processing apparatus according to the fourth embodiment is configured to continue to control the output voltages of the variable DC power sources 112 and 113 so that the potential difference between the wafer 103 and the inner wall surface 101a is reduced.

  Not limited to this, the output voltage may be controlled so that the potential difference between the wafer 103 and the inner wall surface 101a is within a predetermined value. In the case of this embodiment, the potential difference between the wafer 103 and the inner wall surface 101a may be controlled to be within ± 10 V using, for example, a value that is a guideline for obtaining a foreign matter reduction effect in the first embodiment. .

[Effects]
As described above, according to the plasma processing method in the plasma processing apparatus of the fourth embodiment, in the processing of the product wafer, an unintended potential difference is generated between the wafer 103 and the inner wall surface 101a while the plasma discharge is interrupted. It is possible to suppress the adhesion of foreign matter to the wafer 103.

  As described above, the present invention has been specifically described based on the embodiment. However, in the present invention, when the wafer is mounted on the wafer mounting table and the plasma is not generated, the wafer and the processing chamber wall surface are formed. The present invention relates to a plasma processing apparatus for controlling the output voltage of a variable DC power supply for a wafer attracting electrode so as to reduce a potential difference.

  In addition, this invention is not limited to each Example mentioned above, Various modifications are included in the range which does not deviate from the summary of this invention. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of the other embodiment, and the configuration of the other embodiment can be added to the configuration of the one embodiment. Furthermore, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  For example, the above-mentioned “when the wafer is placed on the sample stage and no plasma is generated” is not only during the discharge interruption in the first to fourth embodiments, but also the wafer is carried into the processing chamber, The period until the plasma discharge is started is also included.

  In each embodiment, when the average value of the output voltage of the variable DC power supply 112 and the variable DC power supply 113 is changed, the same amount is changed in both the variable DC power supply 112 and the variable DC power supply 113. . This voltage change may be changed by different amounts in each of the variable DC power supply 112 and the variable DC power supply 113. For example, when the average value of the output voltages of the variable DC power sources 112 and 113 is changed by +10 V from the state where the output voltage of the variable DC power source 112 is +500 V and the output voltage of the variable DC power source 113 is −500 V, the variable DC power source 112 is changed. May be set to + 520V, and the output voltage of the variable DC power supply 113 may be set to -500V.

  Further, in each of the embodiments, the case has been described where the output voltage values of the variable DC power supply 112 and the variable DC power supply 113 are respectively changed. However, it is not always necessary to change both of the voltage values, and at least the variable DC power supply 112 is variable. Control may be performed so that the potential difference between the inner wall surface of the processing chamber and the wafer becomes zero by the voltage value of the output of the DC power source 112 or the variable DC power source 113. Note that when the voltage values of the outputs of the variable DC power supply 112 and the variable DC power supply 113 are respectively changed, the wafer is more effective than when only the voltage value of one output of the variable DC power supply 112 or the variable DC power supply 113 is changed. Can be stably electrostatically adsorbed to the sample stage.

  In addition, for example, the plasma processing apparatus according to the fourth embodiment includes an inner wall surface potential measurement probe that measures a wall surface potential. However, as described in Examples 1 to 3, in the present invention, the inner wall surface potential is interrupted by plasma. When it is estimated that the voltage quickly reaches 0V, a configuration without the inner wall surface potential measurement probe may be used. Further, for example, the present invention may be configured not to include the inner wall surface potential measurement probe even when the inner wall surface potential during plasma interruption is measured and grasped in advance.

  Further, for example, when the inner wall surface is charged with plasma and the potential can be reliably estimated from the plasma parameters, the present invention may be configured without the inner wall potential measuring probe. In addition to the above-described example, the present invention can also be applied to the inner wall surface potential when the potential is generated on the inner wall surface due to various factors and the potential can be reliably estimated by a method other than the direct measurement of the inner wall surface potential. A configuration without a measurement probe may be used.

  As described above, the technical idea of the present invention is “to reduce the potential difference between the potential of the sample and the potential of the inner wall of the plasma processing chamber in the absence of plasma”. Further, when the potential of the inner wall of the plasma processing chamber is substantially zero, the technical idea of the present invention can be expressed as “reducing the potential of the sample when plasma is absent”. it can. Furthermore, the present invention can be variously modified without departing from the gist of the technical idea of the present invention.

  In addition, the present invention provides that the plasma does not have a voltage value of the DC power source determined in advance as a voltage value of the DC power source that reduces the potential difference between the potential of the sample and the potential of the inner wall of the plasma processing chamber in the absence of plasma. In the case of existence, the output value of the DC power supply is also included. Furthermore, the present invention outputs the voltage value of the DC power source obtained in advance as the voltage value of the DC power source for reducing the potential of the sample in the absence of plasma as the output value of the DC power source in the absence of plasma. Also includes form.

DESCRIPTION OF SYMBOLS 101 ... Processing chamber, 101a ... Inner wall surface, 102 ... Mounting stage, 103 ... Wafer, 104 ... High frequency electrode, 105 ... High frequency power source, 106 ... Microwave oscillation source, 107 ... Solenoid coil, 108 ... Waveguide, 109, 110 ... Electrostatic adsorption electrode, 111 ... Dielectric layer, 112, 113 ... Variable DC power supply, 114 ... Memory device, 115, 803, 1003 ... Control device, 801, 802 ... Ammeter, 804 ... Plasma for verification, 1001 ... Wafer Potential measurement probe, 1002... Inner wall surface potential measurement probe.

Claims (10)

A processing chamber in which a sample is plasma-treated using plasma;
A high frequency power supply for supplying high frequency power for generating the plasma;
An electrode for electrostatically adsorbing the sample, and a sample stage on which the sample is placed;
A DC power supply for applying a DC voltage to the electrodes;
And a control device that controls the DC power supply so as to apply a voltage value to the electrode to reduce the absolute value of the potential of the sample in the absence of the plasma when the plasma is absent. A plasma processing apparatus. A processing chamber in which a sample is plasma-treated using plasma;
A high frequency power supply for supplying high frequency power for generating the plasma;
An electrode for electrostatically adsorbing the sample, and a sample stage on which the sample is placed;
A DC power supply for applying a DC voltage to the electrodes;
When the plasma is not present, the direct current is applied so that a voltage value that reduces the absolute value of the potential difference between the potential of the sample and the potential of the inner wall of the processing chamber when the plasma is absent is applied to the electrode. A plasma processing apparatus comprising: a control device that controls a power source. In the plasma processing apparatus according to claim 1 or 2,
The plasma processing apparatus, wherein the voltage value is obtained based on a resistance value between the sample and the electrode. In the plasma processing apparatus according to claim 1 or 2,
The plasma processing apparatus according to claim 1, wherein the voltage value is a voltage value at which the potential of the sample is in a range of −10 to + 10V. In the plasma processing apparatus according to claim 1 or 2,
The plasma processing apparatus characterized in that the value of the DC voltage when the plasma is absent is larger than the value of the DC voltage when the plasma is present. The plasma processing apparatus according to claim 5, wherein
The plasma processing apparatus is characterized in that the value of the DC voltage when the plasma is absent is gradually larger than the value of the DC voltage when the plasma is present. The plasma processing apparatus according to claim 1,
The plasma processing apparatus, wherein the voltage value is obtained based on correlation data obtained in advance between the potential of the sample and the DC voltage. The plasma processing apparatus according to claim 2, wherein
The plasma processing apparatus, wherein the voltage value is obtained based on correlation data obtained in advance between the potential difference and the DC voltage. In the plasma processing apparatus according to claim 1 or 2,
The plasma processing apparatus, wherein the voltage value is obtained based on a value of a current flowing through the sample. The plasma processing apparatus according to claim 9, wherein
The plasma processing apparatus, wherein the current value is a value obtained in advance.

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