JP2018107296A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
JP2018107296A
JP2018107296A JP2016252468A JP2016252468A JP2018107296A JP 2018107296 A JP2018107296 A JP 2018107296A JP 2016252468 A JP2016252468 A JP 2016252468A JP 2016252468 A JP2016252468 A JP 2016252468A JP 2018107296 A JP2018107296 A JP 2018107296A
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JP
Japan
Prior art keywords
pad
wire
corner
group
semiconductor chip
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Application number
JP2016252468A
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Japanese (ja)
Inventor
祐貴 ▲柳▼生
祐貴 ▲柳▼生
Yuki Yagyu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2016252468A priority Critical patent/JP2018107296A/en
Priority to US15/829,250 priority patent/US10128130B2/en
Priority to TW106143636A priority patent/TW201839943A/en
Priority to EP17208831.2A priority patent/EP3349240A1/en
Priority to KR1020170177023A priority patent/KR20180076318A/en
Priority to CN201711425972.5A priority patent/CN108242408B/en
Publication of JP2018107296A publication Critical patent/JP2018107296A/en
Priority to HK18109635.2A priority patent/HK1250281A1/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To achieve a small-sized and highly reliable semiconductor device.SOLUTION: A semiconductor device manufacturing method includes a mold process in which bonding wires BW located near a gate and bonding wires BW located near a vent opposite to the gate across the center of a semiconductor chip SC have loop shapes falling inside the semiconductor chip SC, and each of which has a weaker pulling force (tension) compared with other bonding wires BW and is pulled loosely and gently. In the mold process, the bonding wires BW located near the gate are the first wire W1 and the fifth wire W5, for example, which are connected to a first electrode pad B1 and a fifth electrode pad B5, respectively. Further, in the mold process, the bonding wires BW located near the vent are the third wire W3 and the seventh wire W7, for example, which are connected to a third electrode pad B3 and a seventh electrode pad B7, respectively.SELECTED DRAWING: Figure 1

Description

本発明は半導体装置の製造方法に関し、例えばボンディングワイヤを用いた半導体装置をトランスファモールド方式によって樹脂封止するパッケージング技術に好適に利用できるものである。   The present invention relates to a method for manufacturing a semiconductor device, and can be suitably used for, for example, a packaging technique in which a semiconductor device using a bonding wire is resin-sealed by a transfer molding method.

配線基板の上面にチップを搭載し、配線基板のボンディングリードとチップのボンディングパッドとをワイヤで電気的に接続する半導体装置において、チップのコーナー部に最も近い位置に配置されている、ワイヤ長が最も長いワイヤの径を他のワイヤの径よりも太くすることにより、隣接ワイヤ間のショートを抑制する技術が特開２０１２−２８４２９号公報（特許文献１）に記載されている。   In a semiconductor device in which a chip is mounted on the upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically connected by a wire, the wire length disposed at the position closest to the corner portion of the chip is Japanese Unexamined Patent Application Publication No. 2012-28429 (Patent Document 1) describes a technique for suppressing a short-circuit between adjacent wires by making the diameter of the longest wire larger than the diameters of other wires.

特開２０１２−２８４２９号公報JP 2012-28429 A

ボンディングワイヤを用いた半導体装置の小型化および低コスト化を実現する手段として、ボンディングワイヤの線径を細くすることが考えられている。しかし、例えばＱＦＰ（Quad Flat Package）およびＨＱＦＰ（Quad Flat Package with Heatspreader）のように、半導体チップを樹脂で封止するパッケージでは、ボンディングワイヤの線径を細くすると、例えば信頼性試験において、（１）ボンディングワイヤと電極パッドとの接合部が剥離する、（２）ボンディングワイヤのボール部と芯部との接合部（ネック部）が切断する、などの課題が生じやすくなることが、本発明者の検討により明らかとなった。   As means for realizing miniaturization and cost reduction of a semiconductor device using a bonding wire, it is considered to reduce the diameter of the bonding wire. However, for example, in a package in which a semiconductor chip is sealed with a resin, such as QFP (Quad Flat Package) and HQFP (Quad Flat Package with Heatspreader), when the wire diameter of the bonding wire is reduced, for example, in a reliability test, (1 The present inventor is prone to problems such as: the bonding portion between the bonding wire and the electrode pad peels off, and (2) the bonding portion (neck portion) between the ball portion and the core portion of the bonding wire is cut. It became clear by examination.

その他の課題と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

一実施の形態によれば、モールド工程において成形金型のゲートの近傍に位置するボンディングワイヤおよび半導体チップの中心を挟んで当該ゲートに対向する成形金型のベントの近傍に位置するボンディングワイヤのそれぞれは、ボンディングワイヤの一部が、そのボンディングワイヤのボール部と半導体チップの電極パッドとの接合部よりも半導体チップの内側に位置するようなループ形状を有している。   According to one embodiment, each of the bonding wire located near the gate of the molding die in the molding process and the bonding wire located near the vent of the molding die facing the gate across the center of the semiconductor chip. Has a loop shape such that a part of the bonding wire is located inside the semiconductor chip with respect to the bonding portion between the ball portion of the bonding wire and the electrode pad of the semiconductor chip.

一実施の形態によれば、小型で、かつ、信頼性の高い半導体装置を実現することができる。   According to one embodiment, a small and highly reliable semiconductor device can be realized.

実施の形態による半導体装置の上面図である。It is a top view of the semiconductor device by an embodiment. 図１のＸ−Ｘ´線に沿った断面図である。It is sectional drawing along the XX 'line of FIG. （ａ）は、図１のＸ１−Ｘ１´線に沿った断面図、（ｂ）は、図１のＸ２−Ｘ２´線に沿った断面図、（ｃ）は、図１のＸ１−Ｘ１´線に沿った断面と図１のＸ２−Ｘ２´線に沿った断面とを重ね合わせた断面図である。1A is a cross-sectional view taken along line X1-X1 ′ in FIG. 1, FIG. 1B is a cross-sectional view taken along line X2-X2 ′ in FIG. 1, and FIG. FIG. 2 is a cross-sectional view in which a cross section taken along a line and a cross section taken along a line X2-X2 ′ in FIG. （ａ）および（ｂ）はそれぞれ、実施の形態によるリードフレーム（単位フレーム）の一例を示す平面図および断面図である。(A) And (b) is the top view and sectional drawing which show an example of the lead frame (unit frame) by embodiment, respectively. （ａ）および（ｂ）はそれぞれ、実施の形態によるダイボンディング工程における半導体装置を示す平面図および断面図である。(A) And (b) is the top view and sectional drawing which show the semiconductor device in the die-bonding process by embodiment, respectively. （ａ）および（ｂ）はそれぞれ、実施の形態によるワイヤボンディング工程における半導体装置を示す平面図および断面図である。(A) And (b) is the top view and sectional drawing which show the semiconductor device in the wire bonding process by embodiment, respectively. 実施の形態によるキャピラリーの軌跡の一例を説明する模式図である。It is a schematic diagram explaining an example of the locus | trajectory of the capillary by embodiment. （ａ）および（ｂ）はそれぞれ、実施の形態によるモールド工程における半導体装置を示す平面図および断面図である。(A) And (b) is the top view and sectional drawing which show the semiconductor device in the mold process by embodiment, respectively. 実施の形態によるモールド工程における樹脂の流れを説明する平面図である。It is a top view explaining the flow of resin in the molding process by an embodiment. （ａ）および（ｂ）はそれぞれ、実施の形態によるリード切断工程における半導体装置を示す平面図および断面図である。(A) And (b) is the top view and sectional drawing which respectively show the semiconductor device in the lead cutting process by embodiment. （ａ）および（ｂ）はそれぞれ、実施の形態によるリード成形工程における半導体装置を示す平面図および断面図である。(A) And (b) is the top view and sectional drawing which show the semiconductor device in the lead shaping | molding process by embodiment, respectively. （ａ）は、モールド工程における、ゲートからベントへの樹脂の流れを説明する断面図、（ｂ）は、モールド工程における、ゲート近傍およびベント近傍のそれぞれに位置するボンディングワイヤの周辺の樹脂の流れを説明する断面図である。(A) is sectional drawing explaining the flow of the resin from a gate to a vent in a molding process, (b) is the flow of the resin around the bonding wire located in the gate vicinity and the vent vicinity in a molding process, respectively. FIG. 第１の課題の説明図であり、（ａ）は、モールド工程においてゲート近傍に位置するボンディングワイヤが受ける応力状態図、（ｂ）は、ボンディングワイヤのボール部の剥がれを説明する模式図である。It is explanatory drawing of a 1st subject, (a) is a stress state figure which the bonding wire located in the gate vicinity receives in a molding process, (b) is a schematic diagram explaining peeling of the ball | bowl part of a bonding wire. . 第２の課題の説明図であり、（ａ）は、モールド工程においてベント近傍に位置するボンディングワイヤが受ける応力状態図、（ｂ）は、ボンディングワイヤのボール部と芯部との接合部（ネック部）の切断を説明する模式図である。It is explanatory drawing of a 2nd subject, (a) is a stress state figure which the bonding wire located in the vent vicinity receives in a molding process, (b) is the junction part (neck) of the ball | bowl part and core part of a bonding wire It is a schematic diagram explaining the cutting | disconnection of a part. 第３の課題の説明図であり、モールド工程における、ゲートからベントへの樹脂の流れを説明する平面図である。It is explanatory drawing of a 3rd subject, and is a top view explaining the flow of the resin from a gate to a vent in a molding process. 第１および第２の課題の解決が必要となるボンディングワイヤの一例を説明する平面図である。It is a top view explaining an example of the bonding wire which needs to solve the 1st and 2nd subject. 第１および第２の課題の解決が必要となるボンディングワイヤの他の例を説明する平面図である。It is a top view explaining the other example of the bonding wire which needs to solve the 1st and 2nd subject. 実施の形態の変形例１による半導体装置の上面図である。It is a top view of the semiconductor device by the modification 1 of embodiment. 実施の形態の変形例２による半導体装置の上面図である。It is a top view of the semiconductor device by the modification 2 of embodiment. 実施の形態の変形例３による半導体装置の断面図である。It is sectional drawing of the semiconductor device by the modification 3 of embodiment. 実施の形態の変形例４による半導体装置の上面図である。It is a top view of the semiconductor device by the modification 4 of embodiment. 実施の形態の変形例５による半導体装置の上面図である。It is a top view of the semiconductor device by the modification 5 of embodiment.

以下の実施の形態においては便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、応用例、詳細説明、補足説明等の関係にある。また、以下の実施の形態において、要素の数等（個数、数値、量、範囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でもよい。   In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数等（個数、数値、量、範囲等を含む）についても同様である。   Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless specifically specified or apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

以下、実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一または関連する符号を付し、その繰り返しの説明は省略する。また、複数の類似の部材（部位）が存在する場合には、総称の符号に記号を追加し個別または特定の部位を示す場合がある。また、以下の実施の形態では、特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。   Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In addition, when there are a plurality of similar members (parts), a symbol may be added to the generic symbol to indicate an individual or specific part. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

また、実施の形態で用いる図面においては、断面図であっても図面を見易くするためにハッチングを省略する場合もある。また、平面図であっても図面を見易くするためにハッチングを付す場合もある。   In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

また、断面図および平面図において、各部位の大きさは実デバイスと対応するものではなく、図面を分かりやすくするため、特定の部位を相対的に大きく表示する場合がある。また、断面図と平面図が対応する場合においても、図面を分かりやすくするため、特定の部位を相対的に大きく表示する場合がある。   In the cross-sectional view and the plan view, the size of each part does not correspond to the actual device, and a specific part may be displayed relatively large for easy understanding of the drawing. Even when the cross-sectional view and the plan view correspond to each other, a specific part may be displayed relatively large in order to make the drawing easy to understand.

（実施の形態）
≪本実施の形態による半導体装置の構成≫
本実施の形態による半導体装置の構成について、図１〜図３を用いて説明する。 (Embodiment)
<< Configuration of Semiconductor Device According to this Embodiment >>
The structure of the semiconductor device according to the present embodiment will be described with reference to FIGS.

図１は、本実施の形態による半導体装置の上面図である。図２は、図１のＸ−Ｘ´線に沿った断面図である。図３（ａ）は、図１のＸ１−Ｘ１´線に沿った断面図である。図３（ｂ）は、図１のＸ２−Ｘ２´線に沿った断面図である。図３（ｃ）は、図１のＸ１−Ｘ１´線に沿った断面と図１のＸ２−Ｘ２´線に沿った断面とを重ね合わせた断面図である。なお、図１では、封止体を透視した状態を示している。また、図１では、見易さのため、端子数を少なく示しており、端子数は、例えば１００を超えるような数である。   FIG. 1 is a top view of the semiconductor device according to the present embodiment. FIG. 2 is a cross-sectional view taken along line XX ′ in FIG. FIG. 3A is a cross-sectional view taken along line X1-X1 ′ of FIG. FIG. 3B is a cross-sectional view taken along line X2-X2 ′ of FIG. 3C is a cross-sectional view in which a cross section taken along the line X1-X1 ′ in FIG. 1 and a cross section taken along the line X2-X2 ′ in FIG. In addition, in FIG. 1, the state which saw through the sealing body is shown. In FIG. 1, the number of terminals is shown to be small for easy viewing, and the number of terminals is, for example, more than 100.

図１および図２に示すように、本実施の形態による半導体装置ＳＭは、ダイパッド（タブ、チップ搭載部）ＤＰと、複数の吊りリード（支持リード）ＨＬと、複数のリード（外部端子）ＬＥと、半導体チップＳＣと、複数のボンディングワイヤ（導電性ワイヤ、ワイヤ）ＢＷと、封止体（封止樹脂）ＲＥと、を有する。   As shown in FIGS. 1 and 2, the semiconductor device SM according to the present embodiment includes a die pad (tab, chip mounting portion) DP, a plurality of suspension leads (support leads) HL, and a plurality of leads (external terminals) LE. And a semiconductor chip SC, a plurality of bonding wires (conductive wires, wires) BW, and a sealing body (sealing resin) RE.

詳細に説明すると、ダイパッドＤＰは、その平面形状が四角形から成り、半導体チップＳＣが搭載される上面（チップ搭載面）Ｄａと、この上面Ｄａとは反対側の下面（露出面）Ｄｂと、を有している。そして、ダイパッドＤＰの下面Ｄｂは、封止体ＲＥの下面（実装面）Ｒｂから露出している。   More specifically, the die pad DP has a quadrangular planar shape, and includes an upper surface (chip mounting surface) Da on which the semiconductor chip SC is mounted, and a lower surface (exposed surface) Db opposite to the upper surface Da. Have. The lower surface Db of the die pad DP is exposed from the lower surface (mounting surface) Rb of the sealing body RE.

吊りリードＨＬは、ダイパッドＤＰの４つの角部のそれぞれに連結され、ダイパッドＤＰを支持している。   The suspension lead HL is connected to each of the four corners of the die pad DP and supports the die pad DP.

リードＬＥの一部（インナーリード、インナー部）は、封止体ＲＥで覆われている。言い換えると、リードＬＥの他部（アウターリード、アウター部）は、封止体ＲＥから露出している。そして、リードＬＥのうちの封止体ＲＥから露出した部分（他部、アウターリード、アウター部）は、ダイパッドＤＰの４つの辺に沿った方向に対して、それぞれ垂直な４方向からつき出ており、さらに、封止体ＲＥの上面Ｒａ側から下面Ｒｂ側に向かって折り曲げられている。すなわち、半導体装置ＳＭは、外形が四角形で、４側面からガルウイング状の複数のリードＬＥの他部（アウターリード、アウター部）がつき出し、底面にダイパッドＤＰの下面が露出した表面実装型の半導体装置、所謂、ＱＨＰまたはＨＱＦＰである。   Part of the lead LE (inner lead, inner part) is covered with a sealing body RE. In other words, the other part (outer lead, outer part) of the lead LE is exposed from the sealing body RE. And the part (other part, outer lead, outer part) exposed from the sealing body RE of the lead LE protrudes from the four directions perpendicular to the directions along the four sides of the die pad DP. Further, the sealing body RE is bent from the upper surface Ra side to the lower surface Rb side. That is, the semiconductor device SM is a surface-mount type semiconductor in which the outer shape is a quadrangle, the other parts (outer leads, outer parts) of the plurality of gull-wing leads LE stick out from the four side surfaces, and the lower surface of the die pad DP is exposed on the bottom surface. A device, so-called QHP or HQFP.

半導体チップＳＣは、その平面形状が四角形から成り、主面（第１主面、表面）Ｓａと、主面Ｓａと反対側の裏面（第２主面）Ｓｂと、を有している。すなわち、半導体チップＳＣは、平面視において、第１辺Ｓ１と、第１辺Ｓ１と対向する第２辺Ｓ２と、第１辺Ｓ１および第２辺Ｓ２のそれぞれと交差する第３辺Ｓ３と、第１辺Ｓ１および第２辺Ｓ２のそれぞれと交差し、第３辺Ｓ３と対向する第４辺Ｓ４と、を有する。さらに、半導体チップＳＣは、第１辺Ｓ１と第３辺Ｓ３とが交わる第１角部Ｃ１と、第２辺Ｓ２と第４辺Ｓ４とが交わる第２角部Ｃ２と、第３辺Ｓ３と第２辺Ｓ２とが交わる第３角部Ｃ３と、第４辺Ｓ４と第１辺Ｓ１とが交わる第４角部Ｃ４と、を有する。   The semiconductor chip SC has a quadrangular planar shape, and has a main surface (first main surface, front surface) Sa and a back surface (second main surface) Sb opposite to the main surface Sa. That is, the semiconductor chip SC has a first side S1, a second side S2 facing the first side S1, a third side S3 intersecting with each of the first side S1 and the second side S2 in plan view, A fourth side S4 intersects with each of the first side S1 and the second side S2 and faces the third side S3. Further, the semiconductor chip SC includes a first corner C1 where the first side S1 and the third side S3 intersect, a second corner C2 where the second side S2 and the fourth side S4 intersect, and a third side S3. It has a third corner C3 where the second side S2 intersects and a fourth corner C4 where the fourth side S4 and the first side S1 intersect.

半導体チップＳＣの裏面ＳｂとダイパッドＤＰの上面Ｄａとが対向して、半導体チップＳＣがダイボンド材（接着剤）ＣＲを介してダイパッドＤＰの上面Ｄａに配置されている。半導体チップＳＣの主面Ｓａ側には、例えば複数の半導体素子と、絶縁層と配線層とをそれぞれ複数段積み重ねた多層配線と、この多層配線を覆うようにして形成された表面保護膜と、から構成される集積回路が形成されている。なお、ダイボンド材ＣＲは、例えばペースト状またはフィルム状の導電性部材から成る。また、非導電性部材（例えば樹脂材）から成るダイボンド材を使用してもよいが、導電性部材を使用することで、半導体チップＳＣの放熱性を向上することができる。   The back surface Sb of the semiconductor chip SC and the upper surface Da of the die pad DP face each other, and the semiconductor chip SC is disposed on the upper surface Da of the die pad DP with a die bond material (adhesive) CR interposed therebetween. On the main surface Sa side of the semiconductor chip SC, for example, a plurality of semiconductor elements, a multilayer wiring in which a plurality of insulating layers and wiring layers are stacked, a surface protection film formed so as to cover the multilayer wiring, The integrated circuit comprised from these is formed. The die bond material CR is made of, for example, a paste-like or film-like conductive member. Further, although a die bond material made of a non-conductive member (for example, a resin material) may be used, the heat dissipation of the semiconductor chip SC can be improved by using the conductive member.

半導体チップＳＣの主面Ｓａ側には、さらに、複数の電極パッド（ボンディングパッド、表面電極）ＢＰが形成されている。この複数の電極パッドＢＰは、集積回路に形成された多層配線のうちの最上層の配線（例えばアルミニウム（Ａｌ））から成り、表面保護膜に形成された開口部により露出している。   On the main surface Sa side of the semiconductor chip SC, a plurality of electrode pads (bonding pads, surface electrodes) BP are further formed. The plurality of electrode pads BP are made of the uppermost layer wiring (for example, aluminum (Al)) among the multilayer wirings formed in the integrated circuit, and are exposed through the openings formed in the surface protective film.

複数の電極パッドＢＰは、平面視において、半導体チップＳＣの第２辺Ｓ２よりも第１辺Ｓ１の近くに位置し、かつ、第１辺Ｓ１に沿って配置された第１パッド群Ｇ１と、半導体チップＳＣの第１辺Ｓ１よりも第２辺Ｓ２の近くに位置し、かつ、第２辺Ｓ２に沿って配置された第２パッド群Ｇ２と、を有する。さらに、複数の電極パッドＢＰは、平面視において、半導体チップＳＣの第４辺Ｓ４よりも第３辺Ｓ３の近くに位置し、かつ、第３辺Ｓ３に沿って配置された第３パッド群Ｇ３と、半導体チップＳＣの第３辺Ｓ３よりも第４辺Ｓ４の近くに位置し、かつ、第４辺Ｓ４に沿って配置された第４パッド群Ｇ４と、を有する。   The plurality of electrode pads BP are located closer to the first side S1 than the second side S2 of the semiconductor chip SC in plan view, and are arranged along the first side S1, And a second pad group G2 which is located closer to the second side S2 than the first side S1 of the semiconductor chip SC and arranged along the second side S2. Further, the plurality of electrode pads BP are located closer to the third side S3 than the fourth side S4 of the semiconductor chip SC in plan view, and are arranged along the third side S3. And a fourth pad group G4 which is located closer to the fourth side S4 than the third side S3 of the semiconductor chip SC and arranged along the fourth side S4.

そして、複数の電極パッドＢＰと複数のリードＬＥの一部とが複数の導電性部材によりそれぞれ電気的に接続されている。導電性部材はワイヤ、すなわち、ボンディングワイヤＢＷであり、その線径は、例えば１５μｍφ〜２０μｍφ程度である。ボンディングワイヤＢＷは、例えば金（Ａｕ）または銅（Ｃｕ）を主成分とする材料から成る。しかし、ボンディングワイヤＢＷに銅（Ｃｕ）を用いた場合、ボンディングワイヤＢＷに金（Ａｕ）を用いた場合と比べると、例えば信頼性試験、特に、温度サイクル試験において、ボンディングワイヤＢＷと電極パッドＢＰとの接合部が剥離しやすい。このため、金（Ａｕ）を主成分とする材料から成るボンディングワイヤＢＷを使用することが望ましい。   The plurality of electrode pads BP and a part of the plurality of leads LE are electrically connected by a plurality of conductive members, respectively. The conductive member is a wire, that is, a bonding wire BW, and its wire diameter is, for example, about 15 μmφ to 20 μmφ. The bonding wire BW is made of, for example, a material mainly composed of gold (Au) or copper (Cu). However, when copper (Cu) is used for the bonding wire BW, compared with the case where gold (Au) is used for the bonding wire BW, for example, in the reliability test, particularly in the temperature cycle test, the bonding wire BW and the electrode pad BP The joints with are easy to peel off. For this reason, it is desirable to use a bonding wire BW made of a material mainly composed of gold (Au).

また、ダイパッドＤＰの下面ＤｂおよびリードＬＥのうちの封止体ＲＥから露出した部分の表面には、メッキ膜（メッキ層）ＰＦが形成されている。これにより、半導体装置ＳＭの実装工程において、ダイパッドＤＰの下面ＤｂおよびリードＬＥのうちの封止体ＲＥから露出した部分の濡れ性（接合性）を向上することができる。すなわち、ダイパッドＤＰの下面ＤｂおよびリードＬＥのうちの封止体ＲＥから露出した部分と実装基板（マザーボード）の電極パッドとをそれぞれ電気的に接続する際に使用される、導電性部材（半田材）から成る接合材の、ダイパッドＤＰの下面ＤｂおよびリードＬＥのうちの封止体ＲＥから露出した部分のそれぞれに対する濡れ性を向上することができる。   A plating film (plating layer) PF is formed on the surface of the lower surface Db of the die pad DP and the surface of the lead LE exposed from the sealing body RE. Thereby, in the mounting process of the semiconductor device SM, the wettability (bondability) of the portion exposed from the sealing body RE in the lower surface Db of the die pad DP and the lead LE can be improved. That is, a conductive member (solder material) used when the lower surface Db of the die pad DP and the portion of the lead LE exposed from the sealing body RE and the electrode pad of the mounting board (motherboard) are electrically connected to each other. ), The wettability of the lower surface Db of the die pad DP and the portions of the leads LE exposed from the sealing body RE can be improved.

なお、ダイパッドＤＰは、必ずしも、実装基板の電極パッドと接合されなくてもよい。しかし、半導体装置ＳＭの放熱性を向上したい場合、またはダイパッドＤＰを信号または電源（電源電位、基準電位）の経路として使用する場合には、ダイパッドＤＰに対応する電極パッドを実装基板に設けておき、実装基板の電極パッドとダイパッドＤＰとを、接合材を介して電気的に接続することが好ましい。   Note that the die pad DP is not necessarily bonded to the electrode pad of the mounting substrate. However, when it is desired to improve the heat dissipation of the semiconductor device SM, or when the die pad DP is used as a signal or power supply (power supply potential, reference potential) path, an electrode pad corresponding to the die pad DP is provided on the mounting substrate. The electrode pad of the mounting substrate and the die pad DP are preferably electrically connected through a bonding material.

次に、ボンディングワイヤＢＷの形状について、さらに詳細に説明する。   Next, the shape of the bonding wire BW will be described in more detail.

前述したように、半導体チップＳＣの主面Ｓａ側には、複数の電極パッドＢＰが形成されている。そして、複数の電極パッドＢＰは、半導体チップＳＣの第１辺Ｓ１、第２辺Ｓ２、第３辺Ｓ３および第４辺Ｓ４のそれぞれに沿って配置された第１パッド群Ｇ１、第２パッド群Ｇ２、第３パッド群Ｇ３および第４パッド群Ｇ４に区分することができる。   As described above, the plurality of electrode pads BP are formed on the main surface Sa side of the semiconductor chip SC. The plurality of electrode pads BP include a first pad group G1 and a second pad group arranged along the first side S1, the second side S2, the third side S3, and the fourth side S4 of the semiconductor chip SC. It can be divided into G2, third pad group G3 and fourth pad group G4.

第１パッド群Ｇ１に含まれる複数の電極パッドＢＰのうち、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１に接続される第１ワイヤＷ１のループ形状は、半導体チップＳＣの第４角部Ｃ４の最も近くに位置する第２電極パッドＢ２に接続される第２ワイヤＷ２のループ形状と異なる。   Of the plurality of electrode pads BP included in the first pad group G1, the loop shape of the first wire W1 connected to the first electrode pad B1 located closest to the first corner C1 of the semiconductor chip SC is a semiconductor. This is different from the loop shape of the second wire W2 connected to the second electrode pad B2 located closest to the fourth corner C4 of the chip SC.

また、第２パッド群Ｇ２に含まれる複数の電極パッドＢＰのうち、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３に接続される第３ワイヤＷ３のループ形状は、半導体チップＳＣの第３角部Ｃ３の最も近くに位置する第４電極パッドＢ４に接続される第４ワイヤＷ４のループ形状と異なる。   The loop shape of the third wire W3 connected to the third electrode pad B3 located closest to the second corner portion C2 of the semiconductor chip SC among the plurality of electrode pads BP included in the second pad group G2 is as follows. This differs from the loop shape of the fourth wire W4 connected to the fourth electrode pad B4 located closest to the third corner C3 of the semiconductor chip SC.

また、第３パッド群Ｇ３に含まれる複数の電極パッドＢＰのうち、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第５電極パッドＢ５に接続される第５ワイヤＷ５のループ形状は、半導体チップＳＣの第３角部Ｃ３の最も近くに位置する第６電極パッドＢ６に接続される第６ワイヤＷ６のループ形状と異なる。   The loop shape of the fifth wire W5 connected to the fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC among the plurality of electrode pads BP included in the third pad group G3 is as follows. This is different from the loop shape of the sixth wire W6 connected to the sixth electrode pad B6 located closest to the third corner C3 of the semiconductor chip SC.

また、第４パッド群Ｇ４に含まれる複数の電極パッドＢＰのうち、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第７電極パッドＢ７に接続される第７ワイヤＷ７のループ形状は、半導体チップＳＣの第４角部Ｃ４の最も近くに位置する第８電極パッドＢ８に接続される第８ワイヤＷ８のループ形状と異なる。   The loop shape of the seventh wire W7 connected to the seventh electrode pad B7 located closest to the second corner C2 of the semiconductor chip SC among the plurality of electrode pads BP included in the fourth pad group G4 is as follows. This is different from the loop shape of the eighth wire W8 connected to the eighth electrode pad B8 located closest to the fourth corner C4 of the semiconductor chip SC.

さらに言えば、半導体チップＳＣの主面Ｓａを、平面視において、半導体チップＳＣの第１辺Ｓ１および第２辺Ｓ２のそれぞれを二等分する第１仮想線ＩＬ１と、半導体チップＳＣの第３辺Ｓ３および第４辺Ｓ４のそれぞれを二等分する第２仮想線ＩＬ２と、で区分すると、半導体チップＳＣの主面Ｓａは、４つの領域に区分される。すなわち、半導体チップＳＣの主面Ｓａは、半導体チップＳＣの第１角部Ｃ１を含む第１領域Ａ１と、半導体チップＳＣの第２角部Ｃ２を含む第２領域Ａ２と、半導体チップＳＣの第３角部Ｃ３を含む第３領域Ａ３と、半導体チップＳＣの第４角部Ｃ４を含む第４領域Ａ４と、を有する。   More specifically, the first virtual line IL1 that bisects each of the first side S1 and the second side S2 of the semiconductor chip SC in plan view, and the third surface of the semiconductor chip SC in the plan view. When divided by the second virtual line IL2 that bisects each of the side S3 and the fourth side S4, the main surface Sa of the semiconductor chip SC is divided into four regions. That is, the main surface Sa of the semiconductor chip SC includes a first region A1 including the first corner C1 of the semiconductor chip SC, a second region A2 including the second corner C2 of the semiconductor chip SC, and the first region A1 of the semiconductor chip SC. It has 3rd area | region A3 containing 3 corner | angular part C3, and 4th area | region A4 containing 4th corner | angular part C4 of semiconductor chip SC.

そして、第１パッド群Ｇ１に含まれる複数の電極パッドＢＰのうち、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１に接続される第１ワイヤＷ１のループ形状は、第４領域Ａ４に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状と異なる。さらに、第１パッド群Ｇ１に含まれる複数の電極パッドＢＰのうち、第１領域Ａ１に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状は、第４領域Ａ４に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状と異なる。   The loop shape of the first wire W1 connected to the first electrode pad B1 located closest to the first corner C1 of the semiconductor chip SC among the plurality of electrode pads BP included in the first pad group G1 is: The loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the fourth region A4 is different. Furthermore, among the plurality of electrode pads BP included in the first pad group G1, the loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the first region A1 is the fourth region A4. This is different from the loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located at the same position.

また、第２パッド群Ｇ２に含まれる複数の電極パッドＢＰのうち、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３に接続される第３ワイヤＷ３のループ形状は、第３領域Ａ３に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状と異なる。さらに、第２パッド群Ｇ２に含まれる複数の電極パッドＢＰのうち、第２領域Ａ２に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状は、第３領域Ａ３に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状と異なる。   The loop shape of the third wire W3 connected to the third electrode pad B3 located closest to the second corner portion C2 of the semiconductor chip SC among the plurality of electrode pads BP included in the second pad group G2 is as follows. The loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the third region A3 is different. Furthermore, among the plurality of electrode pads BP included in the second pad group G2, the loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the second region A2 is the third region A3. This is different from the loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located at the same position.

また、第３パッド群Ｇ３に含まれる複数の電極パッドＢＰのうち、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第５電極パッドＢ５に接続される第５ワイヤＷ５のループ形状は、第３領域Ａ３に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状と異なる。さらに、第３パッド群Ｇ３に含まれる複数の電極パッドＢＰのうち、第１領域Ａ１に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状は、第３領域Ａ３に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状と異なる。   The loop shape of the fifth wire W5 connected to the fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC among the plurality of electrode pads BP included in the third pad group G3 is as follows. The loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the third region A3 is different. Furthermore, among the plurality of electrode pads BP included in the third pad group G3, the loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the first region A1 is the third region A3. This is different from the loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located at the same position.

また、第４パッド群Ｇ４に含まれる複数の電極パッドＢＰのうち、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第７電極パッドＢ７に接続される第７ワイヤＷ７のループ形状は、第４領域Ａ４に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状と異なる。さらに、第４パッド群Ｇ４に含まれる複数の電極パッドＢＰのうち、第２領域Ａ２に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状は、第４領域Ａ４に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷのループ形状と異なる。   The loop shape of the seventh wire W7 connected to the seventh electrode pad B7 located closest to the second corner C2 of the semiconductor chip SC among the plurality of electrode pads BP included in the fourth pad group G4 is as follows. The loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the fourth region A4 is different. Further, among the plurality of electrode pads BP included in the fourth pad group G4, the loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the second region A2 is the fourth region A4. This is different from the loop shape of the plurality of bonding wires BW connected to each of the plurality of electrode pads BP located at the same position.

複数のボンディングワイヤＢＷは、全て正ボンディング方式を用いて、複数の電極パッドＢＰと複数のリードＬＥの一部とにそれぞれ接続されている。すなわち、半導体チップＳＣの主面Ｓａ側に形成された電極パッドＢＰとボンディングワイヤＢＷの一部を接続した後に、リードＬＥの一部とボンディングワイヤＢＷの他部を接続している。   The plurality of bonding wires BW are all connected to the plurality of electrode pads BP and a part of the plurality of leads LE, respectively, using a positive bonding method. That is, after connecting the electrode pad BP formed on the main surface Sa side of the semiconductor chip SC and a part of the bonding wire BW, a part of the lead LE and the other part of the bonding wire BW are connected.

図３（ａ）および（ｂ）に示すように、電極パッドＢＰに接続するボンディングワイヤＢＷは、電極パッドＢＰに接触するボール部ＢＷａと、ボール部ＢＷａに繋がる芯部ＢＷｂと、から成る。   As shown in FIGS. 3A and 3B, the bonding wire BW connected to the electrode pad BP includes a ball part BWa that is in contact with the electrode pad BP and a core part BWb that is connected to the ball part BWa.

そして、図３（ａ）に示すように、第５ワイヤＷ５では、ボール部ＢＷａと当該ボール部ＢＷａに繋がる芯部ＢＷｂとの接合部（ネック部）において、芯部ＢＷｂは、その接合部から半導体チップＳＣの内側の方向に引き出されている。言い換えれば、第５ワイヤＷ５では、ボール部ＢＷａと当該ボール部ＢＷａに繋がる芯部ＢＷｂとの接合部（ネック部）において、芯部ＢＷｂは、第５ワイヤＷ５が接続するリードＬＥと反対側の方向に引き出されている。   As shown in FIG. 3A, in the fifth wire W5, in the joint portion (neck portion) between the ball portion BWa and the core portion BWb connected to the ball portion BWa, the core portion BWb is separated from the joint portion. The semiconductor chip SC is drawn in the inner direction. In other words, in the fifth wire W5, at the joint portion (neck portion) between the ball portion BWa and the core portion BWb connected to the ball portion BWa, the core portion BWb is opposite to the lead LE to which the fifth wire W5 is connected. Has been pulled out in the direction.

一方、図３（ｂ）に示すように、第６ワイヤＷ６では、ボール部ＢＷａと当該ボール部ＢＷａに繋がる芯部ＢＷｂとの接合部（ネック部）において、芯部ＢＷｂは、その接合部のほぼ直上方向に引き出されている。   On the other hand, as shown in FIG. 3B, in the sixth wire W6, in the joint portion (neck portion) between the ball portion BWa and the core portion BWb connected to the ball portion BWa, the core portion BWb is It is pulled out almost upward.

従って、図３（ａ）および（ｂ）に示すように、第５ワイヤＷ５でのボール部ＢＷａと芯部ＢＷｂとの接合部（ネック部）における、法線方向に対する芯部ＢＷｂの曲げ角度をθ１、第６ワイヤＷ６でのボール部ＢＷａと芯部ＢＷｂとの接合部（ネック部）における、法線方向に対する芯部ＢＷｂの曲げ角度をθ２とすると、曲げ角度θ１は曲げ角度θ２よりも大きい。   Therefore, as shown in FIGS. 3A and 3B, the bending angle of the core BWb with respect to the normal direction at the joint (neck) between the ball BWa and the core BWb in the fifth wire W5 is θ1, the bending angle θ1 is larger than the bending angle θ2, where θ2 is the bending angle of the core portion BWb with respect to the normal direction at the joint portion (neck portion) of the ball portion BWa and the core portion BWb in the sixth wire W6 .

また、図３（ｃ）に示すように、第５ワイヤＷ５は第６ワイヤＷ６よりも長い。   In addition, as shown in FIG. 3C, the fifth wire W5 is longer than the sixth wire W6.

しかし、例えば図３（ｃ）に示すように、第５ワイヤＷ５の電極パッドＢＰ（または半導体チップＳＣの主面）からのループ高さＨ１と第６ワイヤＷ６の電極パッドＢＰ（または半導体チップＳＣの主面）からのループ高さＨ２とは同じである。   However, as shown in FIG. 3C, for example, the loop height H1 from the electrode pad BP of the fifth wire W5 (or the main surface of the semiconductor chip SC) and the electrode pad BP of the sixth wire W6 (or the semiconductor chip SC). The loop height H2 from the main surface) is the same.

ここでは、図を用いての説明は省略するが、第１ワイヤＷ１、第３ワイヤＷ３および第７ワイヤＷ７は、第５ワイヤＷ５と同様のループ形状を有している。また、第２ワイヤＷ２、第４ワイヤＷ４および第８ワイヤＷ８は、第６ワイヤＷ６と同様のループ形状を有している。   Here, although description with reference to the drawings is omitted, the first wire W1, the third wire W3, and the seventh wire W7 have the same loop shape as the fifth wire W5. The second wire W2, the fourth wire W4, and the eighth wire W8 have a loop shape similar to that of the sixth wire W6.

従って、第１ワイヤＷ１、第３ワイヤＷ３、第５ワイヤＷ５および第７ワイヤＷ７のそれぞれの芯部の曲げ角度は、第２ワイヤＷ２、第４ワイヤＷ４、第６ワイヤＷ６および第８ワイヤＷ８のそれぞれの芯部の曲げ角度よりも大きい。   Accordingly, the bending angles of the core portions of the first wire W1, the third wire W3, the fifth wire W5, and the seventh wire W7 are the second wire W2, the fourth wire W4, the sixth wire W6, and the eighth wire W8. It is larger than the bending angle of each core part.

また、第１ワイヤＷ１、第３ワイヤＷ３、第５ワイヤＷ５および第７ワイヤＷ７のそれぞれの長さは、第２ワイヤＷ２、第４ワイヤＷ４、第６ワイヤＷ６および第８ワイヤＷ８のそれぞれの長さよりも長い。   The lengths of the first wire W1, the third wire W3, the fifth wire W5, and the seventh wire W7 are the lengths of the second wire W2, the fourth wire W4, the sixth wire W6, and the eighth wire W8, respectively. Longer than the length.

しかし、第１ワイヤＷ１、第３ワイヤＷ３、第５ワイヤＷ５および第７ワイヤＷ７のそれぞれの電極パッドＢＰからの高さと、第２ワイヤＷ２、第４ワイヤＷ４、第６ワイヤＷ６および第８ワイヤＷ８のそれぞれの電極パッドＢＰからのループ高さと、は同じである。   However, the height of each of the first wire W1, the third wire W3, the fifth wire W5 and the seventh wire W7 from the electrode pad BP, and the second wire W2, the fourth wire W4, the sixth wire W6 and the eighth wire. The loop height from each electrode pad BP of W8 is the same.

これにより、例えば図１に示すように、第１ワイヤＷ１、第３ワイヤＷ３、第５ワイヤＷ５および第７ワイヤＷ７は、平面視において、ボール部ＢＷａと当該ボール部ＢＷａに繋がる芯部ＢＷｂとの接合部（ネック部）を越えて、半導体チップＳＣの内側方向に延在することがある。   Thereby, as shown in FIG. 1, for example, the first wire W1, the third wire W3, the fifth wire W5, and the seventh wire W7 are, in plan view, the ball portion BWa and the core portion BWb connected to the ball portion BWa. May extend beyond the junction (neck portion) of the semiconductor chip SC in the inner direction.

≪本実施の形態による半導体装置の製造方法≫
本実施の形態による半導体装置の製造方法について、図４〜図１１を用いて説明する。 << Semiconductor Device Manufacturing Method According to this Embodiment >>
A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS.

図４（ａ）および（ｂ）はそれぞれ、本実施の形態によるリードフレーム（単位フレーム）の一例を示す平面図および断面図である。図５（ａ）および（ｂ）はそれぞれ、本実施の形態によるダイボンディング工程における半導体装置を示す平面図および断面図である。図６（ａ）および（ｂ）はそれぞれ、本実施の形態によるワイヤボンディング工程における半導体装置を示す平面図および断面図である。図７は、本実施の形態によるキャピラリーの軌跡の一例を説明する模式図である。図８（ａ）および（ｂ）はそれぞれ、本実施の形態によるモールド工程における半導体装置を示す平面図および断面図である。図９は、本実施の形態によるモールド工程における樹脂の流れを説明する平面図である。図１０（ａ）および（ｂ）はそれぞれ、本実施の形態によるリード切断工程における半導体装置を示す平面図および断面図である。図１１（ａ）および（ｂ）は、リード成形工程における半導体装置を示す平面図および断面図である。   FIGS. 4A and 4B are a plan view and a cross-sectional view showing an example of a lead frame (unit frame) according to the present embodiment, respectively. FIGS. 5A and 5B are a plan view and a cross-sectional view, respectively, showing the semiconductor device in the die bonding process according to the present embodiment. 6A and 6B are a plan view and a cross-sectional view, respectively, showing the semiconductor device in the wire bonding step according to the present embodiment. FIG. 7 is a schematic diagram illustrating an example of a capillary trajectory according to the present embodiment. 8A and 8B are a plan view and a cross-sectional view, respectively, showing the semiconductor device in the molding process according to the present embodiment. FIG. 9 is a plan view for explaining the flow of resin in the molding step according to the present embodiment. 10A and 10B are a plan view and a cross-sectional view, respectively, showing the semiconductor device in the lead cutting step according to the present embodiment. 11A and 11B are a plan view and a cross-sectional view showing the semiconductor device in the lead forming process.

なお、半導体装置の製造方法の一例の説明に用いる図４〜図６、図８、図１０および図１１では、１つの単位フレームＳＦに該当する領域のみを記載している。また、図９では、成形金型を透視した状態を示しており、図中、網掛けのハッチングで示す矢印は、樹脂の流れを示している。   Note that in FIGS. 4 to 6, 8, 10, and 11 used for explaining an example of a method for manufacturing a semiconductor device, only a region corresponding to one unit frame SF is shown. Further, FIG. 9 shows a state where the molding die is seen through, and in the figure, the arrow indicated by hatching indicates the flow of the resin.

１．半導体チップ準備工程
半導体ウエハの回路形成面に集積回路を形成する。集積回路は前工程または拡散工程と呼ばれる製造工程において、所定の製造プロセスに従って半導体ウエハにチップ単位で形成される。続いて、半導体ウエハに形成された各半導体チップの良・不良を判定した後、半導体ウエハをダイシングして、各半導体チップに個片化する。 1. Semiconductor chip preparation step An integrated circuit is formed on a circuit formation surface of a semiconductor wafer. An integrated circuit is formed on a semiconductor wafer in units of chips according to a predetermined manufacturing process in a manufacturing process called a pre-process or a diffusion process. Subsequently, after determining whether each semiconductor chip formed on the semiconductor wafer is good or defective, the semiconductor wafer is diced into individual semiconductor chips.

半導体チップは主面と、主面と反対側の裏面と、を有し、半導体チップの主面上に絶縁膜から露出して複数の電極パッドが形成されている。   The semiconductor chip has a main surface and a back surface opposite to the main surface, and a plurality of electrode pads are formed on the main surface of the semiconductor chip so as to be exposed from the insulating film.

２．基材（リードフレーム）準備工程
第１面（上面、表面）と、第１面とは反対側の第２面（下面、裏面）と、を有し、例えば銅（Ｃｕ）を主材料とした金属製の枠組みであるリードフレーム（配線板、配線部材）ＬＦを準備する。 2. Substrate (lead frame) preparation step It has a first surface (upper surface, front surface) and a second surface (lower surface, back surface) opposite to the first surface, for example, copper (Cu) as a main material A lead frame (wiring board, wiring member) LF, which is a metal frame, is prepared.

図４（ａ）および（ｂ）に示すように、リードフレームＬＦは、例えばリードフレームＬＦの第１方向を列とし、この列の直交する第２方向を行とすると、半導体製品１つ分に該当する単位フレームＳＦが複数行複数列、所謂、マトリックス状に配置された構成となっている。   As shown in FIGS. 4A and 4B, the lead frame LF has, for example, one semiconductor product when the first direction of the lead frame LF is a column and the second direction perpendicular to the column is a row. The corresponding unit frames SF are arranged in a plurality of rows and columns, a so-called matrix.

リードフレームＬＦの第１面に存在する複数の単位フレームＳＦのそれぞれの中央部には、半導体チップが搭載される略四角形のダイパッドＤＰが設けられ、ダイパッドＤＰは吊りリードＨＬを介してリードフレームＬＦと一体として繋がっている。ダイパッドＤＰを支持する吊りリードＨＬは、ダイパッドＤＰの４つの角部のそれぞれに連結されている。   A substantially square die pad DP on which a semiconductor chip is mounted is provided at the center of each of the plurality of unit frames SF existing on the first surface of the lead frame LF. The die pad DP is connected to the lead frame LF via the suspension leads HL. Connected as one. The suspension lead HL that supports the die pad DP is connected to each of the four corners of the die pad DP.

また、吊りリードＨＬが連結されていないダイパッドＤＰの４つの辺とそれぞれ対向し、その４つの辺と離間して、複数のリードＬＥが設けられている。複数のリードＬＥは第１方向または第２方向のそれぞれに延在するタイバーＴＢにより繋がれている。また、図示は省略するが、リードフレームＬＦの周辺には、リードフレームＬＦの位置決めのため、あるいは樹脂封止に伴うリードフレームＬＦの歪みを緩和するための複数の孔が設けられている。   In addition, a plurality of leads LE are provided so as to face the four sides of the die pad DP to which the suspension leads HL are not connected, and to be separated from the four sides. The plurality of leads LE are connected by tie bars TB extending in the first direction or the second direction. Although not shown, a plurality of holes are provided around the lead frame LF for positioning the lead frame LF or for reducing distortion of the lead frame LF due to resin sealing.

３．ダイボンディング工程
図５（ａ）および（ｂ）に示すように、複数の単位フレームＳＦのそれぞれのダイパッドＤＰの上面（リードフレームＬＦの第１面）に良品と判定された半導体チップＳＣを搭載する。このとき、ダイパッドＤＰの上面と半導体チップＳＣの裏面Ｓｂとをダイボンド材ＣＲ、例えばペースト状の接着剤（例えば銀（Ａｇ）ペースト）を用いて接合する。なお、ダイパッドＤＰの上面と半導体チップＳＣの裏面Ｓｂとの接合は、ペースト状の接着剤に限定されるものではなく、例えば金−錫（Ａｕ−Ｓｎ）共晶を用いた接合などでもよい。 3. Die Bonding Process As shown in FIGS. 5A and 5B, the semiconductor chip SC determined as a non-defective product is mounted on the upper surface of each die pad DP (the first surface of the lead frame LF) of each of the plurality of unit frames SF. . At this time, the upper surface of the die pad DP and the back surface Sb of the semiconductor chip SC are bonded using a die bonding material CR, for example, a paste adhesive (for example, silver (Ag) paste). Note that the bonding between the upper surface of the die pad DP and the back surface Sb of the semiconductor chip SC is not limited to a paste-like adhesive, and may be bonding using, for example, a gold-tin (Au—Sn) eutectic.

半導体チップＳＣは、前述したように、その平面形状が四角形から成り、主面Ｓａと、主面Ｓａと反対側の裏面Ｓｂと、を有している。すなわち、半導体チップＳＣは、平面視において、第１辺Ｓ１と、第１辺Ｓ１と対向する第２辺Ｓ２と、第１辺Ｓ１および第２辺Ｓ２のそれぞれと交差する第３辺Ｓ３と、第１辺Ｓ１および第２辺Ｓ２のそれぞれと交差し、第３辺Ｓ３と対向する第４辺Ｓ４と、を有する。さらに、半導体チップＳＣは、第１辺Ｓ１と第３辺Ｓ３が交わる第１角部Ｃ１と、第２辺Ｓ２と第４辺Ｓ４とが交わる第２角部Ｃ２と、第３辺Ｓ３と第２辺Ｓ２とが交わる第３角部Ｃ３と、第４辺Ｓ４と第１辺Ｓ１とが交わる第４角部Ｃ４と、を有する。   As described above, the semiconductor chip SC has a quadrangular planar shape, and has a main surface Sa and a back surface Sb opposite to the main surface Sa. That is, the semiconductor chip SC has a first side S1, a second side S2 facing the first side S1, a third side S3 intersecting with each of the first side S1 and the second side S2 in plan view, A fourth side S4 intersects with each of the first side S1 and the second side S2 and faces the third side S3. Further, the semiconductor chip SC includes a first corner C1 where the first side S1 and the third side S3 intersect, a second corner C2 where the second side S2 and the fourth side S4 intersect, a third side S3 and the third side S3. It has a third corner C3 where the two sides S2 intersect, and a fourth corner C4 where the fourth side S4 and the first side S1 intersect.

４．ワイヤボンディング工程
図６（ａ）および（ｂ）に示すように、例えば熱圧着に超音波振動を併用したネイルヘッドボンディング（ボールボンディング）法により、半導体チップＳＣの主面Ｓａに形成された複数の電極パッドＢＰと複数のリードＬＥとを複数の導電性部材、例えばボンディングワイヤＢＷを用いてそれぞれ電気的に接続する。具体的には、ボンディングワイヤＢＷの先端をアーク放電により溶融して表面張力でボール部ＢＷａを形成し、それをキャピラリ（すなわち円筒状の接続治具）により電極パッドＢＰおよびリードＬＥに、例えば１２０ｋＨｚの超音波振動を加えながら熱圧着する。 4). Wire Bonding Step As shown in FIGS. 6A and 6B, for example, a plurality of layers formed on the main surface Sa of the semiconductor chip SC by a nail head bonding (ball bonding) method in which ultrasonic vibration is used in combination with thermocompression bonding. The electrode pad BP and the plurality of leads LE are electrically connected to each other using a plurality of conductive members, for example, bonding wires BW. Specifically, the tip of the bonding wire BW is melted by arc discharge to form a ball portion BWa by surface tension, and this is applied to the electrode pad BP and the lead LE by a capillary (that is, a cylindrical connection jig), for example, 120 kHz. Thermocompression bonding while applying ultrasonic vibration.

ボンディングワイヤＢＷの材料としては、金（Ａｕ）、銅（Ｃｕ）およびアルミニウム（Ａｌ）などの金属材料を挙げることができる。金（Ａｕ）の場合、例えば１５μｍφ〜２０μｍφの金（Ａｕ）線を用いる場合が多い。   Examples of the material of the bonding wire BW include metal materials such as gold (Au), copper (Cu), and aluminum (Al). In the case of gold (Au), for example, a gold (Au) wire of 15 μmφ to 20 μmφ is often used.

また、図７に示すように、ワイヤボンディング工程では、正ボンディング方式、すなわち、半導体チップＳＣの主面Ｓａに形成された電極パッドＢＰとボンディングワイヤＢＷの一部を接続した後に、リードＬＥとボンディングワイヤＢＷの他部を接続する方法を用いる。   In addition, as shown in FIG. 7, in the wire bonding process, after the electrode pad BP formed on the main surface Sa of the semiconductor chip SC and a part of the bonding wire BW are connected in the positive bonding method, the lead LE and the bonding are bonded. A method of connecting the other part of the wire BW is used.

ここで、図６（ａ）に示すように、半導体チップＳＣの主面Ｓａに形成された複数の電極パッドＢＰのうち、第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第５電極パッドＢ５のそれぞれに接続される第１ワイヤＷ１および第５ワイヤＷ５は、図７に示す、第２ワイヤボンディング方法（II−１、II−２、II−３およびII−４の軌跡）が用いられる。さらに、第１ワイヤＷ１および第５ワイヤＷ５に限定されず、例えば第１辺Ｓ１に沿って第１電極パッドＢ１の隣に位置する電極パッドＢＰおよび第３辺Ｓ３に沿って第３電極パッドＢ３の隣に位置する電極パッドＢＰのそれぞれに接続されるボンディングワイヤＢＰにも、図７に示す第２ボンディング方法を用いてもよい。   Here, as shown in FIG. 6A, among the plurality of electrode pads BP formed on the main surface Sa of the semiconductor chip SC, the first electrode pad B1 and the first electrode pad BP located closest to the first corner portion C1. The first wire W1 and the fifth wire W5 connected to each of the five electrode pads B5 are the second wire bonding method (the locus of II-1, II-2, II-3 and II-4) shown in FIG. Is used. Further, the electrode is not limited to the first wire W1 and the fifth wire W5. For example, the electrode pad BP located next to the first electrode pad B1 along the first side S1 and the third electrode pad B3 along the third side S3. The second bonding method shown in FIG. 7 may also be used for the bonding wires BP connected to each of the electrode pads BP located next to the electrode pads BP.

また、半導体チップＳＣの主面Ｓａに形成された複数の電極パッドＢＰのうち、半導体チップＳＣの中心を挟んで第１角部Ｃ１に対向する第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第７電極パッドＢ７のそれぞれに接続される第３ワイヤＷ３および第７ワイヤＷ７は、図７に示す、第２ワイヤボンディング方法（II−１、II−２、II−３およびII−４の軌跡）が用いられる。さらに、第３ワイヤＷ３および第７ワイヤＷ７に限定されず、例えば第２辺Ｓ２に沿って第３電極パッドＢ３の隣に位置する電極パッドＢＰおよび第４辺Ｓ４に沿って第７電極パッドＢ７の隣に位置する電極パッドＢＰのそれぞれに接続されるボンディングワイヤＢＰにも、図７に示す第２ボンディング方法を用いてもよい。   In addition, among the plurality of electrode pads BP formed on the main surface Sa of the semiconductor chip SC, a third one located closest to the second corner C2 facing the first corner C1 across the center of the semiconductor chip SC. The third wire W3 and the seventh wire W7 connected to the electrode pad B3 and the seventh electrode pad B7, respectively, are connected to the second wire bonding method (II-1, II-2, II-3 and II shown in FIG. -4 trajectory) is used. Furthermore, the electrode is not limited to the third wire W3 and the seventh wire W7. For example, the electrode pad BP located next to the third electrode pad B3 along the second side S2 and the seventh electrode pad B7 along the fourth side S4. The second bonding method shown in FIG. 7 may also be used for the bonding wires BP connected to each of the electrode pads BP located next to the electrode pads BP.

これに対して、半導体チップＳＣの主面Ｓａに形成された複数の電極パッドＢＰのうち、第３角部Ｃ３の最も近くに位置する第４電極パッドＢ４および第６電極パッドＢ６のそれぞれに接続される第４ワイヤＷ４および第６ワイヤＷ６は、図７に示す、第１ワイヤボンディング方法（Ｉ−１、Ｉ−２、Ｉ−３およびＩ−４の軌跡）が用いられる。   On the other hand, among the plurality of electrode pads BP formed on the main surface Sa of the semiconductor chip SC, connection is made to each of the fourth electrode pad B4 and the sixth electrode pad B6 located closest to the third corner portion C3. As the fourth wire W4 and the sixth wire W6, the first wire bonding method (trajectory of I-1, I-2, I-3 and I-4) shown in FIG. 7 is used.

また、半導体チップＳＣの主面Ｓａに形成された複数の電極パッドＢＰのうち、半導体チップＳＣの中心を挟んで第３角部Ｃ３に対向する第４角部Ｃ４の最も近くに位置する第２電極パッドＢ２および第８電極パッドＢ８のそれぞれに接続される第２ワイヤＷ２および第８ワイヤＷ８は、図７に示す、第１ワイヤボンディング方法（Ｉ−１、Ｉ−２、Ｉ−３およびＩ−４の軌跡）が用いられる。   In addition, among the plurality of electrode pads BP formed on the main surface Sa of the semiconductor chip SC, the second is located closest to the fourth corner C4 facing the third corner C3 across the center of the semiconductor chip SC. The second wire W2 and the eighth wire W8 connected to the electrode pad B2 and the eighth electrode pad B8, respectively, are connected to the first wire bonding method (I-1, I-2, I-3 and I -4 trajectory) is used.

さらに言えば、図６（ａ）に示すように、半導体チップＳＣの主面Ｓａを、平面視において、半導体チップＳＣの第１辺Ｓ１および第２辺Ｓ２のそれぞれを二等分する第１仮想線ＩＬ１と、半導体チップＳＣの第３辺Ｓ３および第４辺Ｓ４のそれぞれを二等分する第２仮想線ＩＬ２と、で区分すると、半導体チップＳＣの主面Ｓａは、４つの領域に区分される。すなわち、半導体チップＳＣの主面Ｓａは、半導体チップＳＣの第１角部Ｃ１を含む第１領域Ａ１と、半導体チップＳＣの第２角部Ｃ２を含む第２領域Ａ２と、半導体チップＳＣの第３角部Ｃ３を含む第３領域Ａ３と、半導体チップＳＣの第４角部Ｃ４を含む第４領域Ａ４と、を有する。   Further, as shown in FIG. 6A, the first virtual surface that bisects each of the first side S1 and the second side S2 of the semiconductor chip SC in plan view on the main surface Sa of the semiconductor chip SC. When the line IL1 is divided into the second virtual line IL2 that bisects each of the third side S3 and the fourth side S4 of the semiconductor chip SC, the main surface Sa of the semiconductor chip SC is divided into four regions. The That is, the main surface Sa of the semiconductor chip SC includes a first region A1 including the first corner C1 of the semiconductor chip SC, a second region A2 including the second corner C2 of the semiconductor chip SC, and the first region A1 of the semiconductor chip SC. It has 3rd area | region A3 containing 3 corner | angular part C3, and 4th area | region A4 containing 4th corner | angular part C4 of semiconductor chip SC.

そして、半導体チップＳＣの主面Ｓａ形成された複数の電極パッドＢＰのうち、第１領域Ａ１および第２領域Ａ２のそれぞれに位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷに、図７に示す、第２ワイヤボンディング方法（II−１、II−２、II−３およびII−４の軌跡）を用いてもよい。   Then, among the plurality of electrode pads BP formed on the main surface Sa of the semiconductor chip SC, a plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in each of the first region A1 and the second region A2. In addition, the second wire bonding method (the trajectory of II-1, II-2, II-3 and II-4) shown in FIG. 7 may be used.

これに対して、半導体チップＳＣの主面Ｓａに形成された複数の電極パッドＢＰのうち、第３領域Ａ３および第４領域Ａ４のそれぞれに位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷは、図７に示す、第１ワイヤボンディング方法（Ｉ−１、Ｉ−２、Ｉ−３およびＩ−４の軌跡）が用いられる。   On the other hand, among the plurality of electrode pads BP formed on the main surface Sa of the semiconductor chip SC, a plurality connected to each of the plurality of electrode pads BP located in each of the third region A3 and the fourth region A4. For the bonding wire BW, the first wire bonding method (trajectory of I-1, I-2, I-3 and I-4) shown in FIG. 7 is used.

ここで、第１ワイヤボンディング方法（Ｉ−１、Ｉ−２、Ｉ−３およびＩ−４の軌跡）について、図７を用いて以下に説明する。   Here, the first wire bonding method (the trajectories of I-1, I-2, I-3, and I-4) will be described below with reference to FIG.

まず、ワイヤの先端にボールが形成された状態から、ワイヤクランプが開いてキャピラリーＣＡが降下する。この際、ボールはチャンファー内に捕捉され、キャピラリーＣＡの先端面の中央に位置合わせされている。   First, from the state where the ball is formed at the tip of the wire, the wire clamp is opened and the capillary CA is lowered. At this time, the ball is captured in the chamfer and is aligned with the center of the tip surface of the capillary CA.

次に、キャピラリーＣＡを降下させて、ボールを半導体チップＳＣの主面Ｓａに形成された電極パッドＢＰと接触させた後、熱、荷重および超音波をボールに加えて、ボールと電極パッドＢＰとを接合して、ボール部ＢＷａを形成する（第１ボンド、ボールボンド）。   Next, the capillary CA is lowered to bring the ball into contact with the electrode pad BP formed on the main surface Sa of the semiconductor chip SC, and then, heat, load and ultrasonic waves are applied to the ball, and the ball, the electrode pad BP, Are joined to form a ball portion BWa (first bond, ball bond).

次に、キャピラリーＣＡを、ボール部ＢＷａを接合した電極パッドＢＰから一定の高さまで上昇させた後、ワイヤにループを形成しながら、キャピラリーＣＡをワイヤが接続するリードＬＥへ移動させる。   Next, after raising the capillary CA to a certain height from the electrode pad BP to which the ball portion BWa is bonded, the capillary CA is moved to the lead LE to which the wire is connected while forming a loop in the wire.

次に、ワイヤをリードＬＥと接触させた後、熱、荷重および超音波をワイヤに加えて、ワイヤとリードＬＥとを接合する（第２ボンド、ステッチボンド）。   Next, after bringing the wire into contact with the lead LE, heat, load and ultrasonic waves are applied to the wire to join the wire and the lead LE (second bond, stitch bond).

次に、キャピラリーＣＡはワイヤを残したまま上昇し、キャピラリーＣＡの先端に一定の長さのテイルを確保した後、ワイヤクランプを閉じてワイヤを切断する。これにより、ボンディングワイヤＢＷが形成される。   Next, the capillary CA rises with the wire left, and after securing a tail of a certain length at the tip of the capillary CA, the wire clamp is closed and the wire is cut. Thereby, the bonding wire BW is formed.

第１ボンド点ＦＢＰでボールを電極パッドＢＰに接合し、第２ボンド点ＳＢＰでワイヤをリードＬＥに接合するまでの間において、ワイヤに所望する形のループを形成するために、キャピラリーＣＡを特殊な軌跡で移動させてワイヤに「くせ」つける動作をする。   In order to form a loop of a desired shape in the wire until the ball is bonded to the electrode pad BP at the first bond point FBP and the wire is bonded to the lead LE at the second bond point SBP, a special capillary CA is used. It moves with a simple trajectory and “squeezes” the wire.

例えば図７に示すように、キャピラリーＣＡを電極パッドＢＰ（第１ボンド点ＦＢＰ）から直上に引き上げた後（Ｉ−１）、キャピラリーＣＡを半導体チップＳＣの内側方向、すなわち、ワイヤを接続するリードＬＥと反対方向に移動させる（Ｉ−２）。このときの、平面視における、第１ボンド点ＦＢＰからのキャピラリーＣＡの移動距離はＬ１である。続いて、キャピラリーＣＡをさらに直上に引き上げた後（Ｉ−３）、ワイヤを接続するリードＬＥへ、キャピラリーＣＡを降下させながら移動させて、ワイヤをリードＬＥ（第２ボンド点ＳＢＰ）上に押し付ける（Ｉ−４）。   For example, as shown in FIG. 7, after the capillary CA is pulled up directly from the electrode pad BP (first bond point FBP) (I-1), the capillary CA is connected to the inside of the semiconductor chip SC, that is, a lead for connecting wires. Move in the opposite direction to LE (I-2). At this time, the moving distance of the capillary CA from the first bond point FBP in plan view is L1. Subsequently, after the capillary CA is further pulled up (I-3), the capillary CA is moved down to the lead LE to which the wire is connected, and the wire is pressed onto the lead LE (second bond point SBP). (I-4).

第２ワイヤボンディング方法（ＩＩ−１、ＩＩ−２、ＩＩ−３およびＩＩ−４の軌跡）について、図７を用いて以下に説明する。   The second wire bonding method (the trajectories of II-1, II-2, II-3, and II-4) will be described below with reference to FIG.

第２ワイヤボンディング方法における、ワイヤと半導体チップＳＣの主面Ｓａに形成された電極パッドＢＰとの接続およびワイヤとリードＬＥとの接続の動作は、上記第１ワイヤボンド方法における、ワイヤと半導体チップＳＣの主面Ｓａに形成された電極パッドＢＰとの接続およびワイヤとリードＬＥとの接続の動作と基本的には同じである。   In the second wire bonding method, the connection between the wire and the electrode pad BP formed on the main surface Sa of the semiconductor chip SC and the operation of the connection between the wire and the lead LE are the same as those in the first wire bonding method. The operation is basically the same as the connection between the electrode pad BP formed on the main surface Sa of the SC and the connection between the wire and the lead LE.

また、第１ボンド点ＦＢＰでボールを電極パッドＢＰに接合し、第２ボンド点ＳＢＰでワイヤをリードＬＥに接合するまでの間において、ワイヤに所望する形のループを形成するために、キャピラリーＣＡを特殊な軌跡で移動させてワイヤに「くせ」つける動作をする。   Further, in order to form a loop of a desired shape on the wire until the ball is bonded to the electrode pad BP at the first bond point FBP and the wire is bonded to the lead LE at the second bond point SBP, the capillary CA is formed. Move the wire with a special trajectory to “kake” the wire.

しかし、第１ワイヤボンディング方法のキャピラリーＣＡの軌跡と、第２ワイヤボンディング方法のキャピラリーＣＡの軌跡とは互いに異なる。   However, the trajectory of the capillary CA of the first wire bonding method is different from the trajectory of the capillary CA of the second wire bonding method.

例えば図７に示すように、キャピラリーＣＡを電極パッドＢＰ（第１ボンド点ＦＢＰ）から直上に引き上げた後（II−１）、キャピラリーＣＡを半導体チップＳＣの内側方向、すなわち、ワイヤを接続するリードＬＥと反対方向に移動させる（II−２）。このときの、平面視における、第１ボンド点ＦＢＰからのキャピラリーＣＡの移動距離はＬ２であり、第２ワイヤボンディング方法の移動距離Ｌ２は、第１ワイヤボンディング方法の移動距離Ｌ１よりも大きい。続いて、キャピラリーＣＡをさらに直上に引き上げた後（II−３）、ワイヤを接続するリードＬＥへ、キャピラリーＣＡを降下させながら移動させて、ワイヤをリードＬＥ（第２ボンド点ＳＢＰ）上に押し付ける（II−４）。   For example, as shown in FIG. 7, after the capillary CA is pulled up directly from the electrode pad BP (first bond point FBP) (II-1), the capillary CA is moved inward of the semiconductor chip SC, that is, a lead for connecting wires. Move in the opposite direction to LE (II-2). At this time, the moving distance of the capillary CA from the first bond point FBP in plan view is L2, and the moving distance L2 of the second wire bonding method is larger than the moving distance L1 of the first wire bonding method. Subsequently, after the capillary CA is further pulled up (II-3), the capillary CA is moved down to the lead LE to which the wire is connected, and the wire is pressed onto the lead LE (second bond point SBP). (II-4).

従って、第１ワイヤボンディング方法を用いて形成されたボンディングワイヤＢＷのループ形状と、第２ワイヤボンディング方法を用いて形成されたボンディングワイヤＢＷのループ形状と、は異なることになる。   Therefore, the loop shape of the bonding wire BW formed using the first wire bonding method is different from the loop shape of the bonding wire BW formed using the second wire bonding method.

すなわち、第２ワイヤボンディング方法を用いて形成された第１ワイヤＷ１、第３ワイヤＷ３、第５ワイヤＷ５および第７ワイヤＷ７のそれぞれは、ボール部ＢＷａが位置する第１ボンド点ＦＢＰから半導体チップＳＣの内側方向（第１ワイヤＷ１、第３ワイヤＷ３、第５ワイヤＷ５および第７ワイヤＷ７がそれぞれ接続するリードＬＥと反対側の方向）に、引き出されている。   That is, each of the first wire W1, the third wire W3, the fifth wire W5, and the seventh wire W7 formed by using the second wire bonding method starts from the first bond point FBP where the ball portion BWa is located. It is drawn in the inner direction of the SC (the direction opposite to the lead LE to which the first wire W1, the third wire W3, the fifth wire W5 and the seventh wire W7 are respectively connected).

これに対して、第１ワイヤボンディング方法を用いて形成された第２ワイヤＷ２、第４ワイヤＷ４、第６ワイヤＷ６および第８ワイヤＷ８のそれぞれは、ボール部ＢＷａが位置する第１ボンド点ＦＢＰから半導体チップＳＣの内側方向（第２ワイヤＷ２、第４ワイヤＷ４、第６ワイヤＷ６および第８ワイヤＷ８がそれぞれ接続するリードＬＥと反対側の方向）に、引き出されていない。   In contrast, each of the second wire W2, the fourth wire W4, the sixth wire W6, and the eighth wire W8 formed using the first wire bonding method has a first bond point FBP where the ball portion BWa is located. To the inside of the semiconductor chip SC (the direction opposite to the lead LE to which the second wire W2, the fourth wire W4, the sixth wire W6 and the eighth wire W8 are respectively connected).

従って、第１ワイヤＷ１の芯部の曲げ角度は、第２ワイヤＷ２の芯部の曲げ角度よりも大きく、第３ワイヤＷ３の芯部の曲げ角度は、第４ワイヤＷ４の芯部の曲げ角度よりも大きく、第５ワイヤＷ５の芯部の曲げ角度は、第６ワイヤＷ６の芯部の曲げ角度よりも大きく、および第７ワイヤＷ７の芯部の曲げ角度は、第８ワイヤＷ８の芯部の曲げ角度よりも大きくなる（図３（ｃ）参照）。   Therefore, the bending angle of the core portion of the first wire W1 is larger than the bending angle of the core portion of the second wire W2, and the bending angle of the core portion of the third wire W3 is the bending angle of the core portion of the fourth wire W4. The bending angle of the core portion of the fifth wire W5 is larger than the bending angle of the core portion of the sixth wire W6, and the bending angle of the core portion of the seventh wire W7 is the core portion of the eighth wire W8. (See FIG. 3C).

また、第１ワイヤＷ１は第２ワイヤＷ２よりも長く、第３ワイヤＷ３は第４ワイヤＷ４よりも長く、第５ワイヤＷ５は第６ワイヤＷ６より長く、および第７ワイヤＷ７は第８ワイヤＷ８よりも長くなる（図３（ｃ）参照）。   The first wire W1 is longer than the second wire W2, the third wire W3 is longer than the fourth wire W4, the fifth wire W5 is longer than the sixth wire W6, and the seventh wire W7 is the eighth wire W8. (See FIG. 3C).

なお、上記説明では、第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第５電極パッドＢ５のそれぞれに接続する第１ワイヤＷ１および第５ワイヤＷ５、並びに第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第７電極パッドＢ７のそれぞれに接続する第３ワイヤＷ３および第７ワイヤＷ７に、第２ワイヤボンディング方法を適用したが、これに限定されるものではない。   In the above description, the first wire W1 and the fifth wire W5 connected to the first electrode pad B1 and the fifth electrode pad B5 located closest to the first corner C1, respectively, and the second corner C2. Although the second wire bonding method is applied to the third wire W3 and the seventh wire W7 connected to the third electrode pad B3 and the seventh electrode pad B7 located closest to each other, the present invention is not limited to this. .

すなわち、第２ワイヤボンディング方法を適用するボンディングワイヤＢＷは、後述するモールド工程における樹脂の流れを考慮して決定される。   That is, the bonding wire BW to which the second wire bonding method is applied is determined in consideration of the flow of resin in the molding process described later.

例えば図６（ａ）に示すように、第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第１辺Ｓ１に沿って第１電極パッドＢ１の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷに、第２ワイヤボンディング方法を適用することができる。また、第１角部Ｃ１の最も近くに位置する第５電極パッドＢ５および第３辺に沿って第５電極パッドＢ５の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷに、第２ワイヤボンディング方法を適用することができる。また、第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第２辺Ｓ２に沿って第３電極パッドＢ３の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷに、第２ワイヤボンディング方法を適用することができる。また、第２角部Ｃ２の最も近くに位置する第７電極パッドＢ７および第４辺Ｓ４に沿って第７電極パッドＢ７の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷに、第２ワイヤボンディング方法を適用することができる。   For example, as shown in FIG. 6A, each of the first electrode pad B1 located closest to the first corner C1 and the electrode pad BP located next to the first electrode pad B1 along the first side S1. The second wire bonding method can be applied to the plurality of bonding wires BW connected to the. In addition, a plurality of bonding wires BW connected to each of the fifth electrode pad B5 located closest to the first corner C1 and the electrode pad BP located next to the fifth electrode pad B5 along the third side. The second wire bonding method can be applied. In addition, a plurality of bonding wires BW connected to the third electrode pad B3 located closest to the second corner C2 and the electrode pad BP located next to the third electrode pad B3 along the second side S2 In addition, the second wire bonding method can be applied. Also, a plurality of bonding wires BW connected to each of the seventh electrode pad B7 located closest to the second corner C2 and the electrode pad BP located next to the seventh electrode pad B7 along the fourth side S4. In addition, the second wire bonding method can be applied.

これに対して、第２ワイヤボンディング方法を適用しない電極パッドＢＰに、第１ワイヤボンディング方法を適用することができる。   On the other hand, the first wire bonding method can be applied to the electrode pads BP to which the second wire bonding method is not applied.

さらに言えば、例えば図６（ａ）に示すように、半導体チップＳＣの主面Ｓａに形成された複数の電極パッドＢＰのうち、第１領域Ａ１および第２領域Ａ２のそれぞれに位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷに、第２ワイヤボンディング方法を適用することができる。   Further, for example, as shown in FIG. 6A, among the plurality of electrode pads BP formed on the main surface Sa of the semiconductor chip SC, a plurality of positions located in each of the first region A1 and the second region A2. The second wire bonding method can be applied to the plurality of bonding wires BW connected to each of the electrode pads BP.

これに対して、半導体チップＳＣの主面Ｓａに形成された複数の電極パッドＢＰのうち、第３領域Ａ３および第４領域Ａ４のそれぞれに位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷに、第１ワイヤボンディング方法を適用することができる。   On the other hand, among the plurality of electrode pads BP formed on the main surface Sa of the semiconductor chip SC, a plurality connected to each of the plurality of electrode pads BP located in each of the third region A3 and the fourth region A4. The first wire bonding method can be applied to the bonding wire BW.

ただし、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第５電極パッドＢ５のそれぞれに接続される第１ワイヤＷ１および第５ワイヤＷ５、並びに半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第７電極パッドＢ７のそれぞれに接続される第３ワイヤＷ３および第７ワイヤＷ７には、必ず第２ワイヤボンディング方法を適用する。   However, the first wire W1 and the fifth wire W5 connected to the first electrode pad B1 and the fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC, respectively, and the first of the semiconductor chip SC. The second wire bonding method is always applied to the third wire W3 and the seventh wire W7 connected to the third electrode pad B3 and the seventh electrode pad B7 located closest to the corner C2, respectively.

このように、第１ワイヤボンディング方法または第２ワイヤボンディング方法を用いて、互いにループ形状の異なる複数のボンディングワイヤＢＷを形成することにより、モールド工程における樹脂の流れに起因して生じるボンディングワイヤＢＷの不良を低減することができる。ボンディングワイヤＢＷの不良とは、例えば（１）ボンディングワイヤＢＷの電極パッドＢＰからの剥がれ、（２）ボンディングワイヤＢＷのボール部ＢＷａと芯部ＢＷｂとの接合部（ネック部）の切断、または（３）ボンディングワイヤＢＷの流れなどである。   In this way, by using the first wire bonding method or the second wire bonding method, a plurality of bonding wires BW having different loop shapes are formed, so that the bonding wires BW generated due to the resin flow in the molding process can be obtained. Defects can be reduced. The defect of the bonding wire BW is, for example, (1) peeling of the bonding wire BW from the electrode pad BP, (2) cutting of the bonding portion (neck portion) between the ball portion BWa and the core portion BWb of the bonding wire BW, or ( 3) The flow of the bonding wire BW.

なお、本実施の形態による半導体装置の特徴および効果については、後述する≪比較例による半導体装置の構成および課題≫、並びに≪本実施の形態による半導体装置の特徴および効果≫において、詳細に説明する。   Note that the features and effects of the semiconductor device according to the present embodiment will be described in detail in << Configuration and Problem of Semiconductor Device According to Comparative Example >> and << Features and Effects of Semiconductor Device According to this Embodiment >> described later. .

５．モールド工程
図８（ａ）および（ｂ）、並びに図９に示すように、リードフレームＬＦに搭載された複数の半導体チップＳＣのそれぞれを封止体ＲＥにより樹脂封止する。 5. Molding Step As shown in FIGS. 8A and 8B and FIG. 9, each of the plurality of semiconductor chips SC mounted on the lead frame LF is sealed with a sealing body RE.

まず、ワイヤボンディングされた複数の半導体チップＳＣが搭載されたリードフレームＬＦをトランスファモールド装置に備わる成形金型にセットする。   First, a lead frame LF on which a plurality of wire-bonded semiconductor chips SC are mounted is set in a molding die provided in a transfer mold apparatus.

成形金型は、リードフレームＬＦが配置される下金型ＭＤａと、下金型ＭＤａの上方に位置し、この下金型ＭＤａと係合してリードフレームＬＦを密閉する上金型ＭＤｂとを有している。リードフレームＬＦは下金型ＭＤａと上金型ＭＤｂとの間に配置される。下金型ＭＤａおよび上金型ＭＤｂには、それぞれ半導体チップＳＣを樹脂封止するパッケージ領域（または樹脂封止領域とも言う）となるキャビティＣＶａおよびキャビティＣＶｂが複数形成されている。   The molding die includes a lower die MDa in which the lead frame LF is disposed, and an upper die MDb that is located above the lower die MDa and engages with the lower die MDa to seal the lead frame LF. Have. The lead frame LF is disposed between the lower mold MDa and the upper mold MDb. In the lower mold MDa and the upper mold MDb, a plurality of cavities CVa and cavities CVb serving as package regions (also referred to as resin-sealed regions) for resin-sealing the semiconductor chip SC are formed.

さらに、キャビディＣＶａ、ＣＶｂ内に樹脂ＲＥａを流入する際の入り口となるゲートＧＡが、下金型ＭＤａおよび上金型ＭＤｂのそれぞれに形成されている。   Further, gates GA serving as entrances when the resin REa flows into the cavities CVa and CVb are formed in each of the lower mold MDa and the upper mold MDb.

図９に示すように、ゲートＧＡは、４つの吊りリードＨＬのうちのある吊りリードＨＬ（第１ワイヤＷ１が接続するリードＬＥと第５ワイヤＷ５が接続するリードＬＥとの間に位置する吊りリードＨＬ）の近傍に設けられており、図１２に示すように、上金型ＭＤｂ（この吊りリードＨＬの上側）および下金型ＭＤａ（この吊りリードＨＬの下側）のそれぞれに設けられたゲートＧＡを介して、成形金型のポット部（図示しない）からキャビティＣＶａ、ＣＶｂ内に樹脂ＲＥａが流し込まれる。また、上記４つの吊りリードＨＬのうちの残り３つの吊りリードＨＬの近傍にはベント（エアベントとも言う）ＶＥが設けられており、上金型ＭＤｂ（残りの吊りリードＨＬの上側）および下金型ＭＤａ（残りの吊りリードＨＬの下側）のそれぞれに設けられたベントＶＥを介して、キャビティＣＶａ、ＣＶｂ内の空気またはガスを、キャビティＣＶａ、ＣＶｂの外側に排気する（図１２参照）。   As shown in FIG. 9, the gate GA is a suspension lead HL (a suspension located between a lead LE to which the first wire W1 is connected and a lead LE to which the fifth wire W5 is connected) among the four suspension leads HL. As shown in FIG. 12, the upper mold MDb (upper side of the suspension lead HL) and the lower mold MDa (lower side of the suspension lead HL) are provided. The resin REa is poured into the cavities CVa and CVb from the pot portion (not shown) of the molding die through the gate GA. A vent (also referred to as an air vent) VE is provided in the vicinity of the remaining three suspension leads HL among the four suspension leads HL, and an upper mold MDb (upper side of the remaining suspension leads HL) and a lower mold are provided. The air or gas in the cavities CVa and CVb is exhausted to the outside of the cavities CVa and CVb via the vents VE provided on each of the molds MDa (below the remaining suspension leads HL) (see FIG. 12).

そして、下金型ＭＤａと上金型ＭＤｂとを閉じることにより、リードフレームＬＦは下金型ＭＤａと上金型ＭＤｂとでクランプされる。このとき、リードフレームＬＦを下金型ＭＤａと上金型ＭＤｂとの間に樹脂ＲＥａが洩れることのないように隙間無く挟み、リードフレームＬＦを固定する。キャビティＣＶａ、ＣＶｂによって形成された１つのパッケージ領域内には、半導体チップＳＣ、複数のボンディングワイヤＢＷ、ダイパッドＤＰ、複数のリードＬＥの一部および複数の吊りリードＨＬが配置される。   Then, by closing the lower mold MDa and the upper mold MDb, the lead frame LF is clamped by the lower mold MDa and the upper mold MDb. At this time, the lead frame LF is sandwiched between the lower mold MDa and the upper mold MDb so that the resin REa does not leak, and the lead frame LF is fixed. In one package region formed by the cavities CVa and CVb, the semiconductor chip SC, the plurality of bonding wires BW, the die pad DP, a part of the plurality of leads LE, and the plurality of suspension leads HL are arranged.

次に、温度を上げて液状化した樹脂ＲＥａを、ゲートＧＡからキャビティＣＶａ、ＣＶｂ内に圧送して流し込み、キャビティＣＶａ、ＣＶｂ内を樹脂ＲＥａによって充填させる。充填圧は、例えば１５ＭＰａ程度である。   Next, the resin REa liquefied by raising the temperature is pumped from the gate GA into the cavities CVa and CVb, and the cavities CVa and CVb are filled with the resin REa. The filling pressure is, for example, about 15 MPa.

図９に示すように、樹脂ＲＥａは、ゲートＧＡからキャビティＣＶａ、ＣＶｂ内に流れ込み、半導体チップＳＣの上面側および側面側を流れ、半導体チップＳＣの中心を挟んでゲートＧＡに対向するベントＶＥ方向へと流れる。これにより、半導体チップＳＣ、複数のボンディングワイヤＢＷ、ダイパッドＤＰ、複数のリードＬＥの一部および複数の吊りリードＨＬを樹脂ＲＥａで封止して封止体ＲＥが形成される。封止体ＲＥは、低応力化を図ることを目的として、例えばフェノール系硬化剤、シリコーンゴムおよび多数のフィラー（例えばシリカ）などが添加されたエポキシ系の熱硬化性絶縁樹脂から成る。   As shown in FIG. 9, the resin REa flows from the gate GA into the cavities CVa and CVb, flows on the upper surface side and the side surface side of the semiconductor chip SC, and faces the gate GA across the center of the semiconductor chip SC. It flows to. As a result, the semiconductor chip SC, the plurality of bonding wires BW, the die pad DP, a part of the plurality of leads LE, and the plurality of suspension leads HL are sealed with the resin REa to form the sealing body RE. The sealing body RE is made of an epoxy-based thermosetting insulating resin to which, for example, a phenol-based curing agent, silicone rubber, and many fillers (for example, silica) are added for the purpose of reducing stress.

その後、トランスファモールド装置から複数の封止体ＲＥが形成されたリードフレームＬＦを取り出す。   Thereafter, the lead frame LF on which the plurality of sealing bodies RE are formed is taken out from the transfer mold apparatus.

次に、複数の封止体ＲＥが形成されたリードフレームＬＦに対して、アニール処理（ベーク処理、アフターキュア）を施す。アニール処理は、例えば温度１６０℃〜１９０℃程度の温度で約７時間程度行う。この熱処理により、封止体ＲＥの更なる硬化促進を行い、リードフレームＬＦへの密着性等を向上させる。   Next, an annealing process (baking process, after-cure) is performed on the lead frame LF on which the plurality of sealing bodies RE are formed. The annealing treatment is performed for about 7 hours at a temperature of about 160 ° C. to 190 ° C., for example. This heat treatment further accelerates the curing of the sealing body RE and improves the adhesion to the lead frame LF and the like.

６．メッキ工程
次に、リードフレームＬＦにめっき処理を施す。これにより、樹脂封止されていないリードフレームＬＦの第１面および第２面に、例えば厚さ１０μｍ以下の錫（Ｓｎ）、錫−銀（Ｓｎ−Ａｇ）系合金、錫−銅（Ｓｎ−Ｃｕ）系合金、錫−ビスマス（Ｓｎ−Ｂｉ）系合金、または錫−鉛（Ｓｎ−Ｐｂ）系合金から成るめっき膜を形成する。 6). Plating process Next, the lead frame LF is plated. Thus, for example, tin (Sn), tin-silver (Sn—Ag) alloy, tin-copper (Sn—) having a thickness of 10 μm or less is formed on the first surface and the second surface of the lead frame LF which is not resin-sealed. A plated film made of a Cu) -based alloy, a tin-bismuth (Sn-Bi) -based alloy, or a tin-lead (Sn-Pb) -based alloy is formed.

７．リード切断工程
次に、図１０（ａ）および（ｂ）に示すように、切断装置を用いて複数のリードＬＥの間に設置されたタイバーＴＢを切断した後、封止体ＲＥから余分な樹脂バリを除去する。さらに、切断装置を用いて複数のリードＬＥおよび複数の吊りリードＨＬを切断して、リードフレームＬＦの本体から個々の単位フレームＳＦに切り分ける。 7). Next, as shown in FIGS. 10A and 10B, after cutting the tie bars TB installed between the plurality of leads LE using a cutting device, excess resin is removed from the sealing body RE. Remove burrs. Further, the plurality of leads LE and the plurality of suspension leads HL are cut using a cutting device, and cut into individual unit frames SF from the main body of the lead frame LF.

切断時には、例えば切断装置に備わるダイ（受け台）上にリードフレームＬＦを置いて、まず、複数のリードＬＥを切断し、その後、複数の吊りリードＨＬを切断する。複数の吊りリードＨＬは、タブＤＰおよび封止体ＲＥを吊っているので、複数のリードＬＥを切断した段階では、封止体ＲＥはリードフレームＬＦの本体から分離されず、複数の吊りリードＨＬを切断した段階で、封止体ＲＥはリードフレームＬＦの本体から分離される。   At the time of cutting, for example, the lead frame LF is placed on a die (a cradle) provided in the cutting device, the plurality of leads LE are first cut, and then the plurality of suspension leads HL are cut. Since the plurality of suspension leads HL suspend the tab DP and the sealing body RE, when the plurality of leads LE are cut, the sealing body RE is not separated from the main body of the lead frame LF, and the plurality of suspension leads HL. At the stage of cutting, the sealing body RE is separated from the main body of the lead frame LF.

８．リード成形工程
次に、図１１（ａ）および（ｂ）に示すように、成形金型により封止体ＲＥから露出している複数のリードＬＥを所定の形状、例えばガルウイング形状に成形する。これにより、半導体装置ＳＭが略完成する。 8). Next, as shown in FIGS. 11A and 11B, a plurality of leads LE exposed from the sealing body RE are molded into a predetermined shape, for example, a gull wing shape, by a molding die. Thereby, the semiconductor device SM is substantially completed.

上記説明では、メッキ工程、リード切断工程、リード成形工程の順に半導体装置ＳＭの製造を行っているが、リード切断工程の後に、メッキ工程およびリード成形工程を順に行ってもよい。   In the above description, the semiconductor device SM is manufactured in the order of the plating step, the lead cutting step, and the lead forming step. However, the plating step and the lead forming step may be sequentially performed after the lead cutting step.

９．検査工程
次に、半導体装置ＳＭを、製品規格に応じた電気的検査や外観検査などのテスト工程を経て良品と不良品とに選別する。 9. Inspection Process Next, the semiconductor device SM is classified into a non-defective product and a defective product through a test process such as an electrical inspection or an appearance inspection according to the product standard.

１０．出荷工程
次に、良品と判定された半導体装置ＳＭを製品規格に沿って選別し、さらに最終外観検査を行った後、出荷される。 10. Next, the semiconductor device SM determined to be a non-defective product is selected according to the product standard, and further subjected to final appearance inspection before being shipped.

≪比較例による半導体装置の構成および課題≫
次に、本発明者が検討した比較例による半導体装置の構成および課題について、図１２〜図１７を用いて説明する。 << Configuration and Issues of Semiconductor Device According to Comparative Example >>
Next, the configuration and problems of a semiconductor device according to a comparative example studied by the present inventors will be described with reference to FIGS.

図１２（ａ）は、モールド工程における、ゲートからベントへの樹脂の流れを説明する断面図、図１２（ｂ）は、モールド工程における、ゲート近傍およびベント近傍のそれぞれに位置するボンディングワイヤの周辺の樹脂の流れを説明する断面図である。図１３は、第１の課題の説明図であり、図１３（ａ）は、モールド工程においてゲート近傍に位置するボンディングワイヤが受ける応力状態図、図１３（ｂ）は、ボンディングワイヤのボール部の剥がれを説明する模式図である。図１４は、第２の課題の説明図であり、図１４（ａ）は、モールド工程におけるベント近傍に位置するボンディングワイヤが受ける応力状態図、図１４（ｂ）は、ボンディングワイヤのボール部と芯部との接合部（ネック部）の切断を説明する模式図である。図１５は、第３の課題の説明図であり、モールド工程における、ゲートからベントへの樹脂の流れを説明する平面図である。図１６は、第１および第２の課題の解決が必要となるボンディングワイヤの一例を説明する平面図である。図１７は、第１および第２の課題の解決が必要となるボンディングワイヤの他の例を説明する平面図である。   FIG. 12A is a cross-sectional view illustrating the flow of resin from the gate to the vent in the molding process, and FIG. 12B is a periphery of the bonding wire located in the vicinity of the gate and the vent in the molding process. It is sectional drawing explaining the flow of this resin. FIG. 13 is an explanatory diagram of the first problem. FIG. 13 (a) is a stress state diagram received by the bonding wire located near the gate in the molding process, and FIG. 13 (b) is a diagram of the ball portion of the bonding wire. It is a schematic diagram explaining peeling. 14A and 14B are explanatory views of the second problem. FIG. 14A is a stress state diagram received by the bonding wire located in the vicinity of the vent in the molding process, and FIG. It is a schematic diagram explaining the cutting | disconnection of a junction part (neck part) with a core part. FIG. 15 is an explanatory diagram of the third problem, and is a plan view illustrating the flow of resin from the gate to the vent in the molding process. FIG. 16 is a plan view illustrating an example of a bonding wire that needs to solve the first and second problems. FIG. 17 is a plan view for explaining another example of the bonding wire that needs to solve the first and second problems.

なお、モールド工程で使用するトランスファモールド装置に備わる成形金型には、３つのベントが設けられているが、ここで「ベント」と言うときは、半導体チップＳＣの中心を挟んでゲートに対向するベント、すなわち、３つベントのうち、最後にキャビティＣＶａ、ＣＶｂ内の空気またはガスを排気するベントを意味する。また、図１２（ａ）および（ｂ）、並びに図１５に網掛けのハッチングで示す矢印は、樹脂の流れを示している。   Note that the molding die provided in the transfer molding apparatus used in the molding process is provided with three vents. Here, the term “vent” refers to the gate across the center of the semiconductor chip SC. The vent means a vent for exhausting air or gas in the cavities CVa and CVb among the three vents. Moreover, the arrow shown by the hatching of FIG. 12 (a) and (b) and FIG. 15 has shown the flow of resin.

図１２（ａ）に示すように、キャビディＣＶａ、ＣＶｂ内に樹脂を流入する際の入り口となるゲートＧＡが、下金型ＭＤａおよび上金型ＭＤｂに形成されている。従って、吊りリードＨＬの上側および下側から樹脂がキャビティＣＶａ、ＣＶｂ内に流し込まれる。また、キャビティＣＶａ、ＣＶｂ内の空気またはガスを排気する際の出口となるベントＶＥが、下金型ＭＤａおよび上金型ＭＤｂの、半導体チップＳＣの中心を挟んでゲートＧＡに対向する位置に形成されている。   As shown in FIG. 12A, a gate GA serving as an entrance when the resin flows into the cavities CVa and CVb is formed in the lower mold MDa and the upper mold MDb. Accordingly, the resin is poured into the cavities CVa and CVb from the upper side and the lower side of the suspension lead HL. Further, a vent VE serving as an outlet for exhausting air or gas in the cavities CVa and CVb is formed at a position of the lower mold MDa and the upper mold MDb facing the gate GA across the center of the semiconductor chip SC. Has been.

そして、前述したように、樹脂は、ゲートＧＡから、吊りリードＨＬの上側、下側および側面側を通ってキャビティＣＶａ、ＣＶｂ内に流れ込み、半導体チップＳＣの上面側および側面側を流れ、半導体チップＳＣの中心を挟んでゲートＧＡに対向するベントＶＥの方向へと流れる（図１５参照）。   As described above, the resin flows from the gate GA into the cavities CVa and CVb through the upper side, the lower side, and the side surface side of the suspension lead HL, and flows through the upper surface side and the side surface side of the semiconductor chip SC. It flows in the direction of the vent VE facing the gate GA across the center of the SC (see FIG. 15).

しかし、図１２（ｂ）に示すように、ゲートＧＡ近傍に位置するボンディングワイヤＢＷでは、樹脂は、当該ボンディングワイヤＢＷの上側および下側をそれぞれ上流から下流へと流れ、当該ボンディングワイヤＢＷの上側を流れる樹脂の流速に比べて、当該ボンディングワイヤＢＷの下側を流れる樹脂の流速が遅くなる。   However, as shown in FIG. 12B, in the bonding wire BW located in the vicinity of the gate GA, the resin flows from the upstream side to the downstream side of the bonding wire BW from the upstream side to the downstream side, and the upper side of the bonding wire BW. The flow rate of the resin flowing under the bonding wire BW is slower than the flow rate of the resin flowing through the bonding wire BW.

ゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、例えば図１に示した、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第５電極パッドＢ５のそれぞれに接続される第１ワイヤＷ１および第５ワイヤＷ５である。さらに、ゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、第１ワイヤＷ１および第５ワイヤＷ５に加えて、例えば図１に示した、第１辺Ｓ１に沿って第１電極パッドＢ１の隣に位置する電極パッドＢＰおよび第３辺Ｓ３に沿って第５電極パッドＢ５の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷを含む場合もある。さらに、ゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、第１ワイヤＷ１および第５ワイヤＷ５に加えて、例えば図１に示した、第１領域Ａ１に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷを含む場合もある。   The bonding wire BW located in the vicinity of the gate GA is connected to each of the first electrode pad B1 and the fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC, for example, as shown in FIG. The first wire W1 and the fifth wire W5. Furthermore, the bonding wire BW located in the vicinity of the gate GA is located next to the first electrode pad B1 along the first side S1 shown in FIG. 1, for example, in addition to the first wire W1 and the fifth wire W5. In some cases, it includes a plurality of bonding wires BW connected to each of the electrode pad BP and the electrode pad BP located next to the fifth electrode pad B5 along the third side S3. Further, the bonding wire BW located in the vicinity of the gate GA is connected to each of the plurality of electrode pads BP located in the first region A1 shown in FIG. 1, for example, in addition to the first wire W1 and the fifth wire W5. A plurality of bonding wires BW may be included.

また、図１２（ｂ）に示すように、ベントＶＥ近傍に位置するボンディングワイヤＢＷでは、当該ボンディングワイヤＢＷの上側が上流、下側が下流となるため、樹脂は、当該ボンディングワイヤＢＷの上側から下側に向かって流れる。   Further, as shown in FIG. 12B, in the bonding wire BW located in the vicinity of the vent VE, the upper side of the bonding wire BW is upstream and the lower side is downstream. Therefore, the resin is lowered from the upper side of the bonding wire BW. It flows toward the side.

ベントＶＥ近傍に位置するボンディングワイヤＢＷとは、例えば図１に示した、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第７電極パッドＢ７のそれぞれに接続される第３ワイヤＷ３および第７ワイヤＷ７である。さらに、ベントＶＥ近傍に位置するボンディングワイヤＢＷとは、第３ワイヤＷ３および第７ワイヤＷ７に加えて、例えば図１に示した、第２辺Ｓ２に沿って第３電極パッドＢ３の隣に位置する電極パッドＢＰおよび第４辺Ｓ４に沿って第７電極パッドＢ７の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷを含む場合もある。さらに、ベントＶＥ近傍に位置するボンディングワイヤＢＷとは、第３ワイヤＷ３および第７ワイヤＷ７に加えて、例えば図１に示した、第２領域Ａ２に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷを含む場合もある。   The bonding wire BW located in the vicinity of the vent VE is connected to each of the third electrode pad B3 and the seventh electrode pad B7 located closest to the second corner C2 of the semiconductor chip SC, for example, as shown in FIG. The third wire W3 and the seventh wire W7. Further, the bonding wire BW positioned in the vicinity of the vent VE is positioned next to the third electrode pad B3 along the second side S2 shown in FIG. 1, for example, in addition to the third wire W3 and the seventh wire W7. In some cases, it includes a plurality of bonding wires BW connected to each of the electrode pads BP and the electrode pads BP located next to the seventh electrode pad B7 along the fourth side S4. Further, the bonding wire BW located in the vicinity of the vent VE is connected to each of the plurality of electrode pads BP located in the second region A2 shown in FIG. 1, for example, in addition to the third wire W3 and the seventh wire W7. A plurality of bonding wires BW may be included.

このため、図１３（ａ）に示すように、モールド工程において、ゲートＧＡ近傍に位置するボンディングワイヤＢＷに、その下側から上側に向かう方向に荷重がかかることになる。   For this reason, as shown in FIG. 13A, in the molding process, a load is applied to the bonding wire BW located in the vicinity of the gate GA in the direction from the lower side to the upper side.

ゲートＧＡ近傍に位置するボンディングワイヤＢＷに、上記上向きの荷重がかかると、図１３（ｂ）に示すように、例えば信頼性試験、特に、温度サイクル試験において、樹脂の熱膨張や伸縮により、ボンディングワイヤＢＷのボール部ＢＷａと電極パッドＢＰとの接合部での引張力が大きくなり、ボンディングワイヤＢＷの電極パッドＢＰからの剥がれが生じやすくなる（第１の課題）。   When the upward load is applied to the bonding wire BW located in the vicinity of the gate GA, as shown in FIG. 13B, for example, in the reliability test, particularly in the temperature cycle test, the bonding is caused by the thermal expansion and expansion / contraction of the resin. The tensile force at the joint between the ball portion BWa of the wire BW and the electrode pad BP is increased, and the peeling of the bonding wire BW from the electrode pad BP is likely to occur (first problem).

また、図１４（ｂ）に示すように、モールド工程において、ベントＶＥ近傍に位置するボンディングワイヤＢＷに、その上側から下側に向かう方向に荷重がかかることになる。   Further, as shown in FIG. 14B, in the molding process, a load is applied to the bonding wire BW located near the vent VE in the direction from the upper side to the lower side.

ベントＶＥ近傍に位置するボンディングワイヤＢＷに、上記下向きの荷重がかかると、図１４（ｂ）に示すように、例えば信頼性試験、特に、温度サイクル試験において、ボンディングワイヤＢＷのボール部ＢＷａと芯部ＢＷｂとの接合部（ネック部）に応力が集中し、当該接合部（ネック部）の切断（せん断破壊、き裂）が生じやすくなる（第２の課題）。   When the downward load is applied to the bonding wire BW located in the vicinity of the vent VE, as shown in FIG. 14B, for example, in the reliability test, particularly in the temperature cycle test, the ball portion BWa and the core of the bonding wire BW Stress concentrates on the joint (neck part) with the part BWb, and the joint (neck part) is likely to be cut (shear fracture, crack) (second problem).

さらに、モールド工程においては、樹脂の流れに沿った方向にループ形状を有するボンディングワイヤＢＰは少なく、このため、複数のボンディングワイヤＢＷでは、ワイヤ流れの問題がある（第３の課題）。   Furthermore, in the molding process, there are few bonding wires BP having a loop shape in the direction along the resin flow, and therefore there is a problem of wire flow in the plurality of bonding wires BW (third problem).

本発明者が検討したところ、図１５に示すように、ゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷ以外のボンディングワイヤＢＷにおいて、ワイヤ流れが生じやすいことが明らかとなった。   As a result of examination by the present inventor, as shown in FIG. 15, it has been clarified that a wire flow is likely to occur in the bonding wires BW other than the bonding wires BW located near the gate GA and the vent VE.

ただし、ゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷ以外のボンディングワイヤＢＷは、ゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷと比べると、モールド工程において、上向きの荷重（図１３（ａ）参照）はかかりにくいので、ボンディングワイヤＢＷの剥がれは生じにくい。   However, the bonding wires BW other than the bonding wires BW positioned in the vicinity of the gate GA and the vicinity of the vent VE have an upward load in the molding process as compared with the bonding wires BW positioned in the vicinity of the gate GA and the vicinity of the vent VE, respectively. (See FIG. 13A), it is difficult to apply, so that the bonding wire BW does not easily peel off.

また、ゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷ以外のボンディングワイヤＢＷは、ゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷと比べると、モールド工程において、下向きの荷重（図１４（ａ）参照）はかかりにくいので、ボンディングワイヤＢＷの切断は生じにくい。   Further, the bonding wires BW other than the bonding wires BW located near the gate GA and the vent VE, respectively, have a downward load in the molding process as compared to the bonding wires BW located near the gate GA and the vent VE. (See FIG. 14 (a)), it is difficult to apply, so that the bonding wire BW is hardly cut.

現在、ボンディングワイヤＢＷの線径は、例えば１５μｍφ〜２０μｍφである。しかし、半導体装置の小型化および高密度化により、互いに隣り合う電極パッドＢＰの間隔の狭小化が急速に進んでいる。これに伴って、ボンディングワイヤＢＷの線径はさらに細くなっており、１０μｍφまたはそれ以下の線径のボンディングワイヤＢＷの要求も予想される。   Currently, the wire diameter of the bonding wire BW is, for example, 15 μmφ to 20 μmφ. However, as the size and density of semiconductor devices are reduced, the distance between adjacent electrode pads BP is rapidly decreasing. Accordingly, the wire diameter of the bonding wire BW is further reduced, and a demand for a bonding wire BW having a wire diameter of 10 μmφ or less is expected.

このように、ボンディングワイヤＢＷの線径が、１０μｍφまたはそれ以下になると、ボンディングワイヤＢＷの剥がれ（第１の課題）、ボンディングワイヤＢＷの切断（第２の課題）およびボンディングワイヤＢＷのワイヤ流れ（第３の課題）はさらに深刻となる。例えば信頼性試験、特に、温度サイクル試験においては、ボンディングワイヤＢＷの剥がれ（第１の課題）およびボンディングワイヤＢＷの切断（第２の課題）が回避できない恐れもある。   As described above, when the wire diameter of the bonding wire BW becomes 10 μmφ or less, peeling of the bonding wire BW (first problem), cutting of the bonding wire BW (second problem), and wire flow of the bonding wire BW ( The third problem) becomes even more serious. For example, in a reliability test, particularly a temperature cycle test, peeling of the bonding wire BW (first problem) and cutting of the bonding wire BW (second problem) may not be avoided.

図１６に、剥がれ（第１の課題）または切断（第２の課題）が生じやすいボンディングワイヤＢＷを示す。   FIG. 16 shows a bonding wire BW that is likely to be peeled off (first problem) or cut (second problem).

剥がれの問題を解決する必要があるボンディングワイヤＢＷは、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第５電極パッドＢ５、並びに第１辺Ｓ１に沿って第１電極パッドＢ１の隣に位置する電極パッドＢＰおよび第３辺Ｓ３に沿って第５電極パッドＢ５の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷである。さらに、剥がれの問題を解決する必要があるボンディングワイヤＢＷは、半導体チップＳＣの主面を、平面視において、第１仮想線ＩＬ１と第２仮想線ＩＬ２とで区分した場合、半導体チップＳＣの第１角部Ｃ１を含む第１領域Ａ１に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷを含む場合もある。   The bonding wire BW that needs to solve the peeling problem is the first electrode pad B1 and the fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC, and the first side S1 along the first side S1. A plurality of bonding wires BW connected to the electrode pad BP located next to the one electrode pad B1 and the electrode pad BP located next to the fifth electrode pad B5 along the third side S3. Further, the bonding wire BW that needs to solve the peeling problem is obtained when the main surface of the semiconductor chip SC is divided into the first imaginary line IL1 and the second imaginary line IL2 in plan view. There may be a case where a plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the first region A1 including the corner portion C1 are included.

また、切断の問題を解決する必要があるボンディングワイヤＢＷは、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第７電極パッドＢ７、並びに第２辺Ｓ２に沿って第３電極パッドＢ３の隣に位置する電極パッドＢＰおよび第４辺Ｓ４に沿って第７電極パッドＢ７の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷである。さらに、切断の問題を解決する必要があるボンディングワイヤＢＷは、半導体チップＳＣの主面を、平面視において、第１仮想線ＩＬ１と第２仮想線ＩＬ２とで区分した場合、半導体チップＳＣの第２角部Ｃ２を含む第２領域Ａ２に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷを含む場合もある。   In addition, the bonding wire BW that needs to solve the cutting problem is along the third electrode pad B3 and the seventh electrode pad B7 located closest to the second corner portion C2 of the semiconductor chip SC, and the second side S2. A plurality of bonding wires BW connected to the electrode pad BP located next to the third electrode pad B3 and the electrode pad BP located next to the seventh electrode pad B7 along the fourth side S4. Further, the bonding wire BW that needs to solve the cutting problem is obtained when the main surface of the semiconductor chip SC is divided into the first virtual line IL1 and the second virtual line IL2 in a plan view, and the first surface of the semiconductor chip SC. There may be a case where a plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the second region A2 including the corner portion C2 are included.

図１７に、剥がれ（第１の課題）および切断（第２の課題）が最も生じやすいボンディングワイヤＢＷを示す。   FIG. 17 shows a bonding wire BW that is most likely to be peeled (first problem) and cut (second problem).

剥がれの問題を解決する必要があるボンディングワイヤＢＷは、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第５電極パッドＢ５のそれぞれに接続される複数のボンディングワイヤＢＷである。   The bonding wire BW that needs to solve the peeling problem is a plurality of bonding wires connected to each of the first electrode pad B1 and the fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC. BW.

また、切断の問題を解決する必要があるボンディングワイヤＢＷは、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第７電極パッドＢ７のそれぞれに接続される複数のボンディングワイヤＢＷである。   In addition, the bonding wire BW that needs to solve the cutting problem has a plurality of electrodes connected to the third electrode pad B3 and the seventh electrode pad B7 that are located closest to the second corner C2 of the semiconductor chip SC. It is a bonding wire BW.

≪本実施の形態による半導体装置の特徴および効果≫
本実施の形態による半導体装置では、例えば図１に示したように、モールド工程においてゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷは、半導体チップＳＣの内側に向かって大きく迂回しており、半導体チップＳＣの内側方向に倒れるループ形状（以下、内倒れループ形状という場合もある。）を有している。すなわち、モールド工程においてゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷは、引っ張る力（張力）が弱く、余裕をもって緩やかに張られている。 << Characteristics and Effects of Semiconductor Device According to this Embodiment >>
In the semiconductor device according to the present embodiment, for example, as shown in FIG. 1, in the molding process, the bonding wires BW positioned in the vicinity of the gate GA and the vicinity of the vent VE largely detour toward the inside of the semiconductor chip SC. And has a loop shape that falls inwardly of the semiconductor chip SC (hereinafter also referred to as an inwardly fallen loop shape). That is, in the molding process, the bonding wires BW located in the vicinity of the gate GA and the vicinity of the vent VE have a weak pulling force (tension) and are gently stretched with a margin.

これに対して、モールド工程においてゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷ以外のボンディングワイヤＢＷは、半導体チップＳＣの内側に向かって迂回しておらず、半導体チップＳＣの内側方向に倒れないループ形状を有している。すなわち、モールド工程においてゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷ以外のボンディングワイヤＢＷは、引っ張る力（張力）が強く、ピンと張られている。   On the other hand, the bonding wires BW other than the bonding wires BW positioned in the vicinity of the gate GA and the vicinity of the vent VE in the molding process are not detoured toward the inner side of the semiconductor chip SC, and the inner direction of the semiconductor chip SC. It has a loop shape that does not fall over. That is, in the molding process, the bonding wires BW other than the bonding wires BW positioned in the vicinity of the gate GA and the vicinity of the vent VE have a strong pulling force (tension) and are tightly pinched.

ここで、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第５電極パッドＢ５のそれぞれに接続される第１ワイヤＷ１および第５ワイヤＷ５である。または、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、第１ワイヤＷ１および第５ワイヤＷ５に加えて、第１辺Ｓ１に沿って第１電極パッドＢ１の隣に位置する電極パッドＢＰに接続されるボンディングワイヤＢＷおよび第３辺Ｓ３に沿って第５電極パッドＢ５の隣に位置する電極パッドＢＰに接続されるボンディングワイヤＢＷである。または、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、半導体チップＳＣの主面を第１仮想線ＩＬ１と第２仮想線ＩＬ２とで区分した場合、半導体チップＳＣの第１角部Ｃ１を含む第１領域Ａ１に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷである。   Here, the bonding wire BW located in the vicinity of the gate GA in the molding step is connected to each of the first electrode pad B1 and the fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC. The first wire W1 and the fifth wire W5. Alternatively, the bonding wire BW positioned in the vicinity of the gate GA in the molding step is the electrode pad BP positioned next to the first electrode pad B1 along the first side S1 in addition to the first wire W1 and the fifth wire W5. A bonding wire BW connected to the electrode pad BP located adjacent to the fifth electrode pad B5 along the third side S3. Alternatively, the bonding wire BW positioned in the vicinity of the gate GA in the molding step is the first corner C1 of the semiconductor chip SC when the main surface of the semiconductor chip SC is divided by the first virtual line IL1 and the second virtual line IL2. Are a plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the first region A1.

また、モールド工程においてベントＶＥ近傍に位置するボンディングワイヤＢＷとは、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第７電極パッドＢ７のそれぞれに接続される第３ワイヤＷ３および第７ワイヤＷ７である。または、モールド工程においてベントＶＥ近傍に位置するボンディングワイヤＢＷとは、第３ワイヤＷ３および第７ワイヤＷ７に加えて、第２辺Ｓ２に沿って第３電極パッドＢ３の隣に位置する電極パッドＢＰに接続されるボンディングワイヤＢＷおよび第４辺Ｓ４に沿って第７電極パッドＢ７の隣に位置する電極パッドＢＰに接続されるボンディングワイヤＢＷである。または、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、半導体チップＳＣの主面を第１仮想線ＩＬ１と第２仮想線ＩＬ２とで区分した場合、半導体チップＳＣの第２角部Ｃ２を含む第２領域Ａ２に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷである。   Further, the bonding wire BW positioned in the vicinity of the vent VE in the molding process is connected to the third electrode pad B3 and the seventh electrode pad B7 that are positioned closest to the second corner C2 of the semiconductor chip SC. Three wires W3 and a seventh wire W7. Alternatively, the bonding wire BW located in the vicinity of the vent VE in the molding step is an electrode pad BP located next to the third electrode pad B3 along the second side S2 in addition to the third wire W3 and the seventh wire W7. Are the bonding wire BW connected to the electrode pad BP located next to the seventh electrode pad B7 along the fourth side S4. Alternatively, the bonding wire BW positioned in the vicinity of the gate GA in the molding process is the second corner C2 of the semiconductor chip SC when the main surface of the semiconductor chip SC is divided by the first virtual line IL1 and the second virtual line IL2. Are a plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the second region A2 including.

前述したように、半導体装置の製造工程の一つであるモールド工程においては、ゲートＧＡ近傍に位置するボンディングワイヤＢＷに、その下側から上側に向かう方向に荷重がかかる（図１３（ａ）参照）。このため、例えば信頼性試験、特に、温度サイクル試験における樹脂の熱膨張や収縮により、上記上向きの荷重が起因となって、モールド工程においてゲートＧＡ近傍に位置したボンディングワイヤＢＷのボール部ＢＷａと電極パッドＢＰとの接合部における引張力が大きくなる。その結果、ボンディングワイヤＢＷは電極パッドＢＰから剥がれやすくなる（第１の課題）。   As described above, in the molding process which is one of the manufacturing processes of the semiconductor device, a load is applied to the bonding wire BW located near the gate GA in the direction from the lower side to the upper side (see FIG. 13A). ). For this reason, for example, due to the thermal expansion and contraction of the resin in the reliability test, particularly in the temperature cycle test, the upward load causes the ball part BWa and the electrode of the bonding wire BW located in the vicinity of the gate GA in the molding process. The tensile force at the joint with the pad BP increases. As a result, the bonding wire BW is easily peeled off from the electrode pad BP (first problem).

しかし、本実施の形態では、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷを内倒れループ形状としている。すなわち、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷは、引っ張る力（張力）が弱く、余裕をもって緩やかに張られている。従って、モールド工程において、ゲートＧＡ近傍に位置するボンディングワイヤＢＷに上向きの荷重がかかっても、例えば信頼性試験、特に、温度サイクル試験において生じる、ゲートＧＡ近傍に位置したボンディングワイヤＢＷのボール部ＢＷａと電極パッドＢＰとの接合部における引張力は小さいので、ボンディングワイヤＢＷは電極パッドＢＰから剥がれにくくなる（第１の課題の解決）。   However, in the present embodiment, the bonding wire BW located in the vicinity of the gate GA in the molding process has an inwardly falling loop shape. That is, in the molding process, the bonding wire BW located in the vicinity of the gate GA has a weak pulling force (tension) and is gently stretched with a margin. Therefore, even if an upward load is applied to the bonding wire BW located in the vicinity of the gate GA in the molding process, the ball portion BWa of the bonding wire BW located in the vicinity of the gate GA, which occurs in, for example, a reliability test, particularly a temperature cycle test. Since the tensile force at the joint between the electrode pad BP and the electrode pad BP is small, the bonding wire BW is difficult to peel off from the electrode pad BP (solution of the first problem).

また、前述したように、半導体装置の製造工程の一つであるモールド工程においては、ベントＶＥ近傍に位置するボンディングワイヤＢＷに、その上側から下側に向かう方向に荷重がかかる（図１４（ａ）参照）。このため、例えば信頼性試験、特に、温度サイクル試験における樹脂の熱膨張や収縮により、上記下向きの荷重が起因となって、モールド工程においてベントＶＥ近傍に位置したボンディングワイヤＢＷのボール部ＢＷａと芯部ＢＷｂとの接合部（ネック部）は切断しやすくなる（第２の課題）。   Further, as described above, in the molding process which is one of the manufacturing processes of the semiconductor device, a load is applied to the bonding wire BW located in the vicinity of the vent VE in the direction from the upper side to the lower side (FIG. 14A )reference). For this reason, for example, due to the thermal expansion and contraction of the resin in the reliability test, in particular, the temperature cycle test, the downward load causes the ball portion BWa and the core of the bonding wire BW located near the vent VE in the molding process. The joint portion (neck portion) with the portion BWb is easily cut (second problem).

しかし、本実施の形態では、モールド工程においてベントＶＥ近傍に位置するボンディングワイヤＢＷを内倒れループ形成としている。すなわち、モールド工程においてベントＶＥ近傍に位置するボンディングワイヤＢＷは、引っ張る力（張力）が弱く、余裕をもって緩やかに張られている。従って、モールド工程において、ベントＶＥ近傍に位置するボンディングワイヤＢＷに下向きの荷重がかかっても、例えば信頼性試験、特に、温度サイクル試験において生じる、ベントＶＥ近傍に位置したボンディングワイヤＢＷのボール部ＢＷａと芯部ＢＷｂとの接合部（ネック部）には応力が集中しないので、ボンディングワイヤＢＷは切断しにくくなる（第２の課題の解決）。   However, in the present embodiment, the bonding wire BW located in the vicinity of the vent VE in the molding process is formed inwardly to form a loop. That is, the bonding wire BW located in the vicinity of the vent VE in the molding process has a weak pulling force (tension) and is gently stretched with a margin. Therefore, even if a downward load is applied to the bonding wire BW located in the vicinity of the vent VE in the molding step, the ball portion BWa of the bonding wire BW located in the vicinity of the vent VE, which occurs in, for example, a reliability test, particularly a temperature cycle test, Since stress does not concentrate on the joint (neck portion) between the core portion BWb and the core portion BWb, the bonding wire BW is difficult to cut (solution of the second problem).

また、前述したように、半導体装置の製造工程の一つであるモールド工程においては、樹脂の流れに起因するワイヤ流れの問題がある。ワイヤ流れが生じやすいボンディングワイヤＢＷとは、モールド工程においてゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷ以外のボンディングワイヤＢＷである。または、ワイヤ流れが生じやすいボンディングワイヤＢＷとは、半導体チップＳＣの主面を第１仮想線ＩＬ１と第２仮想線ＩＬ２とで区分した場合、半導体チップＳＣの第３角部Ｃ２を含む第３領域Ａ３および半導体チップＳＣの第４角部Ｃ４を含む第４領域Ａ４のそれぞれに位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷである（第３の課題）。   Further, as described above, in the molding process, which is one of the semiconductor device manufacturing processes, there is a problem of wire flow due to the flow of resin. The bonding wire BW in which a wire flow is likely to occur is a bonding wire BW other than the bonding wire BW located in the vicinity of the gate GA and the vicinity of the vent VE in the molding process. Alternatively, the bonding wire BW in which the wire flow is likely to occur is the third including the third corner portion C2 of the semiconductor chip SC when the main surface of the semiconductor chip SC is divided by the first virtual line IL1 and the second virtual line IL2. A plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in each of the region A3 and the fourth region A4 including the fourth corner C4 of the semiconductor chip SC (third problem).

しかし、本実施の形態では、モールド工程においてゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷ以外のボンディングワイヤＢＷは、引っ張る力（張力）が強く、ピンと張られている。または、半導体チップＳＣの第３角部Ｃ２を含む第３領域Ａ３および半導体チップＳＣの第４角部Ｃ４を含む第４領域Ａ４のそれぞれに位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷは、引っ張る力（張力）が強く、ピンと張られている。その結果、樹脂の流れに起因するボンディングワイヤＢＷのワイヤ流れの問題を回避することができる（第３の課題の解決）。   However, in the present embodiment, the bonding wires BW other than the bonding wires BW located in the vicinity of the gate GA and the vent VE in the molding process have a strong pulling force (tension) and are stretched. Alternatively, a plurality of electrode pads BP connected to each of the plurality of electrode pads BP located in each of the third region A3 including the third corner portion C2 of the semiconductor chip SC and the fourth region A4 including the fourth corner portion C4 of the semiconductor chip SC. The bonding wire BW has a strong pulling force (tension) and is tightly pinched. As a result, the wire flow problem of the bonding wire BW due to the resin flow can be avoided (solution of the third problem).

このように、本実施の形態によれば、ボンディングワイヤＢＷの剥がれ（第１の課題）、ボンディングワイヤＢＷの切断（第２の課題）およびボンディングワイヤＢＷのワイヤ流れ（第３の課題）を回避することができる。これにより、半導体装置の小型化および低コスト化を実現する手段として、ボンディングワイヤの線径を細くしても、信頼性の高い半導体装置を実現することができる。   Thus, according to the present embodiment, peeling of the bonding wire BW (first problem), cutting of the bonding wire BW (second problem), and wire flow of the bonding wire BW (third problem) are avoided. can do. Thereby, as a means for realizing miniaturization and cost reduction of the semiconductor device, a highly reliable semiconductor device can be realized even if the wire diameter of the bonding wire is reduced.

なお、本実施の形態では、半導体装置の製造工程の一つであるモールド工程では、キャビディＣＶａ、ＣＶｂ内に樹脂を流入する際の入り口となるゲートＧＡが、下金型ＭＤａおよび上金型ＭＤｂに形成された成形金型を用いた（図１２参照）。すなわち、リードフレームＬＦの上面側に位置する上ゲートとリードフレームＬＦの下面側に位置する下ゲートから、樹脂がキャビティＣＶａ、ＣＶｂ内に流し込まれる。しかし、本実施の形態は、これに限定されるものではなく、キャビディＣＶａ、ＣＶｂ内に樹脂を流入する際の入り口となるゲートＧＡが、下金型ＭＤａのみに形成された成形金型を用いたモールド工程にも適用することができる。すなわち、リードフレームＬＦの下面側に位置する下ゲートのみから、樹脂がキャビティＣＶａ、ＣＶｂ内に流し込まれた場合も、ゲートＧＡ近傍に位置するボンディングワイヤＢＷに、その下側から上側に向かう方向に荷重がかかり、ボール部ＢＷａは、電極パッドＢＰから剥がれやすくなる（第１の課題）。従って、下ゲートのみを備えた成形金型を用いたモールド工程において、半導体装置を製造する場合においても、本実施の形態によるボンディングワイヤＢＷのループ形状を適用することは有効である。   In the present embodiment, in the molding process, which is one of the semiconductor device manufacturing processes, the gate GA serving as an entrance when the resin flows into the cavities CVa and CVb is used as the lower mold MDa and the upper mold MDb. The molding die formed in (1) was used (see FIG. 12). That is, resin is poured into the cavities CVa and CVb from the upper gate located on the upper surface side of the lead frame LF and the lower gate located on the lower surface side of the lead frame LF. However, the present embodiment is not limited to this, and a molding die in which the gate GA serving as an entrance when the resin flows into the Cavidies CVa and CVb is formed only in the lower die MDa is used. It can also be applied to the molding process. That is, even when resin is poured into the cavities CVa and CVb from only the lower gate located on the lower surface side of the lead frame LF, the bonding wire BW located near the gate GA is directed in the direction from the lower side to the upper side. A load is applied, and the ball part BWa is easily peeled off from the electrode pad BP (first problem). Therefore, it is effective to apply the loop shape of the bonding wire BW according to the present embodiment even when a semiconductor device is manufactured in a molding process using a molding die having only a lower gate.

≪変形例≫
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。 ≪Modification≫
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

＜変形例１＞
本実施の形態の変形例１による半導体装置について、図１８を用いて説明する。 <Modification 1>
A semiconductor device according to the first modification of the present embodiment will be described with reference to FIG.

図１８は、本実施の形態の変形例１による半導体装置の上面図である。   FIG. 18 is a top view of a semiconductor device according to Modification 1 of the present embodiment.

なお、変形例１による半導体装置ＳＭ１と前述の実施の形態による半導体装置ＳＭとの相違点は、ボンディングワイヤの線径およびループ形状である。その他の構成は、両者においてほぼ同様である。以下、相違点を中心に説明する。   The difference between the semiconductor device SM1 according to the modification 1 and the semiconductor device SM according to the above-described embodiment is the wire diameter and loop shape of the bonding wire. Other configurations are almost the same in both cases. Hereinafter, the difference will be mainly described.

図１８に示すように、変形例１による半導体装置ＳＭ１では、全てのボンディングワイヤＢＷは、半導体チップＳＣの内側に向かって迂回しておらず、引っ張る力（張力）が強く、ピンと張られている。   As shown in FIG. 18, in the semiconductor device SM1 according to the first modification, all the bonding wires BW are not detoured toward the inside of the semiconductor chip SC, and the pulling force (tension) is strong, and the pins are stretched. .

しかし、変形例１による半導体装置ＳＭ１では、複数のボンディングワイヤのうち、モールド工程においてゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置するボンディングワイヤＢＷの線径が、他部のボンディングワイヤＢＷの線径よりも太く、例えば２０μｍφよりも太い。   However, in the semiconductor device SM1 according to the first modification, among the plurality of bonding wires, the wire diameters of the bonding wires BW positioned in the vicinity of the gate GA and the vent VE in the molding process are the same as those of the other bonding wires BW. Thicker than 20 μmφ, for example.

ここで、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第５電極パッドＢ５のそれぞれに接続される第１ワイヤＷ１および第５ワイヤＷ５である。または、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、第１ワイヤＷ１および第５ワイヤＷ５に加えて、第１辺Ｓ１に沿って第１電極パッドＢ１の隣に位置する電極パッドＢＰに接続されるボンディングワイヤＢＷおよび第３辺Ｓ３に沿って第５電極パッドＢ５の隣に位置する電極パッドＢＰに接続されるボンディングワイヤＢＷである。または、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、半導体チップＳＣの主面を第１仮想線ＩＬ１と第２仮想線ＩＬ２とで区分した場合、半導体チップＳＣの第１角部Ｃ１を含む第１領域Ａ１に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷである。   Here, the bonding wire BW located in the vicinity of the gate GA in the molding step is connected to each of the first electrode pad B1 and the fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC. The first wire W1 and the fifth wire W5. Alternatively, the bonding wire BW positioned in the vicinity of the gate GA in the molding step is the electrode pad BP positioned next to the first electrode pad B1 along the first side S1 in addition to the first wire W1 and the fifth wire W5. A bonding wire BW connected to the electrode pad BP located adjacent to the fifth electrode pad B5 along the third side S3. Alternatively, the bonding wire BW positioned in the vicinity of the gate GA in the molding step is the first corner C1 of the semiconductor chip SC when the main surface of the semiconductor chip SC is divided by the first virtual line IL1 and the second virtual line IL2. Are a plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the first region A1.

また、モールド工程においてベントＶＥ近傍に位置するボンディングワイヤＢＷとは、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第７電極パッドＢ７のそれぞれに接続される第３ワイヤＷ３および第７ワイヤＷ７である。または、モールド工程においてベントＶＥ近傍に位置するボンディングワイヤＢＷとは、第３ワイヤＷ３および第７ワイヤＷ７に加えて、第２辺Ｓ２に沿って第３電極パッドＢ３の隣に位置する電極パッドＢＰに接続されるボンディングワイヤＢＷおよび第４辺Ｓ４に沿って第７電極パッドＢ７の隣に位置する電極パッドＢＰに接続されるボンディングワイヤＢＷである。または、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷとは、半導体チップＳＣの主面を第１仮想線ＩＬ１と第２仮想線ＩＬ２とで区分した場合、半導体チップＳＣの第２角部Ｃ２を含む第２領域Ａ２に位置する複数の電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷである。   Further, the bonding wire BW positioned in the vicinity of the vent VE in the molding process is connected to the third electrode pad B3 and the seventh electrode pad B7 that are positioned closest to the second corner C2 of the semiconductor chip SC. Three wires W3 and a seventh wire W7. Alternatively, the bonding wire BW located in the vicinity of the vent VE in the molding step is an electrode pad BP located next to the third electrode pad B3 along the second side S2 in addition to the third wire W3 and the seventh wire W7. Are the bonding wire BW connected to the electrode pad BP located next to the seventh electrode pad B7 along the fourth side S4. Alternatively, the bonding wire BW positioned in the vicinity of the gate GA in the molding process is the second corner C2 of the semiconductor chip SC when the main surface of the semiconductor chip SC is divided by the first virtual line IL1 and the second virtual line IL2. Are a plurality of bonding wires BW connected to each of the plurality of electrode pads BP located in the second region A2 including.

このように、変形例１によれば、モールド工程においてゲートＧＡ近傍に位置するボンディングワイヤＢＷの線径を太くしたことにより、モールド工程において、ゲートＧＡ近傍に位置するボンディングワイヤＢＷにかかる上向きの荷重が低減される。従って、例えば信頼性試験、特に、温度サイクル試験において、樹脂の熱膨張や収縮が起きても、モールド工程においてゲートＧＡ近傍に位置したボンディングワイヤＢＷのボール部ＢＷａと電極パッドＢＰとの接合部における引張力は小さいので、ボンディングワイヤＷＢは電極パッドＢＰから剥がれにくくなる（第１の課題の解決）。   As described above, according to the first modification, by increasing the diameter of the bonding wire BW located in the vicinity of the gate GA in the molding process, the upward load applied to the bonding wire BW located in the vicinity of the gate GA in the molding process. Is reduced. Therefore, for example, in the reliability test, particularly in the temperature cycle test, even if the resin thermally expands or contracts, the bonding portion between the ball portion BWa of the bonding wire BW and the electrode pad BP located near the gate GA in the molding process. Since the tensile force is small, the bonding wire WB is hardly peeled off from the electrode pad BP (solution of the first problem).

また、変形例１によれば、モールド工程においてベントＶＥ近傍に位置するボンディングワイヤＢＷの線径を太くしたことにより、モールド工程においてベントＶＥ近傍に位置するボンディングワイヤＢＷにかかる下向きの荷重が低減される。従って、例えば信頼性試験、特に、温度サイクル試験において、樹脂の熱膨張や収縮が起きても、モールド工程においてベントＶＥ近傍に位置したボンディングワイヤＢＷのボール部ＢＷａと芯部ＢＷｂとの接合部（ネック部）には応力が集中しないので、ボンディングワイヤＢＷは切断しにくくなる（第２の課題の解決）。   Further, according to the first modification, the downward load applied to the bonding wire BW located near the vent VE in the molding process is reduced by increasing the diameter of the bonding wire BW located near the vent VE in the molding process. The Therefore, for example, in the reliability test, particularly in the temperature cycle test, even when the resin thermally expands or contracts, the bonding portion (the ball portion BWb and the core portion BWb of the bonding wire BW positioned in the vicinity of the vent VE in the molding process) Since stress is not concentrated on the neck portion, the bonding wire BW is difficult to cut (solution of the second problem).

また、変形例１によれば、全てのボンディングワイヤＢＷは、引っ張る力（張力）が強く、ピンと張られているので、樹脂の流れに起因するワイヤ流れの問題を回避することができる（第３の課題の解決）。   Moreover, according to the modification 1, since all the bonding wires BW have a strong pulling force (tension) and are tightly pinned, it is possible to avoid the problem of wire flow caused by the flow of resin (third). Solution of the problem).

＜変形例２＞
本実施の形態の変形例２による半導体装置について、図１９を用いて説明する。 <Modification 2>
A semiconductor device according to Modification 2 of the present embodiment will be described with reference to FIG.

図１９は、本実施の形態の変形例２による半導体装置の上面図である。   FIG. 19 is a top view of a semiconductor device according to the second modification of the present embodiment.

なお、変形例２による半導体装置ＳＭ２と前述の実施の形態による半導体装置ＳＭとの相違点は、ボンディングワイヤのループ形状である。その他の構成は、両者においてほぼ同様である。以下、相違点を中心に説明する。   The difference between the semiconductor device SM2 according to the modification 2 and the semiconductor device SM according to the above-described embodiment is the bonding wire loop shape. Other configurations are almost the same in both cases. Hereinafter, the difference will be mainly described.

図１９に示すように、変形例２による半導体装置ＳＭ２では、全てのボンディングワイヤＢＷは、半導体チップＳＣの内側に向かって迂回しており、引っ張る力（張力）が弱く、余裕をもって緩やかに張られている。   As shown in FIG. 19, in the semiconductor device SM2 according to the second modification, all the bonding wires BW are detoured toward the inside of the semiconductor chip SC, and the pulling force (tension) is weak and is gently stretched with a margin. ing.

半導体装置ＳＭ２の製造工程の一つであるモールド工程において、前述の実施の形態における樹脂の充填圧が低い場合は、全てのボンディングワイヤＢＷを、引っ張る力（張力）が弱く、余裕をもって緩やかに張ることもできる。   In the molding process, which is one of the manufacturing processes of the semiconductor device SM2, when the resin filling pressure in the above-described embodiment is low, the pulling force (tension) of all the bonding wires BW is weak and gently stretched with a margin. You can also.

これにより、例えば信頼性試験、特に、温度サイクル試験において、樹脂の熱膨張や収縮が起きても、モールド工程においてゲートＧＡ近傍に位置したボンディングワイヤＢＷのボール部ＢＷａと電極パッドＢＰとの接合部における引張力は小さいので、ボンディングワイヤＢＷは電極パッドＢＰから剥がれにくくなる（第１の課題の解決）。   Thereby, for example, in the reliability test, particularly in the temperature cycle test, even if the resin thermally expands or contracts, the bonding portion between the ball portion BWa of the bonding wire BW and the electrode pad BP located in the vicinity of the gate GA in the molding process Since the tensile force at is small, the bonding wire BW is difficult to peel off from the electrode pad BP (solution of the first problem).

また、例えば信頼性試験、特に、温度サイクル試験において、樹脂の熱膨張や収縮が起きても、モールド工程においてベントＶＥ近傍に位置したボンディングワイヤＢＷのボール部ＢＷａと芯部ＢＷｂとの接合部（ネック部）には応力が集中しないので、ボンディングワイヤＢＷは切断しにくくなる（第２の課題の解決）
また、樹脂の充填圧が低い場合には、ボンディングワイヤＢＷの長さが長くても、樹脂の流れに起因するワイヤ流れの問題を回避することが可能となる（第３の課題の解決）。 Further, for example, in the reliability test, in particular, in the temperature cycle test, even if the resin undergoes thermal expansion or contraction, the bonding portion (the ball portion BWa and the core portion BWb of the bonding wire BW positioned near the vent VE in the molding process) Since the stress is not concentrated on the neck portion, the bonding wire BW is difficult to cut (solution of the second problem).
Further, when the filling pressure of the resin is low, it is possible to avoid the problem of the wire flow caused by the resin flow even if the length of the bonding wire BW is long (solution of the third problem).

ただし、モールド工程において、キャビディ内への樹脂の充填を完了するまでの時間が長くなり、初期に流し込んだ樹脂が固まる虞がある。   However, in the molding process, it takes a long time to complete the filling of the resin into the cavity, and there is a possibility that the resin poured in the initial stage may be hardened.

＜変形例３＞
本実施の形態の変形例３による半導体装置について、図２０を用いて説明する。 <Modification 3>
A semiconductor device according to Modification 3 of the present embodiment will be described with reference to FIG.

図２０は、本実施の形態の変形例３による半導体装置の断面図である。   FIG. 20 is a cross-sectional view of a semiconductor device according to Modification 3 of the present embodiment.

前述の実施の形態による半導体装置ＳＭは、封止体ＲＥの底面からダイパッドＤＰの下面が露出した、所謂、タブ露出型の半導体装置であるが、変形例３による半導体装置ＳＭ３は、封止体ＲＥの底面からダイパッドの下面が露出しない、所謂、タブ内蔵型の半導体装置である。   The semiconductor device SM according to the above-described embodiment is a so-called tab-exposed semiconductor device in which the lower surface of the die pad DP is exposed from the bottom surface of the sealing body RE. However, the semiconductor device SM3 according to Modification 3 is a sealing body. This is a so-called tab-embedded semiconductor device in which the bottom surface of the die pad is not exposed from the bottom surface of the RE.

なお、その他の構成は、両者においてほぼ同様である。すなわち、モールド工程においてゲートＧＡ近傍およびベントＶＥ近傍のそれぞれに位置する複数のボンディングワイヤＢＷは、前述の実施の形態と同様に、半導体チップＳＣの内側に向かって迂回しており、引っ張る力（張力）が弱く、余裕をもって緩やかに張られている。以下、相違点を中心に説明する。   Other configurations are almost the same in both cases. That is, in the molding process, the plurality of bonding wires BW positioned in the vicinity of the gate GA and the vicinity of the vent VE are detoured toward the inside of the semiconductor chip SC as in the above-described embodiment, and the pulling force (tension) ) Is weak and is stretched gently with a margin. Hereinafter, the difference will be mainly described.

タブ内蔵型の半導体装置ＳＭ３では、タブ露出型の半導体装置ＳＭと比べて、半導体装置ＳＭ３の製造工程の一つであるモールド工程において、ゲート近傍に位置するボンディングワイヤＢＷに、その下側から上側に向かう方向に荷重がかかりにくくなる。従って、タブ内蔵型の半導体装置ＳＭ３では、タブ露出型の半導体装置ＳＭと比べて、例えば信頼性試験、特に、温度サイクル試験において、樹脂の熱膨張や収縮が起きても、モールド工程においてゲート近傍に位置したボンディングワイヤＢＷは電極パッドＢＰから剥がれにくい。   In the tab-embedded semiconductor device SM3, compared to the tab-exposed semiconductor device SM, the bonding wire BW located in the vicinity of the gate is connected from the lower side to the upper side in the molding process which is one of the manufacturing processes of the semiconductor device SM3. It becomes difficult to apply a load in the direction toward Therefore, in the semiconductor device SM3 with a built-in tab, compared with the tab-exposed semiconductor device SM, even in the reliability test, particularly in the temperature cycle test, even if the resin thermal expansion or contraction occurs, The bonding wire BW located at the position is hardly peeled off from the electrode pad BP.

また、タブ内蔵型の半導体装置ＳＭ３では、タブ露出型の半導体装置ＳＭと比べて、半導体装置ＳＭ３の製造工程の一つであるモールド工程において、ベント近傍に位置するボンディングワイヤＢＷに、その上側から下側に向かう方向に荷重がかかりにくくなる。従って、タブ内蔵型の半導体装置ＳＭ３では、タブ露出型の半導体装置ＳＭと比べて、例えば信頼性試験、特に、温度サイクル試験において、樹脂の熱膨張や収縮が起きても、モールド工程においてベント近傍に位置したボンディングワイヤＢＷのボール部と芯部との接合部（ネック部）には応力が集中しないので、ボンディングワイヤＢＷは切断しにくい。   Further, in the semiconductor device SM3 with a built-in tab, compared to the tab-exposed semiconductor device SM, the bonding wire BW located near the vent is connected to the bonding wire BW from the upper side in the molding process which is one of the manufacturing processes of the semiconductor device SM3. The load is less likely to be applied in the downward direction. Therefore, in the semiconductor device SM3 with a built-in tab, compared with the tab-exposed semiconductor device SM, for example, in the reliability test, in particular, in the temperature cycle test, even if resin thermal expansion or contraction occurs, Since the stress is not concentrated on the joint portion (neck portion) between the ball portion and the core portion of the bonding wire BW located at the position, the bonding wire BW is difficult to cut.

このように、タブ内蔵型の半導体装置ＳＭ３は、タブ露出型の半導体装置ＳＭと比べて、ボンディングワイヤＢＷの剥がれ（第１課題）およびボンディングワイヤＢＷの切断（第２課題）は生じにくい。しかし、モールド工程においてゲート近傍およびベント近傍のそれぞれに位置する複数のボンディングワイヤＢＷを、余裕を持って緩やかに張ることにより、ボンディングワイヤＢＷの剥がれ（第１の課題）、ボンディングワイヤＢＷの切断（第２の課題）はさらに生じにくくなる。   As described above, the tab-embedded semiconductor device SM3 is less susceptible to peeling of the bonding wire BW (first problem) and cutting of the bonding wire BW (second problem) than the tab-exposed semiconductor device SM. However, the bonding wire BW is peeled off (first problem) by cutting the bonding wire BW (first problem) by gently stretching the bonding wires BW located near the gate and the vent in the molding process with a margin. The second problem is less likely to occur.

ただし、モールド工程においてゲート近傍およびベント近傍のそれぞれに位置する複数のボンディングワイヤＢＷが無駄に長くなると、ワイヤ流れが生じる虞がある。そこで、タブ内蔵型の半導体装置ＳＭ３では、例えば半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第５電極パッドＢ５のそれぞれに接続される第１ワイヤＷ１および第５ワイヤＷ５を、余裕を持って緩やかに張ることが望ましい（図１参照）。さらに、タブ内蔵型の半導体装置ＳＭ３では、例えば半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第７電極パッドＢ７のそれぞれに接続される第３ワイヤＷ３および第７ワイヤＷ７を、余裕を持って緩やかに張ることが望ましい（図１参照）。すなわち、第１ワイヤＷ１、第５ワイヤＷ５、第３ワイヤＷ３および第７ワイヤＷ７のみを、余裕を持って緩やかに張ることにより、他のワイヤボンディングＢＷのワイヤ流れを防止することができる。   However, if a plurality of bonding wires BW located in the vicinity of the gate and the vent in the molding process become unnecessarily long, there is a possibility that a wire flow may occur. Therefore, in the semiconductor device SM3 with a built-in tab, for example, the first wire W1 and the first wire W1 connected to the first electrode pad B1 and the fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC, respectively. It is desirable that the five wires W5 be gently stretched with a margin (see FIG. 1). Further, in the tab-embedded semiconductor device SM3, for example, the third wire W3 and the third wire W3 connected to the third electrode pad B3 and the seventh electrode pad B7 located closest to the second corner C2 of the semiconductor chip SC, respectively. It is desirable to stretch the 7 wires W7 gently with a margin (see FIG. 1). That is, only the first wire W1, the fifth wire W5, the third wire W3, and the seventh wire W7 are gently stretched with a margin, so that the wire flow of the other wire bonding BW can be prevented.

＜変形例４＞
本実施の形態の変形例４による半導体装置について、図２１を用いて説明する。 <Modification 4>
A semiconductor device according to Modification 4 of the present embodiment will be described with reference to FIG.

図２１は、本実施の形態の変形例４による半導体装置の上面図である。   FIG. 21 is a top view of a semiconductor device according to Modification 4 of the present embodiment.

なお、変形例４による半導体装置ＳＭ４と前述の実施の形態による半導体装置ＳＭとの相違点は、半導体チップの主面に形成される電極パッドの配置である。その他の構成は、両者においてほぼ同様である。以下、相違点を中心に説明する。   The difference between the semiconductor device SM4 according to the modification 4 and the semiconductor device SM according to the above-described embodiment is the arrangement of electrode pads formed on the main surface of the semiconductor chip. Other configurations are almost the same in both cases. Hereinafter, the difference will be mainly described.

図２１に示すように、第１パッド群Ｇ１に含まれる複数の電極パッドＢＰは、前述の実施の形態で説明した複数の電極パッドＢＰのピッチと同じ、例えば第１ピッチで配置されている。そして、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第１辺Ｓ１に沿って第１電極パッドＢ１の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷは、内倒れループ形状を有している。   As shown in FIG. 21, the plurality of electrode pads BP included in the first pad group G1 are arranged at the same pitch as, for example, the first pitch of the plurality of electrode pads BP described in the above embodiment. A plurality of electrodes connected to the first electrode pad B1 located closest to the first corner C1 of the semiconductor chip SC and the electrode pad BP located next to the first electrode pad B1 along the first side S1. The bonding wire BW has an inwardly falling loop shape.

また、第２パッド群Ｇ２に含まれる複数の電極パッドＢＰは、第１パッド群Ｇ１に含まれる複数の電極パッドＢＰのピッチと同じ、例えば第１ピッチで配置されている。そして、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第２辺Ｓ２に沿って第３電極パッドＢ３の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷは、内倒れループ形状を有している。   The plurality of electrode pads BP included in the second pad group G2 are arranged at the same pitch as the plurality of electrode pads BP included in the first pad group G1, for example, the first pitch. A plurality of third electrode pads B3 located closest to the second corner C2 of the semiconductor chip SC and a plurality of electrode pads BP connected to the third electrode pads B3 adjacent to the third electrode pads B3 along the second side S2. The bonding wire BW has an inwardly falling loop shape.

また、第３パッド群Ｇ３に含まれる複数の電極パッドＢＰは、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第５電極パッドＢ５を含む、複数の電極パッドＢＰから構成される第１サブパッド群ＧＰａと、半導体チップＳＣの第３角部Ｃ３の最も近くに位置する第６電極パッドＢ６を含む、複数の電極パッドＢＰから構成される第２サブパッド群ＧＰｂと、を有する。   The plurality of electrode pads BP included in the third pad group G3 includes a plurality of electrode pads BP including a fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC. 1 sub pad group GPa, and 2nd sub pad group GPb comprised from several electrode pad BP including 6th electrode pad B6 located closest to the 3rd corner | angular part C3 of semiconductor chip SC.

第１サブパッド群ＧＰａを構成する複数の電極パッドＢＰおよび第２サブパッド群ＧＰｂを構成する複数の電極パッドＢＰのそれぞれは、第１ピッチで配置されている。一方、第１サブパッド群ＧＰａに含まれる複数の電極パッドＢＰのうち、第２サブパッド群ＧＰｂに最も近い位置にある電極パッドＢＰと、第２サブパッド群ＧＰｂに含まれる複数の電極パッドＢＰのうち、第１サブパッド群ＧＰａに最も近い位置ある電極パッドＢＰとは、第１ピッチよりも大きいピッチで配置されている。すなわち、前述の実施の形態では、第３パッド群Ｇ３に含まれる複数の電極パッドＢＰは同一ピッチで配列されているのに対し、変形例４では、図２１に示すように、この第１ピッチよりも大きいピッチで配列される部分を有する。言い換えれば、第３パッド群Ｇ３は、複数の電極パッドＢＰが等ピッチで配置されていない箇所を有している。そして、第１サブパッド群ＧＰａを構成する複数の電極パッドＢＰのそれぞれに接続されるボンディングワイヤＢＷは、内倒れループ形状を有している。   Each of the plurality of electrode pads BP constituting the first subpad group GPa and the plurality of electrode pads BP constituting the second subpad group GPb are arranged at the first pitch. On the other hand, among the plurality of electrode pads BP included in the first subpad group GPa, the electrode pad BP located closest to the second subpad group GPb and the plurality of electrode pads BP included in the second subpad group GPb, The electrode pads BP located closest to the first subpad group GPa are arranged at a pitch larger than the first pitch. That is, in the above-described embodiment, the plurality of electrode pads BP included in the third pad group G3 are arranged at the same pitch, whereas in the modified example 4, as shown in FIG. And a portion arranged with a larger pitch. In other words, the third pad group G3 has a portion where the plurality of electrode pads BP are not arranged at an equal pitch. The bonding wire BW connected to each of the plurality of electrode pads BP constituting the first subpad group GPa has an inwardly falling loop shape.

なお、図２１では、見易さのため、第１サブパッド群ＧＰａを構成する複数の電極パッドＢＰとして１つの電極パッドＢＰを記載しているが、第１サブパッド群ＧＰａは複数の電極パッドＢＰにより構成されている。ただし、１つの電極パッドＢＰによって構成される第１サブパッド群ＧＰａを排除するものではない。   In FIG. 21, one electrode pad BP is shown as a plurality of electrode pads BP constituting the first subpad group GPa for the sake of clarity. However, the first subpad group GPa includes a plurality of electrode pads BP. It is configured. However, the first subpad group GPa constituted by one electrode pad BP is not excluded.

また、第４パッド群Ｇ４に含まれる複数の電極パッドＢＰは、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第７電極パッドＢ７を含む、複数の電極パッドＢＰから構成される第３サブパッド群ＧＰｃと、半導体チップＳＣの第４角部Ｃ４の最も近くに位置する第８電極パッドＢ８を含む、複数の電極パッドＢＰから構成される第４サブパッド群ＧＰｄと、を有する。   The plurality of electrode pads BP included in the fourth pad group G4 includes a seventh electrode pad BP including a seventh electrode pad B7 located closest to the second corner C2 of the semiconductor chip SC. 3 sub-pad groups GPc, and a fourth sub-pad group GPd composed of a plurality of electrode pads BP including an eighth electrode pad B8 located closest to the fourth corner C4 of the semiconductor chip SC.

第３サブパッド群ＧＰｃを構成する複数の電極パッドＢＰおよび第４サブパッド群ＧＰｄを構成する複数の電極パッドＢＰのそれぞれは、第１ピッチで配置されている。一方、第３サブパッド群ＧＰｃに含まれる複数の電極パッドＢＰのうち、第４サブパッド群ＧＰｄに最も近い位置にある電極パッドＢＰと、第４サブパッド群ＧＰｄに含まれる複数の電極パッドＢＰのうち、第３サブパッド群ＧＰｃに最も近い位置ある電極パッドＢＰとは、第１ピッチよりも大きいピッチで配置されている。すなわち、前述の実施の形態では、第４パッド群Ｇ４に含まれる複数の電極パッドＢＰは同一ピッチで配列されていたのに対し、変形例４では、図２１に示すように、この第１ピッチよりも大きいピッチで配列される部分を有する。言い換えれば、第４パッド群Ｇ４は、複数の電極パッドＢＰが等ピッチで配置されていない箇所を有している。そして、第３サブパッド群ＧＰｃを構成する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷは、内倒れループ形状を有している。   Each of the plurality of electrode pads BP constituting the third sub pad group GPc and the plurality of electrode pads BP constituting the fourth sub pad group GPd are arranged at the first pitch. On the other hand, among the plurality of electrode pads BP included in the third subpad group GPc, among the electrode pads BP closest to the fourth subpad group GPd and among the plurality of electrode pads BP included in the fourth subpad group GPd, The electrode pads BP located closest to the third subpad group GPc are arranged at a pitch larger than the first pitch. That is, in the above-described embodiment, the plurality of electrode pads BP included in the fourth pad group G4 are arranged at the same pitch, whereas in the modified example 4, as shown in FIG. And a portion arranged with a larger pitch. In other words, the fourth pad group G4 has a portion where the plurality of electrode pads BP are not arranged at an equal pitch. The plurality of bonding wires BW connected to each of the electrode pads BP constituting the third subpad group GPc have an inwardly falling loop shape.

なお、図２１では、見易さのため、第３サブパッド群ＧＰｃを構成する複数の電極パッドＢＰとして１つの電極パッドＢＰを記載しているが、第３サブパッド群ＧＰｃは複数の電極パッドＢＰにより構成されている。ただし、１つの電極パッドＢＰによって構成される第３サブパッド群ＧＰｃを排除するものではない。   In FIG. 21, one electrode pad BP is shown as a plurality of electrode pads BP constituting the third sub pad group GPc for the sake of clarity. However, the third sub pad group GPc includes a plurality of electrode pads BP. It is configured. However, the third subpad group GPc constituted by one electrode pad BP is not excluded.

変形例４による半導体装置ＳＭ４のように、一つのパッド群（変形例４では、第３パッド群Ｇ３と第４パッド群Ｇ４）を構成する複数の電極パッドＢＰにおいて、電極パッドＢＰの間隔が異なる箇所を境界として、内倒れループ形状を有するボンディングワイヤＢＷを定めることができる。   Like the semiconductor device SM4 according to the modification example 4, the intervals between the electrode pads BP are different in the plurality of electrode pads BP constituting one pad group (in the modification example 4, the third pad group G3 and the fourth pad group G4). A bonding wire BW having an inwardly falling loop shape can be determined with the location as a boundary.

すなわち、例えば第３パッド群Ｇ３では、第１辺Ｓ１側に位置する第１サブパッド群ＧＰａを構成する複数の電極パッドＢＰのそれぞれに接続されるボンディングパッドＢＷを内倒れループ形状とする。また、例えば第４パッド群Ｇ４では、第２辺Ｓ２側に位置する第３サブパッド群ＧＰｃを構成する複数の電極パッドＢＰのそれぞれに接続されるボンディングパッドＢＷを内倒れループ形状とする。   That is, for example, in the third pad group G3, the bonding pads BW connected to each of the plurality of electrode pads BP constituting the first subpad group GPa located on the first side S1 side are formed in an inclining loop shape. Further, for example, in the fourth pad group G4, the bonding pads BW connected to each of the plurality of electrode pads BP constituting the third subpad group GPc located on the second side S2 side are inwardly looped.

これにより、前述の実施の形態と同様に、ボンディングワイヤＢＷの剥がれ（第１の課題）、ボンディングワイヤＢＷの切断（第２の課題）およびボンディングワイヤＢＷのワイヤ流れ（第３の課題）を回避することができる。   This avoids peeling of the bonding wire BW (first problem), cutting of the bonding wire BW (second problem), and wire flow of the bonding wire BW (third problem), as in the above-described embodiment. can do.

なお、変形例４では、第３パッド群Ｇ３および第４パッド群Ｇ４のそれぞれに、互いに間隔の異なる電極パッドＢＰを配置したが、第１パッド群Ｇ１および第２パッド群Ｇ２に、互いに間隔の異なる電極パッドＢＰを配置できることは、言うまでない。この場合も、第１パッド群Ｇ１および第２パッド群Ｇ２のそれぞれを構成する複数の電極パッドＢＰにおいて、電極パッドＢＰの間隔が異なる箇所を境界として、内倒れループ形状を有するボンディングワイヤＢＷを定めることができる。   In the modified example 4, the electrode pads BP having different intervals are arranged in the third pad group G3 and the fourth pad group G4, respectively, but the first pad group G1 and the second pad group G2 are spaced apart from each other. Needless to say, different electrode pads BP can be arranged. Also in this case, in the plurality of electrode pads BP constituting each of the first pad group G1 and the second pad group G2, a bonding wire BW having an inwardly looped shape is defined with a location where the interval between the electrode pads BP is different as a boundary. be able to.

＜変形例５＞
本実施の形態の変形例５による半導体装置について、図２２を用いて説明する。 <Modification 5>
A semiconductor device according to Modification 5 of the present embodiment will be described with reference to FIG.

図２２は、本実施の形態の変形例５による半導体装置の上面図である。   FIG. 22 is a top view of a semiconductor device according to Modification 5 of the present embodiment.

なお、変形例５による半導体装置ＳＭ５と前述の実施の形態による半導体装置ＳＭとの相違点は、ボンディングワイヤの有無である。その他の構成は、両者においてほぼ同様である。以下、相違点を中心に説明する。   The difference between the semiconductor device SM5 according to the modification 5 and the semiconductor device SM according to the above-described embodiment is the presence or absence of a bonding wire. Other configurations are almost the same in both cases. Hereinafter, the difference will be mainly described.

図２２に示すように、第１パッド群Ｇ１に含まれる複数の電極パッドＢＰは、前述の変形例４と同様、例えば第１ピッチで配置されている。そして、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第１電極パッドＢ１および第１辺Ｓ１に沿って第１電極パッドＢ１の隣に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷは、内倒れループ形状を有している。   As shown in FIG. 22, the plurality of electrode pads BP included in the first pad group G <b> 1 are arranged at, for example, the first pitch, similarly to the above-described fourth modification. A plurality of electrodes connected to the first electrode pad B1 located closest to the first corner C1 of the semiconductor chip SC and the electrode pad BP located next to the first electrode pad B1 along the first side S1. The bonding wire BW has an inwardly falling loop shape.

また、第２パッド群Ｇ２に含まれる複数の電極パッドＢＰは、例えば第１ピッチで配置されている。そして、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第３電極パッドＢ３および第２辺Ｓ２に沿って第３電極パッドＢ３の隣に位置する電極パッドＢＰのそれぞれに接続されるボンディングワイヤＢＷは、内倒れループ形状を有している。   In addition, the plurality of electrode pads BP included in the second pad group G2 are arranged at a first pitch, for example. The bonding is connected to each of the third electrode pad B3 located closest to the second corner C2 of the semiconductor chip SC and the electrode pad BP located next to the third electrode pad B3 along the second side S2. The wire BW has an inwardly falling loop shape.

また、第３パッド群Ｇ３に含まれる複数の電極パッドＢＰは、例えば第１ピッチで配置されているが、ボンディングワイヤＢＷが接続されない電極パッドＢ０が配置されている。そして、半導体チップＳＣの第１角部Ｃ１の最も近くに位置する第５電極パッドＢ５、および第１電極パッドＢ５とボンディングワイヤＢＷが接続されない電極パッドＢ０との間に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷは、内倒れループ形状を有している。   In addition, the plurality of electrode pads BP included in the third pad group G3 are arranged at the first pitch, for example, but the electrode pads B0 to which the bonding wires BW are not connected are arranged. Each of the fifth electrode pad B5 located closest to the first corner C1 of the semiconductor chip SC and the electrode pad BP located between the first electrode pad B5 and the electrode pad B0 to which the bonding wire BW is not connected are provided. The plurality of bonding wires BW connected to each have an inwardly falling loop shape.

なお、図２２では、見易さのため、第５電極パッドＢ５とボンディングワイヤＢＷが接続されない電極パッドＢ０との間の電極パッドＢＰは省略している。   In FIG. 22, the electrode pad BP between the fifth electrode pad B5 and the electrode pad B0 to which the bonding wire BW is not connected is omitted for easy viewing.

また、第４パッド群Ｇ４に含まれる複数の電極パッドＢＰは、例えば第１ピッチで配置されているが、ボンディングワイヤＢＷが接続されない電極パッドＢ０が配置されている。そして、半導体チップＳＣの第２角部Ｃ２の最も近くに位置する第７電極パッドＢ７、および第７電極パッドＢ７とボンディングワイヤＢＷが接続されない電極パッドＢ０との間に位置する電極パッドＢＰのそれぞれに接続される複数のボンディングワイヤＢＷは、内倒れループ形状を有している。   The plurality of electrode pads BP included in the fourth pad group G4 are arranged at, for example, the first pitch, but electrode pads B0 to which the bonding wires BW are not connected are arranged. Each of the seventh electrode pad B7 located closest to the second corner C2 of the semiconductor chip SC and the electrode pad BP located between the seventh electrode pad B7 and the electrode pad B0 to which the bonding wire BW is not connected are provided. The plurality of bonding wires BW connected to each have an inwardly falling loop shape.

なお、図２２では、見易さのため、第７電極パッドＢ７とボンディングワイヤＢＷが接続されない電極パッドＢ０との間の電極パッドＢＰは省略している。   In FIG. 22, the electrode pad BP between the seventh electrode pad B7 and the electrode pad B0 to which the bonding wire BW is not connected is omitted for easy viewing.

変形例５による半導体装置ＳＭ５のように、一つのパッド群（変形例５では、第３パッド群Ｇ３と第４パッド群Ｇ４）を構成する複数の電極パッドＢＰにおいて、ボンディングワイヤＢＷが接続されない電極パッドＢＰを境界として、内倒れループ形状を有するボンディングワイヤＢＷを定めることができる。   As in the semiconductor device SM5 according to the modification 5, the electrodes to which the bonding wires BW are not connected in the plurality of electrode pads BP constituting one pad group (in the modification 5, the third pad group G3 and the fourth pad group G4) A bonding wire BW having an inwardly falling loop shape can be determined with the pad BP as a boundary.

すなわち、例えば第３パッド群Ｇ３では、ボンディングワイヤＢＷが接続されない電極パッドＢＰと第１辺Ｓ１との間に位置する複数の電極パッドＢＰのそれぞれに接続されるボンディングパッドＢＷを内倒れループ形状とする。また、例えば第４パッド群Ｇ４では、ボンディングワイヤＢＷが接続されない電極パッドＢＰと第２辺Ｓ２との間に位置する複数の電極パッドＢＰのそれぞれに接続されるボンディングパッドＢＷを内倒れループ形状とする。   That is, for example, in the third pad group G3, the bonding pad BW connected to each of the plurality of electrode pads BP located between the electrode pad BP to which the bonding wire BW is not connected and the first side S1 is inwardly looped. To do. For example, in the fourth pad group G4, the bonding pad BW connected to each of the plurality of electrode pads BP located between the electrode pad BP to which the bonding wire BW is not connected and the second side S2 is inwardly looped. To do.

これにより、前述の実施の形態と同様に、ボンディングワイヤＢＷの剥がれ（第１の課題）、ボンディングワイヤＢＷの切断（第２の課題）およびボンディングワイヤＢＷのワイヤ流れ（第３の課題）を回避することができる。   This avoids peeling of the bonding wire BW (first problem), cutting of the bonding wire BW (second problem), and wire flow of the bonding wire BW (third problem), as in the above-described embodiment. can do.

なお、変形例５では、第３パッド群Ｇ３と第４パッド群Ｇ４に、ボンディングワイヤＢＷが接続されない電極パッドＢ０を配置したが、第１パッド群Ｇ１および第２パッド群Ｇ２に、ボンディングワイヤＢＷが接続されない電極パッドＢ０を配置できることは、言うまでもない。この場合も、第１パッド群Ｇ１および第２パッド群Ｇ２のそれぞれを構成する複数の電極パッドＢＰにおいて、ボンディングワイヤＢＷが接続されない電極パッドＢＰを境界として、内倒れループ形状を有するボンディングワイヤＢＷを定めることができる。   In the modified example 5, the electrode pad B0 to which the bonding wire BW is not connected is arranged in the third pad group G3 and the fourth pad group G4, but the bonding wire BW is arranged in the first pad group G1 and the second pad group G2. Needless to say, the electrode pad B0 not connected to can be arranged. Also in this case, in the plurality of electrode pads BP constituting each of the first pad group G1 and the second pad group G2, the bonding wire BW having an inwardly looped shape is formed with the electrode pad BP to which the bonding wire BW is not connected as a boundary. Can be determined.

Ａ１〜Ａ４ 第１領域〜第４領域
Ｂ０ 電極パッド
Ｂ１〜Ｂ８ 第１電極パッド〜第８電極パッド
ＢＰ 電極パッド（ボンディングパッド、表面電極）
ＢＷ ボンディングワイヤ（導電性ワイヤ、ワイヤ）
ＢＷａ ボール部
ＢＷｂ 芯部
Ｃ１〜Ｃ４ 第１角部〜第４角部
ＣＡ キャピラリー
ＣＲ ダイボンド材（接着剤）
ＣＶａ、ＣＶｂ キャビティ
Ｄａ ダイパッドの上面（チップ搭載面）
Ｄｂ ダイパッドの下面（露出面）
ＤＰ ダイパッド（タブ、チップ搭載部）
ＦＢＰ 第１ポイント点
Ｇ１〜Ｇ４ 第１パッド群〜第４パッド群
ＧＡ ゲート
ＧＰａ 第１サブパッド群
ＧＰｂ 第２サブパッド群
ＧＰｃ 第３サブパッド群
ＧＰｄ 第４サブパッド群
Ｈ１、Ｈ２ ループ高さ
ＨＬ 吊りリード（支持リード）
ＩＬ１ 第１仮想線
ＩＬ２ 第２仮想線
ＬＥ リード（外部端子）
ＬＦ リードフレーム（配線板、配線部材）
ＭＤａ 下金型
ＭＤｂ 上金型
ＰＦ メッキ膜（メッキ層）
Ｒａ 封止体の上面
Ｒｂ 封止体の下面（実装面）
ＲＥ 封止体（樹脂封止）
ＲＥａ 樹脂
Ｓ１〜Ｓ４ 第１辺〜第４辺
Ｓａ 半導体チップの主面（第１主面、表面）
Ｓｂ 半導体チップの裏面（第２主面）
ＳＢＰ 第２ポイント点
ＳＣ 半導体チップ
ＳＦ 単位フレーム
ＳＭ、ＳＭ１〜ＳＭ５ 半導体装置
ＴＢ タムバー
ＶＥ ベント
Ｗ１〜Ｗ８ 第１ワイヤ〜第８ワイヤ
θ１、θ２ 曲げ角度 A1-A4 1st area | region-4th area | region B0 Electrode pad B1-B8 1st electrode pad-8th electrode pad BP Electrode pad (bonding pad, surface electrode)
BW bonding wire (conductive wire, wire)
BWa Ball part BWb Core part C1 to C4 First corner part to fourth corner part CA Capillary CR Die bond material (adhesive)
CVa, CVb Cavity Da Upper surface of die pad (chip mounting surface)
Db Bottom surface of die pad (exposed surface)
DP die pad (tab, chip mounting part)
FBP 1st point point G1-G4 1st pad group-4th pad group GA Gate GPa 1st subpad group GPb 2nd subpad group GPc 3rd subpad group GPd 4th subpad group H1, H2 Loop height HL Hanging lead (support) Lead)
IL1 First virtual line IL2 Second virtual line LE Lead (external terminal)
LF Lead frame (wiring board, wiring member)
MDa Lower mold MDb Upper mold PF Plating film (plating layer)
Ra Top surface of the sealing body Rb Bottom surface of the sealing body (mounting surface)
RE sealing body (resin sealing)
REa Resins S1 to S4 First side to fourth side Sa Semiconductor chip principal surface (first principal surface, surface)
Back side of Sb semiconductor chip (second main surface)
SBP Second point point SC Semiconductor chip SF Unit frame SM, SM1 to SM5 Semiconductor device TB Tambar VE Vent W1 to W8 First wire to eighth wire θ1, θ2 Bending angle

Claims (19)

以下の工程を含む半導体装置の製造方法：
（ａ）上面および前記上面とは反対側の下面を有し、平面形状が四角形からなるダイパッドと、前記ダイパッドを支持する複数の支持リードと、平面視において前記ダイパッドの周囲に配置された複数のリードと、を有するリードフレームを準備する工程；
（ｂ）前記（ａ）工程の後、主面、前記主面とは反対側の裏面および前記主面に形成された複数の電極パッドを有し、平面形状が四角形からなる半導体チップを、前記裏面と前記ダイパッドの前記上面とが対向するように、前記ダイパッドの前記上面に搭載する工程；
（ｃ）前記（ｂ）工程の後、前記複数の電極パッドと前記複数のリードとを、複数のワイヤを介してそれぞれ接続する工程；
（ｄ）前記（ｃ）工程の後、前記半導体チップおよび前記複数のワイヤを樹脂で封止する工程、
ここで、
前記半導体チップは、平面視において、第１辺と、前記第１辺と対向する第２辺と、前記第１辺および第２辺のそれぞれと交差する第３辺と、前記第１辺および前記第２辺のそれぞれと交差し、かつ、第３辺と対向する第４辺と、前記第１辺と前記第３辺とが交わる第１角部と、前記第２辺と前記第４辺とが交わる第２角部と、前記第３辺と前記第２辺とが交わる第３角部と、前記第４辺と前記第１辺とが交わる第４角部と、を有し、
前記複数の電極パッドは、平面視において、前記半導体チップの前記第２辺よりも前記第１辺の近くに位置し、かつ、前記第１辺に沿って配置された第１パッド群と、前記半導体チップの前記第１辺よりも前記第２辺の近くに位置し、かつ、前記第２辺に沿って配置された第２パッド群と、前記半導体チップの前記第４辺よりも前記第３辺の近くに位置し、かつ、前記第３辺に沿って配置された第３パッド群と、前記半導体チップの前記第３辺よりも前記第４辺の近くに位置し、かつ、前記第４辺に沿って配置された第４パッド群と、を有し、
前記第１パッド群は、前記第１角部の最も近くに位置する第１パッドと、前記第１パッドよりも前記第１角部から遠くに位置する第２パッドと、を含み、
前記第２パッド群は、前記第２角部の最も近くに位置する第３パッドと、前記第３パッドよりも前記第２角部から遠くに位置する第４パッドと、を含み、
前記第３パッド群は、前記第１角部の最も近くに位置する第５パッドと、前記第５パッドよりも前記第１角部から遠くに位置する第６パッドと、を含み、
前記第４パッド群は、前記第２角部の最も近くに位置する第７パッドと、前記第７パッドよりも前記第２角部から遠くに位置する第８パッドと、を含み、
前記複数のワイヤは、前記第１パッド、前記第３パッド、前記第５パッドおよび前記第７パッドのそれぞれに接続される第１ワイヤと、前記第２パッド、前記第４パッド、前記第６パッドおよび前記第８パッドのそれぞれに接続される第２ワイヤと、を含み、
前記（ｃ）工程では、前記第１ワイヤの第１芯部と第１ボール部との接合部における、法線方向に対する前記第１芯部の第１曲げ角度が、前記第２ワイヤの第２芯部と第２ボール部との接合部における、法線方向に対する前記第２芯部の第２曲げ角度よりも大きくなるように、前記複数のワイヤが前記複数の電極パッドにそれぞれ接続され、
前記（ｄ）工程では、前記半導体チップの前記第１角部側から前記第２角部側に向かって前記樹脂が供給される。 A semiconductor device manufacturing method including the following steps:
(A) a die pad having a top surface and a bottom surface opposite to the top surface and having a square shape in plan view; a plurality of support leads for supporting the die pad; and a plurality of pads disposed around the die pad in plan view Preparing a lead frame having leads;
(B) After the step (a), a semiconductor chip having a main surface, a back surface opposite to the main surface, and a plurality of electrode pads formed on the main surface, the planar shape of which is a quadrangle, Mounting on the upper surface of the die pad such that the back surface and the upper surface of the die pad face each other;
(C) After the step (b), connecting the plurality of electrode pads and the plurality of leads through a plurality of wires, respectively;
(D) After the step (c), the step of sealing the semiconductor chip and the plurality of wires with a resin,
here,
The semiconductor chip includes a first side, a second side opposite to the first side, a third side intersecting with each of the first side and the second side, the first side, A fourth side that intersects each of the second sides and faces the third side, a first corner at which the first side and the third side intersect, the second side and the fourth side, A second corner where the two sides intersect, a third corner where the third side and the second side intersect, and a fourth corner where the fourth side and the first side intersect.
The plurality of electrode pads are positioned closer to the first side than the second side of the semiconductor chip in a plan view, and the first pad group disposed along the first side; A second pad group located closer to the second side than the first side of the semiconductor chip and disposed along the second side; and the third group than the fourth side of the semiconductor chip. A third pad group disposed near the side and disposed along the third side; and positioned closer to the fourth side than the third side of the semiconductor chip; and A fourth pad group arranged along the side,
The first pad group includes a first pad located closest to the first corner, and a second pad located farther from the first corner than the first pad,
The second pad group includes a third pad located closest to the second corner, and a fourth pad located farther from the second corner than the third pad,
The third pad group includes a fifth pad located closest to the first corner, and a sixth pad located farther from the first corner than the fifth pad,
The fourth pad group includes a seventh pad located closest to the second corner, and an eighth pad located farther from the second corner than the seventh pad;
The plurality of wires include a first wire connected to each of the first pad, the third pad, the fifth pad, and the seventh pad, the second pad, the fourth pad, and the sixth pad. And a second wire connected to each of the eighth pads,
In the step (c), the first bending angle of the first core portion with respect to the normal direction at the joint portion between the first core portion of the first wire and the first ball portion is the second wire of the second wire. The plurality of wires are respectively connected to the plurality of electrode pads such that the second bending angle of the second core portion with respect to the normal direction at the joint portion between the core portion and the second ball portion is larger than the second bending angle.
In the step (d), the resin is supplied from the first corner portion side of the semiconductor chip toward the second corner portion side. 請求項１記載の半導体装置の製造方法において、
前記（ｃ）工程では、前記複数のワイヤのそれぞれにおいて、前記ワイヤの一部が前記電極パッドに接続された後、前記ワイヤの他部が前記リードに接続される、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
In the step (c), in each of the plurality of wires, after a part of the wire is connected to the electrode pad, the other part of the wire is connected to the lead. 請求項１記載の半導体装置の製造方法において、
前記第１ワイヤの前記半導体チップの前記主面からのループ高さと、前記第２ワイヤの前記半導体チップの前記主面からのループ高さとは同じである、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein a loop height of the first wire from the main surface of the semiconductor chip and a loop height of the second wire from the main surface of the semiconductor chip are the same. 請求項１記載の半導体装置の製造方法において、
平面視において、前記第１ワイヤの長さは、前記第２ワイヤの長さよりも長い、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein a length of the first wire is longer than a length of the second wire in a plan view. 請求項１記載の半導体装置の製造方法において、
前記第２パッドは、前記第１パッド群のうち、前記半導体チップの前記第４角部の最も近くに位置する電極パッドであり、
前記第４パッドは、前記第２パッド群のうち、前記半導体チップの前記第３角部の最も近くに位置する電極パッドであり、
前記第６パッドは、前記第３パッド群のうち、前記半導体チップの前記第３角部の最も近くに位置する電極パッドであり、
前記第８パッドは、前記第４パッド群のうち、前記半導体チップの前記第４角部の最も近くに位置する電極パッドである、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The second pad is an electrode pad located closest to the fourth corner of the semiconductor chip in the first pad group,
The fourth pad is an electrode pad located closest to the third corner of the semiconductor chip in the second pad group,
The sixth pad is an electrode pad located closest to the third corner of the semiconductor chip in the third pad group,
The method for manufacturing a semiconductor device, wherein the eighth pad is an electrode pad located closest to the fourth corner of the semiconductor chip in the fourth pad group. 請求項１記載の半導体装置の製造方法において、
前記半導体チップの前記主面は、平面視において、前記第１辺の中心と前記第２辺の中心とを通る第１仮想線と、前記第３辺の中心と前記第４辺の中心とを通る第２仮想線とで区分された、前記第１角部を含む第１領域、前記第２角部を含む第２領域、前記第３角部を含む第３領域および前記第４角部を含む第４領域を有し、
前記複数の電極パッドのうち、前記第１領域および前記第２領域にそれぞれ位置する電極パッドに接続されるワイヤは、前記第１ワイヤであり、
前記複数の電極パッドのうち、前記第３領域および前記第４領域にそれぞれ位置する電極パッドに接続されるワイヤは、前記第２ワイヤである、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The main surface of the semiconductor chip includes a first imaginary line passing through the center of the first side and the center of the second side, the center of the third side, and the center of the fourth side in plan view. A first region including the first corner, a second region including the second corner, a third region including the third corner, and the fourth corner separated by a second imaginary line passing therethrough. A fourth region including,
Of the plurality of electrode pads, the wires connected to the electrode pads respectively located in the first region and the second region are the first wires,
The method of manufacturing a semiconductor device, wherein a wire connected to an electrode pad located in each of the third region and the fourth region among the plurality of electrode pads is the second wire. 請求項１記載の半導体装置の製造方法において、
前記第１パッド群は、前記第１パッドを含む第１サブパッド群と、前記第２パッドを含む第２サブパッド群と、に区分され、
前記第２パッド群は、前記第３パッドを含む第３サブパッド群と、前記第４パッドを含む第４サブパッド群と、に区分され、
前記複数の電極パッドのうち、前記第１サブパッド群を構成する電極パッドおよび前記第２サブパッド群を構成する電極パッドは、それぞれ第１ピッチで配置され、
前記複数の電極パッドのうち、前記第３サブパッド群を構成する電極パッドおよび前記第４サブパッド群を構成する電極パッドは、それぞれ第２ピッチで配置され、
前記第１サブパッド群を構成する電極パッドのうち、前記第２サブパッド群の最も近くに配置された電極パッドと、前記第２サブパッド群を構成する電極パッドのうち、前記第１サブパッド群の最も近くに配置された電極パッドとの間隔は、前記第１ピッチよりも大きく、
前記第３サブパッド群を構成する電極パッドのうち、前記第４サブパッド群の最も近くに配置された電極パッドと、前記第４サブパッド群を構成する電極パッドのうち、前記第３サブパッド群の最も近くに配置された電極パッドとの間隔は、前記第２ピッチよりも大きく、
前記第１サブパッド群を構成する電極パッドおよび前記第３サブパッド群を構成する電極パッドのそれぞれに前記第１ワイヤが接続され、
前記第２サブパッド群を構成する電極パッドおよび前記第４サブパッド群を構成する電極パッドのそれぞれに前記第２ワイヤが接続される、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The first pad group is divided into a first subpad group including the first pad and a second subpad group including the second pad,
The second pad group is divided into a third subpad group including the third pad and a fourth subpad group including the fourth pad,
Of the plurality of electrode pads, the electrode pads constituting the first subpad group and the electrode pads constituting the second subpad group are each arranged at a first pitch,
Of the plurality of electrode pads, the electrode pads constituting the third subpad group and the electrode pads constituting the fourth subpad group are each arranged at a second pitch,
Of the electrode pads constituting the first subpad group, the electrode pad disposed closest to the second subpad group and the electrode pad constituting the second subpad group closest to the first subpad group The distance between the electrode pads arranged on the electrode pad is larger than the first pitch,
Of the electrode pads constituting the third subpad group, the electrode pad disposed closest to the fourth subpad group and the electrode pad constituting the fourth subpad group closest to the third subpad group The distance between the electrode pads arranged on the electrode pad is larger than the second pitch,
The first wire is connected to each of an electrode pad constituting the first subpad group and an electrode pad constituting the third subpad group;
A method of manufacturing a semiconductor device, wherein the second wire is connected to each of an electrode pad constituting the second subpad group and an electrode pad constituting the fourth subpad group. 請求項７記載の半導体装置の製造方法において、
前記第１サブパッド群を構成する電極パッドのうち、前記第２サブパッド群の最も近くに配置された電極パッドと、前記第２サブパッド群を構成する電極パッドのうち、前記第１サブパッド群の最も近くに配置された電極パッドとの間に、ワイヤが接続されない電極パッドが配置され、
前記第３サブパッド群を構成する電極パッドのうち、前記第４サブパッド群の最も近くに配置された電極パッドと、前記第４サブパッド群を構成する電極パッドのうち、前記第３サブパッド群の最も近くに配置された電極パッドとの間に、ワイヤが接続されない電極パッドが配置されている、半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 7.
Of the electrode pads constituting the first subpad group, the electrode pad disposed closest to the second subpad group and the electrode pad constituting the second subpad group closest to the first subpad group An electrode pad to which no wire is connected is arranged between the electrode pad arranged in
Of the electrode pads constituting the third subpad group, the electrode pad disposed closest to the fourth subpad group and the electrode pad constituting the fourth subpad group closest to the third subpad group A method for manufacturing a semiconductor device, wherein an electrode pad to which no wire is connected is disposed between the electrode pad disposed on the substrate. 請求項１記載の半導体装置の製造方法において、
前記（ｄ）工程では、前記半導体チップの前記第１角部側に設けられた前記支持リードの上面側および下面側から、または下面側から、前記樹脂が供給される、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
In the step (d), the resin is supplied from an upper surface side and a lower surface side of the support lead provided on the first corner portion side of the semiconductor chip, or from a lower surface side. 請求項１記載の半導体装置の製造方法において、
前記（ｄ）工程では、前記ダイパッドの前記下面は、前記樹脂から露出している、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
In the step (d), the lower surface of the die pad is exposed from the resin. 以下の工程を含む半導体装置の製造方法：
（ａ）上面および前記上面とは反対側の下面を有し、平面形状が四角形からなるダイパッドと、前記ダイパッドを支持する複数の支持リードと、平面視において前記ダイパッドの周囲に配置された複数のリードと、を有するリードフレームを準備する工程；
（ｂ）前記（ａ）工程の後、主面、前記主面とは反対側の裏面および前記主面に形成された複数の電極パッドを有し、平面形状が四角形からなる半導体チップを、前記裏面と前記ダイパッドの前記上面とが対向するように、前記ダイパッドの前記上面に搭載する工程；
（ｃ）前記（ｂ）工程の後、前記複数の電極パッドと前記複数のリードとを、複数のワイヤを介してそれぞれ接続する工程；
（ｄ）前記（ｃ）工程の後、前記半導体チップおよび前記複数のワイヤを樹脂で封止する工程、
ここで、
前記半導体チップは、平面視において、第１辺と、前記第１辺と対向する第２辺と、前記第１辺および第２辺のそれぞれと交差する第３辺と、前記第１辺および前記第２辺のそれぞれと交差し、かつ、第３辺と対向する第４辺と、前記第１辺と前記第３辺とが交わる第１角部と、前記第２辺と前記第４辺とが交わる第２角部と、前記第３辺と前記第２辺とが交わる第３角部と、前記第４辺と前記第１辺とが交わる第４角部と、を有し、
前記複数の電極パッドは、平面視において、前記半導体チップの前記第２辺よりも前記第１辺の近くに位置し、かつ、前記第１辺に沿って配置された第１パッド群と、前記半導体チップの前記第１辺よりも前記第２辺の近くに位置し、かつ、前記第２辺に沿って配置された第２パッド群と、前記半導体チップの前記第４辺よりも前記第３辺の近くに位置し、かつ、前記第３辺に沿って配置された第３パッド群と、前記半導体チップの前記第３辺よりも前記第４辺の近くに位置し、かつ、前記第４辺に沿って配置された第４パッド群と、を有し、
前記第１パッド群は、前記第１角部の最も近くに位置する第１パッドと、前記第１パッドよりも前記第１角部から遠くに位置する第２パッドと、を含み、
前記第２パッド群は、前記第２角部の最も近くに位置する第３パッドと、前記第３パッドよりも前記第２角部から遠くに位置する第４パッドと、を含み、
前記第３パッド群は、前記第１角部の最も近くに位置する第５パッドと、前記第５パッドよりも前記第１角部から遠くに位置する第６パッドと、を含み、
前記第４パッド群は、前記第２角部の最も近くに位置する第７パッドと、前記第７パッドよりも前記第２角部から遠くに位置する第８パッドと、を含み、
前記複数のワイヤは、前記第１パッド、前記第３パッド、前記第５パッドおよび前記第７パッドのそれぞれに接続される第１ワイヤと、前記第２パッド、前記第４パッド、前記第６パッドおよび前記第８パッドのそれぞれに接続される第２ワイヤと、を含み、
前記第１ワイヤの第１線径が、前記第２ワイヤの第２線径よりも大きく、
前記（ｄ）工程では、前記半導体チップの前記第１角部側から前記第２角部側に向かって前記樹脂が供給される。 A semiconductor device manufacturing method including the following steps:
(A) a die pad having a top surface and a bottom surface opposite to the top surface and having a square shape in plan view; a plurality of support leads for supporting the die pad; and a plurality of pads disposed around the die pad in plan view Preparing a lead frame having leads;
(B) After the step (a), a semiconductor chip having a main surface, a back surface opposite to the main surface, and a plurality of electrode pads formed on the main surface, the planar shape of which is a quadrangle, Mounting on the upper surface of the die pad such that the back surface and the upper surface of the die pad face each other;
(C) After the step (b), connecting the plurality of electrode pads and the plurality of leads through a plurality of wires, respectively;
(D) After the step (c), the step of sealing the semiconductor chip and the plurality of wires with a resin,
here,
The semiconductor chip includes a first side, a second side opposite to the first side, a third side intersecting with each of the first side and the second side, the first side, A fourth side that intersects each of the second sides and faces the third side, a first corner at which the first side and the third side intersect, the second side and the fourth side, A second corner where the two sides intersect, a third corner where the third side and the second side intersect, and a fourth corner where the fourth side and the first side intersect.
The plurality of electrode pads are positioned closer to the first side than the second side of the semiconductor chip in a plan view, and the first pad group disposed along the first side; A second pad group located closer to the second side than the first side of the semiconductor chip and disposed along the second side; and the third group than the fourth side of the semiconductor chip. A third pad group disposed near the side and disposed along the third side; and positioned closer to the fourth side than the third side of the semiconductor chip; and A fourth pad group arranged along the side,
The first pad group includes a first pad located closest to the first corner, and a second pad located farther from the first corner than the first pad,
The second pad group includes a third pad located closest to the second corner, and a fourth pad located farther from the second corner than the third pad,
The third pad group includes a fifth pad located closest to the first corner, and a sixth pad located farther from the first corner than the fifth pad,
The fourth pad group includes a seventh pad located closest to the second corner, and an eighth pad located farther from the second corner than the seventh pad;
The plurality of wires include a first wire connected to each of the first pad, the third pad, the fifth pad, and the seventh pad, the second pad, the fourth pad, and the sixth pad. And a second wire connected to each of the eighth pads,
The first wire diameter of the first wire is larger than the second wire diameter of the second wire;
In the step (d), the resin is supplied from the first corner portion side of the semiconductor chip toward the second corner portion side. 請求項１１記載の半導体装置の製造方法において、
前記第２パッドは、前記第１パッド群のうち、前記半導体チップの前記第４角部の最も近くに位置する電極パッドであり、
前記第４パッドは、前記第２パッド群のうち、前記半導体チップの前記第３角部の最も近くに位置する電極パッドであり、
前記第６パッドは、前記第３パッド群のうち、前記半導体チップの前記第３角部の最も近くに位置する電極パッドであり、
前記第８パッドは、前記第４パッド群のうち、前記半導体チップの前記第４角部の最も近くに位置する電極パッドである、半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 11.
The second pad is an electrode pad located closest to the fourth corner of the semiconductor chip in the first pad group,
The fourth pad is an electrode pad located closest to the third corner of the semiconductor chip in the second pad group,
The sixth pad is an electrode pad located closest to the third corner of the semiconductor chip in the third pad group,
The method for manufacturing a semiconductor device, wherein the eighth pad is an electrode pad located closest to the fourth corner of the semiconductor chip in the fourth pad group. 請求項１１記載の半導体装置の製造方法において、
前記半導体チップの前記主面は、平面視において、前記第１辺の中心と前記第２辺の中心とを通る第１仮想線と、前記第３辺の中心と前記第４辺の中心とを通る第２仮想線とで区分された、前記第１角部を含む第１領域、前記第２角部を含む第２領域、前記第３角部を含む第３領域および前記第４角部を含む第４領域を有し、
前記複数の電極パッドのうち、前記第１領域および前記第２領域にそれぞれ位置する電極パッドに接続されるワイヤは、前記第１ワイヤであり、
前記複数の電極パッドのうち、前記第３領域および前記第４領域にそれぞれ位置する電極パッドに接続されるワイヤは、前記第２ワイヤである、半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 11.
The main surface of the semiconductor chip includes a first imaginary line passing through the center of the first side and the center of the second side, the center of the third side, and the center of the fourth side in plan view. A first region including the first corner, a second region including the second corner, a third region including the third corner, and the fourth corner separated by a second imaginary line passing therethrough. A fourth region including,
Of the plurality of electrode pads, the wires connected to the electrode pads respectively located in the first region and the second region are the first wires,
The method of manufacturing a semiconductor device, wherein a wire connected to an electrode pad located in each of the third region and the fourth region among the plurality of electrode pads is the second wire. 請求項１１記載の半導体装置の製造方法において、
前記（ｄ）工程では、前記半導体チップの前記第１角部側に設けられた前記支持リードの上面側および下面側から、または下面側から、前記樹脂が供給される、半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 11.
In the step (d), the resin is supplied from an upper surface side and a lower surface side of the support lead provided on the first corner portion side of the semiconductor chip, or from a lower surface side. 請求項１１記載の半導体装置の製造方法において、
前記（ｄ）工程では、前記ダイパッドの前記下面は、前記樹脂から露出している、半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 11.
In the step (d), the lower surface of the die pad is exposed from the resin. 以下の工程を含む半導体装置の製造方法：
（ａ）上面および前記上面とは反対側の下面を有し、平面形状が四角形からなるダイパッドと、前記ダイパッドを支持する複数の支持リードと、平面視において前記ダイパッドの周囲に配置された複数のリードと、を有するリードフレームを準備する工程；
（ｂ）前記（ａ）工程の後、主面、前記主面とは反対側の裏面および前記主面に形成された複数の電極パッドを有し、平面形状が四角形からなる半導体チップを、前記裏面と前記ダイパッドの前記上面とが対向するように、前記ダイパッドの前記上面に搭載する工程；
（ｃ）前記（ｂ）工程の後、前記複数の電極パッドと前記複数のリードとを、複数のワイヤを介してそれぞれ接続する工程；
（ｄ）前記（ｃ）工程の後、前記半導体チップおよび前記複数のワイヤを樹脂で封止する工程、
ここで、
前記半導体チップは、平面視において、第１辺と、前記第１辺と対向する第２辺と、前記第１辺および第２辺のそれぞれと交差する第３辺と、前記第１辺および前記第２辺のそれぞれと交差し、かつ、第３辺と対向する第４辺と、前記第１辺と前記第３辺とが交わる第１角部と、前記第２辺と前記第４辺とが交わる第２角部と、前記第３辺と前記第２辺とが交わる第３角部と、前記第４辺と前記第１辺とが交わる第４角部と、を有し、
前記複数の電極パッドは、平面視において、前記半導体チップの前記第２辺よりも前記第１辺の近くに位置し、かつ、前記第１辺に沿って配置された第１パッド群と、前記半導体チップの前記第１辺よりも前記第２辺の近くに位置し、かつ、前記第２辺に沿って配置された第２パッド群と、前記半導体チップの前記第４辺よりも前記第３辺の近くに位置し、かつ、前記第３辺に沿って配置された第３パッド群と、前記半導体チップの前記第３辺よりも前記第４辺の近くに位置し、かつ、前記第４辺に沿って配置された第４パッド群と、を有し、
前記（ｃ）工程では、平面視において、前記複数のワイヤのそれぞれが、前記リードとの接合部から、前記電極パッドとの接合部を越えて前記半導体チップの内側方向に延在するように、前記複数のワイヤが前記複数の電極パッドのそれぞれに接続され、
前記（ｄ）工程では、前記半導体チップの前記第１角部側から前記第２角部側に向かって前記樹脂が供給される。 A semiconductor device manufacturing method including the following steps:
(A) a die pad having a top surface and a bottom surface opposite to the top surface and having a square shape in plan view; a plurality of support leads for supporting the die pad; and a plurality of pads disposed around the die pad in plan view Preparing a lead frame having leads;
(B) After the step (a), a semiconductor chip having a main surface, a back surface opposite to the main surface, and a plurality of electrode pads formed on the main surface, the planar shape of which is a quadrangle, Mounting on the upper surface of the die pad such that the back surface and the upper surface of the die pad face each other;
(C) After the step (b), connecting the plurality of electrode pads and the plurality of leads through a plurality of wires, respectively;
(D) After the step (c), the step of sealing the semiconductor chip and the plurality of wires with a resin,
here,
The semiconductor chip includes a first side, a second side opposite to the first side, a third side intersecting with each of the first side and the second side, the first side, A fourth side that intersects each of the second sides and faces the third side, a first corner at which the first side and the third side intersect, the second side and the fourth side, A second corner where the two sides intersect, a third corner where the third side and the second side intersect, and a fourth corner where the fourth side and the first side intersect.
The plurality of electrode pads are positioned closer to the first side than the second side of the semiconductor chip in a plan view, and the first pad group disposed along the first side; A second pad group located closer to the second side than the first side of the semiconductor chip and disposed along the second side; and the third group than the fourth side of the semiconductor chip. A third pad group disposed near the side and disposed along the third side; and positioned closer to the fourth side than the third side of the semiconductor chip; and A fourth pad group arranged along the side,
In the step (c), in a plan view, each of the plurality of wires extends from the joint with the lead to the inside of the semiconductor chip beyond the joint with the electrode pad. The plurality of wires are connected to each of the plurality of electrode pads;
In the step (d), the resin is supplied from the first corner portion side of the semiconductor chip toward the second corner portion side. 請求項１６記載の半導体装置の製造方法において、
前記（ｃ）工程では、前記複数のワイヤのそれぞれにおいて、前記ワイヤの一部が前記電極パッドに接続された後、前記ワイヤの他部が前記リードに接続される、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 16,
In the step (c), in each of the plurality of wires, after a part of the wire is connected to the electrode pad, the other part of the wire is connected to the lead. 請求項１６記載の半導体装置の製造方法において、
前記（ｄ）工程では、前記半導体チップの前記第１角部側に設けられた前記支持リードの上面側および下面側から、または下面側から、前記樹脂が供給される、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 16,
In the step (d), the resin is supplied from an upper surface side and a lower surface side of the support lead provided on the first corner portion side of the semiconductor chip, or from a lower surface side. 請求項１６記載の半導体装置の製造方法において、
前記（ｄ）工程では、前記ダイパッドの前記下面は、前記樹脂から露出している、半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 16,
In the step (d), the lower surface of the die pad is exposed from the resin.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020136331A (en) * 2019-02-14 2020-08-31 株式会社日産アーク Semiconductor device and manufacturing method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117413238A (en) 2021-07-19 2024-01-16 萨思学会有限公司 Quality prediction using process data

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01170034A (en) * 1987-12-25 1989-07-05 Hitachi Ltd Lead frame and semiconductor device
JPH08236564A (en) 1995-02-28 1996-09-13 Nec Kyushu Ltd Semiconductor device
JP3062192B1 (en) * 1999-09-01 2000-07-10 松下電子工業株式会社 Lead frame and method of manufacturing resin-encapsulated semiconductor device using the same
IT1317559B1 (en) * 2000-05-23 2003-07-09 St Microelectronics Srl CHIP SUPPORT FRAME WITH LOW RESISTANCE INTERCONNECTIONS.
JP2003338519A (en) * 2002-05-21 2003-11-28 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2004095572A (en) * 2002-08-29 2004-03-25 Hitachi Ltd Semiconductor device and method for manufacturing the same
KR100555495B1 (en) * 2003-02-08 2006-03-03 삼성전자주식회사 Mold die for chip array-molding, array-molding equipment comprising the mold die and chip array-molding method
JP4570868B2 (en) * 2003-12-26 2010-10-27 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4307362B2 (en) * 2004-11-10 2009-08-05 パナソニック株式会社 Semiconductor device, lead frame, and lead frame manufacturing method
US7464854B2 (en) * 2005-01-25 2008-12-16 Kulicke And Soffa Industries, Inc. Method and apparatus for forming a low profile wire loop
JP2009049072A (en) * 2007-08-15 2009-03-05 Panasonic Corp Lead frame, semiconductor apparatus, method for manufacturing lead frame and semiconductor apparatus
JP4957513B2 (en) * 2007-11-05 2012-06-20 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method of semiconductor device
JP5448727B2 (en) * 2009-11-05 2014-03-19 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP5467959B2 (en) 2010-07-21 2014-04-09 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2012109435A (en) * 2010-11-18 2012-06-07 Renesas Electronics Corp Method for manufacturing semiconductor device
JP5795277B2 (en) * 2012-03-22 2015-10-14 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method and semiconductor device
JP6129645B2 (en) * 2013-05-29 2017-05-17 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device
JP6092084B2 (en) 2013-11-29 2017-03-08 アオイ電子株式会社 Semiconductor device and manufacturing method of semiconductor device
JP2015220248A (en) * 2014-05-14 2015-12-07 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method and semiconductor device
JP2018046242A (en) * 2016-09-16 2018-03-22 ルネサスエレクトロニクス株式会社 Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020136331A (en) * 2019-02-14 2020-08-31 株式会社日産アーク Semiconductor device and manufacturing method thereof

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