JP2018098938A - Drive system and power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely reduce a turn-off speed of a semiconductor switching element without generating a malfunction when overcurrent is detected.SOLUTION: When a drive control signal GLu for turning off a semiconductor switching element 20 is changed to an L level, a drive circuit 52 forms a discharge path between a gate electrode 23 of the semiconductor switching element 20 and a reference potential point 8 by turning on a transistor 74p. A discharge speed control circuit 100a includes: a resistance element 105a which is connected to the discharge path of the gate electrode 23; and a bypass switch 110a that is connected in parallel with the resistance element 105a. In accordance with a protection control signal SPu, the bypass switch 105a is controlled in such a manner that the bypass switch is turned on at a normal time in which overcurrent is not detected, and turned off when overcurrent is detected.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a drive system and a power conversion device, and more particularly to a drive system for a semiconductor switching element and a power conversion device including the semiconductor switching element.

  Generally, power conversion is performed by on / off control of power semiconductor switching elements represented by MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor). At this time, a drive circuit that charges and discharges the gate according to a signal for on / off control is applied to the voltage-driven semiconductor switching element.

  For example, in Japanese Patent Application Laid-Open No. 2002-27657 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2001-197724 (Patent Document 2), a gate drive circuit for a power semiconductor element is used between a normal time and an overcurrent time. A circuit configuration for gradually turning off the IGBT by switching the gate discharge path to increase the gate resistance value at the time of overcurrent is described.

JP 2002-27657 A JP 2001-197724 A

  As described in Patent Documents 1 and 2, when an overcurrent occurs, it is preferable to reduce the surge voltage by reducing the turn-off speed. However, in Patent Documents 1 and 2, there are a low-resistance gate discharge path used during a turn-off operation during normal time (that is, when no overcurrent is detected) and a high-resistance gate discharge path used during overcurrent detection. The discharge paths are connected in parallel, and each discharge path includes a switch and a resistance element connected in series.

  Therefore, when an overcurrent is detected, there is a problem that the timing of turning off the switch for forming the low-resistance gate discharge path is different from the timing of turning on the switch for forming the high-resistance gate discharge path. Concerned. Specifically, if both gate discharge paths are formed by mistake, there is a concern that the turn-off speed may be increased when an overcurrent is detected. On the contrary, if both gate discharge paths are not formed, there is a concern that the semiconductor switching element malfunctions due to the gate potential becoming unstable.

  Further, in the normal state, the gate discharge path and the gate charge path are complementarily formed and the gate is driven. However, in the configurations of Patent Documents 1 and 2, it is necessary to reliably cut off the gate charge path when overcurrent is detected. is there. As a result, it is necessary to reflect the presence / absence of overcurrent detection in the control of the switch for controlling the formation and non-formation of the gate discharge path and the gate charge path in the normal state, so that the control configuration of the switch is complicated. There is concern. As a result, there is a risk that not only the number of parts increases, but also problems due to the above-described shift in the on / off timing of the switch may easily occur.

  The present invention has been made to solve such problems, and an object of the present invention is to reliably reduce the turn-off speed of a semiconductor switching element without causing a malfunction when an overcurrent is detected. That is.

  In one aspect of the present invention, a semiconductor switching element driving system that is turned on / off in response to a driving control signal includes a driving circuit, a resistance element, and bypass switching. The drive circuit is configured to selectively execute an operation of charging the gate of the semiconductor switching element toward the first voltage and an operation of discharging the gate toward the second voltage in accordance with the drive control signal. The The resistance element is connected to a discharge path formed by a discharge operation by the drive circuit. The bypass switch is connected in parallel with the resistance element in the discharge path. The bypass switch changes from an on state to an off state in response to detection of an overcurrent of the semiconductor switching element.

  In another aspect of the present invention, a power conversion device includes a semiconductor switching element, a drive circuit, a resistance element, and bypass switching. The semiconductor switching element is turned on / off according to the drive control signal. The drive circuit selectively performs a charge operation for charging the gate of the semiconductor switching element toward the first voltage and a discharge operation for discharging the gate toward the second voltage in accordance with the drive control signal. The overcurrent detector configured is configured to detect an overcurrent of the semiconductor switching element. The resistance element is connected to a discharge path formed by a discharge operation by the drive circuit. The bypass switch is connected in parallel with the resistance element in the discharge path. The bypass switch changes from an on state to an off state in response to overcurrent detection by the overcurrent detector.

  According to the present invention, it is possible to reliably reduce the turn-off speed of the semiconductor switching element without causing malfunction when an overcurrent is detected.

It is a circuit diagram explaining the structure of the power converter device according to Embodiment 1 of the present invention. FIG. 3 is a circuit diagram illustrating a configuration of a drive system for a semiconductor switching element of a lower arm of the power conversion device according to the first embodiment. It is a circuit diagram explaining the structure of the power converter device 1b according to the modification of Embodiment 1. FIG. FIG. 6 is a circuit diagram illustrating a configuration of a power conversion device according to a second embodiment. FIG. 11 is a circuit diagram illustrating a configuration of a drive system for a lower arm semiconductor switching element in a power conversion device according to a second embodiment. FIG. 6 is a circuit diagram illustrating a circuit configuration of a power conversion device according to a third embodiment. FIG. 10 is a circuit diagram illustrating a configuration of a drive system for a semiconductor switching element of a lower arm in a power conversion device according to a third embodiment.

  Embodiments of the present invention will be described below in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram illustrating the configuration of the power conversion device according to the first embodiment of the present invention.

  Referring to FIG. 1, power conversion device 1 a according to the first embodiment is configured by a single-phase inverter, converts a DC voltage from DC power supply 17 connected to an input end into an AC voltage, and supplies load 5. Output. That is, the load 5 operates by receiving an AC voltage (single phase) having a frequency controlled by the power converter 1a.

  The DC power supply 17 can be configured by, for example, a DC / DC converter that boosts or steps down an output voltage from a DC power supply such as a solar battery or a battery. Alternatively, the DC power supply 17 can be configured by an AC / DC converter that converts the voltage of an AC power supply such as a system power supply into a DC voltage and outputs the DC voltage. The DC power supply 17 may be provided in the same housing as the power conversion device 1a, and may be provided on the same circuit board as the power conversion device 1a.

  The load 5 can be configured by, for example, a household electric appliance or an industrial electric appliance that operates by being supplied with an AC voltage from a system power supply of 50 Hz or 60 Hz. Alternatively, the load 5 is a component provided in a device such as a heating coil of an induction heating device or a power feeding coil of a wireless power feeding device that operates by receiving a high-frequency AC voltage of several tens kHz to several hundreds kHz. Also good. Furthermore, the load 5 may be an electric motor of a moving body such as a railway vehicle or an automobile, an electric motor provided in an elevator, an escalator or an industrial device, or a compressor of a refrigeration cycle apparatus such as an air conditioner or a refrigerator.

  The output frequency of power conversion device 1a according to the present embodiment is not particularly limited, and any device or apparatus can be applied to load 5 as long as it operates by receiving an AC voltage supply. it can.

  The power conversion device 1a includes a power supply wiring 18 connected to the positive terminal of the DC power supply 17, a power supply wiring 19 connected to the negative terminal of the DC power supply 17, and semiconductor switching elements 10, 20, 30, and 40. A full bridge circuit, a filter circuit 2 connected to the output terminal of the full bridge circuit, and a control unit 7 for controlling the operation of the full bridge circuit are provided.

  In the full bridge circuit, a U-phase arm circuit and a W-phase arm circuit are connected in parallel. The U-phase arm circuit includes a semiconductor switching element 10 connected between the power supply line 18 and the node Nu, a node Nu, and the like. And a semiconductor switching element 20 electrically connected to the power supply wiring 19. Similarly, the W-phase arm circuit includes a semiconductor switching element 30 connected between power supply line 18 and node Nw, and a semiconductor switching element 40 electrically connected between node Nw and power supply line 19. .

  In the present embodiment, among the semiconductor switching elements constituting each phase arm circuit, the semiconductor switching elements 10 and 30 connected to the power supply wiring 18 (positive side of the DC power supply 17) are also referred to as “upper arm elements”. The semiconductor switching elements 20 and 40 connected to the power supply wiring 18 (the negative electrode side of the DC power supply 17) are also referred to as “lower arm elements”. That is, in the single-phase inverter like the power conversion device 1a, the “opposing arm” is configured by the upper arm element and the lower arm element in each of the U phase and the W phase. Therefore, the semiconductor switching elements 10 and 30 that are upper arm elements correspond to “first semiconductor switching elements”, and the semiconductor switching elements 20 and 40 that are lower arm elements correspond to “second semiconductor switching elements”. .

  Although FIG. 1 illustrates the case where the semiconductor switching element is configured by a MOSFET, the semiconductor switching element may be configured by an IGBT. When the semiconductor switching elements 10 to 40 are constituted by MOSFETs, the diodes 15, 25, 35, and 45 are structurally formed as body diodes. When the semiconductor switching elements 10 to 40 are IGBTs, the diodes 15, 25, 35, and 45 can be provided by connecting the diode elements so that the semiconductor switching elements 10 to 40 are conducted in the direction opposite to the conduction direction of the IGBT.

  The semiconductor switching element can be made of a semiconductor material such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). In particular, it is known that a semiconductor switching element formed of a wide band gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond has a high switching speed and thus has a small loss.

  In the MOSFET using SiC as the semiconductor material, a body diode is structurally formed. However, there is a concern about an increase in loss due to a large voltage drop when a current flows through the body diode. For this reason, it is also possible to connect a diode element (for example, a Schottky barrier diode) whose voltage drop is smaller than that of the body diode in antiparallel with the MOSFET.

  The semiconductor switching element 10 has a positive electrode 11, a negative electrode 12, and a control electrode 13, and the semiconductor switching element 20 has a positive electrode 21, a negative electrode 22, and a control electrode 23. Similarly, the semiconductor switching element 30 has a positive electrode 31, a negative electrode 32, and a control electrode 33, and the semiconductor switching element 40 has a positive electrode 41, a negative electrode 42, and a control electrode 43.

  In the present embodiment, the positive electrode, the negative electrode, and the control electrode of the semiconductor switching element are defined as follows. When the semiconductor switching element is a MOSFET, the drain electrode is defined as a positive electrode, the source electrode is defined as a negative electrode, and the gate electrode is defined as a control electrode. When the semiconductor switching element is an IGBT, the collector electrode is defined as a positive electrode and an emitter. The electrode is defined as a negative electrode, and the gate electrode is defined as a control electrode.

  Filter circuit 2 includes reactors 3 a and 3 b and a capacitor 4. Reactor 3b is connected between node Nu of U-phase arm and load 5. Reactor 3a is connected between node Nw of the W-phase arm and load 5. Capacitor 4 is connected in parallel with load 5 on the connection side of reactors 3 a and 3 b and load 5.

  The control part 7 controls operation | movement of the power converter device 1a by controlling ON / OFF of the semiconductor switching element 10,20,30,40. The control unit 7 can be configured using an arithmetic processor such as a microcomputer and a logic circuit.

  For example, the control unit 7 is configured so that the output of the power conversion device 1a matches the target value based on the output of various sensors (not shown) that measure the voltage and current of each unit of the power conversion device 1a. A signal for controlling on / off of the switching elements 10, 20, 30, 40 is generated.

  Specifically, the control unit 7 controls the on / off of the semiconductor switching element 10 (U-phase upper arm) and the driving control signal GHu for controlling on / off of the semiconductor switching element 10 (U-phase upper arm). A signal GLu, a drive control signal GHw for controlling on / off of the semiconductor switching element 30 (W-phase upper arm), and a drive control signal GLw for controlling on / off of the semiconductor switching element 40 (W-phase lower arm) are output. Drive control signals GLu and GHu are output to control signal lines 151 and 154, respectively. Similarly, drive control signals GHw and GLw are output to control signal lines 251 and 254, respectively. Each control signal is set to a logic low level (hereinafter, also simply referred to as “L level”) during a period in which the corresponding semiconductor switching element is to be turned off, while being set to a logic high level in a period in which the corresponding semiconductor switching element is to be turned on. Level (hereinafter, also simply referred to as “H level”).

  Furthermore, the control part 7 is provided with the protection function for stopping operation | movement of the power converter device 1a, when abnormality is detected. For example, when the overcurrent detector 6 detects an overcurrent of the semiconductor switching element, the control unit 7 generates the protection control signals SPu and SPw. Protection control signals SPu and SPw are output to control signal lines 157 and 257, respectively.

  The overcurrent detector 6 indicates that, for example, the passing current of each semiconductor switching element has exceeded a predetermined threshold based on the output voltage of a shunt resistor provided in each semiconductor switching element 10, 20, 30, 40. Can be configured to detect. Alternatively, the overcurrent detector 6 may be configured to detect an overcurrent when an excessive current is output from the inverter due to a short circuit of the load 5 or the like. In this case, the overcurrent detector 6 can be configured by a current sensor for detecting a current supplied from the power conversion device 1a to the load 5.

  When the overcurrent detector 6 detects that a current exceeding a predetermined reference value has flowed by these current sensors and shunt resistors, the overcurrent detector 6 notifies the control unit 7 of the detection of the overcurrent by the output of the abnormality detection signal Sfl. To do.

  The control unit 7 maintains the protection control signals SPu and SPw at the default L level when no overcurrent is detected (that is, during normal operation). On the other hand, the control unit 7 sets the protection control signals SPu and SPw to the H level when the overcurrent detector 6 outputs the abnormality detection signal Sfl, that is, when overcurrent is detected.

  In an insulated gate semiconductor switching element such as a MOSFET or IGBT, a parasitic capacitance exists between a control electrode (gate) and a negative electrode (source or emitter). The semiconductor switching element is turned on when the parasitic capacitance is charged and the voltage between the control electrode and the negative electrode (gate-source voltage) is higher than the threshold voltage. On the other hand, the semiconductor switching element is turned off when the parasitic capacitance is discharged and the voltage (gate-source voltage) between the control electrode and the negative electrode is lower than the threshold voltage.

  Therefore, the power conversion device 1a has a drive system for charging / discharging the gate electrodes, which are control electrodes of the semiconductor switching elements 10, 20, 30, 40, according to the drive control signals GHu, GLu, GHw, GLw. Drive circuits 51, 52, 53, 54, control power supplies 101, 102, bootstrap circuits 111u, 111w, and smoothing capacitors 16, 26, 36, 46 are further arranged.

  First, the configuration of the drive system for the semiconductor switching elements 10 and 20 in the U-phase arm circuit will be described.

  In the U-phase arm circuit, a control power supply 101, a bootstrap circuit 111u, and smoothing capacitors 16 and 26 are arranged. The smoothing capacitor 26 is connected in parallel with the control power supply 101. The smoothing capacitor 16 is connected to the positive electrode of the control power supply 101 via the bootstrap circuit 111u. The bootstrap circuit 111u includes a diode 112 and a current limiting resistor 113.

  The smoothing capacitor 16 is charged to a voltage equivalent to that of the control power supply 101 by the bootstrap circuit 111u. The negative electrode of the smoothing capacitor 16 and the negative electrode (source) of the semiconductor switching element 10 are electrically connected inside the drive circuit 51. Alternatively, the negative electrode of the smoothing capacitor 16 and the negative electrode of the semiconductor switching element 10 can be electrically connected outside the drive circuit 51.

  A drive circuit 52 is arranged corresponding to the semiconductor switching element 20 of the lower arm. A drive control signal GLu is input to the drive circuit 52 through a control signal line 151. The drive circuit 52 turns on and off the semiconductor switching element 20 by charging and discharging the gate electrode 23 of the semiconductor switching element 20 in accordance with the drive control signal GLu. Further, a discharge rate control circuit 100 a is disposed between the drive circuit 52 and the reference potential point 8. The reference potential point 8 is electrically connected to the smoothing capacitor 26, the negative electrode of the control power source 101, and the negative electrode (source electrode) 22 of the semiconductor switching element 20.

  The discharge speed control circuit 100a includes a resistance element 105a and a bypass switch 110a. The resistance element 105 a is connected in series with a gate resistance described later in a discharge path between the gate electrode 23 of the semiconductor switching element 20 and the reference potential point 8. The bypass switch 110a is connected in parallel with the resistance element 105a in the discharge path.

  The bypass switch 110a is turned on / off according to the protection control signal SPu transmitted from the control unit 7 through the control signal line 157 (FIG. 1). Specifically, the bypass switch 110a is turned on during the L level period (normal time) of the protection control signal SPu, and is turned off during the H level period (when overcurrent is detected) of the protection control signal SPu.

  The configuration of the drive system of the lower arm semiconductor switching element 20 will be further described with reference to FIG.

  Referring to FIG. 2, drive circuit 52 of semiconductor switching element 20 includes a transistor 74 n configured by an npn transistor, a transistor 74 p configured by a pnp transistor, and a gate resistor 84.

  Transistor 74n is connected between power supply line 71 and node N1. Transistor 74p is connected between node N1 and power supply line 72. The gate resistor 84 is connected between the node N1 and the gate electrode 23 of the semiconductor switching element 20.

  The power supply line 71 is electrically connected to the smoothing capacitor 26 and the positive electrode of the control power supply 101. The power supply line 72 is electrically connected to the reference potential point 8 via the discharge rate control circuit 100a.

  Control electrodes (bases) of the transistors 74n and 74p are connected to the control signal line 151. Therefore, the transistor 74n is turned on during the H level period of the drive control signal GLu. At this time, a driving current for charging the gate electrode 23 is supplied from the power supply line 71 to the gate electrode 23 by the transistor 74n. As a result, the gate electrode 23 is driven to the high voltage side by the charging path via the gate resistor 84. Accordingly, the semiconductor switching element 20 is turned on as the gate-source voltage becomes higher than the threshold voltage.

  On the other hand, in the L level period of the drive control signal GLu, the transistor 74n is turned off while the transistor 74p is turned on. As a result, when the discharge path from the gate electrode 23 to the reference potential point 8 via the gate resistor 84 is formed and the gate-source voltage becomes lower than the threshold voltage, the semiconductor switching element 20 is turned off.

  The discharge path from the gate electrode 23 of the semiconductor switching element 20 to the reference potential point 8 is formed by eliminating the resistance element 105a when the bypass switch 110a is turned on. At this time, the discharge rate of the gate electrode 23 is defined by the resistance value of the gate resistor 84.

  On the other hand, when the bypass switch 110a is turned off, the gate resistor 84 and the resistance element 105a are connected in series in the discharge path from the gate electrode 23 to the reference potential point 8. The discharge rate at this time is defined by the sum of the electrical resistances of the gate resistor 84 and the resistance element 105a. Therefore, when the bypass switch 110a is turned off, the electrical resistance value of the discharge path is higher than when the bypass switch 110a is turned on, so that the discharge current of the gate electrode 23 is lowered. As a result, it is understood that the discharge rate of the gate electrode 23 is lowered and the turn-off of the semiconductor switching element 20 is moderated.

  In this way, during the normal time when the protection control signal SPu is at the L level (when no overcurrent is detected), the bypass switch 110a is turned on, so that the discharge rate of the gate electrode 23 is set high, and the semiconductor switching Element 20 is immediately turned off. Thereby, switching loss can be suppressed.

  On the other hand, when an overcurrent is detected in which the protection control signal SPu is at the H level, the bypass switch 110a is turned off, so that the discharge rate for turning off the gate electrode 23 is lowered. As a result, when an overcurrent occurs, the turn-off speed can be moderated to suppress the surge voltage.

  The configuration of the drive circuit 52 shown in FIG. 2 is merely an example, and the drive circuit 52 can also be configured by a gate circuit configured by a gate drive integrated circuit or the like. In other words, the drive circuit 52 can adopt any configuration as long as it has a function of charging and discharging the gate electrode 23 in accordance with a control signal.

  Referring to FIG. 1 again, the upper arm drive circuit 51 can be configured similarly to the drive circuit 52 shown in FIG. In this case, the transistor 74n and the transistor 74p are connected to the gate electrode 13 (semiconductor switching element 10) similarly to the configuration of FIG. 2, and the control electrode (base) of the transistor 74n and the transistor 74p is driven and controlled. It can be connected to a control signal line 154 that transmits the signal GHu.

  Similarly to the semiconductor switching element 10, the boot switching circuit 111 w including the drive circuit 53, the smoothing capacitor 36, the diode 122, and the current limiting resistor 123 is provided for the semiconductor switching element 30 of the W-phase upper arm. The smoothing capacitor 36 is charged by the control power supply 102 via the bootstrap circuit 111w. The drive circuit 53 is configured to have the same function as the drive circuit 51. Specifically, the drive circuit 53 is configured to charge or discharge the gate electrode 33 of the semiconductor switching element 30 in accordance with the drive control signal GHw transmitted by the control signal line 251 (FIG. 1).

  A drive circuit 54, a discharge speed control circuit 100b having a resistance element 105b and a bypass switch 110b, a control power source 102 and a smoothing capacitor 46 are arranged for the semiconductor switching element 40 of the W-phase lower arm. The drive system for the semiconductor switching element 40 can also be configured in the same manner as the drive system for the semiconductor switching element 20 described with reference to FIG.

  In other words, the discharge rate control circuit 100 b is disposed between the drive circuit 54 and the reference potential point 9. The reference potential point 9 is electrically connected to the smoothing capacitor 46, the negative electrode of the control power source 102, and the negative electrode (source electrode) 42 of the semiconductor switching element 40. The drive control signal GLu is input to the drive circuit 54 through the control signal line 254. The drive circuit 54 turns on and off the semiconductor switching element 40 by charging and discharging the gate electrode 43 of the semiconductor switching element 40 in accordance with the drive control signal GLu.

  Specifically, in the configuration of FIG. 2, the control power supply 101, the smoothing capacitor 26, the resistance element 105a, and the bypass switch 110a are replaced with the control power supply 102, the smoothing capacitor 46, the resistance element 105b, and the bypass switch 110b. A drive system of the switching element 40 can be configured.

  Further, the drive circuit 54 connects the npn transistor and the control electrode (base) of the pnp transistor similar to the drive circuit 52 shown in FIG. 2 to the control signal line 254, so that the semiconductor switching is performed according to the protection control signal SPu. The gate electrode 43 of the element 40 can be configured to be charged / discharged.

  In the discharge speed control circuit 100b, the bypass switch 110b is controlled to turn on when the protection control signal SPw transmitted through the control signal line 257 is at L level, and to be turned off when SPw is at H level. Therefore, also in the semiconductor switching element 40, during the normal time when the protection control signal SPw is at the L level (when no overcurrent is detected), the discharge rate of the gate electrode 43 is set high, and the semiconductor switching element 20 quickly Turned off. Thereby, switching loss can be suppressed. On the other hand, at the time of overcurrent detection in which the protection control signal SPw is at the H level, the semiconductor switching element 40 is gently turned off, so that the surge voltage can be suppressed.

Next, operation | movement of the power converter device 1a is demonstrated.
Normally, the control unit 7 maintains the protection control signals SPu and SPw at the L level, so that the bypass switches 110a and 110b are maintained in the on state. In this state, the control unit 7 performs the semiconductor switching elements 10 and 20 so that the power conversion is performed so that the output (AC voltage) of the power conversion device 1a matches the target value (amplitude, frequency, phase, etc.). , 30, 40 drive control signals GHu, GLu, GHw, GLw are generated.

  At this time, when the semiconductor switching elements 20 and 40 of the lower arm are turned off according to the drive control signals GLu and GLw, the resistance elements 105a and 105b are not included in the discharge path of the gate electrodes 23 and 43. . Accordingly, when the semiconductor switching elements 10, 20, 30, and 40 are turned off for power conversion, the electrical resistance value of the discharge path is low, so that the discharge speed is high, and the switching loss is suppressed by being turned off at high speed. The

  On the other hand, when an overcurrent is detected by the overcurrent detector 6, the control unit 7 changes the protection control signals SPu and SPw from the L level to the H level according to the abnormality detection signal Sfl. Thereby, each of bypass switches 110b and 110b changes from the on state to the off state. Thus, the resistance elements 105a and 105b are connected in series with the gate resistor 84 (FIG. 2) in the discharge path of the gate electrodes 23 and 43. As a result, the electrical resistance value of the discharge path becomes higher than normal (when no overcurrent is detected).

  In this state, the control unit 7 sets the drive control signals GHu, GLu, GHw, and GLw to the L level to forcibly activate the semiconductor switching elements 10, 20, 30, and 40 in order to protect the semiconductor switching elements. Turn off.

  At this time, the semiconductor switching elements 20 and 40 in the lower arm, in which the discharge rate control circuits 100a and 100b are arranged, have a higher electrical resistance value in the discharge path than usual, so that the discharge rate is lowered and the semiconductor switching devices 20 and 40 are gradually turned off. Is done.

  Therefore, according to the power conversion device having the drive system according to the first embodiment, the semiconductor in the event of an overcurrent due to a sudden operation fluctuation of the load 5, a sudden output fluctuation of the DC power supply 17, or an arm short circuit or the like. It is possible to suppress the generation of a surge voltage when the switching element is forcibly turned off.

  In particular, voltage-driven semiconductor switching elements (such as MOSFETs and IGBTs) formed of wide band gap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), or diamond have a high switching speed during normal operation. Although there is a concern that the surge voltage will become excessive if it is turned off to generate overcurrent at the same switching speed, the surge voltage can be suppressed by applying the drive system according to the present embodiment.

  In the configuration according to the first embodiment, as described with reference to FIG. 2, the electrical resistance value of the discharge path of the gate electrode can be switched by turning on / off only the bypass switch 110a. For this reason, unlike the configurations of switching between two discharge paths connected in parallel by two switches as in Patent Documents 1 and 2, the electrical resistance of the discharge path caused by the deviation of the on / off timing of the two switches It is possible to reliably avoid the occurrence of a problem that the value becomes lower than normal at the time of overcurrent detection or the discharge path of the gate electrode disappears.

  Furthermore, in the configuration according to the first embodiment, the discharge path of the gate electrode is not formed even if the bypass switch 110a is switched on and off while the transistor 74n for charging the gate electrode is on. For this reason, unlike the configurations of Patent Documents 1 and 2, the semiconductor switching element 20 does not malfunction even if the timings of turning on and off the transistors 74n and 74p and on and off of the bypass switch 110a are shifted. Since the discharge path of the gate electrode 23 is formed regardless of whether the bypass switch 110a is turned on or off, the semiconductor switching elements 20 and 40 are reliably turned off by setting the drive control signals GLu and GLw to the L level. be able to.

  When the control unit 7 receives the abnormality detection signal Sfl from the overcurrent detector 6 in order to reliably turn off the semiconductor switching elements 20 and 40 with the bypass switches 110a and 110b turned off, A certain time delay may be set between the timing when the protection control signals SPu and SPw are changed to the H level and the timing when the drive control signals GHu, GLu, GHw and GLw are set to the L level. The bypass switches 110a and 110b are preferably constituted by semiconductor switches in order to turn on and off at high speed.

  Further, as a modification of the configuration of FIG. 2, the protection control signals SPu and SPw are input to the drive circuit 52, and the transistor 74n is forcibly turned off when the protection control signals SPu and SPw are at the H level. It is also possible to do. For example, a logic that outputs a logical product (AND) of the drive control signal GHu or GLu and the inverted signals of the protection control signals SPu and SPw (L level when overcurrent is detected) to the control electrode (base) of the transistor 74n. A gate can be placed.

  1 exemplifies a configuration in which the discharge rate control circuits 100a and 100b are arranged only in the drive system of the semiconductor switching elements 20 and 40 of the lower arm. Therefore, even when it is desired to finally turn off the semiconductor switching elements 10, 20, 30, 40 due to overcurrent, the lower arm semiconductor switching elements 20, 40 are first turned off and then the upper arm semiconductor switching element. Need to turn off.

  If the semiconductor switching elements 10 and 30 of the upper arm are turned off first, the semiconductor switching elements 10 and 30 in which the discharge speed control circuit is not arranged are high-speed even when an overcurrent occurs as in the normal case. This is because when the overcurrent is cut off, an excessive surge voltage may be generated or the drive circuit may malfunction.

Or it is also possible to comprise a power converter device like the modification shown by FIG.
Referring to FIG. 3, power conversion device 1 b according to the modification of the first embodiment discharges corresponding to semiconductor switching elements 10 and 30 of the upper arm as compared with power conversion device 1 a (FIG. 1). Speed control circuits 100c and 100d are further arranged. Since the configuration and operation of other parts of power conversion device 1b are the same as in FIG. 1, detailed description will not be repeated.

  The discharge speed control circuit 100c includes a resistance element 105c and a bypass switch 110c connected in parallel with the resistance element 105c. Similarly, the discharge speed control circuit 100d includes a resistance element 105d and a bypass switch 110d connected in parallel with the resistance element 105d.

  The control unit 7 further outputs protection control signals SPuh and SPwh in addition to the protection control signals SPu and SPw. The protection control signal SPuh is transmitted to the bypass switch 115c via the control signal line 158, and the protection control signal SPwh is transmitted to the bypass switch 115d via the control signal line 258.

  Similarly to the protection control signals SPu and SPw, the control unit 7 maintains the protection control signals SPuh and SPwh at the L level during normal operation, while protecting according to the output of the abnormality detection signal Sfl from the overcurrent detector 6. The control signals SPuh and SPwh are changed from the L level to the H level.

  The bypass switches 110c and 110d are configured in the same manner as the bypass switches 110a and 110b, and are controlled so as to be turned off during the L level period of the protection control signals SPuh and SPwh while being turned on during the H level period.

  Thus, when the semiconductor switching elements 10 and 30 are turned off in accordance with the drive control signals GHu and GHw, the resistance elements 105c and 105d are bypassed to form the discharge paths of the gate electrodes 13 and 33 in the normal state. When detecting an overcurrent, a discharge path in which a resistance element corresponding to the gate resistor 84 of FIG. 2 and the resistance elements 105c and 105d are connected in series can be formed.

  Therefore, in the power conversion device 1b, similarly to the semiconductor switching elements 20 and 40 of FIG. 1, the turn-off speed is reduced for the upper arm semiconductor switching elements 10 and 30, and the surge voltage is suppressed. As a result, even in the configuration of the power conversion device in which all the semiconductor switching elements need to be turned off at the same time, the semiconductor switching elements are forcibly turned off for protection in response to the overcurrent detection. Surge voltage can be suppressed.

  Or unlike FIG. 1 and FIG. 3, it is also possible to arrange | position a discharge control circuit only with respect to the semiconductor switching element of an upper arm. As described above, in the power conversion device according to the present embodiment, the discharge control circuit shown in FIGS. 1 and 2 can be arranged for any semiconductor switching element.

Embodiment 2. FIG.
FIG. 4 is a circuit diagram illustrating a configuration of power conversion device 1c according to the second embodiment.

  Referring to FIG. 4, power conversion device 1 c according to the second embodiment is driven between lower arm semiconductor switching elements 20 and 40 as compared with power conversion device 1 a (FIG. 1) according to the first embodiment. The difference is that the system is shared.

  In the configuration example of FIG. 4, one drive circuit 55 is arranged for the semiconductor switching elements 20 and 40 instead of the drive circuits 52 and 54 of FIG. 1. On the other hand, drive circuits 51 and 53 similar to those in FIG. 1 are arranged for the upper arm semiconductor switching elements 10 and 30. Furthermore, in the configuration of FIG. 4, the semiconductor switching elements 10, 20, 30, and 40 and the drive circuits 51, 53, and 55 may be stored in the same power module 200.

  For the semiconductor switching elements 10 and 30 of the upper arm, the control power supply 101, the bootstrap circuit 111u, and the smoothing capacitor 16 are connected to the connection terminal to the drive circuit 51 provided in the power module 200, as shown in FIG. Connections can be made in the same manner as the circuit configuration. Further, the control power supply 101, the bootstrap circuit 111w, and the smoothing capacitor 36 shared with the drive circuit 51 can be connected to the connection terminal to the drive circuit 53. Thereby, the drive system of the semiconductor switching elements 10 and 30 can be comprised similarly to the power converter device 1a.

  On the other hand, a discharge rate control circuit 100 is commonly arranged for the semiconductor switching elements 20 and 40 of the lower arm. Discharge rate control circuit 100 includes a resistance element 105 and a bypass switch 110 connected in parallel with resistance element 105. Furthermore, the reference potential point 8 is also connected to the negative electrode (source electrode) 42 of the semiconductor switching element 40 as shown in FIG.

  Protection control signal SPu similar to that of power conversion device 1a according to the first embodiment is transmitted from control unit 7 to bypass switch 110 through control signal line 157. Similarly to the bypass switch 110a, the bypass switch 110 is controlled to be turned on during the L level period (normal time) of the protection control signal SPu while being turned off during the H level period (when overcurrent is detected).

  FIG. 5 shows a configuration of a drive system for the semiconductor switching element of the lower arm in power conversion device 1c according to the second embodiment.

  Referring to FIG. 5, drive circuit 55 further includes transistors 75 n, 75 p and gate resistor 85 connected to semiconductor switching element 20 in addition to transistors 74 n and 74 p and gate resistor 84 connected to semiconductor switching element 20. Including.

  Transistors 74n, 74p and gate resistor 84 are connected to gate electrode 23 of semiconductor switching element 20 similarly to drive circuit 52 shown in FIG. 2, and therefore detailed description will not be repeated.

  Transistor 75n is formed of an npn transistor similarly to transistor 74n, and is connected between power supply line 71 and node N2. The transistor 75p is formed of a pnp transistor similarly to the transistor 74p, and is connected between the node N2 and the power supply line 72. The gate resistor 85 is connected between the node N <b> 2 and the gate electrode 43 of the semiconductor switching element 40. Control electrodes (bases) of the transistors 75n and 75p are connected to a control signal line 254 that transmits a drive control signal GLw from the control unit 7. Therefore, when the transistor 75n or 75n is turned on in accordance with the drive control signal GLw, the gate electrode 43 is charged (turned on) or discharged (turned off).

  As understood from FIG. 5, a part of the discharge path to the reference potential point 8 is shared between the gate electrode 23 of the semiconductor switching element 20 and the gate electrode 43 of the semiconductor switching element 40.

  Discharge rate control circuit 100 is arranged such that resistance element 105 and bypass switch 110 are connected to the common portion of the discharge path. Thus, when the bypass switch 110 is off, the gate resistor 84 and the resistor element 105 are connected in series to the discharge path of the gate electrode 23, while the gate resistor 85 and the resistor element 105 are connected to the discharge path of the gate electrode 43. Are connected in series. On the other hand, when the bypass switch 110 is turned off, the discharge paths of the gate electrodes 23 and 43 are formed by bypassing the resistance element 105.

  Therefore, in the normal state (when no overcurrent is detected), the semiconductor switching elements 20 and 40 are connected to suppress the switching loss in accordance with the drive control signals GLu and GWu without connecting the resistance element 105 to the discharge path. Can be turned off at high speed. On the other hand, at the time of overcurrent detection, the resistive element 105 can be connected in series with the gate resistors 84 and 85 to both the discharge paths of the gate electrode 23 and the gate electrode 43.

  Thus, even in the power conversion device according to the second embodiment, the discharge speed control circuit 100 shared by the lower arm semiconductor switching elements 20 and 40 can provide the same effects as in the first embodiment. The number of parts can be reduced.

  Further, the power module 200 incorporating the drive circuits 51, 53, and 55 is configured to externally connect a single discharge speed control circuit 100 to turn off both the lower arm semiconductor switching elements 20 and 40. Appropriate control can be performed in each of normal time and overcurrent detection. The resistance element 105 has an appropriate electrical resistance value that depends on the allowable surge voltage value of the semiconductor switching element, the amount of passing current, the electrical resistance value of the gate resistance in the drive circuit, etc. Can be configured using resistance elements of several Ω to several tens Ω.

  4 is combined with FIG. 3, and the discharge rate control circuit 100 is arranged only between the semiconductor switching devices 20 and 40 of the lower arm in the configuration in which the discharge rate control circuit is arranged for each semiconductor switching device. It is also possible to share. In this case, discharge speed control circuits 100c and 100d similar to those in FIG. 1 are arranged for the upper arm semiconductor switching elements 10 and 30, respectively. Since the potential of the negative electrode (source or emitter electrode) is not always common between the semiconductor switching elements 10 and 30 in the upper arm, the discharge control is performed like the semiconductor switching element in the lower arm shown in FIG. It is difficult to share the circuit.

Embodiment 3 FIG.
FIG. 6 is a circuit diagram illustrating a circuit configuration of power conversion device 1d according to the third embodiment.

  Referring to FIG. 6, power converter 1 d according to the third embodiment is implemented in that the U-phase arm circuit and the W-phase arm circuit of the single-phase inverter are configured using power modules 210 and 230, respectively. This is different from the configuration of the first embodiment.

  The power module 210 includes three sets of arm circuits including an arm circuit including the semiconductor switching elements 10a and 20a, an arm circuit including the semiconductor switching elements 10b and 20b, and an arm circuit including the semiconductor switching elements 10c and 20c. Circuits 51 and 52 are incorporated.

  In the power module 210, the U-phase upper arm is configured by the semiconductor switching elements 10a, 10b, and 10c connected in parallel. In other words, the positive electrodes (drain electrodes or collector electrodes) of the semiconductor switching elements 10 a, 10 b, and 10 c are electrically connected to the power supply wiring 18 via the terminal 221. Further, the negative electrodes (source electrodes or emitter electrodes) of the semiconductor switching elements 10a, 10b, and 10c are electrically connected to the node Nu in common via the terminals 222 to 224, and inside the drive circuit 51, It is electrically connected to the negative electrode of the smoothing capacitor 16 via the terminal 215. That is, the semiconductor switching elements 10a, 10b, and 10c correspond to an example of “a plurality of first semiconductor switching elements”.

  Similarly, the lower arm of the U phase is configured by the semiconductor switching elements 20a, 20b, and 20c connected in parallel. That is, the positive electrodes (drain electrodes or collector electrodes) of the semiconductor switching elements 20a, 20b, and 20c are electrically connected to the node Nu via the terminals 222 to 224. Further, the negative electrodes (source electrodes or emitter electrodes) of the semiconductor switching elements 20a, 20b, and 20c are connected to the terminals 225 to 227, so that they are electrically connected to the power supply wiring 19 via the common negative electrode connection point 106u. Connected. The semiconductor switching elements 20a, 20b, and 20c correspond to an example of “a plurality of second semiconductor switching elements”.

  The drive circuit 51 charges (turns on) or discharges (turns off) the gate electrodes of the semiconductor switching elements 10a, 10b, and 10c constituting the upper arm in accordance with drive control signals input to the terminals 211, 212, and 213. Configured to do. The terminals 211 to 213 are connected in common with the control signal line 154. Therefore, the semiconductor switching elements 10a, 10b and 10c connected in parallel are controlled to be turned on and off in common according to the drive control signal GHu. Further, power supply terminals 214 and 215 for power input of the drive circuit 51 are connected to the positive terminal and the negative terminal of the smoothing capacitor 16, respectively.

  Similarly, the drive circuit 52 charges (turns on) or discharges the respective gate electrodes of the semiconductor switching elements 20a, 20b, and 20c constituting the lower arm in accordance with the drive control signals input to the terminals 216, 217, and 218. Configured to (turn off). The terminals 216 to 218 are connected in common with the control signal line 151. Therefore, the semiconductor switching elements 20a, 20b and 20c connected in parallel are controlled to be turned on / off in common according to the drive control signal GLu. The power supply input terminals 219 and 220 of the drive circuit 52 are connected to the positive terminal and the negative terminal of the smoothing capacitor 26, respectively.

  In the W-phase arm circuit, power module 230 includes three sets of an arm circuit composed of semiconductor switching elements 30a and 40a, an arm circuit composed of semiconductor switching elements 30b and 40b, and an arm circuit composed of semiconductor switching elements 30c and 40c. An arm circuit and drive circuits 53 and 54 are incorporated.

  In the power module 230, the upper arm of the W phase is configured by the semiconductor switching elements 30a, 30b, and 30c connected in parallel. That is, the positive electrodes (drain electrodes or collector electrodes) of the semiconductor switching elements 30 a, 30 b, and 30 c are electrically connected to the power supply wiring 18 via the terminal 241. Further, the negative electrodes (source electrodes or emitter electrodes) of the semiconductor switching elements 30a, 30b, and 30c are electrically connected to the node Nw in common via the terminals 242 to 244, and within the drive circuit 51, It is electrically connected to the negative electrode of the smoothing capacitor 36 via the terminal 235. The semiconductor switching elements 30a, 30b, and 30c also correspond to an example of “a plurality of first semiconductor switching elements”.

  Similarly, in the power module 230, the W-phase lower arm is constituted by the semiconductor switching elements 40a, 40b, and 40c connected in parallel. That is, the positive electrodes (drain electrodes or collector electrodes) of the semiconductor switching elements 40a, 40b, and 40c are electrically connected to the node Nw via the terminals 242 to 244. Further, the negative electrodes (source electrodes or emitter electrodes) of the semiconductor switching elements 40a, 40b, and 40c are connected to the terminals 245 to 247, so that they are electrically connected to the power supply wiring 19 via the common negative electrode connection point 106w. Connected. The semiconductor switching elements 40a, 40b, and 40c also correspond to an example of “a plurality of second semiconductor switching elements”.

  The drive circuit 53 charges (turns on) or discharges (turns off) the gate electrodes of the semiconductor switching elements 30a, 30b, and 30c constituting the upper arm in accordance with drive control signals input to the terminals 231, 232, and 233. Configured to do. The terminals 231 to 233 are connected to the control signal line 251 in common. Therefore, each of semiconductor switching elements 30a, 30b and 30c connected in parallel is controlled to be turned on / off in common according to drive control signal GHw. Further, power supply terminals 234 and 235 for power supply input of drive circuit 53 are connected to a positive terminal and a negative terminal of smoothing capacitor 36, respectively.

  Similarly, the drive circuit 54 charges (turns on) or discharges the respective gate electrodes of the semiconductor switching elements 40a, 40b, and 40c constituting the lower arm in accordance with the drive control signals input to the terminals 236, 237, and 238. Configured to (turn off). The terminals 236 to 238 are connected in common with the control signal line 254. Therefore, the semiconductor switching elements 40a, 40b and 40c connected in parallel are controlled to be turned on / off in common according to the drive control signal GLw. Further, the power input terminals 239 and 240 of the drive circuit 54 are connected to the positive terminal and the negative terminal of the smoothing capacitor 46, respectively.

  In the configuration example of FIG. 6, the control power supplies 103 and 104 are arranged corresponding to the upper arm drive circuits 51 and 53, respectively, but the bootstrap circuits 111u and 111w are arranged as in FIG. As a result, it is also possible to supply operating power for the drive circuits 51 and 53 by the control power supplies 101 and 102 for the lower arm. Or, conversely, in each of the configuration examples of FIGS. 1 and 3, the control power sources 103 and 104 similar to those in FIG. 6 may be arranged in place of the bootstrap circuits 111u and 111w.

  FIG. 7 is a circuit diagram showing the configuration of the drive system for the semiconductor switching elements 20a to 20c of the U-phase lower arm.

  Referring to FIG. 7, in power conversion device 1d according to the third embodiment, drive circuit 52 includes transistors 74pa, 74pb, and 74pc, transistors 74na, 74nb, and 74nc, and gate resistors 84a, 84b, and 84c. Power supply line 71 is connected to smoothing capacitor 26 and the positive terminal of control power supply 101 via terminal 219. Similarly, the power supply line 72 is connected to the smoothing capacitor 26 and the negative terminal of the control power supply 101 via the terminal 220. The reference potential point 8 is electrically connected to the negative electrodes (source electrodes) 22a to 22c of the semiconductor switching elements 20a to 20c outside the power module 210.

  Transistors 74na and 74pa and gate resistor 84a are connected to gate electrode 23a of semiconductor switching element 20a in the same manner as transistors 74n and 74p and gate resistor 84 are connected to gate electrode 23 in drive circuit 52. . Similarly, the transistors 74nb and 74pb and the gate resistor 84b are connected to the gate electrode 23b of the semiconductor switching element 20b in the same manner as the transistors 74na and 74pa and the gate resistor 84a are connected to the gate electrode 23a. Further, the transistors 74nc and 74pc and the gate resistor 84c are connected to the gate electrode 23c of the semiconductor switching element 20c in the same manner as the transistors 74na and 74pa and the gate resistor 84a are connected to the gate electrode 23a.

  Control electrodes (bases) of the transistors 74pa, 74pb, 74pc, 74na, 74nb, and 74nc are connected in common with a control signal line 151 that transmits a drive control signal GLu via terminals 216 to 218. As a result, in the H level period of the drive control signal GLu, the transistors 74na, 74nb, 74nc are turned on, whereby the gate electrodes 23a for turning on the semiconductor switching elements 20a-20c with respect to the gate electrodes 23a, 23b, 23c are turned on. To 23c are formed through the gate resistors 84a, 84b, and 84c, respectively.

  On the other hand, during the L level period of the drive control signal GLu, when the transistors 74pa, 74pb, and 74pc are turned on, a charging path for turning off the semiconductor switching elements 20a to 20c is provided for the gate electrodes 23a, 23b, and 23c. , Formed between the gate electrodes 23 a to 23 c and the reference potential point 8. That is, the discharge paths of the gate electrodes 23 a to 23 c share a part of the path reaching the reference potential point 8 via the power supply line 72 and the terminal 220.

  The discharge rate control circuit 100a is connected between the terminal 220 and the reference potential point 8, thereby being connected to the common part of the discharge path of the gate electrodes 23a, 23b, and 23c. Therefore, when bypass switch 110a is off, resistance element 105a is connected in series to each of gate resistors 84a to 84c in each of the discharge paths of gate electrodes 23a to 23c. As a result, the turn-off speeds of the semiconductor switching elements 20a to 20c can be made uniform and reduced.

  On the other hand, when the bypass switch 110a is turned on, each of the discharge paths of the gate electrodes 23a to 23c can be formed excluding the resistance element 105a. Therefore, normally, the semiconductor switching elements 20a to 20c are turned off at high speed in order to suppress the switching loss according to the electric resistance values of the gate resistors 84a to 84c.

  In the drive system for the W-phase lower arm semiconductor switching element 40, the drive circuit 54 and the discharge rate control circuit 100b are arranged in the same manner as the drive circuit 52 and the discharge rate control circuit 100a described in FIG. The explanation is not repeated. That is, by switching on / off of the bypass switch 110b in accordance with the protection control signal SPw similar to that of the first embodiment, the turn-off speed of the semiconductor switching elements 40a to 40c is switched at normal time (when no overcurrent is detected). In order to suppress the loss, it can be controlled to be high, and when overcurrent is detected, it can be controlled to be low to suppress the surge voltage.

  As described above, in the power conversion device according to the third embodiment, by connecting the discharge rate control circuit outside the module to the configuration in which the plurality of semiconductor switching elements and the drive circuit connected in parallel are modularized, The turn-off of the semiconductor switching elements 20 and 40 in the lower arm can be appropriately controlled at each of the normal time and the overcurrent detection time.

  Also in the configuration of the third embodiment, by adjusting the electric resistance values of the resistance elements 105a and 105b connected externally, the surge voltage allowable value and the passing current of the semiconductor switching element can be applied to a power module having an arbitrary characteristic. It is possible to set an appropriate turn-off speed for the quantity.

  In the configuration example of FIG. 6, the discharge speed control circuits 100a and 100b are arranged only for the semiconductor switching elements 20 and 40 of the lower arm, but the semiconductor switching elements 10 and 30 of the upper arm are arranged as in FIG. Corresponding discharge rate control circuits 100c and 100d can be further connected to the outside of the power modules 210 and 230.

  Alternatively, the discharge speed control circuits 100a and 100b for the semiconductor switching elements 20 and 40 are separately arranged, but by connecting the terminals 220 and 240, the semiconductor switching element is similar to FIG. 5 (Embodiment 2). It is also possible to share the discharge rate control circuit 100 between 20 and 40. Furthermore, the discharge speed control circuits 100c and 100d (FIG. 3) can be connected to the outside of the power modules 210 and 230 only for the semiconductor switching elements 10 and 30 of the upper arm.

  In the present embodiment, the single-phase inverter circuit is exemplified as the power conversion devices 1a to 1c. However, the present invention is a semiconductor switching element that is turned on / off according to the drive control signal even if it is other than the single-phase inverter circuit. Can be applied to the driving system of the semiconductor switching element.

  In the second and third embodiments, a configuration example in which some elements are built in the same module is shown. However, an electric circuit configuration is similarly formed regardless of whether or not modularization is applied. Is possible.

  Further, the configurations described in the embodiments are appropriately combined within the range in which inconsistencies and contradictions do not occur, including combinations not mentioned in the specification, for the plurality of embodiments described above. This should also be confirmed in the point scheduled from the beginning of the application.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1a, 1b, 1c, 1d Power converter, 2 Filter circuit, 3a, 3b Reactor, 4 Capacitor, 5 Load, 6 Overcurrent detector, 7 Control unit, 8, 9 Reference potential point, 10, 10a, 10b, 10c , 20, 20a, 20b, 20c, 30, 30a, 30b, 30c, 40, 40a, 40b, 40c Semiconductor switching element, 11, 21, 31, 41 positive electrode, 12, 22, 32, 42 negative electrode, 13, 23, 23a, 23b, 23c, 33, 43 Gate electrode (control electrode), 15, 25, 35, 45, 112, 122 Diode, 16, 26, 36, 46 Smoothing capacitor, 17 DC power supply, 18, 19 Power supply wiring 51, 52, 53, 54, 55 Drive circuit, 71, 72 Power supply line, 74n, 74na, 74nb, 74nc, 74p, 7 pa, 74pb, 74pc, 75n, 75p Transistor, 84, 84a, 84b, 84c, 85 Gate resistance, 100, 100a, 100b, 100c, 100d Discharge rate control circuit, 101, 102, 103, 104 Control power supply, 105, 105a , 105b, 105c, 105d resistive element, 106u, 106w negative electrode connection point, 110, 110a, 110b, 110c, 110d, 115c, 115d bypass switch, 111, 111u, 111w bootstrap circuit, 113, 123 current limiting resistor, 151 , 154, 157, 158, 251, 254, 257, 258 Control signal line, 200, 210, 230 Power module, 211-226, 231-246 terminal (power module), 214, 234 Power terminal, G Hu, GHw, GLu, GLw, GWu drive control signal, N1, N2, Nu, Nw node, SPu, SPuh, SPw, SPwh protection control signal, Sfl abnormality detection signal.

Claims (7)

A drive system for a semiconductor switching element that is turned on and off in response to a drive control signal,
An operation of charging the gate of the semiconductor switching element toward the first voltage and an operation of discharging the gate toward the second voltage are selectively executed according to the drive control signal. A drive circuit;
A resistance element connected to a discharge path by the drive circuit;
A bypass switch connected in parallel with the resistance element in the discharge path,
The bypass switch changes from an on state to an off state in response to detection of an overcurrent of the semiconductor switching element. A semiconductor switching element that is turned on and off in response to a drive control signal;
An operation of charging the gate of the semiconductor switching element toward the first voltage and an operation of discharging the gate toward the second voltage are selectively executed according to the drive control signal. A drive circuit;
An overcurrent detector for detecting an overcurrent of the semiconductor switching element;
A resistance element connected to a discharge path by the drive circuit;
A bypass switch connected in parallel with the resistance element in the discharge path,
The bypass switch changes from an on state to an off state in response to overcurrent detection by the overcurrent detector. A plurality of the semiconductor switching elements are arranged to constitute a plurality of opposing arms,
Each of the plurality of opposing arms includes a first semiconductor switching element connected between a first power supply wiring for supplying a first power supply voltage and a load, and a second lower than the first power supply voltage. A second semiconductor switching element electrically connected between the load and a second power supply wiring for supplying a power supply voltage of
The drive circuit is disposed corresponding to each of the semiconductor switching elements,
In two or more opposing arms of the plurality of opposing arms, a part of the discharge path by the drive circuit of each of the two or more second semiconductor switching elements is common.
The resistance element is disposed in a part of the discharge path that is common between the two or more second semiconductor switching elements, and is shared by the two or more second semiconductor switching elements. 2. The power conversion device according to 2. The semiconductor switching element and the drive circuit are arranged in one power module,
The power converter according to claim 2 or 3, wherein the resistance element and the bypass switch are arranged outside the power module. A plurality of the semiconductor switching elements are arranged in the same power module,
The plurality of semiconductor switching elements are:
A plurality of first semiconductor switching elements connected in parallel between a first power supply wiring for supplying a first power supply voltage and a load;
A plurality of second semiconductor switching elements electrically connected between a second power supply wiring for supplying a second power supply voltage lower than the first power supply voltage and the load;
The drive circuit is disposed corresponding to each of the plurality of first semiconductor switching elements and each of the plurality of second semiconductor switching elements,
Among the plurality of second semiconductor switching elements, a part of the discharge path by each of the drive circuits is common,
The resistance element is arranged in the part common to the plurality of second semiconductor switching elements in the discharge path, and is shared by the plurality of second semiconductor switching elements. The power converter described.   The power conversion device according to claim 2, wherein the semiconductor switching element is formed of a wide band gap semiconductor. The power converter according to claim 6, wherein the wide band gap semiconductor includes silicon carbide, gallium nitride, and diamond.

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