JP2018094252A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of improving amusement of games by diversifying game properties regarding continuation of an advantageous state which is advantageous to a player.SOLUTION: In a game machine of the present invention, during an advantageous state, it is possible, in a second advantageous state, to give a plurality of pieces of specific rights for determining whether or not to extend a game period in a first advantageous state. When the first advantageous state finishes, if the specific right is being given, a shift is made to the second advantageous state, and in the second advantageous state, whether or not to extend the game period in the first advantageous state is determined by consuming the specific right. If an extension of the game period is determined, it is possible to continue the first advantageous state. If the plurality of pieces of specific rights has been acquired, all of them are used for determining whether or not to extend the game period in the first advantageous state.SELECTED DRAWING: Figure 72

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called pachi-slot, comprising a plurality of reels each having a plurality of symbols provided on the surface, a start switch, a stop switch, a stepping motor provided for each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter also referred to as “start operation”) after a game medium such as a medal or coin has been inserted into the gaming machine, and the rotation of all reels is detected. Outputs a signal requesting start. The stop switch detects that a stop button provided for each reel has been pressed by the player (hereinafter also referred to as “stop operation”), and outputs a signal requesting the rotation of the corresponding reel to stop. To do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output from the start switch and the stop switch, and performs the rotation operation and stop operation of each reel.

  In such a gaming machine, when a start operation is detected, lottery processing using random numbers (hereinafter referred to as “internal lottery processing”) is performed on the program, and the result of the lottery (hereinafter referred to as “internal winning combination”). And the rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all the reels is stopped and a symbol combination (display combination) related to the winning of the winning is displayed, a privilege corresponding to the symbol combination is given to the player. As an example of a privilege granted to a player, a replay (hereinafter also referred to as “replay”) in which an internal lottery process is performed again without paying out game media (medals, etc.) or consuming the game media. An operation of a special game state (bonus game) in which a game medium payout opportunity increases can be cited.

  Also, in such a gaming machine, a function for navigating establishment of a predetermined combination (for example, a predetermined small combination which is a combination related to payout of game media) with a ramp, that is, an assist time (hereinafter referred to as “AT”). ). In addition, in such a gaming machine, when a specific operating condition is satisfied, a gaming state having a higher replay winning probability than normal is activated, that is, a replay time (hereinafter referred to as “RT”) function. There is also. In addition, there is also an assist replay time (hereinafter referred to as “ART”) function in which AT and RT operate simultaneously.

  Also, in such gaming machines, during the operation of ART, for each unit game, the number of ART sets is given based on the internal winning combination (for example, ART operation with 50 games as one set, or ART continuation is given) It is known that it is possible to continue ART by executing an extra lottery (right to do), winning the extra lottery, and adding the number of ART sets (for example, Patent Document 1) reference).

JP 2013-17520 A

  However, in such a gaming machine, whether or not the ART, which is an advantageous state advantageous to the player described above, continues is determined based on whether or not the addition lottery is won. There was a problem that the sex became monotonous.

  The present invention has been made to solve the above-described problems, and provides a gaming machine that can improve the interest of the game by making the gameability related to the continuation of the advantageous state advantageous to the player diverse. The purpose is to provide.

The gaming machine of the present invention is
A gaming machine (for example, pachislot 1) provided with advantageous state control means (for example, main CPU 101) for controlling to an advantageous state (for example, during ART) advantageous for a player when a predetermined condition is satisfied,
The advantageous states include a first advantageous state (eg, normal ART) and a second advantageous state (eg, continuous challenge);
The advantageous state control means includes:
Rights granting means for deciding whether or not to grant a specific right (for example, CP) that makes it possible to determine whether or not to extend the game period of the first advantageous state in the second advantageous state (For example, the main CPU 101),
When the first advantageous state ends,
If the specific right has not been granted, terminate the advantageous state;
When it is determined that when the specific right is granted, it is possible to play a game in the second advantageous state and the game period of the first advantageous state is extended in the second advantageous state In the extended game period, it is possible to play a game in the first advantageous state,
The right granting means can grant a plurality of the specific rights in the advantageous state,
In the case where a plurality of the specific rights are granted, even if it has already been decided to extend the game period of the first advantageous state in the second advantageous state, Decide whether to extend the game period of the first advantageous state until the right is consumed, and decide to extend in the second advantageous state when all the specific rights are consumed The gaming period of the first advantageous state is added together to extend the gaming period of the first advantageous state.

  In the gaming machine of the present invention, the advantageous state (for example, during ART) is configured to include a first advantageous state (for example, normal ART) and a second advantageous state (for example, continuous challenge). It is configured to be able to grant a plurality of specific rights (for example, CP) for performing an additional lottery (determination of whether or not to extend the game period) in the first advantageous state in the two advantageous states. Yes.

  In addition, when the specific right is granted when the first advantageous state ends, the state is shifted to the second advantageous state, and in the second advantageous state, the specific right is consumed and the first advantageous state is consumed. When the number of games is added, a lottery (deciding whether or not to extend the game period) is performed, and when the winning lottery is won (when it is determined to extend the game period), the first advantageous state is continued. It is configured to be able to.

  If a plurality of specific rights have been acquired, the specific rights will not be wasted and all will be added to the number of games in the first advantageous state (determination of whether to extend the game period) ). Therefore, in the second advantageous state, not only is it determined whether or not to continue the advantageous state, but also a possibility that a large number of games can be added at a time can be created. A variety of characteristics can be achieved, and the fun of the game can be improved.

  According to the gaming machine of the present invention configured as described above, it is possible to improve the interest of the game by making the gameability related to the continuation of the advantageous state advantageous to the player diverse.

It is a figure for demonstrating the function flow of the game machine in one Embodiment of this invention. It is a perspective view which shows the external appearance structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows schematic structure of the various display screens displayed on the sub display apparatus of one Embodiment of this invention. It is a figure which shows the example of a transition of the display screen of the sub display apparatus in one Embodiment of this invention. It is a block diagram which shows the whole circuit structure with which the game machine of one Embodiment of this invention is provided. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram which shows the internal structure of the microprocessor in one Embodiment of this invention. It is a block diagram which shows the internal structure of the sub control circuit in one Embodiment of this invention. It is a block diagram of the various registers | resistors which the main CPU in one Embodiment of this invention has. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure which shows the transition flow of the game state between the bonus state and non-bonus state of a pachislot in one Embodiment of this invention. It is a figure which shows the transition flow of the game state between the ART game state of a pachislot in one Embodiment of this invention, and a non-ART game state. It is a figure which shows an example of the symbol arrangement | positioning table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination, stop operation order (batting order), display combination etc. in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination, stop operation order (batting order), display combination etc. in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination, stop operation order (batting order), display combination etc. in one Embodiment of this invention. It is a figure which shows the structure of the winning request flag storage area | region and winning operation flag storage area | region in one Embodiment of this invention. It is a figure which shows the structure of the carryover combination storage area in one Embodiment of this invention. It is a figure which shows the structure of the game state flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the operation | movement stop button storage area in one Embodiment of this invention. It is a figure which shows the structure of the pressing order storage area | region in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one Embodiment of this invention. It is a figure for demonstrating the normal mode and ART mode in one Embodiment of this invention. It is a figure which shows an example of the normal time ART lottery table in one Embodiment of this invention. It is a figure which shows an example of the normal mode transfer lottery table in one Embodiment of this invention. It is a figure which shows an example of CP acquisition lottery table in CP special zone in one Embodiment of this invention. It is a figure which shows an example of CP acquisition lottery table in double special zone in one Embodiment of this invention. (A) is a figure which shows an example of the double specialization zone start state lottery table in one Embodiment of this invention, (B) is a double specialization zone middle blue 7 o'clock CP in one Embodiment of this invention. It is a figure which shows an example of an acquisition lottery table, (C) is a figure which shows an example of the double special zone middle blue 7 fake lottery table in one Embodiment of this invention, (D) is one figure of this invention. It is a figure which shows an example of the double special zone end lottery table in embodiment. It is a figure for demonstrating the judgment value for special effect lottery in one Embodiment of this invention. It is a figure which shows an example of the special time special effect reservation lottery table in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of power-on (reset interruption) performed by the main control circuit of the gaming machine in one embodiment of the present invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the process at the time of power-on in one Embodiment of this invention. It is a flowchart which shows the example of the game return process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the game return process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change confirmation process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the setting change confirmation process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change command production | generation storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the setting change command production | generation storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the communication data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data pointer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the communication data pointer update process in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of a power failure (external) in one Embodiment of this invention. It is a flowchart which shows the example of the checksum production | generation process (non-regulation) in one Embodiment of this invention. An example of a source program for executing various processes in the flowchart of the checksum generation process according to an embodiment of the present invention, and an operation of updating a stack pointer and an operation of reading data from a register executed in the checksum generation process FIG. It is a flowchart which shows the example of the sum check process (unregulated) in one Embodiment of this invention. It is a flowchart which shows the example of the sum check process (unregulated) in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the sum check process in one Embodiment of this invention. It is a flowchart which shows the example of the main process (main operation process) performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the medal acceptance / start check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of a medal reception and start check process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the medal insertion process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the medal insertion check process in one Embodiment of this invention. It is a flowchart which shows the example of the error process in one Embodiment of this invention. It is a figure which shows an example of a structure of the error table actually referred on the source program of the error processing in one Embodiment of this invention. It is a flowchart which shows the example of the random number acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the internal lottery process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the internal lottery process in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board control process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board output process in one Embodiment of this invention. It is a flowchart which shows the example of the control process classified by state in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of the start in a double special zone in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of the start in a double special zone in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of the start during a continuous challenge in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of the start in the promotion chance in one Embodiment of this invention. It is a flowchart which shows the example of the drawing priority order | rank storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the drawing priority order storage process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol code acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the symbol code acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the AND operation process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing priority order acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the drawing priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop control process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the reel stop control process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the reel stop control process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal OFF process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal ON process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the non-regulation port output process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the non-regulated port output process in one Embodiment of this invention. It is a flowchart which shows the example of the winning search process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the winning search process in one Embodiment of this invention. It is a flowchart which shows the example of the illegal hit check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the illegal hit check process in one Embodiment of this invention. It is a flowchart which shows the example of a prize check and medal payout process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of a prize check and medal payout process in one Embodiment of this invention. It is a flowchart which shows the example of the medal payout number check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the medal payout number check process in one Embodiment of this invention. It is a flowchart which shows the example of the bonus check process in one Embodiment of this invention. It is a flowchart which shows the example of the RT check process in one Embodiment of this invention. It is a flowchart which shows the example of the control processing classified by state at the time of the game end in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of the end in the continuous challenge in one Embodiment of this invention. It is a flowchart which shows the example of the interruption process performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of 7 segment LED drive processing in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the 7 segment LED drive process in one Embodiment of this invention. It is a flowchart which shows the example of 7 segment display data generation processing in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of 7 segment display data generation process in one Embodiment of this invention. It is a figure which shows an example of a structure of the 7 segment cathode table actually referred on the source program of the 7 segment display data generation process in one Embodiment of this invention. It is a flowchart which shows the example of the timer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the timer update process in one Embodiment of this invention. It is a flowchart which shows the example of the trial test signal control process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the rotation brake signal generation process in one Embodiment of this invention. It is a flowchart which shows the example of the special prize signal control process in one Embodiment of this invention. It is a flowchart which shows the example of the condition apparatus signal control process in one Embodiment of this invention. It is a flowchart which shows the example of the condition apparatus signal control process in one Embodiment of this invention. It is a flowchart which shows the example of the power-on process of the sub CPU performed by the sub control circuit of the gaming machine in one embodiment of the present invention. It is a flowchart which shows the example of the interruption interruption process of the sub CPU performed by the sub control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of a process of the main board | substrate communication task in one Embodiment of this invention. It is a flowchart which shows the example of the sub side navigation control process in one Embodiment of this invention. It is a flowchart which shows the example of the player registration process in one Embodiment of this invention. It is a flowchart which shows the example of the log | history management process in one Embodiment of this invention. It is a flowchart which shows the example of the effect determination process in one Embodiment of this invention. It is a flowchart which shows the example of the effect determination process during the promotion chance in one Embodiment of this invention. It is a flowchart which shows the example of the special effect reservation process in one Embodiment of this invention. It is a flowchart which shows the example of the special effect execution process in one Embodiment of this invention. It is a figure which shows an example of the effect display in the promotion chance in one Embodiment of this invention. It is a figure which shows an example of the effect display in the promotion chance in one Embodiment of this invention. It is a figure which shows an example of the effect display in the promotion chance in one Embodiment of this invention. It is a figure for demonstrating the numerical fluctuation display control of a pachislot in one Embodiment of this invention.

  Hereinafter, a pachislot machine is taken as an example of a gaming machine according to an embodiment of the present invention, and the configuration and operation thereof will be described with reference to the drawings. In the present embodiment, a pachislot machine having a bonus operation function and an ART function will be described.

<Function flow>
First, the functional flow of the pachislot will be described with reference to FIG. In the pachislot machine of this embodiment, medals are used as game media for playing games. In addition to medals, for example, coins, game balls, game point data, tokens, or the like can be applied as game media. In addition, the game medium may be referred to as “game value” or “game value”.

  When a player inserts a medal into the pachislot and operates the start lever, one value (hereinafter referred to as a random value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. This internal lottery means is one of various processing means (processing functions) provided in a main control circuit described later. By determining the internal winning combination, a combination of symbols that permits (display is permitted) to display along an after-mentioned effective line (winning determination line) is determined. The types of symbol combinations include those related to “winning” in which benefits such as payout of medals, re-playing (replay) operation, bonus operation, etc. are given to the player, and other so-called “out of”. Such a thing is provided. In the following, a combination relating to the payout of medals is referred to as a “small combination”, and a combination relating to replay (replay) operation is referred to as a “replay combination”. Further, a combination related to the operation of the bonus (bonus game) is referred to as a “bonus combination”. In addition, a role that can be won internally (that is, a combination of symbols permitted to be established) may be simply referred to as a “role”, and the internal winning combination may be “winning role”, “predetermined result”, or Sometimes referred to as “derivative allowance”. Further, the internal lottery means may be referred to as “combination determining means”, “winning combination determining means”, “preliminary determining means”, or “derivative allowance condition determining means”.

  Further, when the start lever is operated, a plurality of reels are rotated. Thereafter, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means performs control to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. The reel stop control means is one of various processing means (processing functions) provided in a main control circuit described later. Note that the operation means for performing the start operation is not limited to a lever shape like a start lever, and any operation means may be used as long as the player can perform the start operation. . The operation means for performing the stop operation is not limited to a button shape like a stop button, and any operation means may be used as long as the player can perform the stop operation. .

  In the pachislot, basically, a control for stopping the rotation of the corresponding reel is performed within a specified time (190 msec or 75 msec) from when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within the specified time is referred to as “the number of sliding pieces”. In this embodiment, when the specified time is 190 msec, the maximum number of sliding symbols (maximum number of sliding symbols) is set to 4 symbols, and when the specified time is 75 msec, the maximum sliding symbols are set. Set the number to one symbol. The specified time is normally 190 msec, and the maximum number of sliding symbols is 4 symbols for each reel. However, during operation of a specific bonus (middle bonus: referred to as MB), the specified reel is specified. The time is 75 msec, and the maximum number of sliding symbols is one symbol.

  The reel stop control means, when an internal winning combination permitting display of a symbol combination related to winning is determined, normally, the symbol combination is an effective line within a specified time of 190 msec (four symbols). The rotation of the reel is stopped so as to display as much as possible. In addition, the reel stop control means stops the rotation of the reel using a specified time so that the combination of symbols that are not permitted to be displayed by the internal winning combination is not displayed along the active line. The symbol displayed when the rotation of the reel is stopped may be referred to as “stop display” or “display result”. In addition, displaying the symbol on the effective line when the reel rotation stops may be expressed as “derivation of stop display” or “derivation of display result”.

 In addition, the reel stop control means automatically stops each reel when a predetermined automatic stop time has elapsed after the reel rotates, even if the player has not performed a stop operation. Stop control may be performed. In this case, since the reels are stopped without the player's stop operation, even if any internal winning combination is determined, any combination of symbols related to winning is also valid. It is desirable to stop the rotation of the reels so that they are not displayed along the line.

  In this way, when all the rotations of the plurality of reels are stopped, the winning determination means determines whether or not the combination of symbols displayed along the active line relates to winning. This winning determination means is also one of various processing means (processing functions) provided in the main control circuit described later. Then, when the combination of the displayed symbols is determined to be related to winning by the winning determination means, a bonus such as a medal payout is given to the player. In the pachislot, a series of flows as described above is performed as one game (unit game).

  The winning determination means determines whether the symbol combination displayed along the active line corresponds to any one of a plurality of symbol combinations determined in advance. It may be determined whether it corresponds to the combination of symbols related to the internal winning combination determined by the internal lottery means. In other words, in the former case, it may be determined whether or not the winning combination is a combination of symbols related to winning. In this case, as long as the stop control is appropriately performed by the reel stop control means, it is possible to sufficiently prevent the occurrence of the erroneous winning a prize, and therefore it becomes possible to reduce the control burden related to the erroneous winning detection. On the other hand, in the latter case, it is possible to determine whether or not the combination of symbols related to winning is a combination of symbols for which winning has been permitted. Therefore, security can be improved.

  Also, in the pachislot, in the series of gaming operations described above, various effects can be achieved by displaying images on a display device, outputting light from various lamps, outputting sound from a speaker, or a combination thereof. Is done.

  Specifically, when the start lever is operated, a random number value for presentation is extracted separately from the random number value used for determining the internal winning combination described above. When the effect random number is extracted, the effect content determination means determines the effect to be executed this time from lots of effect contents associated with the internal winning combination by lottery. This effect content determination means is one of various processing means (processing functions) provided in a sub-control circuit described later.

  Next, when the content of the effect is determined by the effect content determination means, the effect execution means responds in conjunction with each opportunity such as when the rotation of the reel starts, when the rotation of each reel stops, or when the presence or absence of a prize is determined. Execute. In this way, in the pachislot, for example, by executing the production contents associated with the internal winning combination, there is an opportunity to know or predict the determined internal winning combination (in other words, the combination of symbols to be aimed at) It is provided to the player and the player's interest can be improved.

<Pachislot structure>
Next, the structure of a pachislot machine according to an embodiment of the present invention will be described with reference to FIGS.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachi-slot 1.

  As shown in FIG. 2, the pachislot 1 includes an exterior body (game machine main body) 2. The exterior body 2 includes a cabinet 2a that houses a reel, a circuit board, and the like, and a front door 2b that is attached so that the opening of the cabinet 2a can be opened and closed.

  Inside the cabinet 2a, three reels 3L, 3C, 3R (variable display means, display columns) are provided in a horizontal row. Hereinafter, the reels 3L, 3C, and 3R (main reels) are also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 20) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction (reel rotation direction). Each of the reels 3L, 3C, 3R may be expressed as “design display means”, “variable display means”, “variable display”, or the like. In addition, the symbol display area 4 described later may be included as these components. Further, the “symbol” may be information that can be identified by the player by visual recognition, and may be expressed as “identification information” in that sense.

  The front door 2 b includes a door body 9, a front panel 10, a waist panel 12, and a pedestal portion 13. The door body 9 is attached to the cabinet 2a so as to be openable and closable using a hinge (not shown). The hinge is provided at the left side end of the door body 9 when viewed from the front side (player side) of the pachi-slot 1. The cabinet 2a can be simply referred to as a “box”, and the front door 2b can be simply referred to as a “door” or a “front door”. Further, since the cabinet 2a functions as a frame that supports or fixes the front door 2b, it may be expressed as "support", "support frame", or "fixed frame". Further, the front door 2b may be constituted by a plurality of door members. For example, it may be constituted by an upper door member attached to the upper side of the opening of the cabinet 2a and a lower door member attached to the lower side of the opening of the cabinet 2a, as viewed from the front side of the gaming machine. The inner door member attached to the opening side of the cabinet 2a and the outer door member attached to the front side of the gaming machine may be used.

  The front panel 10 is provided on the upper portion of the door body 9. The front panel 10 is constituted by a frame-like member having an opening 10a. The opening 10a of the front panel 10 is closed by the display device cover 30, and the display device cover 30 is disposed to face a display device 11 described later disposed inside the cabinet 2a.

  The display device cover 30 is formed of a black translucent synthetic resin. Therefore, the player can visually recognize the video (image) displayed on the display device 11 described later via the display device cover 30. In the present embodiment, the display device cover 30 is formed of a black translucent synthetic resin, thereby suppressing the entry of external light into the cabinet 2a and the image (image) displayed by the display device 11. Is clearly visible.

  A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, lamps 21 a and 21 b provided on the upper portion of the front panel 10 when viewed from the player side. Each lamp constituting the lamp group 21 is configured by an LED (Light Emitting Diode) or the like (refer to an LED group 85 in FIG. 7 described later), and turns on and off the light in a pattern corresponding to the contents of effects.

  The waist panel 12 is provided at a substantially central portion of the door body 9. The waist panel 12 includes a decorative panel on which an arbitrary image is drawn, and a light source (LED included in an LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

  The pedestal portion 13 is provided between the front panel 10 and the waist panel 12. The pedestal 13 includes a symbol display area 4 and various devices (medal slot 14, MAX bet button 15a, 1 bet button 15b, start lever 16, three stop buttons 17L, 17C, and the like to be operated by the player. 17R, a settlement button (not shown), and the like.

  The symbol display area 4 is an area that overlaps with the three reels 3L, 3C, and 3R when viewed from the front, and is arranged at a position closer to the player than the three reels 3L, 3C, and 3R. 3L, 3C, 3R has a size that enables visual recognition. The symbol display area 4 functions as a display window, and is configured so that each reel 3L, 3C, 3R provided behind the display window 4 can be visually recognized. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  When the rotation of the three reels 3L, 3C, 3R provided behind the reel display window 4 is stopped, the reel display window 4 is continuously arranged among a plurality of symbols provided on the peripheral surface of each reel. Two symbols are displayed in the frame. That is, when the rotation of the three reels 3L, 3C, 3R is stopped, one symbol (three in total) is placed in each of the upper, middle, and lower regions for each reel within the frame of the reel display window 4. ) Is displayed (in the frame of the reel display window 4, symbols are displayed in the form of 3 rows × 3 columns). In the present embodiment, a pseudo line (center line) connecting the middle stage area of the left reel 3L, the middle stage area of the middle reel 3C, and the middle stage area of the right reel 3R within the frame of the reel display window 4, It is defined as an effective line for determining whether or not a prize is won.

  The reel display window 4 is formed by an opening of a frame member 31 provided on the pedestal portion 13. A substantially horizontal plane base region is provided below the frame member 31 that defines the reel display window 4. When viewed from the player side, a medal slot 14 is provided on the right side of the pedestal area, and a MAX bet button 15a and a 1 bet button 15b are provided on the left side.

  The medal slot 14 is provided to accept a medal dropped on the pachislot 1 from the outside by the player. The medals accepted from the medal slot 14 are used for one game up to a predetermined number (for example, three) set in advance, and the number of medals exceeding the predetermined number are deposited inside the pachislot 1. (So-called credit function (game medium storage means)).

  The MAX bet button 15a and the 1 bet button 15b are provided for determining the number of coins used for one game from medals deposited in the cabinet 2a. Note that a bet button LED (not shown) that is lit when a medal can be inserted is provided inside the MAX bet button 15a. The checkout button is provided to draw out (discharge) medals deposited inside the pachislot machine 1 to the outside.

  When the player depresses the MAX bet button 15a, medals corresponding to the number of bets (3) in the unit game are inserted and the effective line is activated. On the other hand, each time the 1-bet button 15b is pressed, one medal is inserted. When the 1-bet button 15b is operated three times, medals for the number of bets (3) in the unit game are inserted and the active line is activated.

  Hereinafter, the operation of the MAX bet button 15a, the operation of the 1 bet button 15b, and the operation of inserting a medal into the medal insertion slot 14 (operation of inserting a medal for playing a game) are all referred to as “insertion operation”.

  The start lever 16 is provided to start rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, and 17R are provided in association with the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are also referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

  In addition, an information display 6 is provided in the approximate center of the pedestal region on a substantially horizontal plane below the reel display window 4. The information display 6 is covered with a transparent window cover (not shown).

  The information display 6 has a 2-digit 7-segment LED for digitally displaying (notifying) information on the number of medals to be paid out to the player as a privilege (hereinafter referred to as “paid-out number”). (Hereinafter referred to as “7-segment LED”) and information such as the number of medals deposited inside the pachislot machine 1 (hereinafter referred to as “credit number”) for digital display (notification) to the player A 2-digit 7-segment LED is provided. In this embodiment, the 2-digit 7-segment LED for displaying the number of paid-out medals is a 2-digit 7-segment LED for digitally displaying (notifying) information about the occurrence of an error and the error type to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the number of paid-out medals is switched from the display mode of the paid-out number to the display mode of the error type information.

  Further, the information display 6 is provided with an instruction monitor (not shown) for notifying information on a stop operation necessary for displaying a symbol combination corresponding to the combination determined as the internal winning combination along the effective line. ing. The instruction monitor (instruction display) is composed of, for example, a two-digit 7-segment LED. The instruction monitor informs the player of necessary stop operation information by turning on, blinking, or turning off the 2-digit 7-segment LED in a manner that uniquely corresponds to the stop operation information to be notified. To do.

  Note that the aspect uniquely corresponding to the information of the stop operation to be notified here is, for example, in the case of informing the pressing order “1st (perform the first stop operation on the left reel 3L)”. When the numerical value “1” is displayed on the instruction monitor and the push order “2nd (perform the first stop operation on the middle reel 3C)” is notified, the numerical value “2” is displayed on the instruction monitor and the push order In a case where “3rd (perform the first stop operation on the right reel 3R)” is notified, a numerical value “3” is displayed on the instruction monitor. Note that the notification mode (navigation data determined on the main side, which will be described later) of stop operation information on the instruction monitor will be described later in detail with reference to FIGS. 19 to 21 described later.

  The information display 6 is electrically connected to the main control board 71 via a door relay board 68 and a game operation display board 81 as shown in FIG. 7 described later. The display operation of the information display 6 is controlled by the main control board. It is controlled by a later-described main control circuit 90 in the substrate 71. Moreover, the control method of the various 7-segment LEDs described above is dynamic lighting control.

  In the pachislot machine 1 of this embodiment, in addition to the instruction monitor controlled by the main control board 71, a configuration for notifying the stop operation information using other means controlled by the sub control board 72 is provided. Specifically, information on a stop operation is notified by a display device 11 described later configured by a projector mechanism 211 and a display unit 212 (see FIG. 3 and FIG. 7 described later).

  When such a configuration is applied, the notification mode in the instruction monitor and the notification mode in other means controlled by the sub-control board 72 may be different from each other. That is, the instruction monitor may be notified in a manner that uniquely corresponds to the information on the stop operation to be notified, and does not necessarily need to notify the information on the stop operation directly (for example, the numerical value “1” in the instruction monitor). Even if is displayed, there is a possibility that the notification content cannot be specified depending on the player, which is not a direct notification). On the other hand, in the notification on the sub side (sub control board side) by other means such as the display device 11 described later, information on the stop operation may be directly notified. For example, when the push order “1st” is notified, the instruction monitor displays a numerical value “1” that uniquely corresponds to the push order to be notified, but other means (for example, the display device 11) displays the left reel 3L. The instruction information for performing the first stop operation may be directly notified.

  In the pachislot machine 1 configured as described above, not only the control of the sub-control board 72 but also the control of the main control board 71 can notify information on necessary stop operation according to the internal winning combination. The presence / absence of notification of such stop operation information may be controlled according to the gaming state (control state). For example, the stop operation information may be notified in the ART game state (see FIG. 14 described later) instead of notifying the stop operation information in the non-ART game state (see FIG. 14 described later).

  Further, a sub display device 18 is provided on the left side of the reel display window 4 when viewed from the player side. As shown in FIG. 2, the sub display device 18 is provided so as to stand substantially vertically from a pedestal region in a substantially horizontal plane of the pedestal portion 13 in the front surface portion of the door body 9. The sub display device 18 includes a liquid crystal display or an organic EL (Electro-Luminescence) display, and displays various types of information.

  A touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 7 described later). The touch sensor 19 operates in accordance with a predetermined operation principle such as a capacitance method, and when a player's operation is accepted, outputs a signal corresponding to the operation as touch input information. The pachislot machine 1 according to the present embodiment has a function that allows the display of the sub display device 18 to be switched in accordance with the player's operation received via the touch sensor 19 (touch input information output from the touch sensor 19). Have The sub display device 18 is controlled by a later-described sub control board 72 (see FIG. 7 described later) based on touch input information output from the touch sensor 19.

  In the lower part of the door body 9, a medal payout opening 24, a medal tray 25, two speaker holes 20L, 20R, and the like are provided. The medal payout port 24 guides medals discharged by driving a medal payout device 51 described later to the outside. The medal tray 25 stores medals discharged from the medal payout opening 24. Sounds such as sound effects and music corresponding to the contents of the effects are output from the two speaker holes 20L and 20R.

[Internal structure]
Next, the internal structure of the pachislot machine 1 will be described with reference to FIGS. FIG. 3 is a diagram showing the internal structure of the cabinet 2a, and FIG. 4 is a diagram showing the internal structure of the back side of the front door 2b.

  As shown in FIG. 3, the cabinet 2a includes a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. And the display apparatus 11 is arrange | positioned in the upper part in the cabinet 2a.

  The display device 11 includes a projector mechanism 211 and a box-shaped projection member 212a onto which the image light projected from the projector mechanism 211 is projected, and displays an image by projection mapping. Specifically, in the display device 11, image light is generated based on the position (projection distance, angle, etc.) and shape of the projection member 212a that is a three-dimensional object, and the image light is projected by the projector mechanism 211 to the projection member. Projected onto the surface of 212a. By providing such an effect function, an advanced and powerful effect can be performed. Although not shown in FIG. 3, another projected member with a curved display surface is provided on the back side of the box-shaped projected member 212 a, and either one of the projected members is provided depending on the gaming state. Used as a screen on which image light is projected. Therefore, the cabinet 2a is also provided with a function (not shown) for switching the projection target member in accordance with the gaming state.

  A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are disposed in the lower part of the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 27b in the cabinet 2a. The hopper device 51 can store a large amount of medals and can discharge them one by one. The hopper device 51 pays out medals when the number of stored medals exceeds 50, for example, or when the settlement button is pressed and settlement of medals is executed. Then, the medals paid out by the hopper device 51 are discharged from the medal payout outlet 24 (see FIG. 2).

  The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is disposed on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. The medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

  The power supply device 53 includes a power switch 53a and a power supply board 53b (power supply means) (see FIG. 7 described later). The power supply device 53 is disposed on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 27c. The power supply device 53 converts the power of the AC voltage 100V supplied from the sub power supply device (not shown) into the power of the DC voltage necessary for each part, and supplies the converted power to each part.

  Further, a sub control board case 57 that houses a sub control board 72 (see FIG. 7 described later) is disposed above the power supply device 53 in the cabinet 2a. A sub control circuit 72 (see FIG. 10 described later), which will be described later, is mounted on the sub control board 72 accommodated in the sub control board case 57. The sub-control circuit 200 is a circuit that controls the execution of effects by displaying images. A specific configuration of the sub control circuit 200 will be described later.

  A sub-relay board 61 is disposed above the sub-control board case 57 in the cabinet 2a. The sub relay board 61 is a relay board on which wiring for connecting the sub control board 72 and a main control board 71 described later is mounted. The sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72, a board disposed around the sub-control board 72, various devices (units), and the like is mounted.

  Although not shown in FIG. 3, a cabinet-side relay board 44 (see FIG. 7 described later) is disposed in the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 7 described later), a hopper device 51, a game medal auxiliary storage switch 77 (see FIG. 7 described later), and a medal payout count switch (not shown). Is a relay board on which wiring for connecting is mounted.

  As shown in FIG. 4, a middle door 41 is disposed at the center of the rear side of the front door 2b, and the reel display window 4 (see FIG. 2) is attached so as to be openable and closable from the back side. Although not shown in FIG. 4, three reels 3L, 3C, 3R are attached to the middle door 41 on the reel display window 4 side, and main control is provided on the opposite side of the middle door 41 from the reel display window 4 side. A main control board case 55 in which a board 71 (see FIG. 7 described later) is housed is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, and 3R through gears having a predetermined reduction ratio.

  The main control board 71 accommodated in the main control board case 55 has a main control circuit 90 (see FIG. 9 described later) described later. The main control circuit 90 (main control means) is a circuit that controls the main flow of the game in the pachislot 1 such as determination of an internal winning combination, rotation and stop of each of the reels 3L, 3C, 3R, and determination of the presence or absence of winning. . In the present embodiment, the main control circuit 90 also performs control such as lottery processing for determining whether ART is determined, processing for displaying navigation information on an instruction monitor, and processing for transmitting various test signals. The specific configuration of the main control circuit 90 will be described later.

  Speakers 65L and 65R are disposed below the middle door 41 on the back side of the front door 2b. The speakers 65L and 65R are disposed at positions facing the speaker holes 20L and 20R (see FIG. 2), respectively.

  A selector 66 and a door open / close monitoring switch 67 are disposed above the speaker 65L. The selector 66 is a device for selecting whether or not the medal material and shape are appropriate, and guides the appropriate medal inserted into the medal insertion slot 14 to the hopper device 51. A medal sensor (game medium detecting means: not shown) for detecting that an appropriate medal has passed is provided on the path through which the medal passes in the selector 66.

  The door open / close monitoring switch 67 is disposed diagonally to the left of the selector 66 when the front door 2b is viewed from the back side. The door opening / closing monitoring switch 67 outputs a security signal for notifying the opening / closing of the front door 2b to the outside of the pachislot 1.

  Although not shown in FIG. 4, a door relay terminal plate 68 is disposed in the area where the front door 2 b is opened and closed by the middle door 41 on the back surface and below the reel display window 4 (see below). 7). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub-relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a testing machine, This is a relay board on which wiring for connecting each of the second interface boards 302 for the testing machine is mounted. Examples of the various buttons and switches include a MAX bet button 15a, a 1 bet button 15b, a door open / close monitoring switch 67, a BET switch 77 described later, a start switch 79, and the like.

<Display example of sub display device>
Here, various display screens displayed on the sub display device 18 will be described with reference to FIGS. 5A to 5E. 5A is a diagram showing a top screen 221 displayed on the sub display device 18, and FIG. 5B is a diagram showing a menu screen 222 displayed on the sub display device 18. 5C to 5E are diagrams showing game information screens 223, 224, and 225 displayed on the sub display device 18. FIG.

  Various display screens are displayed on the sub display device 18 by a player's touch operation, and as shown in FIGS. The display screen is displayed. These display screens are switched based on the player's operation signal received via the touch sensor 19.

  The top screen 221 is an initial screen among the display screens displayed on the sub display device 18, and on the top screen 221, a “MENU” button 221a and a summary game history 221b are displayed. The “MENU” button 221a is an operation button for calling the menu screen 222 shown in FIG. 5B. When a predetermined operation (for example, tapping) is performed by the player on the “MENU” button 221a, the menu screen 222 is called. It is. On the top screen 221, a part of the game history (outline game history) of the pachislot 1 is displayed as the summary game history 221b. In the present embodiment, for example, the number of bonuses, the number of ARTs, and the number of games (number of games) are displayed as the summary game history 221b.

  The menu screen 222 is a screen that displays a menu that can be displayed on the sub display device 18. In the menu screen 222, a "return" button 222a, a "registration" button 222b, an "explanation" button 222c, and an "array payout" button 222d. , A “reach eye” button 222e, a “WEB site” button 222f, and a “volume” button 222g are displayed. The “return” button 222a is an operation button for calling the top screen 221. When the player performs an operation on the “return” button 222a, the top screen 221 is called. The “Register” button 222b to “Volume” button 222g are operation buttons for calling up the display screen of the corresponding menu contents. When the player performs an operation on each button, the corresponding menu contents are displayed. The display screen is called up.

  For example, when the “Register” button 222 b is operated by the player on the menu screen 222, a registration screen (not shown) for registering the player who is playing the game is called up on the display screen of the sub display device 18. In recent pachislot machines, a service is widely used in which a player is registered for each model and various information such as the achievement status of a defined mission is managed based on the player's previous game history. The registration screen called by the “registration” button 222b is a display screen for registering a player when receiving the provision of this service.

  For example, when the “explain” button 222 c is operated by the player on the menu screen 222, an explanation screen (not shown) of the pachislot 1 is called up on the display screen of the sub display device 18. The information displayed on the explanation screen includes, for example, explanation of the specifications of the pachislot 1 such as a bonus winning probability and ART winning probability for each set value, and an introduction explanation of characters appearing in the production of the pachislot 1.

  For example, when the “array payout” button 222 d is operated by the player on the menu screen 222, the array payout screen (not shown) of the pachislot 1 is called on the display screen of the sub display device 18. On the array payout screen, for example, the correspondence (payout table) between the combination of symbols determined to win in the pachislot 1 and the privilege when determined to be a win, and the reels 3L, 3C, and 3R are drawn. A symbol row (reel arrangement) or the like is displayed.

  For example, when the “reach eye” button 222 e is operated by the player on the menu screen 222, the reach eye screen (not shown) of the pachi-slot 1 is called to the display screen of the sub display device 18. On the reach eye screen, information on symbol combinations called “reach eyes” set in the pachi slot 1 is displayed. It should be noted that the symbol combination called “reach eyes” is definite that a special privilege is given (for example, a bonus state or a transition to ART) when the symbol combination is displayed along the active line. It is a symbol combination to be notified to.

  Further, for example, when the “WEB site” button 222 f is operated by the player on the menu screen 222, the WEB introduction screen (not shown) of the pachislot 1 is called up on the display screen of the sub display device 18. On the WEB introduction screen, for example, a two-dimensional code (for example, QR code (registered trademark)) indicating a URL of an arbitrary WEB site such as a special WEB site provided for each model of the pachislot 1 or a WEB site of the manufacturer of the pachislot 1 Is displayed. The player can access the corresponding WEB site by reading the two-dimensional code displayed on the WEB introduction screen with a mobile phone or the like.

  Further, for example, when the “volume” button 222g is operated by the player on the menu screen 222, a volume adjustment screen (not shown) that can adjust the volume of the sound output from the speakers 65L and 65R is displayed on the sub display device. Called 18 display screen. The player can adjust the volume of the effect sound of the pachislot 1 via the volume adjustment screen.

  Since the sub display device 18 is provided separately from the display device 11 (projector mechanism 211 and display unit 212) described above, it can be controlled separately from the display device 11. Therefore, in the pachislot machine 1 of the present embodiment, the display screen of the sub display device 18 can be switched by the player's operation even during the game (during execution of the effect by the display device 11). As a result, for example, when the player wants to know the character appearing in the presentation on the display device 11, the player operates the “explain” button 222 c to call the explanation screen, thereby It is possible to grasp information such as the relationship of the game during the game. Also, for example, if a player wants to grasp the symbol that should be used as a guideline for winning a rare role during reel rotation when a so-called `` rare role '' is won during a game, By operating the “array payout” button 222d to call the array payout screen, the reel arrangement can be grasped.

  The game information screens 223, 224, and 225 are display screens that display detailed game history information including a summary game history displayed on the top screen 221 of the game history of the pachislot 1.

  On the game information screen 223, a “return” button 223a, a “MENU” button 223b, a “previous” button 223c, a “next” button 223d, and a game history 223e are displayed. The “return” button 223a and the “MENU” button 223b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively. The display screen to be called is called. The “Previous” button 223c and the “Next” button 223d are operation buttons for switching the game information screen in a predetermined order. When the “Previous” button 223c is operated by the player, the display screen Is switched from the game information screen 223 to the game information screen 225, and when the “next” button 223d is operated by the player, the display screen is switched from the game information screen 223 to the game information screen 224. As the game history 223e, as shown in FIG. 5C, the number of games (number of games), the number of bonuses, the number of ARTs, and the number of CZ (chance zone) are displayed.

  On the game information screen 224, a “return” button 224a, a “MENU” button 224b, a “previous” button 224c, a “next” button 224d, and a game history 214e are displayed. The “return” button 224a and the “MENU” button 224b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively. The display screen to be called is called. The “Previous” button 224c and the “Next” button 224d are operation buttons for switching the game information screen in a predetermined order. When the “Previous” button 224c is operated by the player, the display screen is changed to the game. When the information screen 224 is switched to the game information screen 223 and the “next” button 224 d is operated by the player, the display screen is switched from the game information screen 224 to the game information screen 225. Further, as shown in FIG. 5D, the game history 224e displays the number of rushes and successes of CZ (chance zone) described later, the number of rushes of promotion chances described later, and the number of rushes of specialized zones described later. The

  On the game information screen 225, a “return” button 225a, a “MENU” button 225b, a “previous” button 225c, a “next” button 225d, and a game history 225e are displayed. The “return” button 225a and the “MENU” button 225b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively. The display screen to be called is called. The “Previous” button 225c and the “Next” button 225d are operation buttons for switching the game information screen in a predetermined order. When the “Previous” button 225c is operated by the player, the display screen is displayed. Is switched from the game information screen 225 to the game information screen 224, and when the “next” button 225d is operated by the player, the display screen is switched from the game information screen 225 to the game information screen 223. Further, as shown in FIG. 5E, the game history 225e includes specific internal winning combinations (for example, “F_black BAR” described later, “F_SP Lip AC” described later, and “F_MB” described later). The number of wins and the win probability (the fraction with a numerator of 1) are displayed.

  In addition, as a switching method of the display screen displayed on the sub display device 18, for example, a switching method based on a tap operation on an operation button displayed on each display screen may be employed. You may employ | adopt the method of switching based on the swipe operation with respect to a display screen.

<Various display screen switching functions of the sub display device>
Next, various display screen switching functions of the sub display device 18 in the pachi-slot 1 of the present embodiment will be described.

[Transition example of the display screen of the sub display device]
First, with reference to FIG. 6A and 6B, the transition example (switching aspect) of the display screen of the sub display apparatus 18 in the pachislot 1 of this embodiment is demonstrated. 6A is a diagram showing an example of transition of the display screen of the sub display device 18 in a situation where the player registration state is not set, and FIG. 6B is a sub display in a situation where the player registration state is set. FIG. 10 is a diagram illustrating a transition example of a display screen of the device 18.

  In the situation where the player registration state is not set, the display screen of the sub display device 18 transitions between the top screen 221 and the menu screen 222 and from the menu screen 222 and the menu screen 222 as shown in FIG. 6A. Transition is possible only between various possible display screens, and transition between these display screens is controlled by a sub control board 72 (sub CPU 201 described later). For example, the sub-control board 72 is connected between the top screen 221 and the menu screen 222 based on a touch operation acquired via the touch sensor 19 (for example, a tap operation on a predetermined button or a swipe operation on the display screen). Switch the display screen. However, in a situation where the player registration state is not set, the sub-control board 72 performs control so that the display of the game information screens 223, 224, 225 is impossible. That is, in a situation where the player registration state is not set, the player cannot display the game information screens 223, 224, 225 on the sub display device 18.

  On the other hand, in the situation where the player registration state is set, as shown in FIG. 6B, the display screen of the sub display device 18 is between the top screen 221 and the menu screen 222, and between the menu screen 222 and the menu screen 222. In addition to the various display screens that can be shifted from, the transition between the menu screen 222 and the game information screens 223, 224, and 225 is also possible. CPU201). In other words, the sub-control board 72 is configured not only between the top screen 221 and the menu screen 222 but also on each of the top screen 221 and the menu screen 222 based on the touch operation acquired via the touch sensor 19 and the game information screen. The display screen can also be switched between 223, 224 and 225. Therefore, in this embodiment, when the player registration state is set, the player can display the game information screens 223, 224, and 225 on the sub display device 18.

  As shown in FIG. 6B, the display screen transition order among the top screen 221, the menu screen 222, and the game information screens 223, 224, and 225 is arbitrary. Therefore, for example, it may be configured such that the top screen 221 can directly transition to the game information screens 223, 224, 225, or the game information screens 223, 224, 225 can be changed only from the top screen 221 via the menu screen 222. You may make it the structure which can be changed.

  In the pachi-slot 1 of the present embodiment, a configuration that allows transition from the top screen 221 to the game information screens 223, 224, and 225 only via the menu screen 222 (configuration that cannot transition directly from the top screen 221 to the game information screens 223, 224, and 225) ) Is adopted. In the pachi-slot 1 of the present embodiment, when the player performs a swipe operation (not a menu selection operation) on the display screen on the menu screen 222, the display screen is changed from the menu screen 222 to the game information screens 223, 224. , 225.

  In the present embodiment, the game information screens 223, 224, and 225 are display screens provided completely independently of the menu screen 222. That is, in the pachislot machine 1 of the present embodiment, information indicating a game result that a player has a strong interest in the game, such as a game history, is independent as information that is not related to a game result such as a payout arrangement or volume control. And display. In the present embodiment, the game information screens 223, 224, and 225 can be displayed without the player performing a menu selection operation on the menu screen 222 in a situation where the player registration state is set. . Therefore, in this embodiment, when the player registration state is set, it is possible to easily access the information game history information desired by the player.

  In the present embodiment, the menu selection operation on the menu screen 222 cannot change the display screen to the game information screens 223, 224, and 225, and the swipe operation (specified in the menu display) is performed on the menu screen 222. If no operation is performed, the display screen cannot be changed to the game information screens 223, 224, 225. Therefore, in the pachi-slot 1 of the present embodiment, the swipe operation for changing the display screen to the game information screens 223, 224, 225 can be handled as a hidden command in the situation where the player registration state is set. In this case, since the player can see more detailed game history information that cannot be seen by other players with little knowledge due to his / her own knowledge of the pachislot 1, than the other players. The game can be advantageously performed, and as a result, it can be expected that the player actively plays the game.

[Display switching function from game information screen to top screen]
The pachi-slot 1 of the present embodiment has a function of changing the display screen of the sub display device 18 from the game information screens 223, 224, 225 to the top screen 221 manually or automatically by the player. Specifically, in this embodiment, when the “return” button is operated on the game information screens 223, 224, 225, the display screen transitions from the game information screens 223, 224, 225 to the top screen 221 (manual transition). function). In the present embodiment, when a predetermined condition is satisfied while the game information screens 223, 224, and 225 are displayed, the display screen automatically changes to the top screen 221 regardless of the player's operation. Transition (automatic transition function).

  More specifically, in the pachi-slot 1, in the state where the game information screens 223, 224, and 225 are displayed, the insertion operation (the operation to the MAX bet button 15a, the operation to the 1 bet button 15b and the medal insertion slot 14). When a medal insertion operation is performed, the display screen of the sub display device 18 automatically transitions to the top screen 221. In the gaming state (high lip state) where the probability that a replay role is determined as an internal winning combination is high, such as the ART gaming state, medals are automatically inserted due to the replaying action associated with the replay winning combination. As a result, in the high lip state, the opportunity to display the game information screens 223, 224, 225 may be limited. Therefore, in the pachi-slot 1 of the present embodiment, when a medal is automatically inserted by the re-game operation, the display screen is automatically displayed in response to the start operation instead of the medal insertion operation. , 224, 225 to the top screen 221.

  That is, in this embodiment, when the re-game is activated and the game information screens 223, 224, 225 are displayed, the display screen is automatically displayed on the game information screens 223, 224 in response to the start operation. , 225 to the top screen 221. On the other hand, when the re-game operation is not performed, the display screen automatically transitions from the game information screens 223, 224, 225 to the top screen 221 in response to the input operation.

[Display switching function from menu content display screen to top screen (or menu screen)]
The pachi-slot 1 of this embodiment has various menu content display screens (a registration screen, an explanation screen, an array payout screen, a reach eye screen, a WEB introduction) on which the display screen of the sub display device 18 can be changed by a menu selection operation on the menu screen 222. The screen has a function of shifting from the screen and the volume adjustment screen) to the top screen 221 (or the menu screen 222) manually or automatically by the player. Specifically, in this embodiment, when a predetermined button (for example, “Return to TOP” button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the top screen 221 ( Manual transition function). In this embodiment, when a specific button (for example, a “return” button) is operated on the menu content display screen, the display screen transits from the menu content display screen to the menu screen 222 (manual transition). function).

  Furthermore, in the present embodiment, when a predetermined time elapses while the menu content display screen is displayed, the display screen automatically changes to the top screen 221 (or the menu screen 222) regardless of the player's operation. Transition (automatic transition function). At this time, the predetermined time that triggers automatic transition to the top screen 221 (or the menu screen 222) varies depending on the type of the menu content display screen currently displayed. For example, if the volume adjustment screen for adjusting the volume output from the pachislot 1 is displayed for a long time, not only may the volume be adjusted to an unintended volume due to an erroneous operation, but other players may be caused by an erroneous operation. There is also a risk of discomfort. Therefore, the volume adjustment screen is set to automatically transition to the top screen 221 (or the menu screen 222) in a shorter time than other menu content display screens. On the other hand, the registration screen is set to automatically transition to the top screen 221 (or the menu screen 222) in a longer time than other menu content display screens in order to facilitate player registration. .

  That is, in each menu content display screen, an elapsed time (automatic transition time) that triggers automatic transition to the top screen 221 (or menu screen 222) is appropriately set according to the type of the menu content display screen. In the volume adjustment screen, an automatic transition time shorter than that of the other menu content display screen is set, and in the registration screen, an automatic transition time longer than that of the other menu content display screen is set.

[Function for selecting whether to operate the menu]
In the pachi-slot 1 of this embodiment, the display screen of the sub display device 18 is changed from the menu screen 222 to a registration screen, an explanation screen, an array payout screen, a reach eye screen, a WEB introduction screen, and a volume adjustment screen. A person can perform various operations according to these menu content display screens, and can confirm various information. It should be noted that a function (a function for selecting whether or not to operate the menu) may be provided so that such a function that allows the player to select a menu can be restricted according to the settings on the game store side.

  For example, the display screen may not be allowed to transition from the menu screen 222 to the volume adjustment screen (for example, the “volume” button 222g is not displayed on the menu screen 222) according to settings at the game store side. In this case, the volume adjustment by the player can be made impossible.

<Control system for pachislot>
Next, a control system provided in the pachislo 1 will be described with reference to FIG. FIG. 7 is a circuit block diagram showing the configuration of the control system of the pachislot 1.

  The pachi-slot 1 includes a main control board 71 provided on the middle door 41 and a sub-control board 72 provided on the front door 2b. The pachi-slot 1 includes a reel relay terminal board 74, a setting key switch 54 (setting switch), and a cabinet-side relay board 44 connected to the main control board 71. Further, the pachi-slot 1 includes an external concentration terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76, and a power supply device 53 connected to the main control board 71 via the cabinet-side relay board 44. In addition, since the structure of the hopper apparatus 51 was mentioned above, the description is abbreviate | omitted here.

  The reel relay terminal plate 74 is disposed inside the reel body of each reel 3L, 3C, 3R. The reel relay terminal board 74 is electrically connected to stepping motors (not shown) of the reels 3L, 3C, 3R, and relays signals output from the main control board 71 to the stepping motors.

  The setting key type switch 54 is provided on the main control board case 55. The setting key switch 54 is used when changing the setting (setting 1 to setting 6) of the pachi-slot 1 or when checking the setting of the pachi-slot 1.

  The cabinet-side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external concentration terminal board 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. It is. The external concentration terminal board 47 is provided for outputting signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52 and detects whether or not the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachislot 1.

  The power supply device 53 includes a power supply board 53b and a power switch 53a connected to the power supply board 53b. The power switch 53a is pressed when supplying the necessary power to the pachi-slot 1. The power supply board 53 b is connected to the main control board 71 via the cabinet side relay board 44 and also connected to the sub control board 72 via the sub relay board 61.

  The pachislot machine 1 includes a door relay terminal plate 68, a selector 66, a door open / close monitoring switch 67, a BET switch 77, a checkout switch 78, which are connected to the main control board 71 via the door relay terminal plate 68. It has a start switch 79, a stop switch board 80, a game operation display board 81, a sub-relay board 61, a first testing machine interface board 301, and a second testing machine interface board 302. Since the selector 66, the door opening / closing monitoring switch 67, and the sub relay board 61 have been described above, the description thereof is omitted here.

  The BET switch 77 (insertion operation detecting means) detects that the MAX bet button 15a or the 1 bet button 15b has been pressed by the player. The settlement switch 78 detects that a settlement button (not shown) has been pressed by the player. The start switch 79 (start operation detecting means) detects that the start lever 16 has been operated by the player (start operation).

  The stop switch substrate 80 (stop operation detecting means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stopable main reel by an LED or the like. The stop switch substrate 80 is provided with a stop switch (not shown). The stop switch detects that each stop button 17L, 17C, 17R has been pressed by the player (stop operation).

  The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. The LED 82 includes, for example, three LEDs for displaying the number of inserted medals (hereinafter referred to as “first LED” to “first LED”) that are turned on in correspondence with the number of medals inserted in the current game (hereinafter referred to as “inserted number”). LED for lighting a medal insertion mark, a game start mark, a replay mark, etc. based on a signal input from the game operation display board 81) Etc. are included. In the first to third LEDs (display means), when one medal is inserted, the first LED is turned on, and when two medals are inserted, the first and second LEDs are turned on, and three medals (game) When the startable number of sheets is inserted, the first to third LEDs are turned on. Since the information display device 6 has been described above, the description thereof is omitted here.

  Both the first interface board 301 for testing machine and the second interface board 302 for testing machine are relay boards used when various signals relating to games are output to the testing machine in the pachislot 1 certification test (trial test) ( Since these relay boards are not mounted on the pachislot machine 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for testing machine and the testing machine. Various electronic components necessary for connecting to the second interface board 302 are also not mounted). For example, a test signal for controlling a main operation related to the game (for example, internal lottery, reel stop control, etc.) is output via the first interface board 301 for testing machine, and is determined by the main control board 71, for example. A test signal or the like related to the pushed push navigation is output via the second interface board 302 for the testing machine.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. The pachislot machine 1 includes a speaker group 84, LED groups 85, a 24h door opening / closing monitoring unit 63, a touch sensor 19, and a display unit 212, which are connected to the sub control board 72 via the sub relay board 61. Since the touch sensor 19 has been described above, the description thereof is omitted here.

  The speaker group 84 includes speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10 and a light source that emits light for illuminating the decorative panel of the waist panel 12 from the back side. The 24h door opening / closing monitoring unit 63 stores opening / closing history information of the middle door 41. Further, the 24h door opening / closing monitoring unit 63 outputs a signal for displaying an error by the display device 11 to the sub control board 72 (sub control circuit 200) when the middle door 41 is opened. The display unit 212 includes, for example, a projection target 212a constituting the display device 11, and another projection target with a curved display surface provided on the back side of the projection target 212a.

  The pachi-slot 1 also includes a ROM cartridge substrate 86 and a liquid crystal relay substrate 87 connected to the sub control substrate 72. The ROM cartridge substrate 86 and the liquid crystal relay substrate 87 are housed in the sub control board case 57 together with the sub control board 72.

  The ROM cartridge substrate 86 is a substrate for managing various control programs executed by the sub CPU 102, production images (videos), sound (speaker groups 84), light (LED groups 85), and communication data. . The liquid crystal relay substrate 87 is a substrate that relays connection wiring between the sub control substrate 72, the projector mechanism 211 constituting the display device 11, and the sub display device 18. Since the projector mechanism 211 and the sub display device 18 have been described above, the description thereof is omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. FIG. 8 is a block diagram illustrating a configuration example of the main control circuit 90 of the pachi-slot 1.

  The main control circuit 90 includes a microprocessor 91, a clock pulse generation circuit 92, a power management circuit 93, and a switching regulator 94 (power supply means).

  The microprocessor 91 is a microprocessor with a security function for gaming machines. In the microprocessor 91 of the present embodiment, as will be described later, various instruction codes specific to the microprocessor 91 that can be defined in the source program (for example, “LDQ” instruction described later, etc., hereinafter: “main CPU 101” A dedicated instruction code). In this embodiment, by using the instruction code dedicated to the main CPU 101, the processing efficiency and the program capacity are reduced. The internal configuration of the microprocessor 91 will be described in detail with reference to FIG. 9 described later, and the instruction code dedicated to the main CPU 101 provided in the microprocessor 91 will be described in detail in various processes executed by a main control circuit described later. To do.

  The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes a control program based on the input clock pulse signal.

  The power management circuit 93 manages fluctuations in the DC 12V power supply voltage supplied from the power supply board 53b (see FIG. 7). The power management circuit 93 outputs a reset signal to the “XSRST” terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the startup voltage value (10V) from 0V). When a power interruption occurs (when the power supply voltage falls below the power failure voltage value (10.5 V) from 12 V), a power interruption detection signal is output to the “XINT” terminal of the microprocessor 91. That is, the power management circuit 93 outputs a reset signal (start signal) to the microprocessor 91 when the power is turned on, and a power failure detection signal (power failure signal) to the microprocessor 91 when a power failure occurs. Also serves as a means to output (power failure means).

  The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (DC power supply voltage of 5 V DC) for the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

<Microprocessor>
Next, the internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 9 is a block diagram showing the internal configuration of the microprocessor 91.

  The microprocessor 91 includes a main CPU 101, a main ROM 102 (first storage means), a main RAM 103 (second storage means), an external bus interface 104, a clock circuit 105, a reset controller 105, an arithmetic circuit 107, A random number circuit 110, a parallel port 111, an interrupt controller 112, a timer circuit 113, a first serial communication circuit 114, and a second serial communication circuit 115 are included. These units constituting the microprocessor 91 are connected to each other via a signal bus 116.

  The main CPU 101 executes various control programs based on the clock pulse generated by the clock circuit 105 and performs control related to the overall game operation. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

  The main CPU 101 counts the number of times pulses are output to the stepping motors of the reels 3L, 3C, 3L (main reel) after detecting the reel index. Thereby, the main CPU 101 manages the rotation angle of each reel (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has made one revolution. The reel index includes, for example, an optical sensor having a light emitting unit and a light receiving unit, and a detection piece provided at a predetermined position of each reel and interposed between the light emitting unit and the light receiving unit by the rotation of each main reel. It is detected by a provided reel position detector (not shown).

  Here, management of the rotation angle of each reel 3L, 3C, 3L (main reel) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Each time the output of a predetermined number of pulses necessary for the rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 103 is incremented by one. A symbol counter is provided for each reel. The value of the symbol counter is cleared when a reel index is detected by a reel position detector (not shown).

  In other words, in the present embodiment, by managing the symbol counter, it is managed how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

  The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control commands (commands) to the sub control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as an internal winning combination determined by execution of the control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail with reference to FIG.

  The external bus interface 104 electrically connects an external signal bus (not shown) to which various components (for example, each reel) provided outside the microprocessor 91 are connected to the microprocessor 104. It is an interface circuit. The clock circuit 105 includes, for example, a frequency divider (not shown) and the like, and the clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is received by other components (for example, the timer circuit 113). Convert to a clock pulse signal of the frequency used. Note that the clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

  The reset controller 106 resets an IAT (Illegal Address Trap) or WDT (watchdog timer) based on the reset signal input from the power management circuit 93. The arithmetic circuit 107 includes a multiplication circuit and a division circuit. For example, when executing a “MUL (multiplication)” instruction (see FIG. 93B described later) on the source program, the arithmetic circuit 107 executes a multiplication process based on the “MUL” instruction.

  The random number circuit 110 generates a random number in a predetermined range (for example, 0 to 65535 or 0 to 255). Although not shown, the random number circuit 110 generates a random number register 0 for obtaining a 2-byte hard latch random number, random number registers 1 to 3 for obtaining a 2-byte soft latch random number, and a 1-byte soft latch random number. It is composed of random number registers 4 to 7 for obtaining. The main CPU 101 extracts one value from a predetermined range of random numbers generated by the random number circuit 110, for example, as a random value for internal lottery. The parallel port 111 is a port (memory map I / O) for signals input / output between the microprocessor 91 and various circuits (for example, the power management circuit 93) provided outside the microprocessor 91. . The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is connected to one of the input ports PI0 to PI4 of the parallel port 111, and the latch signal is sent from the parallel port 111 to the random number register 0 of the random number circuit 110 at a timing (on edge) when the start switch 79 is turned on. Is output. In the random number circuit 110, when the latch signal is input, the random number register 0 is latched, and a 2-byte hard latch random number is acquired.

  The interrupt controller 112 performs an interrupt process by the main CPU 101 based on a power interruption detection signal input from the power management circuit 93 via the parallel port 111 or a time-out signal input from the timer circuit 113 at a cycle of 1.1172 ms. Control the execution timing of. When a power failure detection signal is input from the power management circuit 93 or a time-out signal is input from the timer circuit 113, the interrupt controller 112 sends an interrupt request signal indicating an interrupt processing start command to the main CPU 101. Output to. Based on the interrupt request signal input from the interrupt controller 112 in response to the time-out signal from the timer circuit 103, the main CPU 101 performs input port check processing, reel control processing, communication data transmission processing, 7-segment LED drive processing, timer Various interrupt processes such as an update process (see FIG. 100 described later) are performed.

  The timer circuit 113 (PTC) operates with a clock pulse signal generated by the clock circuit 105 (clock pulse signal having a frequency obtained by dividing a clock pulse signal for operating the main CPU by a frequency divider (not shown)). Count elapsed time). Then, the timer circuit 113 outputs a timeout signal (trigger signal) to the interrupt controller 112 at a cycle of 1.1172 msec.

  The first serial communication circuit 114 is a circuit that controls a serial transmission operation when data (various control commands (commands)) is transmitted from the main control board 71 to the sub-control board 72. The second serial communication circuit 115 is a circuit that controls a serial transmission operation when data is transmitted from the main control board 71 to the second interface board 302 for the testing machine.

<Sub control circuit>
Next, the configuration of the sub control circuit 200 (sub control means) mounted on the sub control board 72 will be described with reference to FIG. FIG. 10 is a block diagram illustrating a configuration example of the sub control circuit 200 of the pachislot 1.

  The sub control circuit 200 is electrically connected to the main control circuit 90 and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 90. The sub control circuit 200 basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

  The sub CPU 201 is connected to the ROM cartridge substrate 86. The driver 205 is connected to the liquid crystal relay substrate 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub display device 18 via the liquid crystal relay substrate 87.

  The sub CPU 201 controls the output of video, sound, and light according to the control program stored in the ROM cartridge substrate 86 in accordance with the command transmitted from the main control circuit 90. The ROM cartridge substrate 86 basically includes a program storage area and a data storage area.

  In the program storage area, a control program executed by the sub CPU 201 is stored. For example, in the control program, a main board communication task for controlling communication with the main control circuit 90 and a random number value for production are extracted, and production registration for determining and registering production contents (production data). Various programs for executing tasks are included. In addition, the control program includes an animation task for controlling the display of video by the display device 11 based on the determined contents of the presentation, a lamp control task for controlling the output of light from a light source such as the LED group 85, and the sound of the speaker group 84. Various programs for executing a sound control task for controlling output are also included.

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to creation of video. Further, the data storage area includes a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to a light on / off pattern, and the like.

  The sub-RAM 202 is provided with a storage area for registering the determined contents and effects data, and a storage area for storing various data such as an internal winning combination and navigation data transmitted from the main control circuit 90.

  The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create a video according to the animation data designated by the contents of the presentation, and display the created video on the display device 11 (projector mechanism 211) and / or Alternatively, it is displayed on the sub display device 18. The display device 11 (projector mechanism 211) and the sub display device 18 are individually controlled by the sub control board 72.

  Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM according to the sound data specified by the contents of the effect. Further, the sub CPU 201 controls lighting and extinguishing of the LED group 85 according to the lamp data designated by the contents of the effect.

<Various registers of main CPU>
Next, various registers included in the main CPU 101 will be described with reference to FIG. FIG. 11 is a schematic configuration diagram of various registers included in the main CPU 101.

  The main CPU 101 includes, as main registers, an accumulator A (hereinafter referred to as “A register”), a flag register F (flag register), a general purpose register B (hereinafter referred to as “B register”), and a general purpose register C (hereinafter referred to as “register A”). General purpose register D (hereinafter referred to as “D register”), general purpose register E (hereinafter referred to as “E register”), general purpose register H (hereinafter referred to as “H register”) and general purpose register L (hereinafter referred to as “C register”). , Referred to as “L register”). Further, the main CPU 101 includes, as sub registers, an accumulator A ′, a flag register F ′, a general purpose register B ′, a general purpose register C ′, a general purpose register D ′, a general purpose register E ′, a general purpose register H ′, and a general purpose register L ′. As a general purpose register. Each register is composed of a 1-byte register.

  In this embodiment, the B register and the C register are used as a pair register (hereinafter referred to as “BC register”), and the D register and the E register are used as a pair register (hereinafter referred to as “DE register”). Furthermore, in this embodiment, the H register and the L register are used as a pair register (hereinafter referred to as “HL register”).

  As shown in FIG. 11, predetermined flag information indicating the result of the arithmetic processing is set in each bit of the flag registers F and F ′. For example, in bit 6 (D6), data (zero flag) indicating whether or not the calculation result is “0” in the calculation result determination process is set. Specifically, when the operation result is “0”, data “1” is set in bit 6, and when the operation result is not “0”, data “0” is set in bit 6. In the calculation result determination process, the main CPU 101 performs determination (YES / NO) with reference to the data “0” / “1” of bit 6.

  The main CPU 101 has an extension register Q (hereinafter referred to as “Q register”). The Q register is composed of a 1-byte register. In this embodiment, as will be described in the various processing flows described later, various instruction codes dedicated to the main CPU 101 for performing address designation using the Q register are provided on the source program. As a result, the processing efficiency and the capacity of the main ROM 102 are reduced. In various instruction codes dedicated to the main CPU 101 that perform address designation using the Q register, the address data (address value) on the upper side of the address is stored in the Q register. In the Q register, “F0H” is set as an initial value immediately after the main CPU 101 is reset. In addition, in the “LD Q, n (8-bit data)” instruction using the Q register, the value of the Q register is changed by setting arbitrary 1 byte data to “n” and executing the instruction. be able to.

  Further, the main CPU 101 includes an interrupt page address register I and a memory refresh register R configured by 1-byte registers, and an index register IX and an index register IY configured by 2-byte registers. The stack pointer SP and the program counter PC are provided as dedicated registers.

<Internal configuration of main ROM and main RAM (memory map)>
Next, the internal configuration of the main ROM 102 and the main RAM 103 (hereinafter referred to as “memory map”) included in the main control circuit 90 (microprocessor 91) will be described with reference to FIGS. 12A to 12C. 12A is a diagram showing a memory map of the entire memory, FIG. 12B is a diagram showing a memory map of the main ROM 102, and FIG. 12C is a diagram showing a memory map of the main RAM 103.

  In the memory map of the entire memory included in the main control circuit 90 (microprocessor 91), as shown in FIG. 12A, from the head (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the built-in register area, The XCS decode areas are arranged at predetermined addresses in this order with an unused area in between.

  In the memory map of the main ROM 102, as shown in FIG. 12B, from the head (0000H) side of the address of the main ROM 102, there are a program area, a data area, an unspecified area, a trademark recording area, a program management area, and a security setting area. In order, they are arranged at predetermined addresses.

  In the program area, control programs for various processes executed by the main CPU 101 in various control processes related to game playability performed by the player are stored. In the data area, various data used by the main CPU 101 (for example, a data table such as an internal lottery table, various sub-control circuits 200, etc.) in various control processes related to game playability performed by the player. Data for transmitting a control command (command), etc.) are stored. In other words, the game ROM area (game storage area) composed of a program area and a data area is necessary for control processing (game-related processing) related to game playability actually performed by the player at the game store. Various programs and various data are stored.

  The non-regulated area stores control programs and data for various processes (processes that do not affect the game characteristics) that are not directly related to the game performance of the game executed by the player. For example, a program and data used in a pachislot 1 certification test (trial test), a control program and data used in checksum generation processing at power interruption or sum check processing at power recovery, and a fraud countermeasure program In addition, data necessary for the data and the like are stored in an unspecified area.

  In the memory map of the main RAM 103, as shown in FIG. 12C, from the head (F000H) side of the address of the main RAM 103, a gaming RAM area (predetermined storage area, gaming temporary storage area) and an unspecified RAM area (unspecified temporary area). Storage areas) are arranged at predetermined addresses in this order.

  The game RAM area is provided with a work area and a stack area for temporarily storing various data such as an internal winning combination determined by the execution of a control program related to the game performance of the game executed by the player. . Each of the various data is stored in a work area at a predetermined address in the game RAM area.

  In addition, the non-specified RAM area is provided with a non-standard work area that is a work area for various processes that are not directly related to the game performance of the game executed by the player, and a non-standard stack. In the present embodiment, various processes that are not directly related to the game playability of the game executed by the player, such as a sum check process, are executed using the non-regulated RAM area.

  As described above, in the pachislot machine 1 of the present embodiment, various programs and various data (tables) used for various processes that are not directly related to the game performance of the game performed by the player are stored in the main ROM 102. The data is stored in a non-standard ROM area (non-standard storage area) arranged at an address different from the ROM area. In addition, various processes that are not directly related to game playability performed by such a player are performed in the main RAM 103 using an unspecified RAM area that is arranged at an address different from the game RAM area. .

  In such a configuration of the main ROM 102, programs and data that are not necessary for the game itself actually played by the player are placed in the ROM area (non-specified ROM area) where it is impossible to place a program or the like according to the conventional rules. can do. Therefore, in this embodiment, compression of the capacity of the game ROM area can be avoided.

<Game state transition flow>
Next, various game states managed by the main control circuit 90 (main CPU 101) of the pachi-slot 1 of this embodiment and the transition flow thereof will be described with reference to FIGS. FIG. 13 is a transition flow diagram of the basic gaming state of the pachislot 1. FIG. 14A is a game state transition flow diagram in consideration of whether or not the notification (ART) function is activated, and FIG. 14B is a table summarizing the game state transition conditions.

[Basic game state transition flow]
In the pachi-slot 1 of the present embodiment, a big bonus (hereinafter referred to as “BB”) and a middle bonus (hereinafter referred to as “MB”) are provided as bonus game types. BB is an accessory continuous actuating device related to a first type special feature that continuously operates a regular bonus (hereinafter referred to as “RB”) called a first type special feature, and MB is a second type of special feature. This is a continuous actuating device for a second type special feature that continuously activates a challenge bonus called a special feature (hereinafter referred to as “CB”).

  In the pachi-slot 1 of the present embodiment, the basic gaming state can be roughly divided into a bonus state and a non-bonus state. The bonus state is a state in which the above-described BB is operating (BB gaming state, hereinafter also referred to as “BB in operation”), or an MB in operation (MB gaming state, hereinafter “MB in operation”). The non-bonus state refers to a state where the BB and MB are not operating (general gaming state, hereinafter also referred to as “normally”). In addition, when BB is won in the non-bonus state, the BB winning is carried over until the BB is activated (winning), and the state where the BB is carried over is the bonus winning state (in this embodiment, RT4 state to be described later (hereinafter also referred to as “between flags”). That is, the non-bonus state is further divided into a bonus winning state in which the BB has been won (carried over) and a bonus non-winning state in which the BB has not been won (not carried over). Can be distinguished.

  In the BB gaming state (more specifically, the RB gaming state continuously operated), a game in which the winning probability of a predetermined small role (for example, “F_Common Bell” described later) is higher than the non-bonus state. This is a state (see FIGS. 16 and 17 to be described later), and is a gaming state that is advantageous to the player who can increase the number of medals.

  In addition, the MB gaming state (more specifically, the CB gaming state continuously operated) is the maximum for a specific reel (in this embodiment, the reel 3R) when a stop operation is performed by the player. The number of sliding symbols is reduced from 4 symbols (1st symbol number) to 1 symbol (2nd symbol number), and all of the small winning roles (specifically, internal winning combinations that can be determined) NML01 to 23 described later are game states determined as internal winning combinations (see FIG. 18 and FIG. 64 described later), which is a game state advantageous to the player who can increase medals. Even in the MB gaming state, for the replay combination, the winning probability in the RT state in the non-bonus state (see FIGS. 16 and 17 described later) is taken over and the internal lottery process is performed.

  Further, the non-bonus state is composed of a plurality of RT states in which a part or all of the winning probabilities of a plurality of types of replay combinations can be changed. In this embodiment, the RT state includes an RT0 state (RT0 gaming state, hereinafter simply referred to as “RT0”), an RT1 state (RT1 gaming state, hereinafter also simply referred to as “RT1”), an RT2 state (RT2 gaming state, Hereinafter, it is composed of an RT3 state (RT3 gaming state, hereinafter simply referred to as “RT3”), and an RT4 state (RT4 gaming state, hereinafter also simply referred to as “RT4”).

  As shown in FIG. 13, in the pachislot machine 1 of this embodiment, when the set value is changed (see FIG. 40 described later) (setting change), the RT state is shifted to the RT0 state (RT0). In that sense, the RT0 state (RT0) can be said to be an initial gaming state. Also, when the BB gaming state is ended, the RT state is shifted to the RT0 state (RT0).

  In the RT0 state (RT0), when “bell spilled eyes” is displayed on the active line, the RT state is shifted to the RT1 state (RT1). “Bell spilled eyes” indicates a combination of symbols of “S_RT1 transition A”, “S_RT1 transition B” and “S_RT1 transition C” described later (see FIG. 18 described later).

  In the RT1 state (RT1), when “RT2 transition lip” is displayed on the active line, the RT state is shifted to the RT2 state (RT2). Note that “RT2 transition lip” indicates a combination of symbols of “C_RT2 lip” described later (see FIG. 18 described later). In the RT1 state (RT1), when “RT3 transition lip” is displayed on the active line, the RT state is shifted to the RT3 state (RT3). The “RT3 transition lip” indicates a combination of symbols of “S_RT3 lip”, “C_SP_CL lip”, “C_SP_XU lip”, and “C_SP_XD lip” described later (see FIG. 18 described later).

  In the RT2 state (RT2), when the above-mentioned “RT3 transition lip” is displayed on the valid line, the RT state is shifted to the RT3 state (RT3). In the RT2 state (RT2) and the RT3 state (RT3), when the above-mentioned “bell spill” or “RT1 transition lip” is displayed on the effective line, the RT state is shifted to the RT1 state (RT1). Note that “RT1 transition lip” indicates a combination of symbols of “S_RT1 lip A” and “S_RT1 lip B” described later (see FIG. 18 described later).

  In addition, when BB is determined as an internal winning combination in the RT0 state (RT0), the RT1 state (RT1), the RT2 state (RT2), and the RT3 state (RT3) (conditional device operation relating to “BB”), RT The state is shifted to the RT4 state (RT4). This RT4 state (RT4) is the above-described bonus winning state (inside the BB) and is maintained until the BB is activated (winning).

  In the RT4 state (RT4), when BB operates (wins), that is, when a combination of symbols “C_BB” (see FIG. 18 described later) is displayed on the active line (design combination display of “BB”). The gaming state is shifted to the BB gaming state, and in the BB gaming state (when the BB is operating), the RB gaming state (when the RB is operating) until a predetermined termination condition is satisfied (there is a payout exceeding 144 cards). ) And the predetermined termination condition is satisfied, the BB gaming state and the RB gaming state are terminated, and as described above, the state shifts to the RT0 state (RT0) in the non-bonus state.

  When MB is determined as an internal winning combination in the RT0 state (RT0), the RT1 state (RT1), the RT2 state (RT2), and the RT3 state (RT3) (conditional device operation relating to “MB”), RT The state does not change and the MB win is carried over until the MB is activated (winning). However, in the pachislot machine 1 of this embodiment, the symbol arrangement (see FIG. 15 to be described later) and the combination of symbols (see FIG. 18 to be described later) are defined so that the MB always operates (wins) in the winning game. Therefore, the gaming state as a bonus winning state is not defined.

  The MB operates (wins) in the RT0 state (RT0), the RT1 state (RT1), the RT2 state (RT2), and the RT3 state (RT3), that is, the symbol combination of “C_MB” (see FIG. 18 described later). Is displayed on the active line (“MB” symbol combination display), the gaming state is shifted to the MB gaming state, and in this MB gaming state (in MB operation), a predetermined termination condition is satisfied. When the CB gaming state (when the CB is in operation) is controlled until (there is more than 13 payouts) and a predetermined termination condition is satisfied, the MB gaming state and the CB gaming state are terminated, and the non-bonus state Transition to the RT state.

  Whether or not the bonus combination is won is managed based on data stored in a hit request flag storage area (see FIG. 22 described later) and a carryover combination storage area (see FIG. 23 described later) provided in the main RAM 103. Is done. Further, each gaming state described above is managed based on data stored in a gaming state flag storage area (described later in FIG. 24) provided in the main RAM 103.

[Game State Transition Flow Considering Operation of Notification (ART) Function]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not to activate a function (ART function) that notifies a stop operation that is advantageous to the player. Therefore, in this embodiment, the operating / non-operating state of the ART function is also managed as the gaming state. In FIG. 14, in order to distinguish from the gaming states described in FIG. 13, the gaming state relating to the operation / non-operation state of the ART function will be described as an “effect gaming state”.

  In the pachi-slot 1 of the present embodiment, the basic effect gaming state can be broadly classified into an ART gaming state (ART) and a non-ART gaming state (non-ART). The ART gaming state refers to a state in which the ART function is activated (that is, an effect gaming state in which information on a stop operation advantageous to the player is notified and an advantageous state advantageous to the player), and a non-ART gaming state. Is a state in which the ART function is not activated (that is, an effect gaming state in which information on a stop operation advantageous to the player is not notified and a disadvantageous state disadvantageous to the player).

  Further, as shown in FIG. 14A, the non-ART gaming state is composed of a directing gaming state of “normal time”, “BB history specializing zone”, and “chance zone (CZ)”, and the ART gaming state is “Normal ART”, “Continuous Challenge”, “BB CP Special Zone”, and “Double Special Zone” are produced. As another effect game state, there is an “elevation chance” which is an effect game state for determining (adding) the number of continuous games (ART game number) in the ART game state. However, as will be described later, the “promotion chance” is an effect gaming state that has already been determined to be shifted to the ART gaming state, and thus is substantially included in the ART gaming state.

("Normal time")
The effect game state “normal time” (normal game state) is the most disadvantageous game state for the player, and the player usually starts the game from this “normal time”. In “normal time”, an ART lottery is performed based on the normal mode and the internal winning combination, and by winning the ART lottery, the effect gaming state shifts to the ART gaming state (ART winning). Details of the normal mode and the ART lottery will be described later with reference to FIGS. In addition, in the “normal time”, when an ART lottery is won, a promotion lottery for determining whether or not to shift to a promotion chance is performed, and by winning this promotion lottery, prior to the transition to the ART gaming state. The production gaming state shifts to “promotion chance” (part of the ART win).

  Further, when “BB” operates (wins) in “normal time”, that is, when a combination of symbols “C_BB” (see FIG. 18 described later) is displayed on the active line, the BB gaming state is the effect gaming state. It becomes the “BB history specializing zone” (BB prize).

  Further, in the “normal time”, CZ lottery is performed based on the CZ mode and the internal winning combination, and when the CZ lottery is won, the effect gaming state shifts to the “chance zone” (CZ winning). In the CZ mode, as in the normal mode, the transition lottery is performed based on the current CZ mode and the internal winning combination. For example, as the CZ mode, “normal”, “high accuracy”, and “super high accuracy” are used. CZ mode such as “can be provided. If the CZ mode is “normal”, the CZ lottery winning probability is relatively low (or the CZ lottery is not won). If the CZ mode is “high”, the CZ lottery winning probability is If the CZ mode is relatively high and “super high accuracy”, the CZ lottery winning probability can be configured to be the highest.

("BB special history zone")
The stage gaming state “BB history special zone” is a gaming state that is more advantageous to the player than “normal” in that it is a BB gaming state, but is not an ART gaming state (or an ART gaming state). This is a disadvantageous gaming state for the player in that he has not acquired the right to transition to As described above, the process shifts to the “BB history specialization zone” when the BB operates (wins) in “normal time”.

  In the “BB history specialization zone”, an ART lottery is performed based on a winning history (or a winning history) of internal winning combinations for a predetermined number of games (for example, 5 games). By winning the ART lottery, the effect gaming state shifts to the ART gaming state after the end of the “BB history specializing zone” (that is, after the end of the BB gaming state) (ART winning). In the “BB history specialization zone”, when an ART lottery is won, a promotion lottery is performed as to whether or not to shift to a promotion opportunity. By winning this promotion lottery, the ART gaming state is set. Prior to the transition, the production gaming state shifts to “promotion chance” (part of the ART win).

  An example of the ART lottery based on the winning history of the internal winning combination is as follows. In the “BB history specializing zone”, when the “F_common bell” described later (see FIG. 17 described later) is won, the first history Is stored, and the second history is stored in the case of winning “F_BB chance chance role A”, “F_BB chance chance role B”, and “F_BB chance chance role C” (see FIG. 17 described later). The The ART lottery is performed when the stored second history satisfies a specific condition (for example, when the number of winning histories for five games is three or more). Note that a plurality of specific conditions can be set, and the degree of expectation for winning the ART lottery can be made different. Further, the winning probability of the promotion lottery for determining whether or not to shift to the promotion chance can be made different depending on the specific condition.

  In addition, in the “BB history specializing zone”, when the BB gaming state ends before winning the ART lottery, the effect gaming state shifts to “normal time”.

("Chance Zone" (CZ))
The production gaming state “chance zone” is a gaming state that is more advantageous to the player than “normal time” in terms of high expectation for transition to the ART gaming state, but is not an ART gaming state (or an ART gaming state). This is a disadvantageous gaming state for the player in that he has not acquired the right to enter the gaming state. As described above, the “chance zone” is entered when the CZ lottery is won in “normal time”.

  The “chance zone” continues for a predetermined number of games (for example, 5 games) from the start, and during that time, the internal winning is performed with a higher probability than the “normal time” (see FIG. 29 described later). An ART lottery is performed based on the combination. For example, in the “chance zone”, ART is won with a probability of about 1/8 of every game. Then, by winning the ART lottery, the effect gaming state shifts to the ART gaming state (ART winning). In the “Chance Zone”, when an ART lottery is won, a promotion lottery is performed to determine whether or not to shift to a promotion chance. By winning this promotion lottery, prior to the transition to the ART gaming state, The production gaming state shifts to “promotion chance” (part of the ART win).

  Here, when an ART lottery is won in the “chance zone”, the probability of winning an elevated lottery indicating whether or not to shift to a promotion chance is higher than when an ART lottery is won in other non-ART gaming states. It is supposed to be. Therefore, in that sense, it can be said that the “chance zone” is more advantageous than other non-ART gaming states.

  Also, in the “chance zone”, if the ART lottery is not won even if the above-mentioned predetermined number of games is exhausted, the effect game state shifts to “normal time”. Of course, in the “chance zone”, after the above-mentioned predetermined number of games has been digested, the game end lottery is performed, and when the end lottery is won, the “chance zone” is ended, but the end lottery is not won. In such a case, the “chance zone” may be continued.

  In the non-ART gaming state (more specifically, “normal time” and “chance zone”), if the player wins “F_SP Lip A”, “F_SP Lip B”, and “F_SP Lip C” described later, As the state shifts to the RT3 state (RT3), the production gaming state shifts to the “double special zone” (the blue 7 role is established). That is, the internal winning combination of “F_SP Lip A”, “F_SP Lip B”, and “F_SP Lip C”, which will be described later, is one of the final winning combinations that are determined to shift to the ART gaming state.

  Here, the internal winning combination of “F_SP Lip A” indicates that the “blue 7” symbol, which will be described later, is displayed in the middle area of the left reel 3L, the middle area of the middle reel 3C, and the right reel 3R regardless of the procedure of the stop operation. This is an internal winning combination that allows to be lined up on a line (center line) that connects the middle region of the “F_SP Lip B”. The internal winning combination of “F_SP Lip B” , Which is an internal winning combination that makes it possible to line up a line (cross-up line) connecting the lower area of the left reel 3L, the middle area of the middle reel 3C, and the upper area of the right reel 3R. Regardless of the stopping operation procedure, the internal winning combination is a line (cross-down) in which the “blue 7” symbol described below connects the upper area of the left reel 3L, the middle area of the middle reel 3C, and the lower area of the right reel 3R. line) An internal winning combination that allows aligned (see FIG. 19 described later). Therefore, the player can recognize that the transition to the ART gaming state is confirmed by arranging the “blue 7” symbols.

  Further, in the non-ART gaming state, when winning a “F_black BAR” described later, it is determined that the effect gaming state shifts to the ART gaming state. That is, an internal winning combination of “F_black BAR” to be described later is one of the finalized combinations that are determined to shift to the ART gaming state. Further, the internal winning combination of “F_black BAR” is an internal winning combination that allows the “black BAR” symbols described later to be arranged on the above-described center line regardless of the procedure of the stop operation. 20). In addition, when winning the “F_black BAR” and shifting to the ART gaming state, “100” game is given as the initial ART game number and “3” is given as the ART stock number. ing. Therefore, the player can recognize not only that the transition to the ART gaming state is confirmed by the arrangement of the “black BAR” symbols, but also that a plurality of ART stocks have been given.

  In this way, in the pachislot 1 of the present embodiment, the internal winning combination of “F_black BAR” described later has the highest expectation of the transition of the ART gaming state and the accompanying game media acquisition. It is positioned as a special internal winning role (premium role) that is of most interest to the world.

  Here, “ART stock” is a right to play a game in one set of ART gaming states when a predetermined number of ART games (50 games in this embodiment) is set as one set. means. In other words, “ART stock” is a right that allows a game to be played in “normal ART” described later for at least 50 games. Therefore, “3” is granted as the number of ART stocks is synonymous with the fact that the right to play an ART game (3 sets) of at least 150 games is granted. However, since the number of ART games per set may be added as will be described later, the number of ART games per set is actually indefinite. In the present embodiment, the addition of the number of ART games (or the number of sets) may be described as extending the gaming period in the ART gaming state.

  Also, in the non-ART gaming state (more specifically, “normal time” and “chance zone”), when in the MB gaming state, the MB medium lock effect lottery is performed, and when this MB medium lock performance lottery is won In addition, it is determined that the effect effect state during the MB is executed and the effect game state shifts to the ART game state. In this MB lock effect, the player's gaming operation (for example, stop operation) is invalidated for a predetermined period (for example, about 10 seconds), and any of the “black BAR” symbols described later is selected within this predetermined period. By operating the reels 3L, 3C, 3R so as to line up with other lines (for example, a cross-up line or a cross-down line), the display window is not limited to the center line which is an effective line. 4 is an effect that makes it possible to temporarily stop a “black BAR” described later. In addition, when the MB medium lock effect is executed and the state shifts to the ART gaming state, “100” game is given as the initial ART game number and “3” is given as the ART stock number. Yes. Therefore, the player can recognize that the transition to the ART gaming state has been confirmed by the fact that the “black BAR” symbols are arranged (provisionally stopped), as in the case of winning “F_black BAR” described later. In addition, it can be recognized that a plurality of ART stocks have been given.

  Here, in the pachislot 1 of the present embodiment, except for the MB gaming state, the probability that “F_black BAR” to be described later is determined as an internal winning combination is defined as “8/65536” (ie, 1/8192). (See FIG. 17 described later). In the MB gaming state, the probability that the above-described MB lock effect is determined to be executed is defined as “8/65536” (that is, 1/8192).

  As described above, in the pachislot machine 1 according to the present embodiment, in a gaming state different from the special gaming state (for example, the MB gaming state), a specific combination (for example, “F_black” that is an advantageous state (for example, during ART) BAR ”) and the execution probability of a specific lock effect that triggers the advantageous state in the special gaming state are configured to have the same probability (for example, 8/65536). In other words, an advantageous operation trigger can be obtained with a certain probability regardless of which gaming state the gaming state is. Therefore, the interest of the game can be improved.

  Further, in the pachislot 1 of the present embodiment, when a specific lock effect is executed in a special game state (for example, MB game state), a combination of symbols (for example, “C_black BAR”) related to a specific role is performed. The combination of symbols) is configured to temporarily stop. In other words, if a combination of symbols relating to a specific combination is displayed regardless of which gaming state the gaming state is, the player can be made aware that the trigger for the advantageous state has been established. ing. Therefore, for example, even in a special gaming state, even when there are restrictions on the determination of the internal winning combination and the reel stop control, the player can easily perceive that the operation trigger of the advantageous state has been established. In addition, the interest of the game can be improved.

("Normal ART")
The effect game state “normal ART” is a game state in which an ART game is performed by consuming the acquired number of ART games. That is, it is a basic gaming state in the ART gaming state.

  In the case of transitioning from the non-ART gaming state to “normal ART”, for example, if the current RT state is the RT1 state, until the RT state transitions to the RT3 state by notification of stop operation information (see FIG. 13). ) The acquired number of ART games is not consumed (that is, not subtracted), and the number of ART games is consumed when the RT state becomes the RT3 state. The game state during this period can be defined as “ART ready state” (ie, the state in which only the AT function is activated and the RT function is not yet activated). The gaming state may be managed. The same applies to the case of shifting from “BB CP special zone” or “promotion chance” described later to “normal ART”.

  To “normal ART”, as described above, in the non-ART gaming state, when the ART lottery is won and the promotion lottery is not won (ART win), the “promotion chance” is ended (not promoted). And, when it is determined that the ART gaming state is to be continued when the “continuation challenge” is finished (CP = 0 and ART game (set number stock) exists), the process proceeds.

  In addition, although not shown in FIG. 14, as described above, when the “F_black BAR” described later is won in the non-ART gaming state, when the lock effect during MB is executed, “CP during BB” When the “specialized zone” has ended and when the “double specialized zone” has ended, the effect gaming state shifts to “normal ART”.

  In the present embodiment, the basic number of ART games per set is set to “50” games, and the number of ART games is 0 in “normal ART” (that is, 50 games are not considered when adding up). The “normal ART” in the set ends. Here, if the CP is acquired when the “normal ART” in the set ends, the effect gaming state shifts to the “continuation challenge” (normal ART ends and CP> 0).

  Here, “CP” is an abbreviation of “challenge point”, and it is determined whether or not to add the number of ART games (that is, the number of games of “normal ART”) in the “continuation challenge” described later. Is the right to be able to be done. In that sense, it is not a right that allows the ART gaming state to continue directly, but it is a right that has value to the player. Note that a plurality of CPs can be held in the ART gaming state in the same manner as the above-described ART stock.

  Further, when the “normal ART” in the set ends, even if the CP is not acquired, if the above-mentioned ART stock is acquired, the ART stock is consumed (that is, the ART stock counter). 1 is subtracted), and the game can be played in “Normal ART” until the 50 games are consumed again (that is, the next set is started).

  At this time (that is, when the next set is started), a promotion lottery is performed to determine whether or not to move to the promotion chance. By winning the promotion lottery, the production is performed prior to the start of “Normal ART”. The gaming state shifts to “promotion chance” (part of the start of the next ART set). In addition, if the ART stock is determined to be transferred to a promotion opportunity (special ART stock) when the ART stock is acquired, prior to the start of “Normal ART” without performing a promotion lottery. Thus, the production gaming state shifts to “promotion chance” (part at the start of the next ART set). The special ART stock is easily acquired mainly when winning “F_black BAR”, which will be described later, and when a mid-MB lock effect is executed.

  Here, when the “normal ART” in the set ends, the player has acquired both ART stock and CP (that is, the value of the ART stock counter is “1” or more and the value of the CP counter If it is also “1” or more), before consuming the ART stock and moving to the next set, first decide whether to consume the CP and continue (extend) the set. The game state is shifted to “Continuous Challenge”.

  In addition, when the “normal ART” in the set ends, the player has not acquired the ART stock or CP (that is, the value of the ART stock counter is “0”, and the value of the CP counter is also “ 0 ”), the ART gaming state is terminated, and the non-ART gaming state (more specifically,“ normal time ”) is entered.

  The CP can be acquired mainly in the “BB Specialized Zone in BB” or “Double Specialized Zone” described later, but also in “Normal ART” based on the internal winning combination. The CP acquisition lottery is performed, and when the CP acquisition lottery is won, the CP can be acquired even during the “normal ART”.

  In addition, ART stock can be acquired mainly in a “double specialization zone” described later. As described above, “F_black BAR” described later is determined as an internal winning combination. It can also be obtained when a lock effect during MB is executed, but even during “normal ART”, an ART stock lottery is performed based on the internal winning combination. When the stock lottery is won, the ART stock can be acquired even during “normal ART”.

  In addition, during the “normal ART”, the number of ART games is directly added to a lottery based on the internal winning combination so that a lottery is performed. If the ART game number is added to the lottery, It is also possible to add the number of ART games.

  In “normal ART”, when the BB is activated (winning), that is, when the combination of symbols “C_BB” (see FIG. 18 described later) is displayed on the active line, the BB gaming state is the production gaming state. It becomes “BB special zone for BB” (BB prize in ART).

  In addition, when “F_SP Lip A”, “F_SP Lip B”, and “F_SP Lip C”, which will be described later, are won in “Normal ART”, the production gaming state shifts to the “Double Specialized Zone” (blue 7 role) Established).

("Continuous Challenge")
The production game state “continuation challenge” is a game state in which it is determined whether or not the acquired CP is consumed and the ART game state (more specifically, “normal ART” in the set) is continued. As described above, the “continuation challenge” shifts to the case where the CP has been acquired when the “normal ART” in the set ends.

  In “Continuous Challenge”, as long as there are CPs earned, if you win a replay role (for example, RT3 Lip described later), you will be challenged to aim for a specific symbol (in this case, “Blue BAR” symbol) (An effect that suggests that the display should be stopped) is performed. When the “blue BAR” symbol is arranged on a specific line (in this embodiment, the line is different from the effective line, but may be an effective line), CP is not consumed (ie, CP is subtracted). A predetermined number of ART games (for example, 50 games) is given. On the other hand, when the “blue BAR” symbol does not line up with a specific line, CP is consumed (that is, CP is subtracted) and the number of ART games is not given. However, regardless of whether or not the “blue BAR” symbols are arranged on a specific line, when one challenge effect is executed, CP is always consumed (ie, CP is subtracted). May be.

  The execution of this challenge effect is repeated until the CP becomes 0, and if the number of ART games is acquired when the CP becomes 0, the number of ART games acquired in the set indicates “ Return to "Normal ART". Even if the number of ART games has not been acquired, if the ART stock has been acquired, the acquired ART stock is consumed and a transition is made to “normal ART” in the next set (CP = 0 and the number of ART games) (There is a set number stock)). On the other hand, if the number of ART games and the ART stock have not been acquired when the CP becomes 0, the ART gaming state ends and the state shifts to a non-ART gaming state (more specifically, “normal time”). To do.

  In the “continuation challenge”, when a predetermined replay role (for example, RT3 Lip C described later) is won, a special activation lottery (transition lottery) of “promotion chance” is performed, and when this special activation lottery is won , A definite challenge effect (that is, notification until the pressing order that the specific symbol is arranged in the specific line) that definitely notifies that the specific symbol (in this case, “blue 7” symbol) is aligned in the specific line Based on the fact that this finalized challenge effect is performed, the directing game state shifts to “promotion chance” (part of the extra during the continuous challenge).

  Further, in the “continuation challenge”, when a specific replay role (for example, RT3 Lip B described later) is won, the above-described finalized challenge effect (however, the specific symbol in this case is the “blue BAR” symbol) A predetermined number of ART games (for example, 50 games) is awarded based on the fact that the finalized challenge effect is performed. At this time, the “promotion chance” activation lottery (transition lottery) is performed, and when the activation lottery is won, the production gaming state shifts to “promotion chance” (part of the addition during the continuous challenge).

  That is, in the “continuation challenge”, based on the acquired CP, whether or not to increase the number of ART games is added and lottery for transition to “promotion chance” is also performed. .

  In the “continuation challenge”, the addition lottery mode of the number of ART games based on the acquired CP is not limited to the above. For example, in the “Continuous Challenge”, it is determined whether to add the number of ART games based on each game and internal winning combination, and if it wins, the CP is not consumed, and if it is not won, the CP is consumed. This may be repeated until CP becomes zero.

  Further, when it is determined that the number of ART games is to be added, the number of ART games to be added may be further determined by lottery.

  In addition, the mode of the lottery for the transition to the “promotion chance” based on the acquired CP in the “continuation challenge” is not limited to the above. For example, when a lottery for shifting to “promotion chance” is won, an initial value of “number of continuations” described later in “promotion chance” may be further determined by lottery.

  As described above, in the pachislot machine 1 of the present embodiment, the advantageous state (for example, during ART) includes the first advantageous state (for example, normal ART) and the second advantageous state (for example, continuous challenge), In the advantageous state, in the second advantageous state, a plurality of specific rights (for example, CP) for granting lottery (determining whether or not to extend the game period) of the number of games in the first advantageous state may be granted. It is configured to be possible.

  In addition, when the specific right is granted when the first advantageous state ends, the state is shifted to the second advantageous state, and in the second advantageous state, the specific right is consumed and the first advantageous state is consumed. When the number of games is added, a lottery (deciding whether or not to extend the game period) is performed, and when the winning lottery is won (when it is determined to extend the game period), the first advantageous state is continued. It is configured to be able to.

  If a plurality of specific rights have been acquired, the specific rights will not be wasted and all will be added to the number of games in the first advantageous state (determination of whether to extend the game period) ). Therefore, in the second advantageous state, not only is it determined whether or not to continue the advantageous state, but also a possibility that a large number of games can be added at a time can be created. A variety of characteristics can be achieved, and the fun of the game can be improved.

  Further, in the pachislot machine 1 of the present embodiment, the advantageous state (for example, during ART) includes the first advantageous state (for example, normal ART) and the second advantageous state (for example, continuous challenge), and the advantageous state Then, the first right (for example, ART stock) for continuing the first advantageous state, and the lottery to add the number of games in the first advantageous state in the second advantageous state (determination of whether to extend the game period) The second right (for example, CP) for performing the operation can be granted.

  Then, when the first advantageous state ends, if both the first right and the second right are granted, control is performed so as to give priority to shifting to the second advantageous state. Has been. That is, the second right is digested in preference to the first right.

  In this case, in the second advantageous state, when the second right is consumed and the number of games in the first advantageous state is added and a lottery (determination of whether to extend the game period) is performed, and the additional lottery is won ( If it is decided to extend the game period), the first advantageous state can be continued without consuming the first right, and if the winning lottery is not won (the game period can be extended) The first advantageous state can be continued by consuming the first right even if it is not determined. Therefore, while ensuring the sense of security related to the continuation of the advantageous state, it is possible to make a variety of games and improve the interest of the game.

  In addition, when the first advantageous state ends, the first advantageous state is continued by the consumption of the second right or the consumption of the first right even if the state is shifted to the second advantageous state. Since the possibility can remain, the expectation regarding the continuation of the advantageous state can be maintained.

  Further, in the pachislot machine 1 of the present embodiment, it is possible to acquire a plurality of second rights in an advantageous state. When a plurality of second rights are acquired, the second right is acquired. Are all used for the lottery (determination of whether or not to extend the game period) by adding the number of games in the first advantageous state. Therefore, in the second advantageous state, it is possible not only to determine whether or not to continue the advantageous state, but also to create a possibility that a large number of games can be added at one time. Can improve the interest of the game.

("CP special zone in BB")
The production gaming state “CP special zone during BB” is a gaming state in which the BB is activated (winning) in the ART gaming state (BB winning during ART), and is basically the BB gaming state. . In the “BB special zone for CP”, the internal state (for example, “state 1” or “state 2” described later) is determined at the start, and CP is acquired based on the determined internal state and the internal winning combination. When a lottery is performed and a CP acquisition lottery is won, a CP is awarded.

  Then, when the BB gaming state ends, the “CP special zone during BB” ends, and the rendered gaming state shifts to “normal ART” with the assigned CP. When the above-mentioned “ART ready state” is provided, the effect gaming state shifts (returns) to “normal ART” via the “ART ready state”.

("Double Specialized Zone")
The production gaming state “double specialized zone” is a non-ART gaming state (more specifically, excluding the “BB history specializing zone” which is a BB gaming state) or an ART gaming state (more specifically, a BB gaming state). (Excluding “BB special CP zone”), a game that shifts to a case where “F_SP Lip A”, “F_SP Lip B”, and “F_SP Lip C” described later are won (the blue 7 role is established) This is a gaming state in which both CP acquisition lottery and ART stock acquisition lottery are performed. In that sense, it is called a “double-specialized zone”.

  In the “Double Specialized Zone”, the basic number of guaranteed games for which stay is guaranteed is set to “10” games. When this number of guaranteed games is consumed, the end lottery is performed, and when the end lottery is won, If the “Double Specialized Zone” ends and the staged gaming state before the transition is “Promotion Chance”, the transition is made to “Promotion Chance”, and if the staged gaming state before the transition is “Continuous Challenge”, “Continuous Challenge” If the stage game state before the transition is other stage game state, the process shifts to “normal ART”.

  In the “double specialization zone”, an internal state (for example, “state 1” or “state 2” described later) is determined at the start, and an end lottery is performed based on the internal state. However, when Blue 7 Fake notification described later is performed, when the ART stock is acquired, and when an internal winning combination other than the “normal combination” is determined, the end lottery is not performed and the “double specialized zone” Will continue. The “ordinary combination” here refers to “normal combination 1” and “normal combination 2” described later (see FIG. 29).

  In the “double special zone”, when a predetermined replay role (for example, RT3 Lip A described later) is won, a blue 7 fake notification lottery is performed. (That is, the right reel 3R is stopped for the first time), and a blue 7 challenge effect (an effect that suggests that stop display should be displayed) is performed aiming at a specific symbol (in this case, “blue 7” symbol). However, the predetermined replay combination is an internal winning combination in which the “blue 7” symbol is a so-called “tempe” on a specific line but is not lined up on the specific line. Therefore, when the Blue 7 Challenge effect based on the Blue 7 Fake Notification lottery is executed, the ART stock is not acquired or the CP is not acquired, but the benefit that the “double specialized zone” continues. Can get.

  Further, in the “double specialization zone”, when a specific replay role (for example, RT3 Lip C described later) is won, an ART stock is given and a CP acquisition lottery is performed. If you win, CP will also be awarded. At this time, the blue 7 challenge effect described above is performed. The specific replay combination is an internal winning combination in which “Blue 7” symbols are arranged on a specific line. Therefore, when the blue 7 challenge production based on the winning of this specific replay role is executed, the privilege of acquiring the ART stock and the privilege of continuing the “double specialization zone” can be obtained, There is a case where a privilege of acquiring a CP can be obtained.

  Further, in the “double specialization zone”, when another internal winning combination is determined, a CP acquisition lottery is performed, and when this CP acquisition lottery is won, a CP is awarded. Even in this case, the end lottery may not be performed, and the “double specialized zone” may be continued.

("Promotion opportunity")
The directing gaming state “promotion chance” wins the ART lottery in the non-ART gaming state (or it is determined to shift to ART), and when it wins the promotion lottery (part of the ART winning), “normal ART” If you win the promotion lottery at the start of the set (part at the start of the next ART set), or if you win the activation lottery (transition lottery) in the "continuation challenge" (part of the extra during the continuous challenge) A gaming state. In the “promotion chance”, information on a stop operation that is advantageous to the player is reported, as in the ART gaming state. In that sense, “promotion chance” may be one of the ART gaming states.

  In “Promotion Opportunity”, a continuous lottery of this “Promotion Opportunity” is carried out. If this lottery is won, the “Promotion Opportunity” continues, and if it is not won, the “Promotion Chance” When the stage game state before the transition is “continuation challenge”, the process shifts to “continuation challenge”, and when the stage game state before the transition is other stage game state, the process shifts to “normal ART”. In the “promotion chance”, it is possible to determine in advance whether or not to continue a plurality of consecutive games.

  Note that various methods can be employed for the continuous lottery method. For example, the number of games that will continue in advance may be determined at the time of the transition to “promotion chance”, or the “promotion chance” may be determined at least until the next game in the next game in the “promotion chance”. It may be determined whether or not to continue. Alternatively, it is possible to determine whether or not to continue the “promotion chance” by simply performing a game continuation lottery.

  In the “promotion chance”, the number of ART games is added each time the game continues. For example, when the initial value “50” of the number of ART games is given at the start of the “promotion chance”, the number of ART games is added to “111” in the first game, and the “promotion chance” is set to the second time. If the game is continued, the number of ART games is added to “222”, and if the “promotion chance” is continued until the third game, the number of ART games is added to “333”. That is, in the “promotion chance”, the number of ART games obtained by multiplying the number of games played in the “promotion chance” by “111” is sequentially set.

  The technique for adding the number of ART games in the “promotion chance” is not limited to the above. If the game continues simply at the “promotion chance”, a predetermined number of ART games (for example, 50 games) may be added, or added when the game continues at the “promotion chance”. The number of ART games may be determined by lottery, and the determined number of ART games may be added.

  As described above, in the pachislot machine 1 according to the present embodiment, in the non-ART game state and the ART game state, the above-described effect game states are set to enhance the gameability.

  In the ART gaming state, when “F_black BAR” is determined as an internal winning combination, and when the MB medium lock effect is executed, the number of ART games is “100” as in the non-ART gaming state. In addition to being added to the game, “3” is given as the number of ART stocks. However, in the ART gaming state, when “F_Black BAR” is determined as an internal winning combination, and when the MB lock effect is executed, a profit different from the non-ART gaming state may be given. Good.

  In the present embodiment, as a management method in the ART gaming state (more specifically, “normal ART”), management is performed by the number of sets (that is, the predetermined number of ART games is set as one unit). However, it is not limited to this. For example, the management may be performed only by the number of ART games, not by the number of sets. That is, in the scene where the ART stock is given, the same number of ART games may be given.

  In addition, for example, one set may be managed by a difference number (that is, a net increase number obtained by subtracting the inserted number from the payout number), or the number of times of pushing order (for example, batting order bell) is notified (that is, actually The number of times of stop operation information that is advantageous to the player related to the payout of medals may be managed. In these cases, if an increase occurs, the difference number or the number of notifications may be added.

  Here, the ART game state is continued (added or extended) is not limited to the above-mentioned number of ART games or ART stock, or the number of differences or the number of notifications, but the ART game state continuation probability (continuation) Rate) may be increased. For example, when a continuous lottery (end lottery) is performed every time one set is completed, the continuation probability can be increased to substantially increase the continuation probability.

  Also, for example, when the ART gaming state and the BB gaming state, or only the ART gaming state are managed as a series of advantageous sections, and the number of continuous advantageous sections reaches a predetermined number of games (for example, 1500 games) Even if the number of ART games, ART stock, and CP still remain, the ART gaming state may be forcibly ended and the state may be shifted to “normal time”. In other words, a certain limit (limiter) may be provided for continuation of the advantageous section that is advantageous to the player. By configuring in this way, it is possible to prevent the player from being excessively involved in the game.

<Configuration of data table stored in main ROM>
Next, the configuration of various data tables stored in the main ROM 102 will be described with reference to FIGS. The configuration of various data tables related to the ART function will be described later with reference to FIGS.

[Design arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table includes the position of each symbol in the rotation direction of each of the left reel 3L, the middle reel 3C, and the right reel 3R, and data (hereinafter referred to as symbol code) specifying the type of symbol arranged at each position. Define the correspondence.

  In the symbol arrangement table, when the reel index is detected, the position of the symbol located in the middle area of each reel within the frame of the reel display window 4 is defined as “0”. Then, in each reel, the symbol counter value “0” corresponds to the value of the symbol counter in the order of advance in the reel rotation direction (the direction from symbol position “19” in FIG. 15 toward symbol position “0”). “0” to “19” are assigned to the symbols as symbol positions.

  That is, by referring to the symbol counter values (“0” to “19”) and the symbol arrangement table, the symbols are displayed in the upper, middle, and lower regions of each reel within the frame of the reel display window 4. It is possible to specify the type of design. In the present embodiment, the symbols “blue BAR”, “black BAR”, “blue 7”, “white 7”, “bell 1”, “bell 2”, “bell 3”, “bell 4”, Nine kinds of symbols “Lip” are used.

  In the present embodiment, the symbol “blue BAR” (symbol code 1) is assigned “00000001” as data, and the symbol “black BAR” (symbol code 2) is “00000010” as data. Is assigned to symbol “blue 7” (symbol code 3) as data “00000011”, and symbol “white 7” (symbol code 4) is assigned “00000100” as data. .

  Also, symbol “BELL 1” (symbol code 5) is assigned “00000101” as data, symbol “BELL 2” (symbol code 6) is assigned “00000110” as data, and symbol “BELL 3” is assigned. ”(Symbol code 7) is assigned data“ 00000111 ”, the symbol“ bell 4 ”(symbol code 8) is assigned data“ 00001000 ”, and the symbol“ lip ”(symbol code 9) is assigned. Is assigned “00000101” as data.

[Internal lottery table]
Next, an internal lottery table referred to when determining an internal winning combination will be described with reference to FIGS. 16 and 17.

  The internal lottery table is provided for each gaming state, and defines the correspondence between various internal winning combinations and lottery values when each internal winning combination is determined. The lottery value is defined for each set value (set values 1 to 6) for adjusting the expected value of the internal winning such as bonus combination or small combination set in advance. This set value is changed using, for example, the reset switch 76 and the setting key switch 54 (see FIG. 7).

  In the internal lottery process of this embodiment, first, a random number value extracted from a predetermined numerical range (for example, 0 to 65535) by the random number register 0 of the random number circuit 110 is assigned to each internal winning combination. Sequentially add with the specified lottery value. Next, it is determined whether or not the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result has overflowed). When the lottery result exceeds 65535 in a predetermined internal winning combination, it is determined that the internal winning combination is won. In the internal lottery process of the present embodiment, the lottery value is added to the extracted random number value to perform lottery. However, the internal lottery process of the present embodiment is not limited to this, and the lottery value is determined from the random value. May be determined by determining whether the subtraction result (lottery result) is below “0” (whether the lottery result has underflowed) or not.

  Therefore, in the internal lottery process of the present embodiment, the probability of being determined is higher for an internal winning combination having a larger numerical value defined as a lottery value. The winning probability of each internal winning combination can be expressed by “the lottery value specified for each winning number / the number of all random numbers that may be extracted (random number denominator: 65536)”.

  As shown in FIGS. 16 and 17, in this embodiment, as the internal winning combination, “F_normal lip” (winning number “1”), “F_RT1_RT2U lip 1” to “F_RT1_RT2U lip 6” (winning number “2”) To “7”), “F_RT2_RT3U Lip 1” to “F_RT2_RT3U Lip 6” (winning numbers “8” to “13”), “F_RT2 keeping Lip 1” to “F_RT2 keeping Lip 6” (winning numbers “14” to “14”) 19 ”),“ F_RT3 Lip A1 ”to“ F_RT3 Lip A4 ”(winning numbers“ 20 ”to“ 23 ”),“ F_RT3 Lip B1 ”to“ F_RT3 Lip B4 ”(winning numbers“ 24 ”to“ 27 ”), “F_RT3 Lip C1” to “F_RT3 Lip C4” (winning numbers “28” to “31”), “F_SP Lip A” (winning number “32”), “F_SP Lip B” (winning number) 33 ”),“ F_SP Lip C ”(winning number“ 34 ”),“ F_SP Faiclip A ”(winning number“ 35 ”),“ F_SP Faiclip B ”(winning number“ 36 ”),“ F_Chance Lip A ”( “F_chance lip B” (winning number “38”) is defined.

  Note that “F_RT1_RT2U Lip 1” to “F_RT1_RT2U Lip 6” are mainly internal winning combinations determined in the RT1 state, and therefore, in the present embodiment, they may be simply described as “RT1 Lip” (RT1 middle Lip). is there.

  Further, since “F_RT2_RT3U Lip 1” to “F_RT2_RT3U Lip 6” and “F_RT2 Maintenance Lip 1” to “F_RT2 Maintenance Lip 6” are mainly internal winning combinations determined in the RT2 state, It may be described simply as “RT2 Lip” (RT2 Lip).

  “F_RT3 Lip A1” to “F_RT3 Lip A4”, “F_RT3 Lip B1” to “F_RT3 Lip B4”, and “F_RT3 Lip C1” to “F_RT3 Lip C4” are mainly internal winnings determined in the RT3 state. In the present embodiment, there are cases where it is simply described as “RT3 Lip” (RT3 Lip). In addition, “F_RT3 Lip A1” to “F_RT3 Lip A4” may be simply described as “RT3 Lip A” (Lip A in RT3), and “F_RT3 Lip B1” to “F_RT3 Lip B4” are simply “RT3”. Lip B ”(Rip B during RT3) may be described, and“ F_RT3 Lip C1 ”to“ F_RT3 Lip C4 ”may be simply described as“ RT3 Lip C ”(Rip C during RT3).

  In the present embodiment, “F_batting order bell 1A” to “F_batting order bell 6A” and “F_batting order bell 1B” to “F_batting order bell 6B” (winning numbers “39” to “50”) are used as internal winning combinations. , “F_1 single combination” (winning number “51”), “F_weak chance combination” (winning number “52”), “F_medium chance combination” (winning number “53”), “F_strong bell” (winning number) “54”), “F_common bell” (winning number “55”), “F_black BAR” (winning number “56”), “F_special role A” (winning number “57”), “F_special role B (Winning number “58”), “F_special role C” (winning number “59”), “F_BB chance chance role A” (winning number “60”), “F_BB chance chance role B” (winning number “61” ”),“ F_BB chance chance role C ”(winning number“ 62 ”),“ F_MB ” Number “63”), “F_BB + F_chance lip B” (winning number “64”), “F_BB + F_special role A” (winning number “65”), “F_BB + F_special role B” (winning number “66”), and “ “F_BB + F_Special role C” (winning number “67”) is defined.

  In the present embodiment, the lottery values shown in FIGS. 16 and 17 are defined for these internal winning combinations in each gaming state or in common with each gaming state, and the above-described arithmetic processing using this lottery value As a result, the internal winning combination is determined.

  As described above, in the MB gaming state, for the replay role, the winning probability of the current RT state (that is, the lottery values shown in FIGS. 16 and 17) is inherited and the lottery is performed. The lottery for the bonus combination is not performed, and all the small combinations can be determined as internal winning combinations (see FIG. 64 described later). In the internal lottery table in the MB gaming state (in MB) shown in FIG. 17, “-” is written in the columns of the winning numbers “39” to “67” in that sense. However, “0” is defined as the lottery value corresponding to these winning numbers, and although it is not actually won, it may be a lottery process common to each gaming state.

  Further, the method of determining the internal winning combination in the MB gaming state is not limited to this. For example, in the MB gaming state, the internal lottery table corresponding to the current RT state is referred to (that is, the internal lottery table in the MB gaming state (in the MB) is not prescribed), and all the winning numbers described above are prescribed. It may be possible to determine whether or not the winning combination is based on the lottery value, and thereafter, all the small combinations may be further determined as internal winning combinations. At this time, for example, when “F_BB + F_special role A” (winning number “65”) is won, only “F_special role A” is determined as an internal winning combination (that is, “F_BB” is determined). The winning request flag storage area (see FIG. 22 described later) and the carryover combination storage area (see FIG. 23 described later) may not be stored. Thereby, the data capacity concerning an internal lottery table can be reduced.

  Also, in the MB gaming state, the internal winning combination in the MB gaming state can be determined by combining the internal winning combination that can be determined in the MB gaming state (that is, only all the small combinations or all the small combinations and each replay combination). The internal lottery table for the MB gaming state (in MB) may be provided by defining a lottery value corresponding to the RT state for each internal winning combination in the MB gaming state. In this case, for example, if the current RT state is the RT0 state, as the internal lottery table in the MB gaming state, an internal winning combination (that is, only all small combinations) whose “corresponding symbol combinations” will be NML01 to NML23 described later. "56558" is specified for the lottery value of "determined", and the internal symbol combination (that is, all small combinations + "F_normal lip" are determined) in which the "corresponding symbol combination" becomes NML01 to NML23 and REP02 described later The lottery value is defined as “8332”, and the “corresponding symbol combination” is the lottery value of the internal winning combination (that is, all small combinations + “F_chance lip A” is determined) to be NML01 to NML23 and REP01 described later. “504” is defined, and the “corresponding symbol combination” is an internal winning combination (that is, all small combinations) that will be NML01 to NML23 and REP20 described later. It is sufficient to provide an internal lottery table "142" is defined in the lottery value of a decision) the "F_ chance descriptor B".

  That is, when an internal lottery table in the MB gaming state (in MB) is provided, an internal combination of all the small combinations and the replay combinations (winning numbers “1” to “38”) shown in FIGS. A winning combination is defined, and for the internal winning combination, a lottery value that is the same as the lottery value defined for each replay combination is defined for each RT state, and the lottery value defined for each RT state from “65536”. What is necessary is just to prescribe | regulate the value which reduced the total value as a lottery value of the internal winning combination from which all the small combinations are determined. This eliminates the need to perform control (S319 and S320, which will be described later) unique to the MB gaming state in the internal lottery process (see 64, which will be described later), thereby reducing the control burden in the internal lottery process, and the MB gaming state. Since the processing procedure of the internal lottery process can be made common regardless of whether or not is provided, the number of man-hours for design can be reduced. In this case, the winning number of the internal winning combination in the MB gaming state is a winning number (for example, winning numbers “68” to “105” following the winning numbers “1” to “67” defined in other gaming states). ) Or the same winning number as the other gaming state (for example, winning numbers “1” to “38”) can be specified. In the latter case, it is only necessary to separately define data that can identify that the “corresponding symbol combination” changes depending on the winning number between the MB gaming state and the other gaming states.

  In the present embodiment, when an internal winning combination is determined, it is permitted (allowed) to display a combination of one or more symbols on the active line. The combinations of symbols permitted to be displayed on the effective line are as shown in “corresponding symbol combinations” shown in FIGS. 16 and 17.

  For example, “F_normal lip” is an internal winning combination that allows a combination of symbols of “REP02” (name: C_TL lip) described later to be displayed on the active line (see FIG. 18 described later). When the state is the RT0 state, it is determined as an internal winning combination with a probability of “8332/65536”, and when the gaming state is the RT4 state, it is determined as an internal winning combination with a probability of “18041/65536” and other games. In the state, it is not determined as an internal winning combination (that is, “0” is specified for the lottery value). However, as described above, in the MB gaming state, the lottery value in the RT state is taken over and the replay role lottery is performed. Therefore, when the MB gaming state is in the RT0 state, “8332/65536 Is determined as an internal winning combination with the probability of "", and is not determined as an internal winning combination when in the MB gaming state and in the RT1 to RT3 states (that is, "0" is defined for the lottery value). Since the RT4 state is between the BB flags (inside the BB), there is no case of shifting to the MB gaming state.

  Further, for example, “F_batting order bell 1A” includes “NML01” (name: S_L1st miss A), “MNL04” (name: S_L1st miss D), “NML05” (name: S_C1st miss A), “NML08”, which will be described later. (Name: S_C1st Miss D), “NML09” (Name: S_R1st Miss A), “NML12” (Name: S_R1st Miss D), and “NML15” (Name: S_BL Bell) are displayed on the active line. Is determined to be an internal winning combination with a probability of “962/65536” when the gaming state is RT0 to RT4 state (that is, non-bonus state). In other game states (that is, bonus states), it is not determined as an internal winning combination (that is, the lottery value is set to “0”). Have been).

  In addition, although mentioned later in detail, in this embodiment, when "F_ batting order bell 6A" and "F_ batting order bell 1B"-"F_ batting order bell 6B" are determined as an internal winning combination. If so-called “missing” occurs, a combination of symbols of “S_RT1 transition A”, “S_RT1 transition B”, and “S_RT1 transition B”, which will be described later, is displayed on the active line. Yes. In this sense, “F_batting order bell 6A” to “F_batting order bell 1A” and “F_batting order bell 6B” are “S_RT1 transition A”, “S_RT1 transition B”, and “S_RT1 transition B”. It can also be said that an internal winning combination in which a combination of symbols “” is permitted to be displayed on the active line.

  Although not shown in the figure, the lottery value of at least a part of the replay combination and / or the small combination is changed by changing the set value. Of course, the bonus combination may also be able to change the lottery value. Specifically, when a predetermined probability variation start condition is satisfied, the lottery value of the bonus combination is high (that is, the bonus combination is lottery with a high probability) until the predetermined probability variation end condition is satisfied. An internal lottery process may be performed by a table. In this case, the predetermined probability variation start condition and the predetermined probability variation end condition can be appropriately set as arbitrary conditions during the game.

[Design combination table]
Next, with reference to FIG. 18, a symbol combination table that defines combinations of symbols related to winning and operation in the present embodiment will be described.

  As shown in FIG. 18, the symbol combination table defines a plurality of symbol combinations related to winning and operating, and data indicating the types of symbol combinations is defined as a display combination (winning operation flag). Yes. The symbol combination table is composed of 7-byte data so as to correspond to a winning request flag storage area, a winning action flag storage area (see FIG. 22 described later), and a symbol code storage area (see FIG. 27 described later). In addition, data indicating a different display combination (winning operation flag) is defined for each bit of each storage area.

  The display combination (winning action flag) “C_BB” and “C_MB” are combinations of symbols related to the bonus combination, and “C_CL Lip”, “S_TL Lip”, “S_BL Lip”, “S_RT1 Lip A”, “S_RT1 Lip B”, “C_RT2 Lip”, “S_RT3 Lip”, “C_SP_CL Lip”, “S_SP_XU Lip”, “S_SP_XD Lip”, “S_SP_TL Lip”, “C_TT_BL Lip”, “S_TT_XD Lip”, “S_TT Lip” ”To“ S_Fake lip F ”and“ C_ Chance Lip ”are combinations of symbols related to the replay role.

  In addition, display combinations (winning operation flags) “S_L1st miss A” to “S_L1st miss D”, “S_C1st miss A” to “S_C1st miss D”, “S_R1st miss A” to “S_R1st miss D”, “C_special role” , “S_CL bell”, “S_BL bell”, “1 for C_CB”, “2 for C_CB”, “C_black BAR”, “S_weak chance”, “S_medium chance”, and “S_chance 1” to “S_ “Chance 3” is a combination of symbols related to the small role, and “S_RT1 transition A”, “S_RT1 transition B”, and “S_RT1 transition B” are out-of-order symbol combinations, but the RT state is shifted to the RT1 state. It is a combination of symbols.

  For example, when the combination of symbols “blue BAR-blue BAR-blue BAR” is displayed on the active line, the display combination (winning operation flag) is “C_BB” in a winning search process (winning determination process) described later. After that, a process for shifting the gaming state to the BB gaming state is performed.

  Also, for example, “black BAR-bell 1-blue BAR”, “black BAR-bell 1-white 7”, “black BAR-bell 2-blue BAR”, “black BAR-bell 2-white 7”, “black” BAR-Bell 3-Blue BAR "," Black BAR-Bell 3-White 7 "," Black BAR-Bell 4-Blue BAR ", and" Black BAR-Bell 4-White 7 " When displayed on the active line, it is determined that the winning combination (winning operation flag) is “S_TL Rip” (REP02) in a winning search process (winning determination process), which will be described later. Will be performed.

  In FIG. 18, for example, in “S_TL Rip” (REP02), the symbol of the middle reel 3C is described as “bells 1 to 4”, as described above, the symbol of the middle reel 3C is “ This means that any of “Bell 1”, “Bell 2”, “Bell 3”, and “Bell 4” may be used, and the symbol of the right reel 3R is displayed as “blue BAR / white 7”. As described above, it means that the symbol of the right reel 3R may be either “blue BAR” or “white 7”.

  Further, for example, when a combination of symbols “black BAR−black BAR−black BAR” is displayed on the active line, the winning combination (winning operation flag) is set to “C_black” in a winning search process (winning determination process) described later. BAR "is determined, and thereafter, a process for paying out 7 medals is performed. That is, when a numerical value is defined as the payout (payout number), the numerical value means the payout number of medals when winning a prize. Note that the symbol combination table shown in FIG. 18 defines the payout number when the number of inserted medals is three.

[Correspondence table between internal winning combination, stop operation order (batting order) and display combination]
Next, the correspondence between the internal winning combination, the stop operation order (batting order), the display combination and the like will be described with reference to FIGS. 19 and 20 are diagrams showing a correspondence table of the internal winning combination, stop operation order (batting order), display combination, etc. in the gaming state excluding the MB gaming state, and FIG. It is a figure which shows the correspondence table | surface with an internal winning combination, stop operation order (batting order), a display combination, etc. FIG.

  In the pachi-slot 1 of the present embodiment, a so-called “push order” is provided in which the symbol combinations displayed differ according to the stop operation order (push order) of the player. Since stop buttons 17L, 17C, and 17R corresponding to the reels 3L, 3C, and 3R are provided, there are a maximum of six stop operation orders (pushing orders).

  In FIG. 19 to FIG. 21, the stop operation order (push order) is “left, middle, right” is shown as “batting order 1”, and the stop operation order (push order) is “left, right, middle”. ”Is shown as“ batting order 2 ”, the stop operation order (push order) is“ middle, left, right ”, as“ batting order 3 ”, and the stop operation order (push order) is The “middle, right, left” order is indicated as “batting order 4”, the stop operation order (push order) is indicated as “right, left, middle” as “batting order 5”, and the stop operation It is indicated as “batting order 6” that the order (pushing order) is “right, middle, left”.

  As shown in FIG. 19 and FIG. 20, in the gaming state (more specifically, the RT0 state and the RT4 state) excluding the MB gaming state, “F_normal lip” is determined not as a push order but as an internal winning combination. In this case, “S_TL Lip” (upper stage Lip) is established regardless of the stop operation order and the stop operation timing.

  In the left reel 3L, the symbol “black BAR” constituting the symbol combination “S_TL Lip” is arranged within 5 frames (within the range of 5 symbols), and in the middle reel 3C, “S_TL Lip” The symbols “Bell 1” to “Bell 4” that make up the symbol combination are arranged within 5 frames (within the range of 5 symbols), and on the right reel 3R, the symbol combination “S_TL Lip” The symbols “Blue BAR” and “White 7” are arranged within 5 frames (within the range of 5 symbols). In other words, “regardless of the timing of the stop operation” means that in principle (ie, when the effective line is one line of “center line” and the maximum number of sliding pieces is “4”), within 5 symbols (design) This means that the symbols are arranged within a range of five). Hereinafter, the same applies to other display combinations (winning operation flag) and the like.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT1 state), “F_RT1_RT2U Lip 1” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order 1 "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than “batting order 1”, the other replay winning combination is established regardless of the timing of the stop operation, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintain).

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT1 state), “F_RT1_RT2U Lip 2” is a pushing order and when the internal winning combination is determined, the stop operation order is “batting order 2”. "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than “batting order 2”, the winning replay combination is established regardless of the timing of the stop operation, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintain).

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT1 state), “F_RT1_RT2U Lip 3” is a pushing order, and when it is determined as an internal winning combination, the stop operation order is “batting order 3”. "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than “batting order 3”, the other replay winning combination is established regardless of the timing of the stop operation, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintain).

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT1 state), “F_RT1_RT2U Lip 4” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order 4”. "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than “batting order 4”, the winning replay combination is established regardless of the timing of the stop operation, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintain).

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT1 state), “F_RT1_RT2U Lip 5” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order 5”. "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than “batting order 5”, other winning replay combinations are established regardless of the stop operation timing, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintain).

  Further, in the gaming state (more specifically, the RT1 state) excluding the MB gaming state, “F_RT1_RT2U Lip 6” is a pushing order combination, and when the internal winning combination is determined, the stop operation order is “batting order 6”. "," C_RT2 lip "is established regardless of the timing of the stop operation, and the RT state shifts to the RT2 state (RT2). On the other hand, if the stop operation order is other than “batting order 6”, the other replay winning combination is established regardless of the timing of the stop operation, the RT state does not shift to the RT2 state, and the RT1 state is maintained. (Maintain).

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT2_RT3U Lip 1” is a pushing order and when the internal winning combination is determined, the stop operation order is “batting order 1 ", Regardless of the timing of the stop operation," S_RT3 Lip "is established, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than “batting order 1”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT2 state), “F_RT2_RT3U Lip 2” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order 2”. ", Regardless of the timing of the stop operation," S_RT3 Lip "is established, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than “batting order 2”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT2 state), “F_RT2_RT3U Lip 3” is a pushing order combination, and when the internal winning combination is determined, the stop operation order is “batting order 3 ", Regardless of the timing of the stop operation," S_RT3 Lip "is established, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than “batting order 3”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state (more specifically, the RT2 state) excluding the MB gaming state, “F_RT2_RT3U Lip 4” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order 4”. ", Regardless of the timing of the stop operation," S_RT3 Lip "is established, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than “batting order 4”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT2_RT3U Lip 5” is a pushing order and when the internal winning combination is determined, the stop operation order is “batting order 5”. ", Regardless of the timing of the stop operation," S_RT3 Lip "is established, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than “batting order 5”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT2_RT3U Lip 6” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order 6”. ", Regardless of the timing of the stop operation," S_RT3 Lip "is established, and the RT state shifts to the RT3 state (RT3). On the other hand, if the stop operation order is other than “batting order 6”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT2_maintenance lip 1” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order”. If “1”, regardless of the timing of the stop operation, “S_TL Lip” is established, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than “batting order 1”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT2_maintenance lip 2” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order”. If “2”, regardless of the timing of the stop operation, “S_TL Lip” is established, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than “batting order 2”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT2_maintenance lip 3” is a pushing order, and when it is determined as an internal winning combination, the stop operation order is “batting order” If “3”, regardless of the timing of the stop operation, “S_TL Lip” is established, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than “batting order 3”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT2 state), “F_RT2_maintenance lip 4” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order”. If “4”, regardless of the timing of the stop operation, “S_TL Lip” is established, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than “batting order 4”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT2_maintenance lip 5” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order”. If “5”, regardless of the timing of the stop operation, “S_TL Lip” is established, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than “batting order 5”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT2 state), “F_RT2_maintenance lip 6” is a pushing order, and when it is determined as an internal winning combination, the stop operation order is “batting order” If “6”, regardless of the timing of the stop operation, “S_TL Lip” is established, the RT state does not shift to the RT1 state, and the RT2 state is maintained (maintained). On the other hand, if the stop operation order is other than “batting order 6”, the winning “S_RT1 Lip A” or “S_RT1 Lip B” is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state. (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_RT3_Lip A1” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order 1 ", Regardless of the timing of the stop operation," S_TL Rip "is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). Further, if the stop operation order is “batting order 3” and “batting order 4” (that is, the middle reel 3C is first stopped), the winning “S_Fail Clip A” to “S_” One of “Fail Clip C” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (fake)). On the other hand, if the stop operation order is other than “batting order 1”, “batting order 3”, and “batting order 4”, the winning “S_RT1 lip A” or “S_RT1 lip B” is irrespective of the timing of the stop operation. As a result, the RT state shifts to the RT1 state (RT1).

  In addition, in the gaming state (more specifically, the RT3 state) excluding the MB gaming state, “F_RT3_Lip A2” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 2 ", Regardless of the timing of the stop operation," S_TL Rip "is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). Further, if the stop operation order is “batting order 5” and “batting order 6” (that is, the right reel 3R is first stopped), the winning “S_Fail Clip A” to “S_” One of “Fail Clip C” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (fake)). On the other hand, if the stop operation order is other than “batting order 2”, “batting order 5”, and “batting order 6”, the winning “S_RT1 lip A” or “S_RT1 lip B” is irrespective of the timing of the stop operation. As a result, the RT state shifts to the RT1 state (RT1).

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT3 state), “F_RT3_Lip A3” is a pushing order combination, and when the internal winning combination is determined, the stop operation order is “batting order 1 ", Regardless of the timing of the stop operation," S_TL Rip "is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). Further, if the stop operation order is “batting order 5” and “batting order 6” (that is, the right reel 3R is first stopped), the winning “S_Fail Clip A” to “S_” One of “Fail Clip C” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (fake)). On the other hand, if the stop operation order is other than “batting order 1”, “batting order 5”, and “batting order 6”, the winning “S_RT1 lip A” or “S_RT1 lip B” is irrespective of the timing of the stop operation. As a result, the RT state shifts to the RT1 state (RT1).

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_RT3_Lip A4” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 2 ", Regardless of the timing of the stop operation," S_TL Rip "is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). Further, if the stop operation order is “batting order 3” and “batting order 4” (that is, the middle reel 3C is first stopped), the winning “S_Fail Clip A” to “S_” One of “Fail Clip C” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (fake)). On the other hand, if the stop operation order is other than “batting order 2”, “batting order 3”, and “batting order 4”, the winning “S_RT1 lip A” or “S_RT1 lip B” is irrespective of the timing of the stop operation. As a result, the RT state shifts to the RT1 state (RT1).

  Note that “maintenance (fake)” means that a specific symbol (in this case, “blue BAR” symbol) forms a so-called “tempe” on a specific line different from the active line, but on the specific line. It means not line up. However, this specific line may be the same line as the effective line.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_RT3_Lip B1” is a pushing order combination, and when the internal winning combination is determined, the stop operation order is “batting order 1 ", Regardless of the timing of the stop operation," S_TL Rip "is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). Further, if the stop operation order is “batting order 3” and “batting order 4” (that is, the middle reel 3C is first stopped), the winning “C_TT_BL RIP” or “S_TT_XD” is performed regardless of the timing of the stopping operation. “Rip” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (BAR)). On the other hand, if the stop operation order is other than “batting order 1”, “batting order 3”, and “batting order 4”, the winning “S_RT1 lip A” or “S_RT1 lip B” is irrespective of the timing of the stop operation. As a result, the RT state shifts to the RT1 state (RT1).

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_RT3_Lip B2” is a pushing order, and when it is determined as an internal winning combination, the stop operation order is “batting order 2”. ", Regardless of the timing of the stop operation," S_TL Rip "is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). Further, if the stop operation order is “batting order 5” and “batting order 6” (that is, the right reel 3C is first stopped), the winning “C_TT_BL Lip” or “S_TT_XD” regardless of the timing of the stopping operation. “Rip” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (BAR)). On the other hand, if the stop operation order is other than “batting order 2”, “batting order 5”, and “batting order 6”, the winning “S_RT1 lip A” or “S_RT1 lip B” is irrespective of the timing of the stop operation. As a result, the RT state shifts to the RT1 state (RT1).

  In addition, in the gaming state (more specifically, the RT3 state) excluding the MB gaming state, “F_RT3_Lip B3” is a pushing order, and when it is determined as an internal winning combination, the stop operation order is “batting order 1 ", Regardless of the timing of the stop operation," S_TL Rip "is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). Further, if the stop operation order is “batting order 5” and “batting order 6” (that is, the right reel 3C is stopped first), the winning “C_TT_BL Lip” or “S_TT_XD” regardless of the timing of the stopping operation. “Rip” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (BAR)). On the other hand, if the stop operation order is other than “batting order 1”, “batting order 5”, and “batting order 6”, the winning “S_RT1 lip A” or “S_RT1 lip B” is irrespective of the timing of the stop operation. As a result, the RT state shifts to the RT1 state (RT1).

  Further, in the gaming state excluding the MB gaming state (more specifically, in the RT3 state), “F_RT3_Lip B4” is a pushing order combination, and when the internal winning combination is determined, the stop operation order is “batting order 2 ", Regardless of the timing of the stop operation," S_TL Rip "is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). Further, if the stop operation order is “batting order 3” and “batting order 4” (that is, the middle reel 3C is first stopped), the winning “C_TT_BL RIP” or “S_TT_XD” is performed regardless of the timing of the stopping operation. “Rip” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintenance (BAR)). On the other hand, if the stop operation order is other than “batting order 2”, “batting order 3”, and “batting order 4”, the winning “S_RT1 lip A” or “S_RT1 lip B” is irrespective of the timing of the stop operation. As a result, the RT state shifts to the RT1 state (RT1).

  “Maintenance (BAR)” means that a specific symbol (in this case, “blue BAR” symbol) is arranged on a specific line different from the active line. However, this specific line may be the same line as the effective line.

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT3 state), “F_RT3_Lip C1” and “F_RT3_Lip C4” are push forwards and stop when determined as an internal winning combination. If the operation order is “batting order 1” and “batting order 2” (that is, the left reel 3L is first stopped), “S_TL Rip” is established regardless of the timing of the stop operation, and the RT3 state is maintained ( Maintenance). Further, if the stop operation order is “batting order 3” and “batting order 4” (that is, the middle reel 3C is first stopped), the winning “S_Fail Clip A” to “S_” One of “Fail Clip C” is established, and the RT3 state is maintained (maintained (fake)). Further, if the stop operation order is “batting order 5” and “batting order 6” (that is, the right reel 3R is first stopped), the winning “C_SP_CL Lip” and “S_SP_XU Lip” are set regardless of the timing of the stop operation. ”Or“ S_SP_TL Lip ”is established, and the RT3 state is maintained (maintained (blue 7)).

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT3 state), “F_RT3_Lip C2” and “F_RT3_Lip C3” are push forwards and stop when determined as an internal winning combination. If the operation order is “batting order 1” and “batting order 2” (that is, the left reel 3L is first stopped), “S_TL Rip” is established regardless of the timing of the stop operation, and the RT3 state is maintained ( Maintenance). Further, if the stop operation order is “batting order 5” and “batting order 6” (that is, the right reel 3R is first stopped), the winning “S_Fail Clip A” to “S_” One of “Fail Clip C” is established, and the RT3 state is maintained (maintained (fake)). Further, if the stop operation order is “batting order 3” and “batting order 4” (that is, the middle reel 3C is first stopped), the winning “C_SP_CL Lip” and “S_SP_XU Lip” are set regardless of the timing of the stop operation. ”Or“ S_SP_TL Lip ”is established, and the RT3 state is maintained (maintained (blue 7)).

  Note that “maintain (blue 7)” means that a specific symbol (in this case, “blue 7” symbol) is arranged on an effective line or on a specific line different from the effective line.

  In addition, in the gaming state excluding the MB gaming state (more specifically, from the RT1 state to the RT3 state), “F_SP Lip A” is determined not as a pushing order but as an internal winning combination, Regardless of the timing of the stop operation, “C_SP_CL Lip” (blue 7 middle stage) is established. In this case, if the RT state is the RT1 state or the RT2 state, the state shifts to the RT3 state (RT3).

  In addition, in the gaming state excluding the MB gaming state (more specifically, from the RT1 state to the RT3 state), “F_SP Lip B” is determined not as a pushing order but as an internal winning combination, Regardless of the timing of the stop operation, “S_SP_XU Lip” (blue 7 upper right) is established. In this case, if the RT state is the RT1 state or the RT2 state, the state shifts to the RT3 state (RT3).

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT1 state to the RT3 state), “F_SP Lip C” is determined not to be a pushing order but an internal winning combination, Regardless of the timing of the stop operation, “S_SP_XD Lip” (blue 7 lower right) is established. In this case, if the RT state is the RT1 state or the RT2 state, the state shifts to the RT3 state (RT3).

  In addition, in the gaming state excluding the MB gaming state (more specifically, from the RT1 state to the RT3 state), when “F_SP faeclip A” is determined not as a pushing order but as an internal winning combination, Regardless of the timing of the stop operation, “S_fake rip E” or “S_fake rip F” (blue 7 upper right fake) is established.

  In addition, in the gaming state excluding the MB gaming state (more specifically, from the RT1 state to the RT3 state), when “F_SP faeclip B” is determined not as a pressing order but as an internal winning combination, Regardless of the timing of the stop operation, “S_fake lip B” or “S_fake lip D” (blue 7 lower right fake) is established.

  In addition, in the game states excluding the MB game state (more specifically, from the RT0 state to the RT3 state), “F_chance lip A” is determined not to be a pushing order but to be an internal winning combination. Regardless of the timing of the stop operation, “C_CL lip” (middle lip) is established.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT0 state to the RT3 state), “F_batting order bell_1A” and “F_batting order bell_1B” are pushing orders and are determined as internal winning combinations. If the stop operation order is “batting order 1”, “S_BL bell” (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than “batting order 1”, if the timing of the stop operation is appropriate, one winning combination (any one of NML01 to NML12, see FIG. 18) is established, One medal is paid out, but if the timing of the stop operation is not an appropriate timing, one of “S_RT1 transition A”, “S_RT1 transition B”, and “S_RT1 transition B” is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Note that whether or not the timing of the stop operation is an appropriate timing is set such that one half of all the timings of the stop operation is an appropriate timing, and the other half is an inappropriate timing. Has been.

  In addition, in the gaming state excluding the MB gaming state (more specifically, from the RT0 state to the RT3 state), “F_batting order bell_2A” and “F_batting order bell_2B” are pushing orders and are determined as internal winning combinations. If the stop operation order is “batting order 2”, “S_BL bell” (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than “batting order 2”, if the timing of the stop operation is appropriate, one winning combination (NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not an appropriate timing, one of “S_RT1 transition A”, “S_RT1 transition B”, and “S_RT1 transition B” is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Note that whether or not the timing of the stop operation is an appropriate timing is set such that one half of all the timings of the stop operation is an appropriate timing, and the other half is an inappropriate timing. Has been.

  In addition, in the game states excluding the MB game state (more specifically, from the RT0 state to the RT3 state), “F_batting order bell_3A” and “F_batting order bell_3B” are pushing orders and are determined as internal winning combinations. If the stop operation order is “batting order 3”, “S_BL bell” (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than “batting order 3”, if the timing of the stop operation is appropriate, one winning combination (any one of NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not an appropriate timing, one of “S_RT1 transition A”, “S_RT1 transition B”, and “S_RT1 transition B” is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Note that whether or not the timing of the stop operation is an appropriate timing is set such that one half of all the timings of the stop operation is an appropriate timing, and the other half is an inappropriate timing. Has been.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT0 state to the RT3 state), “F_batting order bell_4A” and “F_batting order bell_4B” are pushing orders and are determined as internal winning combinations. If the stop operation order is “batting order 4”, “S_BL bell” (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than “batting order 4”, if the timing of the stop operation is appropriate, one winning combination (NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not an appropriate timing, one of “S_RT1 transition A”, “S_RT1 transition B”, and “S_RT1 transition B” is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Note that whether or not the timing of the stop operation is an appropriate timing is set such that one half of all the timings of the stop operation is an appropriate timing, and the other half is an inappropriate timing. Has been.

  In addition, in the gaming state excluding the MB gaming state (more specifically, from the RT0 state to the RT3 state), “F_batting order bell_5A” and “F_batting order bell_5B” are pushing orders and are determined as internal winning combinations. If the stop operation order is “batting order 5”, “S_BL bell” (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than “batting order 5”, if the timing of the stop operation is appropriate, one winning combination (NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not an appropriate timing, one of “S_RT1 transition A”, “S_RT1 transition B”, and “S_RT1 transition B” is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Note that whether or not the timing of the stop operation is an appropriate timing is set such that one half of all the timings of the stop operation is an appropriate timing, and the other half is an inappropriate timing. Has been.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT0 state to the RT3 state), “F_batting order bell_6A” and “F_batting order bell_6B” are pushing orders and are determined as internal winning combinations. If the stop operation order is “batting order 6”, “S_BL bell” (lower bell) is established regardless of the timing of the stop operation, and nine medals are paid out. On the other hand, if the stop operation order is other than “batting order 6”, if the timing of the stop operation is appropriate, one winning combination (any one of NML01 to NML12, see FIG. 18) is established. One medal is paid out, but if the timing of the stop operation is not an appropriate timing, one of “S_RT1 transition A”, “S_RT1 transition B”, and “S_RT1 transition B” is established. In this case, if the RT state is the RT0 state, the RT2 state, or the RT3 state, the state shifts to the RT1 state. Note that whether or not the timing of the stop operation is an appropriate timing is set such that one half of all the timings of the stop operation is an appropriate timing, and the other half is an inappropriate timing. Has been.

  Note that in the RT4 state, “F_batting order bell_1A” to “F_batting order bell_6B” are not pushing orders and are determined as internal winning combinations, regardless of the stop operation order and the timing of the stop operation. The “S_BL bell” (lower bell) is established, and nine medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, from the RT0 state to the RT4 state), the “F_1 single combination” is not a pushing order but an internal winning combination. Regardless of the timing of the stop operation, a single combination (NML01 to NML12, see FIG. 18) is established, and one medal is paid out.

  In addition, in the game states excluding the MB game state (more specifically, from the RT0 state to the RT4 state), the “F_weak chance combination” is not a pushing order but is determined as an internal winning combination, Regardless of the timing of the stop operation, “S_weak chance” is established, and three medals are paid out.

  In addition, in the game states excluding the MB game state (more specifically, from the RT0 state to the RT4 state), the “F_medium chance combination” is not the push order combination but the internal winning combination is determined as the stop operation sequence. Regardless of the timing of the stop operation, “S_medium chance” (upper right) is established, and three medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT0 state to the RT3 state), “F_strong bell” is determined not to be a pushing order but an internal winning combination, Regardless of the timing of the stop operation, “S_CL bell” (middle stage) is established, and nine medals are paid out. In the RT4 state, regardless of the stop operation order and the stop operation timing, “S_BL bell” (lower row) is established, and nine medals are paid out.

  In addition, in the gaming state except the MB gaming state, when “F_Common Bell” is determined as the internal winning combination instead of the pushing order, the “S_BL Bell” is used regardless of the stop operation order and the stop operation timing. (Lower row) is established, and nine medals are paid out.

  In addition, in the game state excluding the MB game state (more specifically, from the RT0 state to the RT3 state and the BB game state), “F_black BAR” is determined not as a push forward but as an internal winning combination. Regardless of the stop operation sequence and the stop operation timing, “C_black BAR” is established, and seven medals are paid out. In the RT4 state, regardless of the stop operation order and the stop operation timing, a single winning combination (NML01 to NML12, see FIG. 18) is established, and one medal is paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT4 state and the BB gaming state), the “F_special role A” is stopped when it is determined as an internal winning combination instead of a pushing order. Regardless of the operation order and the timing of the stop operation, “1 for C_CB” is established, and 14 medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), when “F_special role B” is determined as the internal winning combination instead of the pressing order, the stop operation sequence and the stop Regardless of the operation timing, “2 for C_CB” is established, and 13 medals are paid out.

  In addition, in the game state excluding the MB game state (more specifically, the RT4 state), when “F_special role C” is determined as an internal winning combination instead of a pushing order, Regardless of the operation timing, “C_special role” is established and one medal is paid out.

  In addition, in the game states excluding the MB game state (more specifically, the BB game state), the “F_BB chance chance A” is determined not as a pushing order but as an internal winning combination, Regardless of the timing of the stop operation, “S_chance 1” (chance 1 during BB) is established, and nine medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the BB gaming state), the “F_BB chance chance B” is not a pushing order but is determined as an internal winning combination, Regardless of the timing of the stop operation, “S_chance 2” (chance 2 during BB) is established, and nine medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the BB gaming state), the “F_BB medium chance combination C” is determined not to be a pushing order but an internal winning combination, Regardless of the timing of the stop operation, “S_chance 3” (chance 3 during BB) is established, and nine medals are paid out.

  In addition, in the game state excluding the MB game state (more specifically, from the RT0 state to the RT3 state), when “F_MB” is determined not as a pushing order but as an internal winning combination, Regardless of the operation timing, “C_MB” (MB) is established and the MB gaming state is activated.

  Further, in the gaming state excluding the MB gaming state (more specifically, from the RT0 state to the RT3 state), when “BB + F_chance lip B” is determined as an internal winning combination instead of pushing forward, “F_BB” Is carried over as a carryover combination, the RT state shifts to the RT4 state, and “C_chance lip” (special lip) is established regardless of the stop operation order and the stop operation timing.

  In this embodiment, when the replay combination and the bonus combination are determined as the internal winning combination (including the case where the bonus combination is carried over), the replay combination is established with priority over the bonus combination. Stop control is performed. Of course, stop control that preferentially establishes a bonus combination over a replay combination may be performed.

  Further, in the gaming state excluding the MB gaming state (more specifically, from the RT0 state to the RT3 state), “BB + F_special role A” is “F_BB” when it is determined as an internal winning combination instead of a pushing order. Is carried over as a carryover combination, the RT state shifts to the RT4 state, and “1 for C_CB” is established regardless of the stop operation order and the stop operation timing, and 14 medals are paid out.

  Further, in the gaming state excluding the MB gaming state (more specifically, from the RT0 state to the RT3 state), when “BB + F_special role B” is determined not as a pushing order but as an internal winning combination, “F_BB” Is carried over as a carryover combination, the RT state shifts to the RT4 state, and “2 for C_CB” is established regardless of the stop operation order and the stop operation timing, and 13 medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, from the RT0 state to the RT3 state), when “BB + F_special role C” is determined not as a pressing order but as an internal winning combination, “F_BB” Is carried over as a carryover combination, the RT state shifts to the RT4 state, and regardless of the stop operation order and the stop operation timing, the “C_special combination” is established and one medal is paid out.

  In this embodiment, when a small combination and a bonus combination are determined as an internal winning combination (including a case where a bonus combination is carried over), the small combination is established with priority over the bonus combination. Stop control is performed. Of course, stop control that preferentially establishes a bonus combination over a small combination may be performed.

  As shown in FIG. 21, in the MB gaming state, “F_normal lip”, “F_RT1_RT2U lip 1” to “F_RT1_RT2U lip 6”, “F_RT2_RT3U lip 1” to “F_RT2_RT3U lip 6”, “F_RT2 maintenance lip 1” to “ “F_RT2 maintenance Lip 6”, “F_SP Lip A”, “F_SP Lip B”, “F_SP Lip C”, “F_SP Faiplip A”, “F_SP Faye Lip B”, “F_Chance Lip A” are not pushing orders, When it is determined as an internal winning combination, regardless of the stop operation order and the stop operation timing, “1 for C_CB” is established, and 14 medals are paid out.

  Further, in the MB gaming state, “F_RT3 Lip A1”, “F_RT3 Lip B1”, and “F_RT3 Lip C1” are pushing orders, and the stop operation order is “batting order 1” and “batting order 2” (ie, left If the reel 3L is the first stop), “2 for C_CB” is established regardless of the timing of the stop operation, and 13 medals are paid out. On the other hand, if the stop operation order is other than “batting order 1” and “batting order 2”, “1 for C_CB” is established regardless of the timing of the stopping operation, and 14 medals are paid out.

  Further, in the MB gaming state, “F_RT3 Lip A2”, “F_RT3 Lip B2”, and “F_RT3 Lip C2” are pushing orders, and the stop operation order is “batting order 3” and “batting order 4” (that is, middle ordering). If the reel 3C is the first stop), regardless of the timing of the stop operation, “2 for C_CB” is established, and 13 medals are paid out. On the other hand, if the stop operation order is other than “batting order 3” and “batting order 4”, “1 for C_CB” is established and 14 medals are paid out regardless of the timing of the stopping operation.

  In the MB gaming state, “F_RT3 Lip A3”, “F_RT3 Lip A4”, “F_RT3 Lip B3”, “F_RT3 Lip B4”, “F_RT3 Lip C3”, and “F_RT3 Lip C4” are in order of pushing, If the stop operation order is “batting order 5” and “batting order 6” (that is, the right reel 3R is first stopped), “2 for C_CB” is established regardless of the timing of the stopping operation, and 13 medals are obtained. To be paid out. On the other hand, if the stop operation order is other than “batting order 5” and “batting order 6”, “1 for C_CB” is established regardless of the timing of the stopping operation, and 14 medals are paid out.

  Here, in the MB gaming state, it is considered that the pushing order in which 14 medals are always paid out is advantageous for the player. However, in this embodiment, the medals with the MB gaming state exceeding “13” are paid out. Therefore, when 13 medals are paid out in the first game in the MB gaming state, the second game in the MB gaming state can be performed. You will be able to receive medal medals. Therefore, in the first game in the MB gaming state, when the above-described pushing order is determined as an internal winning combination, the pushing order in which 13 medals are paid out is an advantageous stop operation for the player. In the second game in the MB gaming state, when the above-mentioned push order combination is determined as an internal winning combination, a stop operation in which the push order in which 14 medals are paid out is advantageous for the player It becomes information of.

  In the present embodiment, whether or not the timing of the stop operation is an appropriate timing in any of the cases where 13 medals are paid out and 14 medals are paid out in the MB gaming state. Although it is configured so as not to be required, 13 or 14 if the timing of the stop operation is appropriate so that the technical intervention of the game can be enhanced and the health of the game can be secured. However, if the timing of the stop operation is not an appropriate timing, 13 or 14 medals may not be paid out.

  Further, in the present embodiment, in the MB gaming state, when the replay combination and the small combination are determined as the internal winning combination, stop control for preferentially establishing the small combination over the replay combination is performed. Although configured, stop control that preferentially establishes a replay combination over a small combination can also be performed.

  As described above with reference to FIGS. 19 to 21, the pushing order that is advantageous for the player is uniquely defined in the pushing order. In the present embodiment, when the gaming state is the ART gaming state, information on a stop operation indicating a pressing order that is advantageous to the player is notified. That is, in the gaming state other than the RT4 state which is the bonus winning state and the BB gaming state which is the bonus state, the RT state is shifted to the RT3 state, and the RT state is maintained in the RT3 state. Further, the stop operation order is notified as stop operation information so that the player can receive more medals.

  In this embodiment, stop operation information that is advantageous to the player is transmitted by an instruction monitor controlled by the main control board 71 and other means (for example, the display device 11) controlled by the sub control board 72. Informed.

  For example, when “batting order 1” and “batting order 2” are pushing orders that are advantageous to the player, a numerical value “1” is displayed on the instruction monitor, and the display device 11 displays the pushing order “1-- ”Is displayed, and“ batting order 3 ”and“ batting order 4 ”are pushing orders that are advantageous to the player, a numerical value“ 2 ”is displayed on the instruction monitor, and the pushing order“ -1- "is displayed, and when" batting order 5 "and" batting order 6 "are pushing orders advantageous to the player, a numerical value" 3 "is displayed on the instruction monitor, and the display device 11 displays The push order “--1” is displayed.

  Further, for example, when “batting order 1” is a pressing order that is advantageous to the player, a numerical value “4” is displayed on the instruction monitor, and a pressing order “123” is displayed on the display device 11. When the “batting order 2” is a pressing order that is advantageous to the player, a numerical value “5” is displayed on the instruction monitor, a pressing order “132” is displayed on the display device 11, and “batting order 3”. However, if the pressing order is advantageous to the player, the numerical value “6” is displayed on the instruction monitor, the pressing order “213” is displayed on the display device 11, and the “batting order 4” In the case of the pushing order that is advantageous to the player, the numerical value “7” is displayed on the instruction monitor, the pushing order “312” is displayed on the display device 11, and the “batting order 5” is advantageous to the player. In case of the pressing order, the indication monitor displays the value “8”. The display device 11 displays the push order “231”, and when the “batting order 6” is a push order that is advantageous to the player, a numerical value “9” is displayed on the instruction monitor, and the display device 11 Is displayed in the pressing order “321”.

  Of course, the manner in which the pushing order advantageous to the player is notified is not limited to the above, and any manner may be used as long as the player can recognize the pushing order advantageous. For example, instead of the instruction monitor and / or the display device 11, or in addition to this, the sub display device 18, the LED group 85, the speaker group 84, or the like can be used to notify the player of an advantageous push order. .

  In addition, as long as there is no disadvantage for the player, the instruction monitor and / or the display device 11 is notified of a push order other than the push order that is advantageous to the player for the purpose of enhancing the game performance and the effect. It can also be done. One example thereof will be described later with reference to FIGS. 33C, 69, and 70 described later.

  Here, the stop control (determination method of the stop symbol position) of the reel in the pachi-slot 1 of the present embodiment will be briefly described. In this embodiment, after the stop operation is detected by the stop switch, the reel stop control is performed so that the rotation of the corresponding reel stops within 190 msec (within 75 msec for a specific reel in the MB gaming state). Specifically, the number of sliding symbols “0” to “4” (“0” or “1” for a specific reel in the MB gaming state) is set to the value of the symbol counter corresponding to the reel when the stop operation is detected. The symbol position corresponding to the obtained value is determined as the symbol position where the reel rotation stops (hereinafter referred to as “scheduled stop position”). The symbol position corresponding to the value of the symbol counter corresponding to the reel when the stop operation is detected is the symbol position at which the rotation of the reel starts to be stopped (hereinafter referred to as “stop start position”).

  That is, the number of sliding pieces is the amount of rotation of the reel from when the stop operation is detected by the stop switch until the rotation of the corresponding reel stops. In other words, the number of symbols passing through the middle area of the corresponding reel in the reel display window 4 in the period from when the stop operation is detected by the stop switch until the rotation of the corresponding reel stops. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

  Referring to a stop table (not shown), the number of sliding pieces is acquired according to the stop start position of each reel. In the present embodiment, the number of sliding pieces is acquired based on the stop table, but this is a tentative one, and the acquired number of sliding pieces does not immediately determine the planned stop position of the reel. In the present embodiment, when there is a more appropriate number of sliding pieces than the number of sliding pieces acquired based on the stop table (hereinafter referred to as “sliding piece number determination data”), a drawing priority table (not shown) is referred to. To change the number of sliding pieces. The number-of-sliding piece determination data is used to compare the priorities of symbols from the stop start position to the symbol position that is the maximum number of sliding symbols four points ahead (one for a specific reel in the MB gaming state). Referenced to determine the search order when performing.

<Configuration of storage area provided in main RAM>
Next, the configuration of various storage areas provided in the main RAM 103 will be described with reference to FIGS.

[Hit request flag storage area and winning action flag storage area]
First, with reference to FIG. 22, the structure of the winning request flag storage area (internal winning combination storing area) and the winning action flag storing area (display combination storing area) will be described. In the present embodiment, the winning request flag storage area (flag data storage area, winning flag data storage area) and the winning action flag storage area (winning flag data storage area) have the same configuration.

  In this embodiment, the winning request flag storage area is composed of winning request storing areas 1 to 7 each represented by 1-byte data, and the winning action flag storing area is each a winning operation represented by 1-byte data. It consists of storage areas 1-7. The data stored in the storage areas of the winning request flag storage area and the winning action flag storage area is only 1-byte data in the “data” column in FIG. 22, but in FIG. “Combination” indicating the symbol combination of each reel associated with the bit of the storage area (in the drawing, described in the order of the symbol of the left reel 3L, the symbol of the middle reel 3C and the symbol of the right reel 3R), and The contents (see FIG. 18) are also described.

  In each of the hit request flag storage areas 1 to 7, when “1” is stored in a predetermined bit, it indicates that the internal winning combination corresponding to the predetermined bit has been won internally. In each of the winning action storage areas 1 to 7, when “1” is stored in a predetermined bit, it indicates that a display combination (winning action flag) corresponding to the predetermined bit has won. That is, when “1” is stored in a predetermined bit, it indicates that the symbol combination corresponding to the predetermined bit is displayed on the active line.

  In the winning request flag storage area and the winning action flag storage area, as shown in FIG. 22, a plurality of symbol combinations (combinations) are assigned to one bit (flag) in each storage area. (See FIG. 18). That is, for such a flag, it means that there are a plurality of symbol combinations (combination that can be awarded) that can be stopped and displayed.

[Coverage storage area]
Next, the configuration of the carryover combination storage area will be described with reference to FIG. In the present embodiment, the carryover combination storage area is composed of a 1-byte data storage area.

  When the internal winning combination “F_BB” or “F_MB” is determined as a result of the internal lottery, the internal winning combination (bonus combination) is stored in the carryover combination storage area as a carryover combination. The carryover combination stored in the carryover combination storage area is held without being cleared until the corresponding symbol combination is displayed on the active line. Further, while the carryover combination is stored in the carryover combination storage area, the carryover combination is stored in the hit request storage area in addition to the internal winning combination determined by the internal lottery.

[Game state flag storage area]
Next, the configuration of the game state flag storage area will be described with reference to FIG. The gaming state flag storage area is composed of a 1-byte data storage area. In this embodiment, as shown in FIG. 24, a unique bonus type or RT type is assigned to each bit in the gaming state flag storage area.

  When “1” is stored in a predetermined bit in the game state flag storage area, it indicates that the bonus game or RT corresponding to the predetermined bit is being operated. For example, when “1” is stored in bit 0 of the game state flag storage area, it indicates that the big bonus “BB” is activated and the game state is the BB game state. For example, when “1” is stored in bit 6 of the gaming state flag storage area, it indicates that the gaming state is the RT3 state.

[Operation stop button storage area]
Next, the configuration of the operation stop button storage area will be described with reference to FIG. The operation stop button storage area is composed of a 1-byte data storage area and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operation state of the stop button is assigned to each bit.

  For example, if the left stop button 17L is a stop button that has been pressed this time, that is, an operation stop button, “1” is stored in bit 0 of the operation stop button storage area. Also, for example, if the left stop button 17L is a stop button that has not yet been pressed, that is, an effective stop button, “1” is stored in bit 4. Based on the data stored in the operation stop button storage area, the main CPU 101 identifies a stop button that has been pressed this time and a stop button that has not yet been pressed.

[Push order storage area]
Next, the configuration of the pressing order storage area will be described with reference to FIG. The pressing order storage area is composed of a 1-byte data storage area and stores a pressing order flag consisting of 1 byte.

  In the pressing order flag, the type of stop button pressing order is assigned to each bit. For example, when the stop button pressing order is “left, middle, right”, “1” is stored in bit 0 of the pressing order storage area.

[Design code storage area]
Next, the configuration of the symbol code storage area will be described with reference to FIG. In this embodiment, the symbol code storage area is composed of symbol code storage areas 1 to 7 each represented by 1-byte data. The symbol code storage area has the same configuration as the winning request flag storage area and the winning action flag storage area (see FIG. 22).

  In the symbol code storage area, “1” is stored in the bit corresponding to the symbol combination (combination) that can be stopped on the active line. After all the reels are stopped, the symbol codes corresponding to the display combination (winning operation flag) are stored in the symbol code storage areas 1 to 7.

<Configuration of data table related to ART function>
Next, with reference to FIGS. 28 to 33, the configuration of various data tables stored in the main ROM 102 and related to the ART function will be described.

[Specific internal state related to ART function]
First, with reference to FIG. 28, a specific internal state (hereinafter simply referred to as “mode”) which is one lottery element in the case of lottery related to the ART function in the present embodiment will be described.

  In the pachi-slot 1 of the present embodiment, “low probability 1”, “low probability 2”, “heaven preparation”, “heaven short”, “heaven long”, and “non-art gaming mode (normal mode)” “Super Heaven” is defined and managed by the main CPU 101. In addition, although not shown in FIG. 28, a “precursor mode” is defined in which the transition to the ART gaming state is determined as the normal mode, but the transition to the ART gaming state is awaited. Managed by the main CPU 101. The “precursor mode” can further define a plurality of “precursor modes” that differ in the number of precursor games (that is, the number of games until the transition to the ART gaming state). During the “precursor mode”, a continuous effect (that is, an effect executed over a plurality of games) for increasing the player's expectation of the transition to the ART game state is mainly executed according to the number of predictor games.

  The contents of the normal mode are as shown in FIG. 28, and the expectation level of ART game state transition (ART stock acquisition) is different in each normal mode. Specifically, in the order of “low probability 1”, “low probability 2”, “heaven preparation”, “heaven short”, “heaven long”, and “super heaven”, a lottery state that is relatively unfavorable for the player. Therefore, the lottery state is relatively advantageous for the player.

  Further, in the pachislot machine 1 of the present embodiment, “low accuracy”, “high accuracy preparation”, “high accuracy”, and “super high accuracy” are defined as the ART gaming state mode (ART mode), and the main CPU 101 Managed by.

  The contents of the ART mode are as shown in FIG. 28, and the degree of expectation of continuing the ART gaming state (CP acquisition) is different in each ART mode. Specifically, in the order of “low accuracy”, “high accuracy preparation”, “high accuracy”, and “super high accuracy”, a lottery that is relatively advantageous to the player from a lottery state that is relatively disadvantageous to the player. It is configured to be in a state.

  In the ART mode, not only the degree of expectation of CP acquisition may be different, but the number of ART games may be added or the expectation of addition of ART stock may be different, or these expectations may be made different. In addition, a plurality of other modes (for example, the addition mode) may be defined.

[Normal ART lottery table]
Next, with reference to FIG. 29, a lottery table used in the ART lottery performed in “normal time” will be described. FIG. 29 is a diagram illustrating an example of a normal ART lottery table when the set value is “1” and the probability denominator is “256”. The normal ART lottery table is a table that is referred to during an ART lottery performed every game in the normal start process (see S415 in FIG. 68 described later).

  In FIG. 29, “normal role 1” is “out of” (winning number “0”), “F_normal lip” (winning number “1”), “F_RT1_RT2U lip 1” to “F_RT1_RT2U lip 6” (winning number “0”). 2 ”to“ 7 ”),“ F_RT2_RT3U Lip 1 ”to“ F_RT2_RT3U Lip 6 ”(winning numbers“ 8 ”to“ 13 ”),“ F_RT2 keeping Lip 1 ”to“ F_RT2 keeping Lip 6 ”(winning number“ 14 ”) To “19”), “F_RT3 Lip A1” to “F_RT3 Lip A4” (winning numbers “20” to “23”), “F_RT3 Lip B1” to “F_RT3 Lip B4” (winning numbers “24” to “27”) ), And “F_RT3 Lip C1” to “F_RT3 Lip C4” (winning numbers “28” to “31”).

  Further, in FIG. 29, “ordinary combination 2” is “F_batting order bell 1A” to “F_batting order bell 6A” and “F_batting order bell 1B” to “F_batting order bell 6B” (winning numbers “39” to “50”). ), “F_1 single role” (winning number “51”), “F_common bell” (winning number “55”), “F_special role A” (winning number “57”), “F_special role B” (winning number) Number “58”), “F_special role C” (winning number “59”), and “F_MB” (winning number “63”).

  Further, in FIG. 29, “chance lip” indicates “F_SP faic lip A” (winning number “35”), “F_SP faic lip B” (winning number “36”), and “F_chance lip A” (winning number “37”). )).

  In FIG. 29, “strong bell” indicates “F_strong bell” (winning number “54”).

  In FIG. 29, “weak chance combination” indicates “F_weak chance combination” (winning number “52”).

  In FIG. 29, “medium chance combination” indicates “F_medium chance combination” (winning number “53”).

  In FIG. 29, “MB combination” indicates that all small combinations have been established in the MB gaming state.

  In the pachislot machine 1 of the present embodiment, lottery regarding the ART function is performed on the main control circuit 90 side. Therefore, in order to reduce the control burden at the time of lottery regarding the ART function, when the above internal winning combination is determined, information (grouping information) for grouping these internal winning combinations is generated (that is, the internal winning combination is generated). The information relating to the winning combination may be compressed), and lottery regarding the ART function may be performed based on the generated grouping information.

  For example, when the internal winning combination corresponding to the above-mentioned “normal winning combination 1” is determined, “0” is generated as the grouping information, and when the internal winning combination corresponding to “normal winning combination 2” is determined, When “1” is generated as the grouping information and the internal winning combination corresponding to “chance lip” is determined, “2” is generated as the grouping information and the internal winning combination corresponding to “strong bell” is determined. If “3” is generated as grouping information and an internal winning combination corresponding to “weak chance combination” is determined, “4” is generated as grouping information and corresponds to “medium opportunity combination” When an internal winning combination is determined, “5” is generated as grouping information, and when an internal winning combination corresponding to “MB combination” is determined, “6” is generated as grouping information. ART lot based on information It may be performed. The same applies to a mode transition lottery shown in FIG. 30 described later and a CP acquisition lottery shown in FIG. 32 described later.

  In the normal ART lottery table shown in FIG. 29, based on the internal winning combination, the current normal mode, and the random number for production, the game state is shifted to the ART gaming state (winning) or is not shifted to the ART gaming state. (Non-winning) is determined.

[Normal mode transition lottery table]
Next, with reference to FIG. 30, a lottery table used in the mode transition lottery performed in “normal time” will be described. FIG. 30 is a diagram illustrating an example of the normal mode transition lottery table when the set value is “1” and the probability denominator is “256”. The normal mode transition lottery table is a table that is referred to in the mode transition lottery performed for each game in the normal start process (see S415 in FIG. 68 described later).

  In FIG. 30, “normal role 1”, “normal role 2”, “chance lip”, “strong bell”, “weak chance role”, “medium chance role”, and “MB role” are explained with reference to FIG. As already mentioned in.

  In the normal ART lottery table shown in FIG. 30, the normal mode (transfer destination) of the transfer destination is determined based on the internal winning combination, the current normal mode, and the random number for presentation.

[CP lottery table in CP special zone]
Next, with reference to FIG. 31, a lottery table used in the CP acquisition lottery performed in the “CP special zone in BB” will be described. FIG. 31 is a diagram illustrating an example of the CP specialization zone CP acquisition lottery table when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. This CP special zone CP acquisition lottery table is a table that is referred to during CP acquisition lottery performed every game in the BB CP special zone start process (see S405 in FIG. 68 described later). is there.

  In FIG. 31, “normal role” indicates “F_common bell” (winning number “55”), and “rare role” indicates “chance role A during F_BB” (winning number “60”), “ F_BB chance chance role B "(winning number" 61 ") and" F_BB chance chance role C "(winning number" 62 ") are shown, and" special role "is" F_special role A "(winning number) "57").

  As described above, the grouping information may be generated also in the “BB special CP zone” (that is, the BB gaming state). For example, when an internal winning combination corresponding to “normal combination” is determined, “0” is generated as grouping information, and when an internal winning combination corresponding to “rare combination” is determined, “ 1 ”is generated, and when an internal winning combination corresponding to“ special combination ”is determined,“ 2 ”is generated as grouping information, and CP acquisition lottery is performed based on the grouping information. Also good.

  In the CP specialization zone CP acquisition lottery table shown in FIG. 31, the CP is added (winning) or the CP is not added based on the internal winning combination, the current state, and the random number for performance ( Non-winning) is determined. In this embodiment, when it is determined that CP is to be added (winning), “1” can be obtained for CP (that is, “1” is added to the CP counter).

  Although not shown in the figure, a state lottery is performed at the start of the “CP special zone in BB”, as will be described later with reference to FIG. Therefore, the internal state of “state 1” or “state 2” is set. Then, as shown in FIG. 31, it is easier to acquire a CP when “state 2” is set than when “state 1” is set. In that sense, “state 2” is an internal state that is more advantageous to the player than “state 1”.

[Double-specialized zone CP acquisition lottery table]
Next, with reference to FIG. 32, the lottery table used in the CP acquisition lottery performed in the “double specialized zone” will be described. FIG. 32 is a diagram illustrating an example of the CP acquisition lottery table in the double specialized zone when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. This double special zone CP acquisition lottery table is a table that is referred to during CP acquisition lottery performed in step S433 of the double special zone start process described later with reference to FIGS. 69 and 70. is there.

  In FIG. 32, “normal role 1”, “normal role 2”, “chance lip”, “strong bell”, “weak chance role”, “medium chance role”, and “MB role” are explained with reference to FIG. As already mentioned in.

  In the double special zone CP acquisition lottery table shown in FIG. 32, it is determined whether to add CP (winning) or not to add CP (non-winning) based on the internal winning combination and the random number for presentation. Is done. In this embodiment, when it is determined that CP is to be added (winning), “1” can be obtained for CP (that is, “1” is added to the CP counter).

[Double special zone start state lottery table]
Next, with reference to FIG. 33A, a lottery table used in the state lottery performed at the start of the “double specialized zone” will be described. FIG. 33A is a diagram showing an example of a double specialized zone start state lottery table when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. It is. The double special zone start state lottery table is a table that is referred to during the state lottery performed in S422 of the double special zone start process described later with reference to FIGS. 69 and 70. .

  As will be described later with reference to FIG. 33D, the “double specialized zone” is completed when “state 2” is set rather than when “state 1” is set. It has become difficult. In that sense, “state 2” is an internal state that is more advantageous to the player than “state 1”.

  In the double specialized zone start state lottery table shown in FIG. 33A, “state 1” or “state 2” is determined as the internal state in the double specialized zone based on the random number value for presentation. .

[Double special zone middle blue 7 o'clock CP lottery table]
Next, referring to FIG. 33 (B), when “RT3 Lip C” (ie, “F_RT3_Lip C1” to “F_RT3_Lip C4”) is determined as an internal winning combination in “Double Specialized Zone”. The lottery table used in the CP acquisition lottery performed in the following will be described. FIG. 33B is an example of a lottery table for the 7th CP acquisition lottery in the double special zone when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. FIG. Note that this double special zone blue 7 o'clock CP acquisition lottery table is referred to at the time of CP acquisition lottery performed in S430 of the double special zone start process described later with reference to FIGS. 69 and 70. It is a table.

  In the double special zone blue 7 o'clock CP acquisition lottery table shown in FIG. 33 (B), it is determined whether to add CP (winning) or not to add CP (non-winning) based on the random number for presentation. Is done. In this embodiment, when it is determined that CP is to be added (winning), “1” can be obtained for CP (that is, “1” is added to the CP counter).

[Double special zone medium blue 7 fake lottery table]
Next, referring to FIG. 33C, when “RT3 Lip A” (that is, “F_RT3_Lip A1” to “F_RT3_Lip A4”) is determined as the internal winning combination in the “Double Specialized Zone”. A lottery table used in the blue 7 fake notification lottery performed in FIG. FIG. 33C shows an example of a double specialized zone blue 7 fake lottery table when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. FIG. This double special zone blue 7 fake lottery table is referred to during the blue 7 fake notification lottery performed in S424 of the double special zone start process described later with reference to FIGS. 69 and 70. It is a table.

  In the double-specialized zone blue 7 fake lottery table shown in FIG. 33 (C), blue 7 fake notification is performed (winning) or blue 7 fake notification is not performed (non-winning) based on the random number value for production. ) Is determined. In the present embodiment, when it is determined to perform blue 7 fake notification (winning), the “double specialized zone” is not terminated. In other words, although the privilege that the ART stock can be acquired cannot be received, the privilege that the “double specialized zone” does not end can be received when the blue fake notification is performed. Details will be described later with reference to FIGS. 69 and 70.

  The data structure of the double specialized zone medium blue 7 o'clock CP lottery table shown in FIG. 33 (B) and the double specialized zone medium blue 7 fake lottery table shown in FIG. 33 (C) are the same. Therefore, it may be defined as a common lottery table (that is, one table) to which the same address is referred when each lottery is performed. If defined in this way, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to enhance the game playability.

[Double special zone end lottery table]
Next, with reference to FIG. 33 (D), a lottery table used in an end lottery of the “double specialized zone” will be described. FIG. 33D is a diagram showing an example of the double specialized zone end lottery table when the set value is “common” (that is, the same in settings 1 to 6) and the probability denominator is “256”. . The double special zone end lottery table is a table that is referred to in the end lottery performed in S441 of the start process in the double special zone described later with reference to FIGS. 69 and 70.

  In the double special zone end lottery table shown in FIG. 33 (D), the double special zone is ended (winning) or the double special zone is not ended based on the current state and the random number for production. (I.e., to continue) (non-winning) is determined.

<Data table structure related to special effects>
Next, the configuration of various data tables stored in the data storage area of the ROM cartridge substrate 86, particularly related to special effects, will be described with reference to FIGS.

[Special judgment lottery judgment value]
First, with reference to FIG. 34, the determination value for special effect lottery used for special effect reservation lottery in the present embodiment will be described.

  In the pachislot machine 1 of this embodiment, as described with reference to FIGS. 28 to 30, the specific internal state (mode) related to the ART function is changed. The special effect is an effect that is executed to suggest a change in the mode, and a determination value for the special effect lottery is determined in advance in order to determine whether or not the change in the mode is a target for executing the special effect. It has been.

  As shown in FIG. 34, the determination value “0” determines that the current normal mode is “precursor mode” and the number of predictor games is “1” or more in “normal time”.

  Further, the determination value “1” indicates that the normal mode has shifted from “low 1” to “heaven preparation” to “heaven short” or more as a result of the mode change lottery (see FIG. 30) in “normal time”. judge.

  In addition, the determination value “2” indicates that the normal mode has changed from “low 1” or “low 2” to “heaven preparation” as a result of the mode change lottery (see FIG. 30). judge.

  The determination value “3” determines that the normal mode has shifted to “heaven long” or more as a result of the mode shift lottery (see FIG. 30) in “normal time”.

  Further, the determination value “4” determines that the result of the mode transition lottery (see FIG. 30) was in other cases in “normal time”.

  The determination value “5” is set to “normal ART” and the current ART mode is “precursor mode” (that is, it is determined that the ART stock or the number of ART games will be added, but the addition is awaited. And the number of precursor games is “1” or more.

  The determination value “6” determines that the ART mode has shifted from “high accuracy preparation” or lower to “high accuracy” or higher as a result of mode transition lottery (not shown) in “normal ART”.

  The determination value “7” determines that the ART mode has shifted from “low accuracy” or lower to “high accuracy preparation” as a result of mode transition lottery (not shown) in “normal ART”.

  Further, the determination value “8” determines that the ART mode has shifted to “high accuracy” or higher as a result of the mode shift lottery (not shown) in “normal ART”.

  Further, the determination value “9” determines that the result of the mode transition lottery (not shown) is other cases in “normal ART”.

  Note that although the conditions determined by the determination values described above may overlap, the sub CPU 201 determines whether or not the conditions determined by the determination values match in order from the top (that is, in the order of “0” to “9”). In order to make a determination, when the conditions determined by the determination values overlap, a determination value having a smaller determination value is selected.

[Normal special reservation reservation lottery table]
Next, with reference to FIG. 35, the lottery table used in the special effect reservation lottery will be described. FIG. 35 is a diagram showing an example of a normal special effect reservation lottery table when the probability denominator is “32768”. The normal special effect reservation lottery table is a table that is referred to during the reservation lottery performed in S1194 of the special effect reservation process described later with reference to FIG.

  The normal special performance reservation lottery table shown in FIG. 35 conceptually shows lottery value information. “0” in the table means that the lottery value “0” is defined, and “very low” means that the lottery value is defined within the range of “1” to “99”. To do. “Low” in the table means that the lottery value is defined within the range of “100” to “999”, and “medium” means that the lottery value is within the range of “1000” to “9999”. “High” means that the lottery value is defined as “10000” or more. Further, “all remaining” in the table means that the remaining value obtained by subtracting other lottery values from the probability denominator “32768” is defined as the lottery value. For example, if lottery values such as “all remaining”, “0”, “0”, “0” are defined in the table, the lottery value of “all remaining” is “32768”.

  In the normal special effect reservation lottery table shown in FIG. 35, the special effect “none” corresponds to a special effect reservation parameter “0” described later, and the special effect “weak” indicates a special effect reservation parameter “1” described later. The special effect “medium” corresponds to a special effect reservation parameter “2”, which will be described later, and the special effect “strong” corresponds to a special effect reservation parameter “3”, which will be described later.

  The special effect “None” indicates that the special effect is not reserved, and the special effect “Weak” indicates that, for example, the light effect image is weakly undulated. Yes, the special effect “medium” indicates that, for example, an effect in which the effect image of light is strongly undulated is executed as the special effect, and the special effect “strong” is, for example, the effect of light. This shows that an effect in which images continuously wave is executed.

  In the normal special effect reservation lottery table shown in FIG. 35, the internal winning combination “MB medium bell” is synonymous with the above “MB combination”, and the internal winning combination “RT3 medium Lip” is “F_RT3_Lip A1”. ”To“ F_RT3_Lip C4 ”, the internal winning combination“ Blue 7 Fake ”indicates“ F_SP Faiclip A ”and“ F_SP Faiclip B ”, and the internal winning role“ Blue 7 ” F_SP Lip A ”to“ F_SP Lip C ”are shown.

  In the normal special effect reservation lottery table shown in FIG. 35, the special effect reservation parameter “0” is based on the determination value (see FIG. 34), the internal winning combination, and the effect random number value extracted on the sub-control circuit 200 side. ] To “3” are determined.

<Description of main control circuit operation>
Next, the contents of various processes executed by the main CPU 101 of the main control circuit 90 using a program will be described with reference to FIGS.

[Processing at power-on (reset interrupt)]
First, the process at the time of power-on (reset interrupt) of the pachislot 1 performed under the control of the main CPU 101 will be described with reference to FIGS. FIG. 36 is a flowchart showing a procedure of processing at power-on (reset interrupt). FIGS. 37A to 37C are sources for executing the processing of S2, S7 and S8, and S13 in the flowchart, respectively. It is a figure which shows an example of a program. 36, when the power supply management circuit 93 detects that the supply of the power supply voltage to the microprocessor 91 is started, the reset signal is sent to the “91” of the microprocessor 91. This is executed based on an interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 determines whether or not the power monitoring port (power monitoring means) is in an on state (S1).

  In S1, when the main CPU 101 determines that the power monitoring port is on (when S1 is YES), the main CPU 101 repeats the process of S1. Here, the power monitoring port being in the ON state is a state where the power supply voltage (DC + 5V) supplied to the main CPU 101 is not stable.

  On the other hand, when the main CPU 101 determines in S1 that the power monitoring port is not in the ON state (when S1 is NO), the main CPU 101 performs initialization processing of the timer circuit 113 (PTC) (S2). In this process, the main CPU 101 performs initial setting of the timer circuit 113. Specifically, the main CPU 101 sets a division ratio in a timer prescaler register (not shown), sets an interrupt enable setting in the timer control register (not shown), and sets a timer counter (not shown). Set the initial count value.

  Next, the main CPU 101 initializes the first serial communication circuit 114 (SCU1) between the main control circuit 90 and the sub control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. An initialization process is performed (S3). Next, the main CPU 101 performs initialization processing of the random number circuit 110 (RDG) (S4). Next, the main CPU 101 performs a write test on the main RAM 103 (S5).

  Next, the main CPU 101 determines whether or not writing to the main RAM 103 has been normally performed as a result of the writing test (S6).

  In S6, when the main CPU 101 determines that the writing to the main RAM 103 has not been performed normally (when S6 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, when the main CPU 101 determines in S6 that the writing to the main RAM 103 has been performed normally (when S6 is YES), the main CPU 101 determines the state of the timer control register (not shown) of the timer circuit 113. Is acquired (S7).

  Next, the main CPU 101 determines whether or not the current state is the generation timing of the interrupt process based on the acquired state of the timer control register (S8). Specifically, the main CPU 101 determines whether 1.1172 ms has elapsed since the start of the timer count based on the acquired state of the timer control register.

  In the present embodiment, when the timer time 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the count process of the CPU built-in timer is started. Thereafter, the status of the timer circuit 113 can be acquired by reading information in a timer control register (not shown). In this embodiment, a bit (determination bit) that can determine (refer to) whether or not the current state is the generation timing of an interrupt process (whether or not it is a timer interrupt state) in the timer control register. ) Is provided.

  Therefore, in the process of S7, the main CPU 101 reads information in the timer control register (not shown), and in the process of S8, the main CPU 101 turns on / off the discrimination bit in the timer control register ( By referring to “1” / “0”), it is determined whether or not the current state is the generation timing of the interrupt process. When 1.1172 ms elapses from the count start by the timer circuit 113 (if the count value of the timer circuit 113 is 0), the determination bit is turned on.

  In S8, when the main CPU 101 determines that the current state is not the generation timing of the interrupt process (when S8 is NO), the main CPU 101 returns the process to the process of S7 and repeats the processes after S7.

  On the other hand, when the main CPU 101 determines in S8 that the current state is the generation timing of the interrupt process (when S8 is YES), the main CPU 101 performs a sum check process (not specified) (S9). . In this process, the main CPU 101 performs a sum check process of the main RAM 103, and the work of this process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. The program used in the sum check process is stored in an unspecified area in the main ROM 102 (see FIG. 12B). The details of the sum check process will be described later with reference to FIGS. 51 and 52 described later.

  In S8, when the main CPU 101 determines that the current state is the generation timing of the interrupt process (when S8 is YES), the main CPU 101 determines the below-described interrupt before the process of S9. (See FIG. 100 described later). As a result of this interrupt processing, a no-operation command is transmitted from the main control circuit 90 (main control board 71) to the sub control circuit 200 (sub control board 72).

  After the process of S9, the main CPU 101 determines whether or not the setting key type switch 54 is in an on state (S10).

  In S10, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when S10 is YES), the main CPU 101 performs the process of S15 described later. On the other hand, when the main CPU 101 determines in S10 that the setting key switch 54 is not in the ON state (when S10 is NO), the main CPU 101 determines the sum check based on the result of the sum check process in S9. It is determined whether or not the result is normal (S11).

  In S11, when the main CPU 101 determines that the sum check determination result is not normal (when S11 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, when the main CPU 101 determines in S11 that the sum check determination result is normal (when S11 is YES), the main CPU 101 performs a game return process (S12). In this process, the main CPU 101 performs a process of returning the game state to the state before the power interruption detection. The details of the game return process will be described later with reference to FIG.

  When S6 or S11 is NO, the main CPU 101 displays a character string “rr” indicating an error occurrence on the information display 6 (7-segment LED display) (S13). Thereafter, the main CPU 101 repeats the WDT clear process (S14).

  Here, returning to the process of S10 again, if S10 is YES, the main CPU 101 performs a setting change confirmation process (S15). In this process, the main CPU 101 mainly performs a setting change command generation and storage process at the start of setting change. The details of the setting change confirmation process will be described later with reference to FIG.

  Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets the address “at the time of RAM abnormality or setting change start” in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. The information up to the last address in the RAM area is erased (cleared). After the process of S16, the main CPU 101 starts a main process (described later, see FIG. 54).

  In the present embodiment, processing at power-on (reset interrupt) is performed as described above. Then, the process of S2 during the power-on (reset interrupt) process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 37A.

  In the source program of FIG. 37A, 10 MHz is set as the CPU clock (supply clock is 20 MHz), 228 is set as the prescaler register setting value, and 49 is set as the initial count value. As a result, 1.1172 ms (= 1 / (10 MHz / 288) × 49) is calculated as the timer time (execution cycle) of the interrupt process.

  Further, the processing of S7 and S8 during the above power-on (reset interrupt) processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 37B. Specifically, the timer control register state acquisition process in S7 is executed by the “LD” instruction in FIG. 37B, and the determination process in S8 is executed by the “JBIT” instruction in FIG. 37B. Then, the “LD” instruction in FIG. 37B and the “JBIT” instruction in FIG. 37B are repeatedly performed until 1.1172 ms has elapsed from the start of counting by the timer circuit 113, and when 1.1172 ms has elapsed from the start of counting by the timer circuit 113. Then, an interrupt request signal is output from the timer circuit 113 to the main CPU 101 via the interrupt controller 112. The main CPU 101 starts the interrupt process of the first 1.1172 ms cycle after the power is restored, triggered by the input of this interrupt request signal.

  Note that in the first 1.1172 ms interrupt process immediately after the power is restored (after initialization at the time of power-on), no command related to the game operation is set, so that the main control circuit 90 transfers to the sub control circuit 200. A no-operation command is sent. In this way, by permitting the interrupt processing immediately after the power is restored, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

  In addition, the communication parameters 1 to 5 constituting the no-operation command transmitted in this communication operation are set with data stored in the L register, H register, E register, D register, and C register, respectively, when the power is restored. Is done. Therefore, in the present embodiment, the data set in the communication parameters 1 to 5 of the no-operation command transmitted in the first interrupt process after the power return is made different (undefined) at each power return. Can do. That is, the sum value (BCC) of the no-operation command transmitted in the interrupt process immediately after the power return (after initialization at the time of power-on) can be made different for each power return. In this case, fraudulent acts such as goto can be suppressed.

  Further, the process of S13 (interrupt prohibition process) during the above-described power-on (reset interrupt) process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 37C. . Then, the control for displaying the error code “rr” on the 2-digit 7-segment LED in the information display 6 is executed by one source code “LDW HL, 100H * cZCHRAR + cBX_PAYSEG” as shown in FIG. 37C. Then, the output operation of the 7-segment common output data to the 2-digit 7-segment LED and the output operation of the 7-segment cathode output data are simultaneously performed.

  That is, in the pachi-slot 1 of the present embodiment, when the two-digit 7-segment LED is controlled to be dynamically lit, 7-segment common output data and 7-segment cathode output data are simultaneously output. In this case, it is possible to reduce the number of instruction codes necessary for dynamic lighting control of the 7-segment LED on the source program, and to reduce the capacity of the source program (usage capacity of the main ROM 102). Therefore, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  Here, “7-segment common output data” is LED drive data output to the common (common) terminal of the 7-segment LED when the 7-segment LED is dynamically controlled, and “7-segment cathode output data” is , LED drive data output to each cathode terminal of the 7-segment LED when the 7-segment LED is dynamically controlled.

[Game return processing]
Next, with reference to FIG. 38 and FIG. 39, the game return process performed in S12 during the power-on (reset interrupt) process (see FIG. 36) will be described. FIG. 38 is a flowchart showing the procedure of the game return process, and FIG. 39 is a diagram showing an example of a source program for executing the processes of S25 to S32 in the flowchart.

  First, the main CPU 101 sets the stack pointer at the time of power interruption to the stack pointer (SP) (S21). Next, the main CPU 101 clears (turns off) the on-edge data before the interrupt processing of the input port and the currently set on-edge data (S22). Next, the main CPU 101 sets the backup data of the output port to the output port (S23). Next, the main CPU 101 reads the data of the input port and saves the data in the data storage area of the current input port and before the one interrupt process (S24).

  Next, the main CPU 101 sets the address of the spinning cylinder control data storage area (S25). Next, the main CPU 101 sets the number of reels to be checked (“3” in this embodiment) (S26).

  Next, the main CPU 101 acquires reel control management information (data relating to display row fluctuation control when power interruption occurs) based on the address of the set spinning cylinder control data storage area (S27). Note that the reel control management information (display row variation control management information) is information related to the control state (rotation state) of each reel, and is backed up and stored when power is interrupted.

  Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation state during the reel acceleration, the constant speed waiting, or the constant speed (S28).

  In S28, when the main CPU 101 determines that the condition of S28 is not satisfied (when S28 is NO), the main CPU 101 performs a process of S31 described later. On the other hand, when the main CPU 101 determines in S28 that the condition of S28 is satisfied (when S28 is YES), the main CPU 101 clears the spinning control data (reel control management information) (S29). With this process, after the game returns, the reel rotation control is started from the acceleration process. Next, the main CPU 101 sets a reel operation timing value (rotation control data execution start timing “1”) (S30). If “1” is set as the reel operation timing, the main CPU 101 accelerates the reel rotation control in the reel control process (see S903 in FIG. 100 to be described later). Start with

  After the process of S30 or when S28 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S31). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is “0” (S32).

  In S32, when the main CPU 101 determines that the value of the number of reels after subtraction is not “0” (when S32 is NO), the main CPU 101 changes the reel to be checked and changes the process to the process of S27. Return and repeat the processing from S27.

  On the other hand, when the main CPU 101 determines in S32 that the value of the number of reels after subtraction is “0” (when S32 is YES), the main CPU 101 performs a RAM initialization process (S33). In this process, the main CPU 101 sets the address at the time of “power recovery” in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the start of initialization, and starts from the start address to the end of the game RAM area. Erase (clear) information up to the address.

  Next, the main CPU 101 restores all the register data saved at the time of detecting power interruption to all the registers (S34). After the process of S34, the main CPU 101 ends the game return process and returns the process to the process at the time of detecting the power interruption.

  In the game return process, the main CPU 101 generates game return command data to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 47B described later) provided in the main RAM 103. The game return command stored and stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. Also good. In this case, the game return command may be configured to include each parameter for specifying the return to the state before the power interruption return.

  In the present embodiment, the game return process is performed as described above. In the game return process of the present embodiment, as described above, the input / output state of each port at the time of power failure is ensured at the time of power recovery, and when the reel is rotating at the time of power failure, the reel control management is performed at the time of power recovery. The processing necessary for acquiring the information and starting the reel re-rotation is also performed (refer to the processing of S25 to S32). Therefore, in the present embodiment, even when the power is restored from the power interruption during the rotation of the spinning cylinder, the reel re-rotation control can be stably performed, and the player does not feel uncomfortable.

  Further, the processing of S25 to S32 during the above-described game return processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As described above, in the microprocessor 91 with a security function for gaming machines used in the pachislot machine 1 of this embodiment, various instruction codes dedicated to the main CPU 101 are provided. For example, the “LDQ” instruction (predetermined read instruction) in FIG. 39 is one of instruction codes dedicated to the main CPU 101.

  For example, when the source code “LDQ HL, k” is executed on the source program, the address specified by the contents (stored data) of the Q register and the 1-byte integer k (direct value) is stored in the HL register. To be loaded. At this time, the contents of the Q register become the address value on the higher side of the designated address, and the integer k (direct value) becomes the address value on the lower side of the designated address. Therefore, when the source code “LDQ HL, .LOW.wR1_CTRL” in FIG. 39 is executed, the contents of the Q register (the address value on the upper side of the address of the drum control data storage area) and the integer value “. The address (address of the spinning cylinder control data storage area) specified by “LOW.wR1_CTRL” (address value on the lower side of the address of the spinning cylinder control data storage area) is loaded into the HL register. “.LOW.” Is not an actual instruction but a pseudo instruction. In this pseudo-instruction function, only the lower address of the storage area address defined following “.LOW.” Is validated. The pseudo instruction is not an instruction stored in the actual ROM, but an instruction for a conversion program (assembler) to refer to when converting the source file into a format for storing in the ROM.

  As described above, in the present embodiment, by using the instruction code dedicated to the main CPU 101 that performs addressing using the Q register (extension register), the main ROM 102, the main RAM 103, and the memory map I / O can be directly converted. Can be accessed. In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Setting change confirmation process]
Next, with reference to FIGS. 40 and 41, the setting change confirmation process performed in S15 during the power-on (reset interrupt) process (see FIG. 36) will be described. 40 is a flowchart showing the procedure of setting change confirmation processing, FIG. 41A is a diagram showing an example of a source program for executing the processing of S44 to S47 in the flowchart, and FIG. It is a figure which shows an example of the source program for performing the process of S57 in this flowchart.

  First, the main CPU 101 performs an initialization process for an unspecified RAM area in the main RAM 103 (S41). Next, the main CPU 101 performs one interrupt waiting process (S42). In this process, the main CPU 101 stands by until the transmission process of the no-operation command to the sub control circuit 200 by the interrupt process is completed.

  Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets the address “at the time of RAM abnormality or setting change start” in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. The information up to the last address in the RAM area is erased (cleared).

  Next, the main CPU 101 determines whether or not the setting key type switch 54 is on (S44). A setting key (not shown) inserted into the setting key type switch 54 is an operation key for operating the setting (setting values 1 to 6) of the pachislot 1. When the setting key is turned on, the setting key is set. The key switch 54 is turned on.

  In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (in the case where S44 is NO), the main CPU 101 ends the setting change confirmation processing and turns on the power (reset interrupt). ) The process proceeds to S16 in the time process (see FIG. 36). On the other hand, when the main CPU 101 determines in S44 that the setting key type switch 54 is in the ON state (when S44 is YES), the main CPU 101 performs a medal acceptance prohibition process (S45). By this process, the solenoid of the selector 66 (see FIG. 7) is not driven, and the inserted medal is discharged from the medal payout opening 24 (see FIG. 2).

  Next, the main CPU 101 sets setting change start or setting check start information (005H: first value) in the L register, and generates and stores a setting change command (setting change / setting check start) (S46). . In this process, the main CPU 101 generates setting change command data (first command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process. The data is stored in a communication data storage area provided in the main RAM 103. Details of the setting change command generation / storage process will be described later with reference to FIG. Also, the setting change command (setting change / setting confirmation start) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. Sent to.

  Next, the main CPU 101 sets the error count relay to an on state (S47). Next, the main CPU 101 determines which setting change or setting confirmation has been performed (S48).

  In S48, when the main CPU 101 determines that the setting has not been changed (setting has been confirmed) (when S48 is NO), the main CPU 101 performs the process of S55 described later.

  On the other hand, when the main CPU 101 determines in S48 that the setting has been changed (the setting has not been confirmed) (when S48 is YES), the main CPU 101 performs a setting value update process (S49). ). Next, the main CPU 101 performs setting value 7-segment display setting processing (S50). By this processing, the updated set value can be displayed by the 7-segment LED in the information display 6.

  Next, the main CPU 101 determines whether or not the reset switch 76 is on (S51).

  When the main CPU 101 determines in S51 that the reset switch 76 is in the on state (when S51 is YES), the main CPU 101 returns the process to the process of S49 and repeats the processes after S49. On the other hand, when the main CPU 101 determines in S51 that the reset switch 76 is not in the on state (when S51 is NO), the main CPU 101 determines whether or not the start switch 79 is in the on state (S52). .

  In S52, when the main CPU 101 determines that the start switch 79 is not on (when S52 is NO), the main CPU 101 returns the process to the process of S51 and repeats the processes after S51. On the other hand, when the main CPU 101 determines in S52 that the start switch 79 is on (when S52 is YES), the main CPU 101 sets a setting value storage area (not shown) provided in the main RAM 103. The value is stored (S53).

  Next, the main CPU 101 determines whether or not the setting key switch 54 is in an OFF state (S54).

  In S54, when the main CPU 101 determines that the setting key switch 54 is not in the OFF state (when S54 is NO), the main CPU 101 repeats the process of S54. On the other hand, when the main CPU 101 determines in S54 that the setting key type switch 54 is in the off state (when S54 is YES), the main CPU 101 performs the process of S55 described later.

  When S48 is NO or S54 is YES, the main CPU 101 determines whether setting change or setting confirmation has been performed (S55).

  When the main CPU 101 determines in S55 that the setting has not been changed (setting confirmation has been performed) (when S55 is NO), the main CPU 101 performs the process of S57 described later. On the other hand, when the main CPU 101 determines in S55 that the setting has been changed (the setting has not been confirmed) (when S55 is YES), the main CPU 101 performs a RAM initialization process (S56). . In this process, the main CPU 101 uses, as a start address for starting initialization, an address at the “setting change end” (not shown) in the game RAM area of the main RAM 103 shown in FIG. The information from the head address to the last address of the game RAM area is erased (cleared).

  After the process of S56 or when S55 is NO, the main CPU 101 sets setting change end information or setting check end information (004H: second value) in the L register, and a setting change command (setting change / setting check end). ) Is generated and stored (S57). In this process, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change process or the setting confirmation process. The data is stored in a communication data storage area provided in the main RAM 103. Details of the setting change command generation / storage process will be described later with reference to FIG. Also, the setting change command (setting change / setting confirmation end) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. Sent to. After the process of S57, the main CPU 101 ends the setting change confirmation process, and moves the process to the process of S16 of the power-on (reset interrupt) process (see FIG. 36).

  In the present embodiment, the setting change confirmation process is performed as described above. The processing of S44 to S47 during the setting change confirmation processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 41A. Among them, for example, the setting key state determination process of S44 is executed by the source code “BITQ 7, (.LOW. (WIBUF + 4))” in FIG. 41A, and sets the error count relay of S47 to the ON state. The processing is executed by the source code “SETQ 1, (.LOW.wECRREQ)” in FIG. 41A.

  Both the “BITQ” instruction and the “SETQ” instruction are instruction codes dedicated to the main CPU 101 for performing addressing using the Q register (extension register).

  For example, when the source code “BITQ b, (k)” is executed on the source program, data stored in the Q register (upper address value) and 1-byte integer value k (direct value: lower address value) ) Is checked, and if the bit b stores “1”, the zero flag (bit 6: see FIG. 11) of the flag register F is set to “0”. If “0” is stored in the bit b, “1” is set in the zero flag (predetermined bit area) of the flag register F. Therefore, when the source code “BITQ 7, (.LOW. (WIBUF + 4)” in FIG. 41A is executed, the address specified by the data stored in the Q register and the integer value “.LOW. (WIBUF + 4)” If bit 7 of this memory is checked and "1" is stored in bit 7, "0" is set in the zero flag of flag register F, and if "0" is stored in bit 7 , “1” is set in the zero flag of the flag register F.

  For example, when the source code “SETQ b, (k)” is executed on the source program, data stored in the Q register (upper address value) and 1-byte integer value k (direct value: lower side) "1" is set in the bit b of the memory at the address specified by (address value). Therefore, when the source code “SETQ 1, (.LOW.wECRREQ)” in FIG. 41A is executed, the data stored in the Q register and the memory at the address specified by the integer value “.LOW.wECRREQ” are stored. Bit 1 is set to “1”.

  That is, in the setting change confirmation process of the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extended register) as described above are used, and by using these main CPU 101 dedicated instruction codes, a direct value is obtained. Thus, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to increase the free space of the main ROM 102 and to increase the processing speed.

  In addition, the setting change command (initialization command) generation / storage process performed at the start of setting change / setting check in S46 during the setting change check process described above is performed by the main CPU 101 executing the “CALLF” instruction in FIG. 41A. The process for generating and storing the setting change command (initialization command) performed at the end of the setting change / setting confirmation in S57 described above is performed by the main CPU 101 executing the “CALLF” instruction in FIG. 41B. The “CALLF” instruction is also a dedicated instruction code for the main CPU 101.

  For example, when the source code “CALLF mn” is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is designated by the stack pointer (SP). The data is saved in the memory, the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address specified by "mn". However, the “CALLF” instruction is a 2-byte instruction, and an address range that can be jumped is a range of 0000H to 11FFH. Therefore, for example, when the source code “CALLF SB_PCINIT_00” in FIG. 41A is executed, the current PC register value is saved in the memory specified by the stack pointer (SP), and the stack pointer is updated by −2. The address of “SB_PCINIT_00” is stored in the PC register, and the process jumps to the address specified by “SB_PCINIT_00”.

  In the present embodiment, an instruction code called a “CALL” instruction is also prepared as an instruction code of the same type as the “CALLF” instruction. For example, when the source code “CALL mn” is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is stored as in the “CALLF” instruction. The data is stored in the memory designated by the stack pointer (SP), the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address designated by "mn". However, the “CALL” instruction is a 3-byte instruction, and the address range that can be jumped is different from that of the “CALLF” instruction, and the address range that can be jumped is the range of 0000H to FFFFH. Since the “CALLF” instruction is an instruction code having a smaller number of bytes than the “CALL” instruction, the capacity of the source program (usable capacity of the main ROM 102) can be reduced and the processing efficiency can be improved. be able to.

  Further, in the setting change confirmation process of this embodiment, as shown in FIGS. 41A and 41B, the jump destination address “SB_PCINIT_00” designated by the “CALLF” instruction in S46 is the jump destination designated by the “CALLF” instruction in S57. Is the same address as That is, in the present embodiment, a setting change command (initialization command) generation and storage process to be transmitted to the sub-control circuit 200 at the time of setting change (when a gaming machine is started), at the time of setting check start (during normal operation), and at the end of setting check Are the same as each other, and the source program of the setting change command generation / storage process used in both the processes of S46 and S57 is shared (modularized).

  In this case, since it is not necessary to provide a source program for the setting change command generation / storage process separately in both the processes of S46 and S57, the capacity of the source program (the capacity of the main ROM 102) can be reduced accordingly. . As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Setting change command generation and storage processing]
Next, the setting change command generation / storage process performed in S46 and S57 in the setting change confirmation process (see FIG. 40) will be described with reference to FIGS. 42 is a flowchart showing the procedure of the setting change command generation / storage process, and FIG. 43 is a diagram showing an example of a source program for executing the setting change command generation / storage process.

  First, the main CPU 101 sets information of setting values (1 to 6) in the E register (S61). Next, the main CPU 101 sets RT state information in the C register (S62). Next, the main CPU 101 sets the command type information (02H) of the setting change command in the A register (S63).

  Next, the main CPU 101 performs communication data storage processing (S64). In this process, the main CPU 101 determines the information set in each register in S61 to S63 and the information set in the D register in S46 or S57 (see FIG. 40) (setting change start / setting change end / setting status). The setting change command data is generated using the setting confirmation start / setting confirmation end), and the generated command data is stored in the communication data storage area. Details of the communication data storage processing will be described later with reference to FIG. 44 described later.

  After the process of S64, the main CPU 101 ends the setting change command generation / storage process. When ending the setting change command generation / storage process performed in S46 during the setting change confirmation process (see FIG. 40), the main CPU 101 executes the process of the setting change confirmation process (see FIG. 40) after the process in S64. The process proceeds to S47. Further, when ending the setting change command generation / storage processing performed in S57 during the setting change confirmation processing (see FIG. 40), the main CPU 101 ends the setting change command generation / storage processing after the processing of S64 and sets the setting. The change confirmation process (see FIG. 40) is also terminated.

  In the present embodiment, the setting change command generation / storage process is performed as described above. The setting change command generation / storage process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG.

  As described above, in the setting change command generation / storage process, the setting status is stored in the D register as the communication parameter 4 immediately before the setting change command generation / storage process is executed, and the setting value is set during the execution of the setting change command generation / storage process. Is stored in the E register as communication parameter 3, and RT information is stored in the C register as communication parameter 5. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), the communication parameters 3 to 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side. New information is set in the communication parameter. On the other hand, the other communication parameters 1 and 2 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side. Therefore, the values stored in the L register and the H register at the present time are set, respectively. Therefore, the values of the communication parameters 1 and 2 when the setting change command (initialization command) is transmitted are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[Communication data storage processing]
Next, with reference to FIGS. 44 and 45, for example, the communication data storage process performed in S64 during the setting change command generation / storage process (see FIG. 42) will be described. The communication data storage process is executed not only when the setting change command is generated but also when other commands are generated. FIG. 44 is a flowchart showing a procedure of the communication data storage process, and FIG. 45 is a diagram showing an example of a source program for executing the processes of S71 to S76 during the communication data storage process.

  First, the main CPU 101 stores the data set in the A register as communication command type data in a communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register in the communication data temporary storage area (predetermined storage area) in the main RAM 103 as communication command parameters 1 and 2, respectively (S72). .

  Next, the main CPU 101 stores the data set in the D register and E register as communication command parameters 3 and 4 in the communication data temporary storage area in the main RAM 103 (S73). Next, the main CPU 101 stores the data set in the B register and the C register in the communication data temporary storage area in the main RAM 103 as the communication command parameter 5 and the RT state data, respectively (S74).

  Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in a communication data temporary storage area in the main RAM 103 (S76).

  After the process of S76, the main CPU 101 determines whether or not there is an empty communication data storage area in the main RAM 103 (S77). In the present embodiment, a maximum of nine command data can be stored in the communication data storage area (see FIG. 47B described later).

  In S77, when the main CPU 101 determines that there is no free space in the communication data storage area (when S77 is NO), the main CPU 101 ends the communication data storage process and, for example, a setting change command generation storage process ( The process also ends (see FIG. 42).

  On the other hand, when the main CPU 101 determines in S77 that the communication data storage area is free (when S77 is YES), the main CPU 101 is stored in the communication data temporary storage area by the processes of S71 to S76 described above. The communication data is stored in the communication data storage area as communication command data (S78).

  Next, the main CPU 101 performs communication data pointer update processing (S79). In this process, the main CPU 101 mainly performs a process of updating a communication data pointer indicating a storage address of communication data in the communication data storage area. Details of the communication data pointer update process will be described later with reference to FIG. 46 described later.

  Then, after the process of S79, the main CPU 101 ends the communication data storage process and also ends the setting change command generation / storage process (see FIG. 42), for example.

  In the present embodiment, the communication data storage process is performed as described above. Note that the processing of S71 to S76 in the communication data storage processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. In this series of processing, the storage process of the communication command type data, various communication parameters, gaming state flag data, and BCC data included in the command data is performed as shown in FIG. It is executed using an “LDQ” instruction, which is a dedicated instruction code for the main CPU 101 that performs addressing using (extension register).

  Specifically, when the source code “LDQ (.LOW. (WPDT_TMP + 0)), A” is executed, the type data of the communication command stored in the A register becomes the stored data (upper address value) of the Q register and 1 It is stored in the communication data temporary storage area at the address specified by the integer value “.LOW. (WPDT_TMP + 0)” (lower address value). Further, when the source code “LDQ (.LOW. (WPDT_TMP + 1)), HL” is executed, the communication parameter 1 stored in the L register is changed to the data stored in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 1)”. The communication parameter 2 stored in the communication data temporary storage area at the address designated by "" and stored in the H register is stored in the communication data temporary storage area at the next address. In addition, when the source code “LDQ (.LOW. (WPDT_TMP + 3)), DE” is executed, the communication parameter 3 stored in the E register is stored in the Q register and the integer value “.LOW. (WPDT_TMP + 3) in 1 byte. The communication parameter 4 stored in the communication data temporary storage area of the address designated by “” and stored in the D register is stored in the communication data temporary storage area of the next address. Then, by executing the source code “LDQ (.LOW. (WPDT_TMP + 5)), BC”, the communication parameter 5 stored in the C register is stored in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 5)”. The gaming state flag data stored in the communication data temporary storage area of the address designated by “B” and stored in the B register is stored in the communication data temporary storage area of the next address.

  Further, the BCC data serving as the sum value of the command data set in the communication data storing process is calculated by executing a series of source codes “ADD (addition instruction code) A, H” to “ADD A, B”. Stored in a register. Then, by executing the source code “LDQ (.LOW. (WPDT_TMP + 7)), A”, the BCC data stored in the A register becomes the stored data in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 7)”. And stored in the communication data temporary storage area at the address specified by.

  As described above, in this embodiment, when one packet (8 bytes) of communication data (command data) is created, various parameters are transferred from the register and stored in a communication data temporary storage area (communication buffer). In such a command data creation method, data stored in each register at the time of command generation is directly stored in the communication data temporary storage area as various parameters of the command data. Therefore, when command data including an unused parameter is created, the value of the unused parameter becomes an indefinite value every time it is created. In this case, even if there is command data of the same type and the value of the use parameter is the same, the command data sum value (BCC data) can be changed every time the command is created. In this embodiment, the sum value, which is one of the error codes, is calculated by ADD (addition instruction code). However, instead of the addition instruction code, SUB (subtraction instruction code), XOR (exclusive OR) The same effect can be obtained by calculating the error code using the instruction code. Further, the same effect can be obtained by calculating an error code using MUL (multiplication instruction code) or DIV (division instruction code), which is a dedicated instruction for the main CPU 101.

  Therefore, in this embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress illegal acts such as goto, and it is necessary to add unnecessary goth countermeasure processing. Therefore, it is possible to suppress the compression of the program capacity of the main control circuit 90 due to the addition of the anti-going process.

[Communication data pointer update processing]
Next, with reference to FIGS. 46 and 47, the communication data pointer update process performed in S79 during the communication data storage process (see FIG. 44) will be described. 46 is a flowchart showing the procedure of the communication data pointer update process, FIG. 47A is a diagram showing an example of a source program for executing the communication data pointer update process, and FIG. 47B is a communication data pointer. It is a figure which shows the structure of the communication data storage area | region actually set on the source program of an update process.

  First, the main CPU 101 acquires the value of the currently set communication data pointer (S81).

  Next, the main CPU 101 adds and updates the value of the communication data pointer for one packet (8 bytes) (S82). In this process, when the updated communication data pointer value is equal to or larger than the upper limit size of the communication data storage area (see FIG. 47B), the main CPU 101 sets the updated communication data pointer value to “0”. Thus, all the command data stored in the communication data storage area are invalidated (the state is the same as the discarded state).

  In the present embodiment, the amount of data (one packet) transmitted in one transmission operation is 8 bytes. That is, in this embodiment, one command data can be transmitted by one transmission operation. In the present embodiment, since a maximum of nine command data can be stored in the communication data storage area (see FIG. 47B), the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). . Therefore, in this embodiment, the range of the communication data pointer is set to “0” to “71”, and the value of the communication data pointer after the update (when the communication data pointer is updated by +8) is “71 ( If the value exceeds the upper limit value), set the updated communication data pointer value to “0” (return the communication data storage destination address to the top address) and store the communication data. Invalidate all command data stored in the area (similar to the discarded state). If the value of the communication data pointer is set to “0”, the next time command data is stored in the communication data storage area, it is stored from the start address of the communication data storage area. The command data is overwritten with new command data. Therefore, in this embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds “71 (upper limit value)”.

  After the process of S82, the main CPU 101 ends the communication data pointer update process and also ends the communication data storage process (see FIG. 44).

  In the present embodiment, the communication data pointer update process is performed as described above. The communication data pointer update process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 47A. Among them, the update processing of the communication data pointer in S82 is executed by the “ADD” instruction and the “ICPLD” instruction (predetermined update instruction) in FIG. 47A. This “ICPLD” instruction is also dedicated to the main CPU 101. Instruction code.

  In the source program, for example, when the source code “ICPLD A, n” is executed, the content (stored data) of the A register is compared with the integer n, and the content of the A register is less than the integer n. When “1” is added to the contents of the A register and the contents of the A register are equal to or greater than the integer n, “0” is set in the A register.

  Therefore, when the communication data pointer update process of S82 is executed, the source code “ADD A, 7” is first executed on the source program of FIG. “7” is added to the value), and the addition result is stored in the A register. Next, the source code “ICPLD A, 71” is executed, and the content of the A register (the value of the communication data pointer after addition of 7) is compared with the integer “71”, and the content of the A register is less than the integer “71”. In some cases, “1” is added to the content of the A register, and when the content of the A register is equal to or greater than the integer “71”, “0” is set in the A register. That is, in the process of S82, when the value of the communication data pointer is updated by +7 and the updated communication data pointer value exceeds the upper limit “71”, the process of clearing the communication data pointer to zero (communication Processing for returning the data storage address to the start address of the communication data storage area is performed. On the other hand, if the updated communication data pointer value does not exceed the upper limit value “71”, “1” is further added to the communication data pointer by the “ICPLD” instruction, so that the communication data pointer value is totaled. +8 update.

  As described above, in this embodiment, in the communication data pointer update process, communication data is updated by one “ICPLD” instruction code (an instruction code in which a transmission buffer upper limit determination instruction and a determination branch instruction are integrated). The pointer update (addition of 1) process, the updated communication data pointer determination check process, and the communication data pointer clear process can be executed together. In this case, there is no need to provide an instruction code for executing each process separately. For example, it is possible to omit the branch instruction code for determining whether or not the value of the updated communication data pointer exceeds the upper limit “71”.

  Therefore, by using the “ICPLD” instruction code dedicated to the main CPU 101 in the communication data pointer update processing or the like, the capacity of the source program (the capacity used by the main ROM 102) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Power failure (external) processing]
Next, the process at the time of power failure (external) of the pachislot 1 performed under the control of the main CPU 101 will be described with reference to FIG. FIG. 48 is a flowchart illustrating a procedure of processing at the time of power interruption (external). 48, the power interruption (external) process is performed when the power management circuit 93 detects a decrease (power interruption) in the power supply voltage supplied to the microprocessor 91. And is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 saves data set in all registers (S91). Next, the main CPU 101 reads data set in the power interruption detection port (S92).

  Next, the main CPU 101 determines whether or not the power failure detection port is on (S93).

  In S93, when the main CPU 101 determines that the power interruption detection port is not in the on state (when S93 is NO), the main CPU 101 sets the interrupt processing permission (S94). Then, after the processing of S94, the main CPU 101 terminates the power interruption (external) processing. It should be noted that these processes performed when S93 is NO corresponds to the instantaneous power failure countermeasure process that occurs when the power management circuit 93 instantaneously detects a power interruption.

  On the other hand, when the main CPU 101 determines in S93 that the power failure detection port is in the ON state (when S93 is YES), the main CPU 101 sets the medal insertion impossible and sets the stop of the hopper device 51. (S95).

  Next, the main CPU 101 stores the value of the currently set stack pointer (SP) in the stack area of the game RAM area in the main RAM 103 (S96).

  Next, the main CPU 101 performs checksum generation processing of the main RAM 103 (S97). This process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. Further, the program used in the checksum generation process is stored in an unspecified area in the main ROM 102 (see FIG. 12B). The details of the checksum generation process will be described later with reference to FIG. 49 described later.

  Next, the main CPU 101 sets prohibition of access to the main RAM 103 (S98). Then, after the process of S98, an infinite loop process is performed until the power supply stops (until the power supply voltage reaches a voltage at which the main CPU 101 cannot operate).

[Checksum generation processing (not specified)]
Next, with reference to FIG. 49 and FIG. 50, the checksum generation processing performed in S97 during power interruption (external) processing (see FIG. 48) will be described. 49 is a flowchart showing the procedure of the checksum generation process, FIG. 50A is a diagram showing an example of a source program for executing the checksum generation process, and FIG. 50B is the checksum generation process. It is a figure which shows the mode of the update operation | movement of the stack pointer performed, and the read-out operation | movement of the data to the register from main RAM103.

  First, the main CPU 101 stores the current stack pointer (SP) value (the in-use address of the stack area of the game RAM area) in the non-standard stack area of the non-standard RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (S102). Next, the main CPU 101 sets an upper address value (F0H) of the RAM address (non-standard stack area address) in the Q register (S103). Next, the main CPU 101 sets a power interruption occurrence flag (S104).

  Next, the main CPU 101 sets the calculation start address of the sum value in the game RAM area to the stack pointer, and sets the sum calculation counter to the value obtained by dividing the number of bytes in the storage area for the sum value calculation by “2”. Set (S105). The sum calculation counter is a counter for determining the end timing of the sum value calculation, and is provided in the main RAM 103. When the sum calculation counter set in S105 becomes “0”, the game RAM area sum value calculation process of the main RAM 103 ends.

  Next, the main CPU 101 clears the HL register to 0 (sets the value “0”) (S106). By this process, the initial value “0” of the sum value is set.

  Next, the main CPU 101 executes an instruction code called “POP instruction” (specific instruction) (source code “POP DE” described in FIG. 50A) and stores it in the main RAM 103 set in the stack pointer (SP). Data (stored value) of the area of 2 bytes is read from the area address to the DE register (S107).

  When the “POP” instruction is executed, the data (memory contents) stored in the 1-byte area at the address specified by the stack pointer is loaded into the lower register of the pair register and specified by the stack pointer. The data (memory contents) stored in the 1-byte area of the address obtained by updating the updated address by 1 is loaded into the upper register of the pair register. When the “POP” instruction is executed, an address update process for 2 bytes (a process of adding “2” to the address) is performed on the address set in the stack pointer (SP).

  Therefore, in the process of S107, the data (memory contents) stored at the address specified by the stack pointer is loaded into the E register and stored at the address obtained by adding “1” to the address specified by the stack pointer. Data (memory contents) is loaded into the D register.

  FIG. 50B shows the operation of reading data into the DE register and updating the address set in the stack pointer when the “POP” instruction is executed. If the address set in the stack pointer (SP) is “F010h” at the start of the calculation of the sum value, the data (memory contents) stored in the address “F010h” is loaded into the E register, and the address Data (memory contents) stored in “F011h” is loaded into the D register. At this time, an update process of adding 2 to the address set in the stack pointer (SP) is performed, and the address set in the stack pointer (SP) is changed from “F010h” to “F012h”. Next, when the “POP” instruction is executed again, the data (memory content) stored at the address “F012h” is loaded into the E register, and the data (memory content) stored at the address “F013h” is loaded. Loaded into the D register. At this time, the address set in the stack pointer (SP) is updated, and the address set in the stack pointer (SP) is changed from “F012h” to “F014h”. Thereafter, every time the “POP” instruction is executed, the above-described operation for reading data into the DE register and the operation for updating the address set in the stack pointer are repeated.

  After the process of S107, the main CPU 101 performs a sum value calculation process (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value in the HL register as a sum value.

  Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S110).

  In S110, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S110 is NO), the main CPU 101 returns the process to the process of S107 and repeats the processes after S107. That is, the processes of S107 to S110 are repeated until the sum value calculation process of the game RAM area of the main RAM 103 is completed.

  On the other hand, when the main CPU 101 determines in S110 that the value of the sum calculation counter is “0” (in the case where S110 is YES), the main CPU 101 stores the non-standard RAM area in the main RAM 103 in the DE register. The sum calculation start address is set, and the non-standard sum count value is set in the sum calculation counter (S111). The non-standardized thumb count value is the number of bytes in the non-standardized storage area. Therefore, when the sum calculation counter set in S111 becomes “0”, the sum value calculation process for the non-standard RAM area of the main RAM 103, that is, the sum value calculation process for the entire main RAM 103 is completed.

  Next, the main CPU 101 reads data (stored value) of an area of 1 byte from the address of the non-regulated RAM area set in the DE register to the A register (S112).

  Next, the main CPU 101 performs a sum value calculation process (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value in the HL register as a sum value.

  Next, the main CPU 101 adds 1 to the address stored in the DE register, and subtracts 1 from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S115).

  In S115, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S115 is NO), the main CPU 101 returns the process to the process of S112 and repeats the processes after S112. That is, the processes of S112 to S115 are repeated until the process of adding the sum value of the unspecified RAM area of the main RAM 103 to the sum value of the game RAM area is completed.

  On the other hand, when the main CPU 101 determines in S115 that the value of the sum calculation counter is “0” (in the case where S115 is YES), the main CPU 101 uses the value stored in the HL register when the power interruption occurs. Is stored in a sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the non-standard stack area in S101 to the stack pointer (S117). After the process of S117, the main CPU 101 ends the checksum generation process, and moves the process to the process of S98 of the power interruption (external) process (see FIG. 48).

  In the present embodiment, the checksum generation process is performed as described above. The checksum generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 50A. As described above, in the present embodiment, the checksum of the main RAM 103 when a power interruption occurs is calculated by an addition formula. At this time, in the calculation of the sum value of the game RAM area, an addition process is performed in units of 2 bytes (refer to the source code “ADD HL, DE” in FIG. 50A). (See source code “ADDWB HL, A” in FIG. 50A).

[Sum check processing (not specified)]
Next, the sum check process performed in S9 during the power-on process (see FIG. 36) will be described with reference to FIGS. 51 and 52 are flowcharts showing the procedure of the sum check process, and FIG. 53 is a diagram showing an example of a source program for executing the processes of S122 to S132 during the sum check process.

  First, the main CPU 101 stores the current stack pointer (SP) value in the non-standard stack area (S121). Next, the main CPU 101 sets the address of the sum value storage area in the stack pointer, and sets a value obtained by dividing the number of bytes in the sum value calculation target storage area by “2” in the sum calculation counter (S122). The sum calculation counter set here is a counter for determining the end timing of the sum value calculation (sum value subtraction process), and is provided in the main RAM 103. Next, the main CPU 101 obtains a sum value (check sum) from the sum value storage area (S123). By this process, the checksum (initial value before subtraction) generated when the power interruption occurs is stored in the HL register.

  Next, the main CPU 101 executes a “POP” instruction, and reads data (stored value) of 2 bytes from the storage area address of the main RAM 103 set in the stack pointer (SP) to the DE register (S124). . At this time, by executing the “POP” instruction, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the E register, and the address specified by the stack pointer is set. Data (memory contents) stored in the 1-byte area of the updated address is loaded into the D register (see FIG. 50B). When the “POP” instruction is executed, an address update process for two bytes (a process for adding two addresses) is performed on the address set in the stack pointer (SP).

  Next, the main CPU 101 performs a sum value calculation (subtraction) process (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (the initial value of the sum value or the sum value after the previous subtraction process). The value is stored in the HL register as a sum value.

  Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S127).

  In S127, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S127 is NO), the main CPU 101 returns the process to the process of S124 and repeats the processes after S124. That is, the processes of S124 to S127 are repeated until the sum value subtraction process is completed over the entire game RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S127 that the value of the sum calculation counter is “0” (in the case where S127 is YES), the main CPU 101 stores the non-standard RAM area in the main RAM 103 in the DE register. The sum calculation start address is set, and the non-standard sum count value is set in the sum calculation counter (S128). The non-standard thumb count value is the number of bytes in the non-standard RAM area.

  Next, the main CPU 101 reads data (stored value) of an area of 1 byte from the address of the non-regulated RAM area set in the DE register to the A register (S129).

  Next, the main CPU 101 performs a sum value calculation (subtraction) process (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value in the HL register as a sum value.

  Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S132).

  In S132, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S132 is NO), the main CPU 101 returns the process to the process of S129 and repeats the processes after S129. That is, the processes of S129 to S132 are repeated until the subtraction process of the sum value is completed over the entire non-standard RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S132 that the value of the sum calculation counter is “0” (when S132 is YES), the main CPU 101 sets “sum abnormality” in the determination result of the sum check process. (S133). Next, the main CPU 101 determines whether or not the calculated sum value is “0” (S134).

  In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether or not the sum value is “0”. In the present embodiment, the sum value is “0” when the value of the sum calculation counter set in S128 becomes “0”, that is, when the sum value subtraction process is completed over the entire area of the main RAM 103. Is set to “1” in the zero flag of the flag register F, and “0” is set in the zero flag of the flag register F when the sum value is not “0”. Therefore, if “1 (ON state)” is set in the zero flag of the flag register F at the time of the processing of S134, the main CPU 101 determines that the sum value is “0”.

  In S134, when the main CPU 101 determines that the calculated sum value is not “0” (when S134 is NO), the main CPU 101 performs the process of S139 described later. On the other hand, when the main CPU 101 determines in S134 that the calculated sum value is “0” (when S134 is YES), the main CPU 101 sets “power failure abnormality” as the determination result (S135). ).

  Next, the main CPU 101 acquires a power interruption occurrence flag (S136). Next, the main CPU 101 determines whether or not the power interruption occurrence flag is in a state without power interruption (off state) (S137).

  In S137, when the main CPU 101 determines that the power interruption occurrence flag is in a state where there is no power interruption (when S137 is YES), the main CPU 101 performs a process of S139 described later. On the other hand, when the main CPU 101 determines in S137 that the power interruption occurrence flag is not in the state without power interruption (when S137 is NO), the main CPU 101 sets “normal” as the determination result (S138).

  After S138, if S134 is NO or S137 is YES, the main CPU 101 stores the determination result in the sum check determination result and clears (turns off) the power interruption occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the non-standard stack area in S121 to the stack pointer (S140). After the process of S140, the main CPU 101 ends the sum check process, and moves the process to the process of S10 of the power-on process (see FIG. 36).

  In the present embodiment, the sum check process is performed as described above. And the process of S122-S132 in the sum check process mentioned above is performed when the main CPU101 executes each source code prescribed | regulated by the source program of FIG. 53 sequentially.

  As described above, in the thumbchock determination process of the main RAM 103 in the present embodiment, first, the checksum value generated when the power interruption occurs is sequentially subtracted by the data stored in the main RAM 103 when the power is restored. At this time, subtraction processing (see source code “SUB HL, DE” in FIG. 53) is performed in the gaming RAM area (see source code “SUB HL, DE” in FIG. 53), and subtraction processing (in FIG. 53) is performed in the unspecified RAM area. Source code “SUBWB HL, A”). Next, whether or not an abnormality has occurred is determined based on whether or not the final subtraction result is “0” (whether or not the zero flag is on). When the subtraction result is “0” (when the zero flag is in the on state), it is determined as normal, and when the subtraction result is not “0” (when the zero flag is in the off state), it is determined as abnormal. Determined.

  In other words, in the present embodiment, the checksum generation process when power interruption occurs is performed by the addition method, and the checksum determination process when power is restored is performed by the subtraction method. Then, normal / abnormal determination is performed based on the final checksum subtraction result. When such checksum generation processing and determination processing are performed, it is not necessary to generate the checksum again when the power is restored and to check the checksum against the checksum when the power interruption occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, in the main ROM 102, a free space corresponding to the omission of the collation instruction code can be secured, and the increased free space can be used to improve the game performance. Note that the “POP” instruction executed in the checksum generation process when the power interruption occurs and the checksum determination process when the power is restored is a stack pointer (SP) operation-dedicated instruction, and the source code “ In addition to “POP DE”, source codes “POP HL”, “POP AF”, and the like exist.

[Main processing of pachislot by control of main CPU]
Next, with reference to FIG. 54, the main process (main operation process) of the pachi-slot 1 executed under the control of the main CPU 101 will be described. FIG. 54 is a flowchart (hereinafter referred to as a main flow) showing the procedure of the main process.

  First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address at the end of one game in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the start of initialization, and starts from the start address in the game RAM area. Erase (clear) information up to the last address. The storage area in this range is a storage area that needs to be erased for each unit game (game) such as an internal winning combination storage area or a display combination storage area.

  Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this processing, the main CPU 101 performs input check processing such as a medal sensor (not shown) and the start switch 79. The details of the medal acceptance / start check process will be described later with reference to FIG. 55 described later.

  Next, the main CPU 101 performs random number acquisition processing (S203). In this processing, the main CPU 101 uses a random number value for internal winning combination lottery (0 to 65535: the value of the random number register 0 of the random number circuit 110 to be a hard latch random number) or a random number value for effects used in various lotteries related to ART ( 0 to 65535: each value of the random number registers 1 to 3 of the random number circuit 110 serving as a soft latch random number, 0 to 255: each value of the random number registers 4 to 7 of the random number circuit 110 serving as a soft latch random number) The various random numbers extracted are stored in a random value storage area (not shown) provided in the main RAM 103. The details of the random number acquisition process will be described later with reference to FIG. 63 described later.

  Next, the main CPU 101 performs an internal lottery process (S204). In this process, the main CPU 101 performs an internal winning combination determination process by lottery based on the random number value (hard latch random number) extracted in S203. Details of the internal lottery process will be described later with reference to FIG. 64 described later.

  Next, the main CPU 101 performs a symbol setting process (S205). In this process, the main CPU 101, for example, generates an internal winning combination from the hit request flag status (flag status information), expands the hit request flag data, and stores the hit request flag data in the hit request flag storage area. Etc. That is, the main CPU 101 performs a process of setting a combination of symbols allowed to be stopped and displayed on the active line in the current unit game among a plurality of predetermined symbol combinations (see FIG. 18). .

  Although detailed control is omitted, if the bonus combination (BB) has already been stored in the carryover combination storage area (see FIG. 23) in the symbol setting process of S205, the main CPU 101 If the combination of symbols allowed to be stopped and displayed on the active line is set in this unit game including BB) and the bonus combination (BB) is determined as the internal winning combination, the bonus A process of storing the combination (BB) as a carryover combination in the carryover combination storage area (see FIG. 23) is performed. In this case, processing for setting the RT4 state (RT4) as the RT state is performed.

  Next, the main CPU 101 performs a start command generation / storage process (S206). In this process, the main CPU 101 generates start command data to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. Note that the start command includes parameters that specify an internal winning combination.

  Next, the main CPU 101 performs a second interface board control process (S207). Note that the second interface board control process is executed in a non-standard work area of the main RAM 103. Details of the second interface board control process will be described later with reference to FIG. 66 described later.

  Next, the main CPU 101 performs state-specific control processing (S208). In this process, the main CPU 101 mainly performs a game start process (start process) according to the state in which the game is performed (for example, each state shown in FIG. 14). The details of the state-specific control processing will be described later with reference to FIG. 68 described later.

  Next, the main CPU 101 performs reel stop initial setting processing (S209). In this process, the main CPU 101 refers to a reel stop initial setting table (not shown), and acquires a drawing priority table selection table number, a drawing priority table number, and a stop table number based on the internal winning combination and the gaming state. And a process of storing “3” in the stop button non-operation counter.

  Next, the main CPU 101 performs reel rotation start processing (S210). In this process, the main CPU 101 requests the start of rotation of all reels. When rotation of all reels is requested, three stepping motors (not shown) are driven by an interrupt process (see FIG. 100, which will be described later) executed at a constant cycle (1.1172 msec). Controlled, rotation of the left reel 3L, middle reel 3C and right reel 3R is started. Next, each reel is controlled to be accelerated until its rotational speed reaches a constant speed, and then controlled so as to maintain the constant speed.

  Next, the main CPU 101 performs reel rotation start command generation / storage processing (S211). In this process, the main CPU 101 generates reel rotation start command data to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. The reel rotation start command includes a parameter indicating that the reel rotation start operation has started.

  Next, the main CPU 101 performs a pull-in priority storage process (S212). In this process, the main CPU 101 acquires the pull-in priority data and stores it in the pull-in priority data storage area. The details of the pull-in priority storage process will be described later with reference to FIG. 73 described later.

  Next, the main CPU 101 performs a reel stop control process (S213). In this process, the main CPU 101 performs stop control of rotation of the corresponding reel based on the timing when the left stop button 17L, the middle stop button 17C, and the right stop button 17R are respectively pressed and the internal winning combination. The details of the reel stop control process will be described later with reference to FIG. 81 described later.

  Next, the main CPU 101 performs a winning search process (S214). In this process, the main CPU 101 stores the data in the symbol code storage area (see FIG. 27) in the winning action flag storage area (see FIG. 22). In this process, the main CPU 101 displays the display combination on the active line (that is, which of the plurality of predetermined symbol combinations shown in FIG. 18 is displayed on the active line). ) Determine whether or not, and set the number of medals to be paid out based on the determination result. Details of the winning search process will be described later with reference to FIG. 88 described later.

  Next, the main CPU 101 performs an illegal hit check process (S215). In this process, the main CPU 101 combines a winning request flag (internal winning combination) and a winning action flag (display combination), and determines the presence or absence of an illegal hit error based on the combined result. Details of the illegal hit check process will be described later with reference to FIG. 90 described later.

  Next, the main CPU 101 performs a winning check / medal payout process (S216). In this process, the main CPU 101 performs a winning operation command generation process. Further, in this process, the main CPU 101 drives the hopper device 51 and updates the number of credits based on the number of display combination payouts determined in S214, and performs a medal payout process. Details of the winning check / medal payout process will be described later with reference to FIG. 92 described later.

  Next, the main CPU 101 performs a bonus check process (S217). In this process, the main CPU 101 controls the operation and termination of the bonus state. Details of the bonus check process will be described later with reference to FIG. 96 described later.

  Next, the main CPU 101 performs RT check processing (S218). In this process, the main CPU 101 performs RT state transition control based on the symbol combination that is stopped and displayed on the active line. Details of the RT check process will be described later with reference to FIG. 97 described later.

  Next, the main CPU 101 performs control processing according to the state at the end of the game (S219). In this process, the main CPU 101 mainly performs a game end process (that is, a process after all stops) according to the state in which the game is performed (for example, each state shown in FIG. 14). Note that the details of the game end state control process will be described later with reference to FIG. 98 described later. After the process of S219 (after the end of one game), the main CPU 101 returns the process to the process of S201.

[Medal reception / start check processing]
Next, with reference to FIGS. 55 and 56, the medal acceptance / start check process performed in S202 in the main flow (see FIG. 54) will be described. FIG. 55 is a flowchart showing the procedure of medal acceptance / start check processing, and FIG. 56 is a diagram showing an example of a source program for executing the processing of S231 to S233 during medal acceptance / start check processing. is there.

  First, the main CPU 101 determines whether or not the value of the automatic insertion medal counter is “0” (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is “1” or more, the main CPU 101 determines that there is an automatic insertion request. The automatic insertion medal counter is data for identifying whether or not a display combination relating to replay (replay) has been established in the previous unit game. When the display combination related to the re-game is established, the medals for the number of coins inserted in the previous unit game are automatically inserted into the automatic insertion medal counter.

  In S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is “0” (when S221 is YES), the main CPU 101 performs the process of S225 described later.

  On the other hand, when the main CPU 101 determines in S221 that the value of the automatic insertion medal counter is not “0” (when S221 is NO), the main CPU 101 performs medal insertion processing (S222). In this process, the main CPU 101 performs a medal insertion command generation / storage process, a medal insertion number LED lighting control process, and the like. The details of the medal insertion process will be described later with reference to FIG.

  Next, the main CPU 101 subtracts 1 from the value of the automatic insertion medal counter (S223). Next, it is determined whether or not the value of the automatically inserted medal counter after subtraction is “0” (S224).

  In S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is not “0” (when S224 is NO), the main CPU 101 returns the process to S222 and repeats the processes after S222.

  On the other hand, when the main CPU 101 determines in S224 that the value of the automatic insertion medal counter is “0” (when S224 is YES), or when S221 is YES, the main CPU 101 stores the medal auxiliary storage. A warehouse switch check process is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals based on the on / off state of the medal auxiliary storage switch 75.

  Next, the main CPU 101 performs a medal insertion state check process (S226). Next, the main CPU 101 determines whether or not a medal can be inserted based on the result of the medal insertion state check process (S227).

  When the main CPU 101 determines in S227 that the medal cannot be inserted (when S227 is NO), the main CPU 101 performs a process of S231 described later.

  On the other hand, when the main CPU 101 determines in S227 that the medal can be inserted (when S227 is YES), the main CPU 101 performs a medal insertion check process (S228). In this process, for example, based on the medal sensor input state, the main CPU 101 determines whether or not a medal has passed normally, and credits the medal when a medal is inserted beyond a prescribed number. Perform processing. Details of the medal insertion check process will be described later with reference to FIG. 59 described later.

  Next, based on the result of the medal insertion check process, the main CPU 101 determines whether or not a medal can be inserted or credited (S229).

  When the main CPU 101 determines in S229 that the medal can be inserted or credited (YES in S229), the main CPU 101 performs a process of S231 described later. On the other hand, when the main CPU 101 determines in S229 that the medal cannot be inserted or credited (NO in S229), the main CPU 101 performs a medal acceptance prohibition process (S230). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medal is discharged from the medal payout opening 24.

  After S230, when S227 is NO or when S229 is YES, the main CPU 101 determines whether or not the current number of inserted medals is the game start possible number (S231). In this embodiment, the number of games that can be started is three (see FIG. 18).

  In S231, when the main CPU 101 determines that the current number of inserted medals is the game start number (when S231 is YES), the main CPU 101 performs the process of S234 described later. On the other hand, when the main CPU 101 determines in S231 that the current number of inserted medals is not the game start possible number (when S231 is NO), the main CPU 101 determines whether or not there are medals inserted (S232). ).

  When the main CPU 101 determines in S232 that a medal has been inserted (when S232 is YES), the main CPU101 returns the process to S226 and repeats the processes after S226. On the other hand, when the main CPU 101 determines in S232 that no medal has been inserted (NO in S232), the main CPU 101 performs the setting change confirmation process described in FIG. 40 (S233). In this processing, the main CPU 101 performs processing for generating and storing a setting change command at the start of setting confirmation.

  After the processing of S233 or when S231 is YES, the main CPU 51 determines whether or not the start switch 79 is on (S234).

  In S234, when the main CPU 101 determines that the start switch 79 is not in the ON state (when S234 is NO), the main CPU 101 returns the process to S226 and repeats the processes after S226.

  On the other hand, when the main CPU 101 determines in S234 that the start switch 79 is on (when S234 is YES), the main CPU 101 performs a medal acceptance prohibition process (S235). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medal is discharged from the medal payout opening 24. After the process of S235, the main CPU 101 ends the medal acceptance / start check process, and moves the process to S203 of the main flow (see FIG. 54).

  In the present embodiment, the medal acceptance / start check process is performed as described above. The processing in S231 to S233 during the above-described medal acceptance / start check processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. Among them, in the process of S233, the process is jumped to the address “SB_WVSC_00” of the execution program of the setting change confirmation process by the “CALLF” instruction which is the instruction code dedicated to the main CPU 101, and the setting change confirmation explained in FIGS. Process.

  Then, the processing of S233 during the above-described medal acceptance / start check processing, that is, the setting change confirmation processing is executed regardless of the gaming state. Therefore, in this embodiment, regardless of the gaming state, that is, even if the gaming state is a bonus state (special prize operating state), the set value and the hall menu (various history data (error, power interruption history, etc.)) are displayed. It is possible to confirm, and it is possible to suppress illegal acts such as goto.

[Medal insertion processing]
Next, with reference to FIGS. 57 and 58, the medal insertion process performed in S222 in the medal acceptance / start check process (see FIG. 55) will be described. FIG. 57 is a flowchart showing a procedure of medal insertion processing, and FIG. 58 is a diagram showing an example of a source program for executing medal insertion processing.

  First, the main CPU 101 adds “1” to the value of the medal counter (S241). The medal counter is a counter for counting the number of inserted medals, and is provided in the main RAM 103.

  Next, the main CPU 101 performs medal insertion command generation / storage processing (S242). In this process, the main CPU 101 generates medal insertion command data to be transmitted to the sub-control circuit 200 and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 every time a medal is inserted. The medal insertion command includes a parameter for specifying the number of inserted coins.

  Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 7) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the medal insertion number based on the medal insertion number (medal counter value) (S244). In this process, for example, when the number of inserted medals is 1, LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated. For example, the number of inserted medals is 3. LED lighting data for lighting all the first to third LEDs for displaying the number of inserted medals is calculated. The method for calculating the LED lighting data will be described in detail later.

  Next, the main CPU 101 uses the calculated LED lighting data to light up the corresponding medal insertion number display LED (S245). After the process of S245, the main CPU 101 ends the medal insertion process, and moves the process to S223 of the medal acceptance / start check process (see FIG. 55).

  In the present embodiment, the medal insertion process is performed as described above. The medal insertion process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. In the process of S244, the LED lighting data for displaying the number of inserted medals is generated not by the loop process referring to the table but by the calculation process. This arithmetic processing is performed by the main CPU 101 sequentially executing source codes “LD A, L” to “OR L” in the source program shown in FIG.

  In this calculation process, first, by executing the source code “LD A, L”, data of the number of inserted medals stored in the L register is stored in the A register. For example, when the number of inserted medals is 3, “00000011B” (decimal number “3”) is stored in the A register. In the present embodiment, 1-byte data is described as “*******”, but the last character “B” is “0” or “1” indicated before the character “B”. "Means bit data.

  Next, by executing the source code “ADD A, A”, the data stored in the A register is added to the data stored in the A register, and the addition result is stored in the A register. For example, if the data stored in the A register before the execution of the “ADD” instruction is “00000011B” (when the number of inserted medals is three), the addition result is obtained by the “ADD” instruction. “00000110B” is stored in the A register.

  Next, by executing the source code “DEC A”, 1 is subtracted from the data stored in the A register, and the subtraction result is stored in the A register. For example, when the data stored in the A register before the execution of the “DEC” instruction is “00000110B”, “00000101B” as a subtraction result is stored in the A register by the “DEC” instruction. .

  Next, by executing the source code “OR L”, a logical sum operation is performed on the data stored in the L register (the number of inserted medals) and the data stored in the A register, and the operation result is stored in the A register. Stored. For example, when the data stored in the A register before the execution of the “OR” instruction is “00000101B” and the data stored in the L register is “00000011B” (the number of inserted medals is 3) In this case, “000011B”, which is the result of the logical OR operation of both data, is stored in the A register by this “OR” instruction. The data stored in the A register by the execution of the “OR” instruction becomes LED lighting data for displaying the number of medal insertions (data indicating the lighting state of the medal insertion LED).

  For example, when the number of inserted medals is 3, as described above, the final calculation result “00000111B” is displayed for displaying the number of inserted medals by the calculation processing of the LED lighting data for displaying the number of inserted medals in S244. LED lighting data. In this embodiment, “0” of bit 0 of the finally calculated LED lighting data is “ON / OFF” of the output port to the first medal insertion number display LED (first LED). "1/0" of bit 1 corresponds to the "on / off" state of the output port to the LED for displaying the second medal insertion number (second LED), and "1" of bit 2 "/ 0" corresponds to the "ON / OFF" state of the output port to the third medal insertion number display LED (third LED). Therefore, when the number of inserted medals is 3, as described above, “00000111B” is generated as the LED lighting data, so that all output ports of the first to third LEDs for displaying the number of inserted medals are displayed. It is set to the on state, and all the first to third LEDs for displaying the number of inserted medals are turned on.

  When the LED lighting data for displaying the number of inserted medals is generated by the arithmetic processing as described above, the table data to be referred to when generating the LED lighting data for displaying the number of inserted medals is unnecessary, so the table area of the main ROM 102 Free space can be increased, and an increase in program capacity can be minimized. That is, in the above-described medal insertion process of the present embodiment, the medal insertion LED display process can be made more efficient, the free capacity of the main ROM 102 is secured (increased), and the increased free area is utilized, It becomes possible to improve game nature.

[Medal insertion check process]
Next, with reference to FIGS. 59 and 60, the medal insertion check process performed in S228 in the medal acceptance / start check process (see FIG. 55) will be described. 59 is a flowchart showing the procedure of the medal insertion check process, and FIG. 60 is a diagram showing an example of a source program for executing the processes of S255 to S258 during the medal insertion check process.

  First, the main CPU 101 determines whether or not replaying is in progress (S251).

  When the main CPU 101 determines in S251 that the game is being replayed (if S251 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check process (see FIG. 55). To S229.

  On the other hand, when the main CPU 101 determines in S251 that the game is not being replayed (when S251 is NO), the main CPU 101 permits medal acceptance (S252). In this processing, the solenoid of the selector 66 (see FIG. 4) is driven, and medals inserted from the medal insertion slot 24 are accepted. The received medals are counted and guided to the hopper device 51.

  Next, the main CPU 101 performs a bet button check process (S253). In this process, the main CPU 101 determines whether or not the bet button (MAX bet button 15a or 1 bet button 15b) has been operated based on the on / off state of the BET switch 77. Next, the main CPU 101 determines whether or not the betting operation is completed based on the result of the bet button check process in S253 (S254).

  When the main CPU 101 determines in S254 that the betting operation has been completed (when S254 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check process (see FIG. 55). To S229.

  On the other hand, when the main CPU 101 determines in S254 that the betting operation has not been completed (in the case where S254 is NO), the main CPU 101 determines the medal sensor input state (game medium acceptance state) during the current process, The medal sensor input state at the time of the previous process is acquired (S255). The medal sensor input state is information indicating the passage status of medals received in the medal insertion slot 24 in the selector 66, and the detection results of each medal sensor (not shown) provided at the entrance and the exit of the selector 66. Is generated by

  In this embodiment, the medal sensor input state is represented by 1-byte (8-bit) data, and the first medal sensor (not shown) on the upstream side provided side by side in the medal passage direction at the exit of the selector 66. The detection result corresponds to the information of bit 0 (“0” or “1”), and the detection result of the second medal sensor (not shown) on the downstream side corresponds to the information of bit 1 (“0” or “1”). To do. When the passage of the medal is detected by the first medal sensor, “1” is set to the bit 0, and when the passage of the medal is detected by the second medal sensor, “1” is set to the bit 1. Is done. Therefore, the medal sensor input state “00000000B” indicates the state before or after passing the medal (at the time of passing), and the medal sensor input state “00000001B” indicates the state when the medal passage starts, and the medal sensor input state “ “00000011B” indicates a state in which a medal is passing, and a medal sensor input state “00000010B” indicates a state immediately before completion of medal passing.

  Next, the main CPU 101 determines whether or not the medal sensor input state during the current process has changed from the medal sensor input state during the previous process (S256).

  In S256, when the main CPU 101 determines that the medal sensor input state during the current process has not changed from the medal sensor input state during the previous process (when S256 is NO), the main CPU 101 proceeds to S261 described below. Process.

  On the other hand, when the main CPU 101 determines in S256 that the medal sensor input state during the current process has changed from the medal sensor input state during the previous process (S256 is YES), the main CPU 101 Based on the medal sensor input state, a normal value (normal change value) of the medal sensor input state obtained in the current process is generated by arithmetic processing (S257).

  In this process, when the medal sensor input state at the time of the previous process is “00000000B” (when both the first and second medal sensors are not detected), the normal change value of the medal sensor input state is used. When “00000001B” (when the first medal sensor is medal detection and the second medal sensor is not medal detection) is generated, and the medal sensor input state at the previous processing is “00000001B”, the medal sensor As a normal change value of the input state, “00000011B” (when both the first and second medal sensors are medal detection) is generated. In this process, if the medal sensor input state at the previous process is “00000011B”, the normal change value of the medal sensor input state is “00000010B” (the first medal sensor is not detected, the second When the medal sensor is medal detection) and the medal sensor input state at the time of the previous process is “00000010B”, the normal change value of the medal sensor input state is “00000000B” (first and second medals). When both medals have not been detected yet). The method for generating (calculating) the normal change value of the medal sensor input state will be described in detail later.

  Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current process is the same as the normal change value generated in S257 (S258). In this determination process, it is determined whether or not a medal retrograde error has occurred, and if the determination condition in S258 is not satisfied, the main CPU 101 determines that a medal retrograde error has occurred.

  In S258, when the main CPU 101 determines that the medal sensor input state at the time of the current process is not the same as the normal change value generated in S257 (when S258 is NO), the main CPU 101 performs the process of S262 described later. Do.

  On the other hand, when the main CPU 101 determines in S258 that the medal sensor input state at the current process is the same as the normal change value generated at S257 (when S258 is YES), the main CPU 101 It is determined whether or not the medal sensor input state is a medal passing state (“00000000B”) (S259). In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is a state when the medal passes (when S259 is YES), the main CPU 101 performs the process of S263 described later.

  In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is not a medal passage state (when S259 is NO), the main CPU 101 sets a medal passage check timer (S260). The time set in the medal passage check timer in this process can be set to any time as long as it is possible to determine whether or not the medal has passed the selector 66. Further, the timer value set in this process may be changed according to the medal sensor input state at the time of the current process, for example.

  After the processing of S260 or when S256 is NO, the main CPU 101 determines whether the medal sensor input state at the time of the current processing is a state in which a medal is passing (“00000011B”) and the medal passing check timer is stopped. Is determined (S261). In this determination process, it is determined whether or not a medal passage error (inserted medal passage time error) has occurred, and when the determination condition of S261 is satisfied, the main CPU 101 determines that a medal passage error has occurred.

  In S261, when the main CPU 101 determines that the determination condition of S261 is not satisfied (when S261 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

  On the other hand, in S261, when the main CPU 101 determines that the determination condition of S261 is satisfied (when S261 is YES), or when S258 is NO, that is, a medal passing error or a medal retrograde error has occurred. When it is determined that the main CPU 101 performs error processing (S262). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation / storage process. Details of error processing will be described later with reference to FIG. After the process of S262, the main CPU 101 returns the process to the process of S253, and repeats the processes after S253.

  Here, returning to the process of S259 again, if S259 is YES, the main CPU 101 determines whether or not a prescribed number (three in this embodiment) of medals has been inserted (S263). .

  When the main CPU 101 determines in S263 that the specified number of medals has not been inserted (when S263 is NO), the main CPU 101 performs the medal insertion process described with reference to FIG. 57 (S264). After the process of S264, the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

  On the other hand, when the main CPU 101 determines in S263 that the specified number of medals has been inserted (when S263 is YES), the main CPU 101 adds “1” to the value of the credit counter (S265). ). Next, the main CPU 101 performs medal insertion command generation storage processing (S266). In this process, the main CPU 101 generates medal insertion command data to be transmitted to the sub-control circuit 200 and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the credit number of medals is the upper limit value (50 in the present embodiment) based on the value of the credit counter (S267).

  When the main CPU 101 determines that the medal credit number is not the upper limit value in S267 (when S267 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253. On the other hand, when the main CPU 101 determines in S267 that the credit number of medals is the upper limit value (when S267 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check. The process proceeds to S229 of the process (see FIG. 55).

  In the present embodiment, the medal insertion check process is performed as described above. And the process of S255-S258 in the medal insertion check process mentioned above is performed when the main CPU101 executes each source code prescribed | regulated by the source program of FIG. 60 sequentially. Among them, the generation process of the normal change value of the medal sensor input state in S257 is performed not by the process of obtaining with reference to the table but by the calculation process. Specifically, the normal change value generation process is performed by the main CPU 101 executing the source code “RLA” and “AND cBX_MDINSW” in the source program shown in FIG. 60 in this order.

  The “RLA” instruction is an instruction code that shifts 1-byte data stored in the A register to the left (in the direction from bit 0 to bit 7) once (one bit). In the example shown in FIG. 60, 1-byte data indicating the previous medal sensor input state stored in the A register by the source code “LD A, B” executed before the “RLA” instruction is the “RLA” instruction. Shifts to the left once. At this time, the bit data newly stored in bit 0 is determined based on the execution result of the source code “CP cBX_MDISW2” executed before the “RLA” instruction.

  The “CP” instruction is an instruction code for executing a comparison operation. “CBX_MDISW2” is 1-byte data, and is “00000010B” in the present embodiment. When the source code “CP cBX_MDISW2” is executed, 1-byte data indicating the previous medal sensor input state stored in the A register is compared with “cBX_MDISW2 (00000010B)”.

  If the result of executing the source code “CP cBX_MDISW2” indicates that the 1-byte data indicating the previous medal sensor input state is less than “cBX_MDISW2 (00000010B)”, the carry flag of the flag register F is obtained. “1” is set in (see FIG. 11), and the carry flag “1” of the flag register F is stored in bit 0 of the A register when the “RLA” instruction is executed. On the other hand, as a result of executing the source code “CP cBX_MDISW2”, if the result that the 1-byte data indicating the previous medal sensor input state is “cBX_MDISW2 (00000010B)” or more is obtained, the carry flag of the flag register F “0” is set in (see FIG. 11), and the carry flag “0” of the flag register F is stored in bit 0 of the A register when the “RLA” instruction is executed.

  Therefore, for example, if the 1-byte data indicating the previous medal sensor input state is “00000000B (before or after passing medal) (<cBX_MDISW2”), the “RLA” command If “00000001B” is generated by execution, and the 1-byte data indicating the previous medal sensor input state is “00000001B (the state at the start of medal passage)” (<cBX_MDISW2 ”), the“ RLA ”instruction is executed. As a result, “00000011B” is generated. On the other hand, for example, if 1-byte data indicating the previous medal sensor input state is “00000011B (medal passing state)” (> “cBX_MDISW2”), “00000110B” is generated by executing the “RLA” instruction. If the 1-byte data indicating the previous medal sensor input state is “00000010B (state immediately before completion of medal passage)” (= “cBX_MDISW2”), “00000100B” is generated by executing the “RLA” instruction. The

  Next, when the source code “AND cBX_MDINSW” is executed, 1-byte data (stored data in the A register) generated by executing the “RLA” instruction is logically ANDed with 1-byte data “cBX_MDINSW”, and the medal sensor A normal change value of the input state is calculated. The 1-byte data “cBX_MDISW” is “00000011B” in the present embodiment. Therefore, when the source code “AND cBX_MDINSW” is executed, only the data of bit 0 and bit 1 in the data stored in the A register is masked, and the other bit data becomes “0”.

  As a result, for example, if 1-byte data indicating the previous medal sensor input state is “00000000B (the state before passing the medal)”, the normal change value of the medal sensor input state is “00000001B (the state when the medal passage is started). ) ”Is generated, and if 1-byte data indicating the previous medal sensor input state is“ 00000001B (the state at the start of medal passage) ”, the normal change value of the medal sensor input state is“ 00000011B (the medal passing state). Status) "is generated. On the other hand, for example, if 1-byte data indicating the previous medal sensor input state is “00000011B (medal passing state)”, the normal change value of the medal sensor input state is “00000010B (state immediately before completion of medal passing)”. ”Is generated, and if the 1-byte data indicating the previous medal sensor input state is“ 00000010B ”(a state immediately before completion of medal passage), the normal change value of the medal sensor input state is“ 00000000B (after the medal passage (passing) State) ”is generated.

  As described above, by changing the detection process of the change state of the medal sensor input state from the table reference process to the calculation process, the free space in the table storage area of the main ROM 102 can be increased, and the program capacity can be increased. Can be minimized. Therefore, by adopting the above-described method, it is possible to improve the efficiency of the medal insertion sensor state detection process, and it is possible to improve the gameability by utilizing the increased free space in the main ROM 102.

[Error handling]
Next, with reference to FIGS. 61 and 62, for example, the error process performed in S262 during the medal insertion check process (see FIG. 59) will be described. FIG. 61 is a flowchart showing a procedure of error processing, and FIG. 62 is a diagram showing an example of the configuration of an error table that is actually referred to on the error processing source program.

  In the error table shown in FIG. 62, for each 1-byte data (eg, 1-byte data stored in the address “dERR_HE” in FIG. 62) indicating the on / off state of the port indicating the type of error factor, Error display data (for example, 1-byte data stored in addresses “dERR_HE + 1” and “dERR_HE + 2” in FIG. 62) is defined. This error display data is output to a 2-digit 7-segment LED (used for both the payout number display and the error display) included in the information display 6.

  First, the main CPU 101 performs a medal solenoid off process (S271). Specifically, the main CPU 101 stops driving the solenoid of the selector 66 (see FIG. 7). Next, the main CPU 101 performs evacuation processing of medal payout number display data (S272).

  Next, the main CPU 101 performs error table setting processing (S273). By this processing, the head address of the error table shown in FIG. 62 is set on the source program.

  Next, the main CPU 101 acquires an error factor (S274). Note that the error factor acquired in this process varies depending on the process from which the currently processed error process is read. As the error factors to be targeted in this embodiment, as shown in FIG. 62, “hopper empty error”, “hopper jam error”, “inserted medal passage count error”, “inserted medal passage check error”, “ The “inserted medal passage check error”, “inserted medal passage time error”, “inserted medal retrograde error”, “inserted medal auxiliary storage full error”, and “illegal hit error” are defined. For example, if an error process is read after the process of S258 during the medal insertion check process, the “inserted medal retrograde error (Cr)” in FIG. 62 is acquired as an error factor in this process. Further, for example, when the error process is read after the process of S261 during the medal insertion check process, in this process, “inserted medal passage time error (CE)” in FIG. 62 is acquired as an error factor. .

  Next, the main CPU 101 acquires error display data from the error table and error factors (S275). For example, when the error factor is “inserted medal retrograde error (Cr)”, the error display data shown in FIG. 62 is output as error display data to be output to the high-order 7-segment LED of the 2-digit 7-segment LED. 1-byte data “01001110B” stored at address “dERR_CR + 1” in the table is acquired, and 1-byte data “00001001B” stored at address “dERR_CR + 2” is output as error display data to the 7-segment LED of the lower digit. Is acquired. In this case, two characters “Cr” are displayed as error information on the two-digit 7-segment LED.

  Next, the main CPU 101 performs error command (occurrence) generation and storage processing (S276). In this process, the main CPU 101 generates error command data to be transmitted to the sub control circuit 200 when an error occurs, and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. . The error command at the time of occurrence of an error stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. The error command when an error occurs includes a parameter indicating the error occurrence.

  Next, the main CPU 101 performs standby processing for one interrupt time (1.1172 ms) (S277). Next, the main CPU 101 determines whether or not the error has been canceled (S278).

  When the main CPU 101 determines in S278 that the error has not been canceled (when S278 is NO), the main CPU 101 returns the process to the process of S277 and repeats the processes after S277.

  On the other hand, when the main CPU 101 determines in S278 that the error has been canceled (in the case where S278 is YES), the main CPU 101 performs error factor clear processing (S279). This process is performed in a non-standard work area of the main RAM 103. Next, the main CPU 101 performs a return process of the payout number display data of medals saved in S272 (S280).

  Next, the main CPU 101 performs error command (cancellation) generation and storage processing (S281). In this process, the main CPU 101 generates error command data to be transmitted to the sub-control circuit 200 at the time of error cancellation, and stores the command data in a communication data storage area (see FIG. 47B) provided in the main RAM 103. . The error command at the time of error cancellation stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. The error command at the time of error cancellation includes a parameter indicating error cancellation. After the process of S281, the main CPU 101 ends the error process, and moves the process to S253 in the medal insertion check process (see FIG. 59), for example. In the error cancellation, the error factor that has occurred is canceled, and the error state is canceled by pressing the reset switch 76.

[Random number acquisition processing]
Next, with reference to FIG. 63, the random number acquisition process performed in S203 in the main flow (see FIG. 54) will be described. FIG. 63 is a flowchart showing the procedure of random number acquisition processing.

  First, the main CPU 101 acquires the hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as the random number value for the internal winning combination lottery in the random value storage area (invalid) in the main RAM 103. (S291).

  Next, the main CPU 101 determines the soft latch random numbers in the random number registers 1 to 7 of the random number circuit (in this embodiment, 0 to 65535: random number value for effect used in lottery processing for executing the lock effect during MB, 0 to 255: ART related) The setting process of the soft latch random number acquisition register for generating the rendering random number value used in the lottery process is performed (S292). Next, the main CPU 101 sets the number of acquired soft latch random numbers (for example, 7) (S293).

  Next, the main CPU 101 obtains the acquired number of soft latch random numbers at once and stores the acquired number of soft latch random numbers in the random number storage area (S294). At this time, the soft latch random number (effect random number value, 2-byte random value) acquired from the random number register 1 of the random number circuit 110 is the hardware acquired from the random number register 0 of the random number circuit in the random value storage area. It is stored in an area different from the area where the latch random number (random number value for internal winning combination lottery) is stored. Then, after the process of S294, the main CPU 101 ends the random number acquisition process, and moves the process to S204 of the main flow (see FIG. 54). In the present embodiment, a predetermined storage area of the main RAM 103 is allocated as a random number storage area so that a plurality of 2-byte random numbers and 1-byte random numbers can be stored.

[Internal lottery processing]
Next, with reference to FIGS. 64 and 65, the internal lottery process performed in S204 in the main flow (see FIG. 54) will be described. 64 is a flowchart showing the procedure of the internal lottery process, FIG. 65A is a diagram showing an example of a source program for executing the processes of S302 to S305 during the internal lottery process, and FIG. It is a figure which shows an example of the source program for performing the process of S308-S309 in an internal lottery process.

  First, the main CPU 101 performs a set value / medal insertion number check process (S301). In this process, the main CPU 101 performs a check process for the current game setting value (any one of 1 to 6) and the number of inserted medals (three in this embodiment).

  Next, the main CPU 101 sets the internal lottery table for general games and the number of lotteries (67 times in this embodiment) (S302). In this process, the value of “winning number” (winning request flag status) in the internal lottery tables (RT0 to RT4) shown in FIGS. 16 and 17 is set in the C register, and “determination data” (not shown: address) The value of (data for determining the reference destination) is set in the A register.

  Next, the main CPU 101 determines whether or not the RB is operating (S303). That is, the main CPU 101 determines whether or not the BB gaming state (BB operation is in progress). In S303, when the main CPU 101 determines that the RB is not operating (when S303 is NO), the main CPU 101 performs a process of S305 described later.

  On the other hand, when the main CPU 101 determines in S303 that the RB is in operation (in the case where S303 is YES), the main CPU 101 uses the internal lottery table for RB (shown in FIGS. 16 and 17 in this embodiment). Further, the number of lotteries (67 times in this embodiment as in the general game) is set (S304). In this process, the internal lottery table and the number of lotteries for the general game set in S302 are overwritten with the internal lottery table for the RB and the number of lotteries. In the internal lottery tables shown in FIGS. 16 and 17, for convenience of explanation, the internal lottery table for general games and the internal lottery table in RB have the same configuration, but in each gaming state It is good also as a different structure so that only a required internal winning combination is lottery.

  After the process of S304 or when S303 is NO, the main CPU 101 acquires the determination data of the lottery target combination from the set internal lottery table, and updates the lottery table address (S305).

  Next, the main CPU 101 determines whether the determination data is RT state data (S306). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination whose lottery value changes according to the RT state. For example, the main CPU 101 determines whether or not the address specified in the determination data of the lottery target combination currently acquired is an address in an RT state-specific lottery value selection table (not shown).

  For example, in the internal lottery table shown in FIGS. 16 and 17, the determination data associated with the internal winning combination “F_normal lip” is the internal winning combination “F_” in the RT state-specific lottery value selection table (not shown). Since the address of “normal lip” is defined, the determination data associated with the internal winning combination “F_normal lip” corresponds to the RT state-specific data. Therefore, when the lottery target combination currently acquired is the internal winning combination “F_normal lip”, in the process of S306, the main CPU 101 determines that the determination data is RT state data.

  In S306, when the main CPU 101 determines that the determination data is not RT state data (when S306 is NO), the main CPU 101 performs the process of S308 described later. On the other hand, in S306, when the main CPU 101 determines that the determination data is the RT state-specific data (when S306 is YES), the main CPU 101 determines the RT state-specific lottery value selection table (not determined) based on the determination data. The selection data is acquired from (shown), and the acquired selection data is set as determination data (S307).

  After the processing of S307 or when S306 is NO, the main CPU 101 determines whether the determination data of the lottery target combination is data by setting (S308). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination whose lottery value changes according to the set value. For example, the main CPU 101 determines whether or not the address defined in the determination data of the lottery target combination that is currently acquired is an address in a setting-specific internal lottery value table (not shown).

  For example, in the internal lottery table shown in FIG. 16 and FIG. 17, when the internal winning combination “F_Common Bell” is defined so that the lottery value becomes higher as the set value is higher, this internal winning combination “F_Common Bell” "Is associated with the internal winning combination" F_Common Bell "because the address of the internal winning combination" F_Common Bell "in the setting-specific lottery value selection table (not shown) is defined. The attached determination data corresponds to setting-specific data. Therefore, when the lottery target combination currently acquired is the internal winning combination “F_Common Bell”, in the processing of S308, the main CPU 101 determines that the determination data is setting-specific data.

  In S308, when the main CPU 101 determines that the determination data is not the setting-specific data (when S308 is NO), the main CPU 101 performs the process of S310 described later. On the other hand, when the main CPU 101 determines in S308 that the determination data is data by setting (when S308 is YES), the main CPU 101 adds the set value data (any of 0 to 5) to the determination data. Then, the added value is set in the determination data (S309). The set value data added to the determination data in this process is data associated with the set value. However, the set value data “0” to “5” is not “the set value itself” but “ Data corresponding to “Setting 1” to “Setting 6”.

  After the process of S309 or when S308 is NO, the main CPU 101 calculates the address of the area in which the lottery value of the lottery target role is stored based on the set determination data, and the lottery stored in the address A value is acquired (S310).

  For example, when the lottery target combination is an internal winning combination (for example, “F_black BAR”) whose lottery value does not vary depending on either the RT state or the set value, the main CPU 101 determines from the address indicated by the determination data. A lottery value “8” is acquired.

  For example, when the lottery target combination is an internal winning combination (for example, “F_normal lip”) whose lottery value varies depending on the RT state, the main CPU 101 determines the RT0 state from the address indicated by the determination data. When it is (RT0), the lottery value “8332” is acquired, when it is the RT4 state (RT4), the lottery value “18041” is acquired, and when it is the other RT state (RT1 to RT3). The lottery value “0” is acquired.

  Further, for example, when the lottery target combination is an internal winning combination (for example, “F_common bell”) whose lottery value varies depending on the RT state, the main CPU 101 determines the set value from the address indicated by the determination data. A lottery value corresponding to “1” to “6” is acquired. At this time, the lottery value corresponding to the set value is acquired by specifying the address obtained by adding the set value data to the determination data (processing in S309).

  Further, for example, when the lottery target combination is an internal winning combination whose lottery value varies depending on both the RT state and the set value, the main CPU 101 determines whether the RT lot-specific internal lottery value table and the setting-specific internal lottery value table The lottery value is acquired with reference to both (see S306 to S309).

  Next, the main CPU 101 acquires a random number value (any one of 0 to 65535) for internal winning combination lottery stored in the random number storage area (S311).

  Next, the main CPU 101 performs lottery execution processing (S312). In this process, the main CPU 101 adds the random number acquired in S311 to the lottery value acquired in S310, and sets the addition result as a lottery result (winning / non-winning for the lottery target role). In this lottery execution process, when the sum of the lottery value and the random number value exceeds 65535 (when overflowing), it is determined that the lottery target combination is won (the lottery target combination is determined as an internal winning combination). The

  Next, the main CPU 101 stores a value obtained by adding the lottery value to the random number value (random number value after lottery execution) as a new random number value in the random number storage area (S313). Next, the main CPU 101 determines whether or not a lottery execution process has been won (whether or not an overflow has occurred) (S314).

  In S314, when the main CPU 101 determines that the lottery execution process has been won (when S314 is YES), the main CPU 101 refers to the internal lottery table, and the winning request flag status (corresponding to the internal winning combination won) (Value of “winning number”) is acquired (S315). For example, in the general game, when a lottery execution process is performed when the lottery target combination is “F_normal lip”, “1” is acquired as the winning request flag status in the process of S315. After the process of S315, the main CPU 101 performs a process of S319 described later.

  On the other hand, when it is determined in S314 that the main CPU 101 has not won the lottery execution process (when S314 is NO), the main CPU 101 updates the lottery object combination to the next combination in the internal lottery table, and lottery is performed. The number of times is subtracted by 1 (S316). Next, the main CPU 101 determines whether or not the number of lotteries after subtraction is “0” (S317).

  In S317, when the main CPU 101 determines that the number of lotteries after subtraction is not “0” (when S317 is NO), the main CPU 101 returns the process to S305 and repeats the processes after S305.

  On the other hand, when the main CPU 101 determines in S317 that the number of lotteries after subtraction is “0” (when S317 is YES), that is, when the internal winning combination is “out”, the main CPU 101 The lose status is set (S318). The “losing status” corresponds to a hit request flag status in which the winning number is “0”. After the process of S318, the main CPU 101 performs a process of S319 described later.

  Next, the main CPU 101 determines whether or not the CB is operating (S319). That is, the main CPU 101 determines whether or not the MB gaming state (MB is operating). In S319, when the main CPU 101 determines that the CB operation is not being performed (when S319 is NO), the main CPU 101 ends the internal lottery process and moves the process to S205 of the main flow (see FIG. 54).

  On the other hand, in S319, when the main CPU 101 determines that the CB is operating (when S319 is YES), the main CPU 101 sets the bits of all small combinations in the winning request flag storage area (internal winning combination storage area). Processing to turn on is performed (S320). That is, during the CB operation, the main CPU 101 performs a process of winning all the small combinations regardless of the result of the internal lottery process. Specifically, the main CPU 101 performs a process of storing “1” in the bits corresponding to NML01 (S_L1st miss A) to NML23 (S_chance 3) in the hit request flag storage area (internal winning combination storage area). . After the process of S320, the main CPU 101 ends the internal lottery process and moves the process to S205 of the main flow (see FIG. 54).

  In the present embodiment, the internal lottery process is performed as described above. Note that the processing of S302 to S305 during the internal lottery processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 65A. Among them, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 65A.

  For example, when the source code “LDIN ss, (HL)” is executed on the source program, a memory specified by an address set in the HL register (pair register) and an address obtained by adding “1” to the address. Is loaded into the ss (BC, DE, AC, AE, or BD) pair register, and the address set in the HL register is updated by +2 (added by 2). Therefore, when the source code “LDIN AC, (HL)” in FIG. 65A is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the AC register, and the address set in the HL register is updated by +2 (added by 2). In the determination data acquisition process in S305, as described above, the determination data is stored in the A register by the “LDIN” instruction (predetermined read instruction), and the request flag status is stored in the C register. .

  As described above, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed with one instruction code ("LDIN" instruction). In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  Further, the processing of S308 and S309 during the internal lottery processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 65B. Among them, the addition processing of the set value data (any one of 0 to 5) in S309 is performed by the main CPU 101 using the source codes “MUL A, 6” and “ADDQ A, (.LOW.wWAVENUM)” in FIG. 65B. This is done by executing in this order. Note that both the “MUL” instruction and the “ADDQ” instruction are instruction codes dedicated to the main CPU 101, and the “ADDQ” instruction is an instruction code dedicated to the main CPU 101 that performs address designation using the Q register (extension register).

  For example, when the source code “MUL A, n” is executed on the source program, the data stored in the A register is multiplied by the 1-byte integer n, and the multiplication result is stored in the A register. Therefore, in the source code “MUL A, 6” in FIG. 65B, the contents (stored data) of the A register are multiplied by a 1-byte integer 6, and the multiplication result is stored in the A register. This multiplication process is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, in the pachislot machine 1 of the present embodiment, an arithmetic dedicated circuit (arithmetic circuit 107) for executing multiplication processing and division processing on the source program is provided, so that the efficiency of the multiplication processing and division processing is improved. Can do.

  For example, when the source code “ADDQ r, (k)” is executed on the source program, the data stored in the Q register (upper address value) and a 1-byte integer k (direct value: lower address value) The data stored in the r register (A, B, C, D, E, H, or L register) is added to the memory contents (stored data) at the address specified in (), and the addition result is stored in the r register. The Therefore, when the source code “ADDQ A, (.LOW.wWAVENUM)” in FIG. 65B is executed, the data stored in the Q register and the memory at the address specified by the integer value “.LOW.wWAVENUM” of 1 byte The contents (stored data) of the A register are added to the contents (set value data), and the addition result is stored in the A register.

  That is, in the example shown in FIG. 65B, in the addition process of the set value in S309, the lottery table selection relative value is multiplied by the coefficient “6”, and the set value data is added to the multiplied value. The address of the lottery table in which the lottery values are stored is calculated.

  As described above, in the present embodiment, in the internal lottery process, the main CPU 101 dedicated instruction code (“ADDQ” instruction) using the Q register (extension register) is used. Thus, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. Therefore, an instruction relating to address setting can be omitted on the source program of the internal lottery process, and the capacity of the source program (usable capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Second interface board control processing (not specified)]
Next, the second interface board control process performed in S207 in the main flow (see FIG. 54) will be described with reference to FIG. FIG. 66 is a flowchart showing the procedure of the second interface board control process. This process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. The program used in the second interface board control process is stored in an unspecified area in the main ROM 102 (see FIG. 12B).

  First, the main CPU 101 saves the address data of the stack area in the main RAM 103 set in the stack pointer (SP) (S361). Next, the main CPU 101 sets the address data of the non-standard stack area in the main RAM 103 to the stack pointer (SP) (S362).

  Next, the main CPU 101 acquires navigation data (S363). Next, the main CPU 101 sets the navigation conversion table in an unspecified work area in the main RAM 103 (S364).

  Next, the main CPU 101 refers to the navigation conversion table and acquires the second interface push order number (S365). Next, the main CPU 101 stores the acquired second interface push order number in a specified extra push order number storage area (not shown) provided in the extra work area (S366). Next, the main CPU 101 sets “0” to the value of the pressed position table selection counter provided in the non-standard work area (S367).

  Next, the main CPU 101 determines whether or not the acquired navigation data is push order navigation (navigation data for a push order small combination) (S368). In S368, when the main CPU 101 determines that the acquired navigation data is push order navigation (when S368 is YES), the main CPU 101 performs the process of S372 described later.

  On the other hand, when the main CPU 101 determines in S368 that the acquired navigation data is not push order navigation (when S368 is NO), the main CPU 101 determines that the acquired navigation data is navigation data for BB1 stop operation (10). It is determined whether or not (S369).

  In S369, when the main CPU 101 determines that the acquired navigation data is navigation data for BB1 stop operation (when S369 is YES), the main CPU 101 performs the process of S371 described later. On the other hand, when the main CPU 101 determines in S369 that the acquired navigation data is not navigation data for the BB1 stop operation (when S369 is NO), the main CPU 101 sets “1” to the value of the pressed position table selection counter. Are added (S370). In S370, the process of adding “1” to the value of the pressed position table selection counter is a process performed to acquire the pressed position of BB2 from the pressed position table (not shown).

  After the process of S370 or when S369 is YES, the main CPU 101 adds “1” to the value of the pressed position table selection counter (S371). In S371, the process of adding “1” to the value of the pressed position table selection counter is a process performed to acquire the pressed position of BB1 or BB2 from the pressed position table (not shown).

  After the process of S371 or when S368 is YES, the main CPU 101 selects a pressed position table (not shown) based on the value of the pressed position table selection counter (S372). Next, the main CPU 101 refers to the selected pressing position table, and acquires pressing position data for three reels (left reel 3L, middle reel 3C, and right reel 3R) (S373). Next, the main CPU 101 stores the acquired pressing position data in a non-standard pressing position storage area (not shown) provided in the non-standard working area (S374). If the navigation data is push order navigation by the processing of S367 to S371, the value of the pressed position table selection counter is “0”, and if the navigation data is navigation data for BB1 stop operation, the value of the pressed position table selection counter is set. The value is “1”, and if the navigation data is navigation data for BB2 stop operation, the value of the pressed position table selection counter is “2”. That is, the pressed position data is acquired based on the navigation data.

  Note that the processing of S369 and S371 is processing when a plurality of “BB” as a bonus combination (for example, two of BB1 and BB2) are provided, and in this embodiment, “BB” as a bonus combination. Since only one is provided (see FIG. 18), the processing of S369 and S371 is not necessary. Of course, in this embodiment, a plurality of “BB” (for example, two or more) as a bonus combination may be provided. In this case, the processing of S369 and S371 or the same processing is performed. Thus, the value of the pressed position table selection counter corresponding to the type of bonus combination may be selected.

  Next, the main CPU 101 performs a second interface board output process (S375). The details of the second interface board output process will be described later with reference to FIG. 67 described later.

  Next, the main CPU 101 performs restoration processing for all registers (S376). Next, the main CPU 101 sets the address data of the stack area saved in S361 to the stack pointer (SP) (S377). After the process of S377, the main CPU 101 ends the second interface board control process, and moves the process to S208 of the main flow (see FIG. 54).

[Second interface board output processing]
Next, the second interface board output process performed in S375 during the second interface board control process (see FIG. 66) will be described with reference to FIG. FIG. 67 is a flowchart showing the procedure of the second interface board output process. The second interface board output process is performed in a non-standard work area of the main RAM 103.

  First, the main CPU 101 determines whether or not a transmission operation is being performed via the second interface serial line (second serial communication circuit 115: SCU2) (S381). When the main CPU 101 determines in S381 that the transmission operation is being performed via the second interface serial line (when S381 is YES), the main CPU 101 ends the second interface board output process, The process moves to S376 of the second interface board control process (see FIG. 66).

  On the other hand, when the main CPU 101 determines in S381 that the transmission operation is not performed via the second interface serial line (when S381 is NO), the main CPU 101 is provided in an unspecified work area. “3” (the number of reels) is set to the value of the loop counter, and the initial value “1” is set to the serial communication thumb value (S382). Next, the main CPU 101 transmits transmission start data via the second interface serial line (second serial communication circuit 115: SCU2) (S383).

  Next, the main CPU 101 refers to the non-regulated pressing position storage area of the predetermined reel (rotating cylinder), and acquires the pressing position data of the predetermined reel (S384). Next, the main CPU 101 updates the non-regulated pressing position storage area to be referred to that of the next target reel (rotor) (S385).

  Next, the main CPU 101 acquires pulse number data corresponding to the pressed position data (design position) based on the pulse conversion data (not shown) and the acquired pressed position data (S386). Although details of the correspondence between the pressed position data (symbol position) and the pulse number data are omitted, for example, the acquired pressed position data (symbol position) is “3” (the symbol “blue 7” in the left reel 3L). ), “38” is acquired as the pulse number data, and when the pressed position data (design position) is “10” (design “black BAR” in the left reel 3L), the pulse number data is obtained as the pulse number data. “155” is acquired. For example, when the acquired pressing position data (symbol position) is “12” (symbol “white 7” in the left reel 3L), “189” is acquired as the pulse number data, and the pressing position data (symbol position) If the (position) is “15” (the symbol “black BAR” in the left reel 3L), “239” is acquired as the pulse number data.

  Next, the main CPU 101 transmits the acquired pulse number data via the second interface serial line (second serial communication circuit 115: SCU2) (S387). Next, the main CPU 101 adds pulse number data to the serial communication sum value (S388). Next, the main CPU 101 subtracts 1 from the value of the loop counter (S389).

  Next, the main CPU 101 determines whether or not the value of the loop counter is “0” (S390). In S390, when the main CPU 101 determines that the value of the loop counter is not “0” (when S390 is NO), the main CPU 101 changes the target reel to the next reel and returns the process to S384. The processes after S384 are repeated.

  On the other hand, when the main CPU 101 determines in S390 that the value of the loop counter is “0” (in the case where S390 is YES), the main CPU 101 converts the serial communication sum value to the second interface serial line (second interface). 2 serial communication circuit 115: SCU2) (S391). After the process of S391, the main CPU 101 ends the second interface board output process, and moves the process to S376 of the second interface board control process (see FIG. 66).

[Control processing by status]
Next, with reference to FIG. 68, the state-specific control process performed in S208 in the main flow (see FIG. 54) will be described. FIG. 68 is a flowchart showing the procedure of the state-specific control process.

  First, the main CPU 101 determines whether or not the current game is in ART (see FIG. 14) (S401). In S401, when the main CPU 101 determines that the current game is not in ART (when S401 is NO), the main CPU 101 performs the process of S409 described later.

  Although not shown in FIG. 68, when the main CPU 101 determines that the current game is in ART (when S401 is YES), depending on the RT state, internal winning combination, etc. Navigation data storage area of the main RAM 103 (see FIG. 102A to be described later) is stored in the navigation data storage area of the main RAM 103 (see FIG. 102A described later). Process to store in.

  On the other hand, when the main CPU 101 determines in S401 that the current game is in ART (when S401 is YES), the main CPU 101 determines whether or not the current game is in the double special zone (see FIG. 14). Is determined (S402). In S402, when the main CPU 101 determines that the current game is in the double special zone (when S402 is YES), the main CPU 101 performs a start process in the double special zone (S403). The details of the start process in the double special zone will be described later with reference to FIGS. 69 and 70 described later. Then, after the processing of S403, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 54).

  On the other hand, when the main CPU 101 determines in S402 that the current game is not in the double special zone (when S402 is NO), the main CPU 101 determines that the current game is in the CP special zone during the BB (see FIG. 14). It is determined whether or not (S404). In S404, when the main CPU 101 determines that the current game is in the CP special zone during BB (when S404 is YES), the main CPU 101 performs a start process during the CP special zone during BB (S405). ). In the start processing in the BB CP special zone, for example, as described above, CP acquisition lottery is performed. Then, after the processing of S405, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 54).

  On the other hand, when the main CPU 101 determines in S404 that the current game is not in the CP special zone in the BB (when S404 is NO), the main CPU 101 is in the ongoing challenge for the current game (see FIG. 14). Whether or not (S406). In S406, when the main CPU 101 determines that the current game is in a continuous challenge (when S406 is YES), the main CPU 101 performs a start-time process during a continuous challenge (S407). The details of the start-time process during the continuous challenge will be described later with reference to FIG. 71 described later. Then, after the processing of S407, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 54).

  On the other hand, when the main CPU 101 determines in S406 that the current game is not in a continuous challenge (NO in S406), the main CPU 101 performs a start-up process during normal ART (S408). In the normal ART start process, for example, as described above, various types of lottery such as ART stock lottery and CP acquisition lottery are performed, and the ART game number counter is decremented by “1” per game, When the counter reaches “0”, a continuation challenge is set from the next game. Then, after the processing of S408, the main CPU 101 ends the state-based control processing, and moves the processing to S209 of the main flow (see FIG. 54).

  In S401, when the main CPU 101 determines that the current game is not in ART (when S401 is NO), the main CPU 101 determines whether or not the current game is being promoted (see FIG. 14) (see FIG. 14). S409). In S409, when the main CPU 101 determines that the current game is being promoted (when S409 is YES), the main CPU 101 performs a start-up process during the promotion chance (S410). Details of the start process during the promotion chance will be described later with reference to FIG. 72 described later. Then, after the processing of S410, the main CPU 101 ends the state-based control processing, and moves the processing to S209 of the main flow (see FIG. 54).

  On the other hand, when the main CPU 101 determines in S409 that the current game is not in the promotion chance (when S409 is NO), the main CPU 101 is in the BB history specialization zone (see FIG. 14). Whether or not (S411). In S411, when the main CPU 101 determines that the current game is in the history special zone during BB (when S411 is YES), the main CPU 101 performs the start processing during the history special zone during BB (S412). ). In the start processing in the BB history specializing zone, for example, as described above, the ART lottery is performed based on the winning history of the internal winning combination. Then, after the processing of S412, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 54).

  On the other hand, when the main CPU 101 determines in S411 that the current game is not in the BB history special zone (when S411 is NO), the main CPU 101 is in the chance zone (see FIG. 14). Whether or not (S413). In S413, when the main CPU 101 determines that the current game is in the chance zone (YES in S413), the main CPU 101 performs a start time process during the chance zone (S414). In the process at the start in the chance zone, for example, as described above, ART lottery is performed with a higher probability than usual during five games. Then, after the processing of S414, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 54).

  On the other hand, when the main CPU 101 determines in S413 that the current game is not in the chance zone (when S413 is NO), the main CPU 101 performs normal start processing (S415). In the normal start process, for example, as described above, various types of lottery such as ART lottery and CZ lottery are performed. Then, after the processing of S415, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 54).

[Processing at start in double special zone]
Next, with reference to FIG. 69 and FIG. 70, the start process in the double special zone performed in S403 in the state-specific control process (see FIG. 68) will be described. FIG. 69 and FIG. 70 are flowcharts showing the procedure of the process at the start in the double special zone.

  First, the main CPU 101 determines whether or not it is the start time of a double specialization zone (S421). That is, the main CPU 101 determines whether or not it is the first game that has shifted to the double specialized zone from another effect gaming state. In S421, when the main CPU 101 determines that it is the start time of the double specialized zone (when S421 is YES), the main CPU 101 performs a lottery at the start of the double specialized zone (S422). Specifically, the main CPU 101 determines the internal state of the double specialized zone based on the double specialized zone start state lottery table (see FIG. 33A).

  On the other hand, in S421, when the main CPU 101 determines that it is not the start time of the double specialization zone (when S421 is NO), and after the processing of S422, the main CPU 101 has won “RT3 Lip A”. Is determined (S423). In S423, when the main CPU 101 determines that “RT3 Lip A” has not been won (when S423 is NO), the main CPU 101 performs processing of S427 described later.

  On the other hand, when it is determined in S423 that the main CPU 101 has won “RT3 Lip A” (when S423 is YES), the main CPU 101 performs a blue 7 fake notification lottery (S424). Specifically, the main CPU 101 determines whether or not to execute the blue 7 challenge effect based on the blue 7 fake lottery table in the double specialization zone (see FIG. 33C).

  Next, in S424, the main CPU 101 determines whether or not a blue 7 fake notification lottery has been won (S425). When the main CPU 101 determines in S425 that the blue 7 fake notification lottery has not been won (when S425 is NO), the main CPU 101 performs the process of S436 described later.

  On the other hand, when it is determined in S425 that the main CPU 101 has won the blue 7 fake notification lottery (when S425 is YES), the main CPU 101 performs a process of turning on the end prohibition flag (S426). By this process, the end lottery of the double special zone is not performed in the game. Then, after the processing of S426, the main CPU 101 performs processing of S436 described later.

  In the above-described S423, when the main CPU 101 determines that “RT3 Lip A” has not been won (when S423 is NO), the main CPU 101 determines whether or not “RT3 Lip C” has been won. (S427). In S427, when the main CPU 101 determines that “RT3 Lip C” has not been won (when S427 is NO), the main CPU 101 performs a process of S433 described later.

  On the other hand, when it is determined in S427 that the main CPU 101 has won “RT3 Lip C” (when S427 is YES), the main CPU 101 performs a process of turning on the end prohibition flag (S428). By this process, the end lottery of the double special zone is not performed in the game. Next, the main CPU 101 performs a process of adding “1” to the ART stock counter (S429). This process adds ART stock. Next, the main CPU 101 performs a blue 7 o'clock CP acquisition lottery (S430). Specifically, the main CPU 101 determines whether or not to acquire a CP based on the CP special lottery table at 7 o'clock in the double special zone (see FIG. 33B).

  Next, the main CPU 101 determines whether or not a blue 7 o'clock CP acquisition lottery has been won (S431). When the main CPU 101 determines in S431 that the blue 7 o'clock CP acquisition lottery has not been won (when S431 is NO), the main CPU 101 performs a process of S436 described later.

  On the other hand, when it is determined in S431 that the main CPU 101 has won the blue 7 o'clock CP acquisition lottery (when S431 is YES), the main CPU 101 performs a process of adding “1” to the CP counter (S432). By this process, CP is added. In this process, the value added to the CP counter may be determined by lottery. After the process of S432, the main CPU 101 performs a process of S436 described later.

  When the main CPU 101 determines that “RT3 Lip C” has not been won in S427 described above (when S427 is NO), the main CPU 101 performs a CP special lottery in the double special zone (S433). Specifically, the main CPU 101 determines whether or not to acquire CP based on the CP acquisition lottery table (see FIG. 32) in the double specialized zone.

  Next, the main CPU 101 determines whether or not the CP acquisition lottery in the double special zone is won (S434). In S434, when the main CPU 101 determines that the double-specialized zone CP acquisition lottery has not been won (when S434 is NO), the main CPU 101 performs processing of S436 described later.

  On the other hand, when it is determined in S434 that the main CPU 101 has won the CP acquisition lottery during the double special zone (when S434 is YES), the main CPU 101 performs a process of adding “1” to the CP counter (S435). ). By this process, CP is added. In this process, the value added to the CP counter may be determined by lottery.

  Next, the main CPU 101 determines whether or not the number of remaining games (guaranteed game number) in the double specialization zone is greater than 0 (S436). That is, the main CPU 101 determines whether or not the double special zone is within the range of the number of guaranteed games. When the main CPU 101 determines in S436 that the number of remaining games (guaranteed game number) in the double specialization zone is greater than 0 (when S436 is YES), the main CPU101 is in the double specialization zone. The remaining game number (guaranteed game number) is subtracted by “1” (S437).

  On the other hand, when the main CPU 101 determines in S436 that the number of remaining games (guaranteed game number) in the double specialization zone is not greater than 0 (when S436 is NO), and after the processing of S437, the main CPU 101 Determines whether the number of remaining games (guaranteed game number) in the double specialization zone is 0 (S438). That is, the main CPU 101 determines whether or not the number of guaranteed games has been consumed. In S438, when the main CPU 101 determines that the number of remaining games (guaranteed game number) in the double specialization zone is not 0 (when S438 is NO), the main CPU 101 performs the process of S450 described later.

  On the other hand, when the main CPU 101 determines in S438 that the number of remaining games (guaranteed game number) in the double specialization zone is 0 (when S438 is YES), the main CPU 101 wins the “normal role”. It is determined whether or not it has been done (S439). In S439, when the main CPU 101 determines that the “normal combination” is not won (when S439 is NO), the main CPU 101 performs the process of S450 described later.

  On the other hand, when it is determined in S439 that the main CPU 101 has won the “normal combination” (when S439 is YES), the main CPU 101 determines whether or not the termination prohibition flag is ON (S440). In S440, when the main CPU 101 determines that the termination prohibition flag is on (in the case where S440 is YES), the main CPU 101 performs the process of S450 described later.

  On the other hand, when it is determined in S440 that the end prohibition flag is not on (when S440 is NO), the main CPU 101 performs a double special zone end lottery (S441). Specifically, the main CPU 101 determines whether or not the double special zone ends based on the double special zone end lottery table (see FIG. 33D).

  Next, the main CPU 101 determines whether or not a double special zone end lottery has been won (S442). When the main CPU 101 determines in S442 that the double specialized zone end lottery has not been won (when S442 is NO), the main CPU 101 performs a process of S450 described later.

  On the other hand, when it is determined in S442 that the main CPU 101 has won the double specialized zone end lottery (when S442 is YES), the main CPU 101 performs a process of ending the double specialized zone (S443).

  Next, the main CPU 101 determines whether or not the pre-start state (that is, the effect game state before the transition to the double specialized zone) is a promotion chance (S444). In S444, when the main CPU 101 determines that the pre-start state is a promotion chance (when S444 is YES), the main CPU 101 sets a promotion chance (S445) and performs the process of S449 described later. By this process, after the end of the double specialization zone, it is returned to the promotion chance.

  On the other hand, when the main CPU 101 determines in S444 that the pre-start state is not a promotion chance (when S444 is NO), the main CPU 101 determines whether or not the pre-start state is a continuous challenge (S446). . In S446, when the main CPU 101 determines that the pre-start state is a continuation challenge (when S446 is YES), the main CPU 101 sets a continuation challenge (S447), and performs the process of S449 described later. By this process, after the completion of the double specialization zone, the continuous challenge is restored.

  On the other hand, when the main CPU 101 determines in S446 that the pre-start state is not a continuous challenge (when S446 is NO), the main CPU 101 sets a normal ART (S448). By this processing, after the end of the double special zone, the normal ART is shifted.

  Next, the main CPU 101 initializes the pre-start state (S449). If the end prohibition flag is on in the game, it is turned off (S450). The process proceeds to S209 of the process (see FIG. 54).

[Processing at start during continuous challenge]
Next, with reference to FIG. 71, the start-time process during the continuous challenge performed in S407 in the state-specific control process (see FIG. 68) will be described. FIG. 71 is a flowchart showing a procedure of a start time process during a continuous challenge.

  First, the main CPU 101 determines whether or not “RT3 Lip C” has been won (S461). In S461, when the main CPU 101 determines that “RT3 Lip C” has not been won (when S461 is NO), the main CPU 101 performs the process of S467 described later.

  On the other hand, when it is determined in S461 that the main CPU 101 has won “RT3 Lip C” (when S461 is YES), the main CPU 101 performs a special promotion lottery for promotion chance (S462). Specifically, for example, the main CPU 101 performs a special trigger lottery for determining whether or not to shift to the promotion chance with a probability of 1/256.

  Next, the main CPU 101 determines whether or not a promotion chance special trigger lottery has been won (S463). When the main CPU 101 determines in S463 that the promotion chance special activation lottery has not been won (when S463 is NO), the main CPU 101 performs the process of S467 described later.

  On the other hand, when it is determined in S463 that the main CPU 101 has won the promotion chance special activation lottery (when S463 is YES), the main CPU 101 sets the navigation data for establishing the blue 7 (S464). By this processing, information (push order) of the stop operation in which a specific symbol (in this case, “blue 7” symbol) is arranged on a specific line is notified.

  Next, the main CPU 101 turns on the promotion chance activation flag (S465). By this processing, the next game is shifted to a promotion chance.

  Next, the main CPU 101 reserves a promotion chance start lock effect (S466). By this process, the lock effect for notifying that the promotion chance starts at the start of the next game is executed. Then, after the process of S466, the start process during the continuous challenge is terminated, and the process proceeds to S209 of the main process (see FIG. 54).

  In S461 described above, when the main CPU 101 determines that “RT3 Lip C” has not been won (when S461 is NO), and in S463 described above, the main CPU 101 wins the promotion chance special trigger lottery. When it is determined that it is not present (when S463 is NO), the main CPU 101 determines whether or not “RT3 Lip B” has been won (S467). In S467, when the main CPU 101 determines that “RT3 Lip B” has not been won (when S467 is NO), the main CPU 101 performs processing of S475 described later.

  On the other hand, when it is determined in S467 that the main CPU 101 has won “RT3 Lip B” (when S467 is YES), the main CPU 101 sets the navigation data for establishing blue 7 (S468). . By this process, information (push order) of the stop operation in which a specific symbol (in this case, “blue BAR” symbol) is arranged on a specific line is notified.

  Next, the main CPU 101 performs a promotion chance activation lottery (S469). Specifically, for example, a lottery for determining whether or not to shift to the promotion chance with a probability of 4/256 is performed.

  Next, the main CPU 101 determines whether or not a promotion chance activation lottery has been won (S470). When the main CPU 101 determines in S470 that the promotion chance activation lottery has not been won (when S470 is NO), the main CPU 101 performs the process of S473 described later.

  On the other hand, when it is determined in S470 that the main CPU 101 has won the promotion chance activation lottery (when S470 is YES), the main CPU 101 turns on the promotion opportunity activation flag (S471). By this processing, the next game is shifted to a promotion chance.

  Next, the main CPU 101 reserves a promotion chance expectation lock effect (success) (S472). By this process, after a common lock effect (for example, an effect in which a reel action that rotates each reel in reverse direction is executed twice) is executed at the start of the next game, a promotion opportunity is expected to start. A confirmed lock effect (for example, an effect in which a reel action for rotating each reel in a reverse direction is executed) to notify that a chance starts is executed. Then, after the process of S472, the start process during the continuous challenge is terminated, and the process proceeds to S209 of the main process (see FIG. 54).

  In S470 described above, when the main CPU 101 determines that the promotion chance activation lottery has not been won (when S470 is NO), the main CPU 101 performs a process of adding “50” to the ART game number counter (S473). ). By this process, after the end of the continuous challenge, it is possible to return to the normal ART in the set with the added number of ART games.

  Next, the main CPU 101 reserves a promotion chance expectation lock effect (failure) (S474). With this process, the common lock effect described above is executed at the start of the next game, but the fixed lock effect is not executed. Then, after the process of S474, the start process during the continuous challenge is terminated, and the process proceeds to S209 of the main process (see FIG. 54).

  In S467 described above, when the main CPU 101 determines that “RT3 Lip B” has not been won (NO in S467), the main CPU 101 performs CP acquisition lottery (S475). Specifically, the main CPU 101 performs a CP acquisition lottery based on an internal winning combination or a random number for performance.

  Next, the main CPU 101 determines whether or not a CP acquisition lottery has been won (S476). When the main CPU 101 determines in S476 that the CP acquisition lottery has been won (when S476 is YES), the main CPU 101 performs a process of adding “1” to the CP counter (S477). By this process, CP is added. In this process, the value added to the CP counter may be determined by lottery. Then, after the process of S477, the start time process during the continuous challenge is terminated, and the process proceeds to S209 of the main process (see FIG. 54).

  On the other hand, when it is determined in S476 that the main CPU 101 has not won the CP acquisition lottery (when S476 is NO), the main CPU 101 determines that “RT1 Lip”, “RT2 Lip”, “RT3 Lip A”, Alternatively, it is determined whether or not “RT3 Lip C” has been won or “disconnected” (S478). In S478, when the main CPU 101 determines that “RT1 Lip”, “RT2 Lip”, “RT3 Lip A”, or “RT3 Lip C” is not winning or “out of” (S478 is NO). The main CPU 101 ends the start process during the continuous challenge, and moves the process to S209 of the main process (see FIG. 54).

  On the other hand, in S478, when the main CPU 101 determines that “RT1 Lip”, “RT2 Lip”, “RT3 Lip A”, or “RT3 Lip C” has been won or “displaced” (YES in S478) ), The main CPU 101 performs a process of subtracting “1” from the CP counter (S479). In this process, the value for subtracting the CP counter may be determined by lottery. Then, after the process of S479, the start process during the continuous challenge is terminated, and the process proceeds to S209 of the main process (see FIG. 54).

[Processing at start during promotion chance]
Next, with reference to FIG. 72, the start-up process during the promotion chance performed in S410 in the state-specific control process (see FIG. 68) will be described. FIG. 72 is a flowchart showing the procedure of the start time processing during the promotion chance. Although not shown in FIG. 72, the main CPU 101 performs a stop operation procedure advantageous to the player (FIGS. 19 to 21) according to the RT state, the internal winning combination, etc. even during the promotion chance. In order to notify (see FIG. 11), navigation data indicating a procedure of a stop operation advantageous to the player is stored in a navigation data storage area (see FIG. 102A described later) of the main RAM 103.

  First, the main CPU 101 performs lottery guarantee lottery of promotion opportunities (S491). Specifically, for example, when the internal winning combination is a specific combination other than the confirmed combination (for example, “F_strong bell”), the main CPU 101 determines to continue the promotion chance with a probability of 1/2. .

  Next, the main CPU 101 determines whether or not a continuation security lottery for a promotion opportunity has been won (S492). In S492, when the main CPU 101 determines that it has won the promotion chance continuation lottery (when S492 is YES), the main CPU 101 performs the process of S495 described later.

  On the other hand, when it is determined in S492 that the main CPU 101 has not won the promotion chance continuation lottery (if S492 is NO), the main CPU 101 performs the promotion chance continuation lottery (S493). Specifically, for example, when the game is the first game of the promotion chance, the main CPU 101 determines to continue the promotion chance with a probability of 85/256, and when it is the game after the second promotion chance, Decide to continue the promotion chance with a probability of 128/256. In this process, it is possible to determine whether or not to continue the promotion chance for a plurality of consecutive games (for example, up to the next game).

  Next, the main CPU 101 determines whether or not the continuous lottery of the promotion chance is won (S494). In S494, when the main CPU 101 determines that the promotion chance continuation lottery is won (when S494 is YES), the main CPU 101 performs a process of adding “1” to the continuation number counter (S495). Then, after the process of S495, the start process during the promotion chance is terminated, and the process proceeds to S209 of the main process (see FIG. 54).

  On the other hand, when the main CPU 101 determines in S494 that the promotion chance continuation lottery has not been won (when S494 is NO), the main CPU 101 adds a value corresponding to the continuation counter to the ART game number counter. Then, a process of clearing the continuation number counter is performed (S496). In this process, for example, if the continuation counter is “0”, the main CPU 101 sets the value of the ART game number counter to “111”. If the continuation counter is “1”, the main CPU 101 sets the value of the ART game number counter. Is “222”. In the case where the ART game number counter value is calculated by calculation (for example, multiplication of the number of games during the promotion chance and the prescribed value “111”), the initial value of the continuation counter is set at the start of the promotion chance. “1” may be set.

  Next, the main CPU 101 determines whether or not the pre-start state is a continuation challenge (S497). When the main CPU 101 determines in S497 that the pre-start state is a continuous challenge (when S497 is YES), the main CPU 101 sets a continuous challenge (S498) and initializes the pre-start state (S499). ). By this process, after the promotion chance is finished, it is returned to the continuous challenge. Then, after the process of S499, the start process during the promotion chance is terminated, and the process proceeds to S209 of the main process (see FIG. 54).

  On the other hand, when the main CPU 101 determines in S497 that the pre-start state is not a continuous challenge (when S497 is NO), the main CPU 101 sets a normal ART (S500). By this process, after the promotion chance is ended, the normal ART is entered. Then, after the process of S500, the start time process during the promotion chance is terminated, and the process proceeds to S209 of the main process (see FIG. 54).

[Retrieve priority storage processing]
Next, with reference to FIGS. 73 and 74, a description will be given of the pull-in priority storage process performed in S212 in the main flow (see FIG. 54). FIG. 73 is a flowchart showing a procedure of the pull-in priority storage process. FIG. 74 is a diagram showing an example of a source program for executing the later-described processing of S625 and S626 during the pull-in priority storage process.

  First, the main CPU 101 sets “3” as the number of search reels (S621). Next, the main CPU 101 performs a pull-in priority table selection process (S622). In this process, a pull-in priority table (not shown) is selected based on the internal winning combination and the operation stop button.

  Next, the main CPU 101 performs a pull-in priority storage area selection process (S623). In this process, the pull-in priority data storage area of the search target reel is selected. Next, the main CPU 101 sets “20” as the number of symbol checks (number of times) (S624).

  Next, the main CPU 101 performs symbol code acquisition processing (S625). In this process, a symbol code is acquired with reference to a winning action flag storage region and a symbol code storage region corresponding to the number of symbol checks. The details of the symbol code acquisition process will be described later with reference to FIG. 75 described later.

  Next, the main CPU 101 performs a logical product operation process (S626). In this processing, the main CPU 101 performs winning operation flag data generation processing. Details of the logical product operation processing will be described later with reference to FIG. 77 described later.

  Next, the main CPU 101 performs a drawing priority order acquisition process (S627). In this process, the main CPU 101 sets the bit to “1” in the winning action flag (display combination) storage area (see FIG. 22), and sets the bit to “1” in the winning request flag storage area. With respect to the winning combination, the drawing priority order data is acquired with reference to the drawing priority table (not shown). Details of the pull-in priority order acquisition process will be described later with reference to FIGS. 78 and 79 described later.

  Next, the main CPU 101 stores the acquired pull-in priority data in a pull-in priority data storage area (not shown) in the main RAM 103 (S628). At this time, the pull-in priority data is stored in the pull-in priority data storage area so that each priority value corresponds to a bit in the storage area.

  The pull-in priority data storage area is provided with a priority data storage area for each main reel type. Each drawing priority data storage area stores drawing priority data determined according to the symbol positions “0” to “19” of the corresponding main reel. In the present embodiment, by referring to this pull-in priority data storage area, it is searched whether there is a more appropriate number of sliding symbols in addition to the number of sliding symbols determined based on the stop table.

  The contents of the priority pull-in data stored in the pull-in priority data storage area differ depending on the type of the pull-in priority table number in the pull-in priority table referenced when determining the pull-in priority data. The pull-in priority data indicates that the higher the value, the higher the priority. By referring to the drawing priority data, it is possible to relatively evaluate the priority among the symbols arranged on the peripheral surface of the main reel. That is, the symbol for which the largest value is determined as the pull-in priority data becomes the symbol with the highest priority. Therefore, it can be said that the pull-in priority data indicates the rank between the symbols arranged on the peripheral surface of the main reel. When there are a plurality of symbols having the same value of the pull-in priority data, one symbol is determined according to the priority order defined by the priority order table.

  Next, the main CPU 101 performs an update process of the pull-in priority storage area (S629). In this process, the main CPU 101 sets a pull-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts 1 from the number of symbol checks (S630). Next, the main CPU 101 determines whether or not the number of symbol checks is “0” (S631).

  In S631, when the main CPU 101 determines that the number of symbol checks is not “0” (when S631 is NO), the main CPU 101 returns the process to the process of S625, and repeats the processes after S625. On the other hand, when the main CPU 101 determines in S631 that the number of symbol checks is “0” (when S631 is YES), the main CPU 101 performs a search target reel changing process (S632).

  Next, the main CPU 101 subtracts 1 from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is “0”, that is, whether or not the above-described series of processing has been performed on all main reels (S634).

  In S634, when the main CPU 101 determines that the number of search reels is not “0” (when S634 is NO), the main CPU 101 returns the process to the process of S622 and repeats the processes after S622. On the other hand, when the main CPU 101 determines in S634 that the number of search reels is “0” (in the case where S634 is YES), the main CPU 101 terminates the pull-in priority storage process, and the process proceeds to the main flow (FIG. 54).

  In the present embodiment, the pull-in priority storage process is performed as described above. The processes of S625 and S626 during the above-described pull-in priority storage process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  Among them, the logical product calculation process of S626 is performed by the main CPU 101 executing the source code “CALLF SB_DAND_00” in FIG. The “CALLF” instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above. When the source code “CALLF SB_DAND_00” in FIG. 74 is executed, the process is performed at the address specified by “SB_DAND_00”. The jump is performed, and the logical product operation process is started.

[Design code acquisition processing]
Next, with reference to FIG. 75 and FIG. 76, the symbol code acquisition process performed in S625 in the pull-in priority storage process (see FIG. 73) will be described. 75 is a flowchart showing the procedure of the symbol code acquisition process, and FIG. 76 is a diagram showing an example of a source program for executing the symbol code acquisition process.

  First, the main CPU 101 performs clear processing of the winning operation flag storage area (S641). In this process, the main CPU 101 sets “0” in all storage areas in the winning action flag storage area (see FIG. 22). Next, the main CPU 101 sets the first reel symbol arrangement table (see FIG. 15) (S642).

  Next, the main CPU 101 determines whether or not the first reel (left reel 3L) is stopped (S643).

  In S643, when the main CPU 101 determines that the first reel (left reel 3L) is stopped (when S643 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, when the main CPU 101 determines in S643 that it is not when the first reel (left reel 3L) is stopped (when S643 is NO), the main CPU 101 displays the second reel symbol arrangement table (see FIG. 15). Set (S644). In this process, the first reel symbol arrangement table set in S642 is overwritten with the second reel symbol arrangement table.

  Next, the main CPU 101 determines whether or not the second reel (medium reel 3C) is stopped (S645).

  In S645, when the main CPU 101 determines that the second reel (medium reel 3C) is stopped (when S645 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, when the main CPU 101 determines in S645 that it is not when the second reel (medium reel 3C) is stopped (when S645 is NO), the main CPU 101 displays the third reel symbol arrangement table (see FIG. 15). Set (S646). In this process, the second reel symbol arrangement table set in S644 is overwritten with the third reel symbol arrangement table.

  After the process of S646, or when S643 or S645 is YES, the main CPU 101 performs a symbol check process when the stop operation is performed on the reel to be stopped and corresponds to the symbol corresponding to the symbol acquired by the symbol check process. A winning action table (not shown) is acquired (S647). The symbol corresponding winning action table (not shown) stores data indicating a winning action flag (display combination) that can be stopped and displayed according to the stopped symbol. For example, when the first reel (left reel 3L) is stopped and the symbol located on the active line is “Replay” during the stop operation (see FIG. 18), “C_CL Lip”, “S_TT_XD Lip”, “C_ The top address of the symbol corresponding winning action table storing data indicating “special combination”, “S_CB 2”, “S_weak chance”, and “S_chance 3” is acquired.

  Next, the main CPU 101 sets a winning operation flag storage area (S648). Next, the main CPU 81 performs a compressed data storage process (S649). In this process, the main CPU 101 mainly performs a process of transferring (developing) winning winning action flag data stored in the symbol corresponding winning action table to a corresponding storage area in the winning action flag storage area.

  After the process of S649, the main CPU 101 sets the winning action flag storage area updated by the compressed data storing process, sets the symbol code storage area, and the data length of the winning action flag storage area (7 bytes in this embodiment). Is set (S650). After the process of S650, the main CPU 101 ends the symbol code acquisition process, and moves the process to S626 of the pull-in priority storage process (see FIG. 73).

  In the present embodiment, the symbol code acquisition process is performed as described above. The symbol code acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. Among them, the compressed data storage process of S649 is performed by the main CPU 101 executing the source code “CALLF SB_BTEP_00” in FIG.

  The “CALLF” instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above. When the source code “CALLF SB_BTEP_00” in FIG. 76 is executed, the process is performed at the address specified by “SB_BTEP_00”. The jump is made to start the compressed data storage process. In this compressed data storing process, as described above, the winning action flag data (compressed data) stored in the symbol corresponding winning action flag table of each reel is expanded (copied) in the winning action flag storage area.

  In this embodiment, the compression / decompression processing of the data related to winning is performed according to the processing procedure described in S647 to S649 during the above-described symbol code acquisition processing, and the above-described instruction code dedicated to the main CPU 101 is included in the processing. By using this, it is possible to increase the efficiency of the data compression / decompression processing related to winning, and to effectively utilize the limited capacity of the main RAM 103.

  In the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address “SB_BTEP_00” specified by the “CALLF” instruction is executed in the symbol setting process (see S205 of FIG. 54). In the compressed data storage process (not shown), the jump destination address specified by the “CALLF” instruction is set to be the same. That is, in this embodiment, the source program for executing the compressed data storage process performed in the symbol code acquisition process is the same as the source program for executing the compressed data storage process performed in the symbol setting process. The processing source program is shared (modularized). Therefore, there is no need to provide a separate source program for storing compressed data, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[AND operation]
Next, with reference to FIG. 77, for example, the AND operation process performed in S626 in the pull-in priority order storage process (see FIG. 73) will be described. FIG. 77 is a flowchart showing a procedure of logical product operation processing. 77 is performed not only in S626 in the pull-in priority storage process (see FIG. 73) but also in S687 in the pull-in priority acquisition process described later (see FIGS. 78 and 79 described later). Is also executed.

  In the logical product operation process executed in S626 in the pull-in priority storage process (see FIG. 73), the two data subjected to the logical product operation are stored in the winning action flag set in S650 during the above-described symbol code acquisition process. Area data and symbol code storage area data. The former data corresponds to “logical product destination data” described later, and the latter data corresponds to “logical product source data” described later. In this case, the number of bytes “7” of the data length (7 bytes) set in S650 during the above-described symbol code acquisition process corresponds to the “number of logical products” described later.

  On the other hand, in the AND operation executed in S687 in the below-described pull-in priority acquisition process (see FIGS. 78 and 79, which will be described later), the two data subjected to the AND operation are the hit (withdrawal) request flag storage area. And data of a winning action flag storage area. The former data corresponds to “logical product destination data” described later, and the latter data corresponds to “logical product source data” described later. In this case, the number of bytes “1” of the data length (1 byte) of the RT operation combination display flag described in FIG. 80B described later corresponds to the “number of logical products” described later. Note that the number of bytes “7”, which is the data length of the winning request flag storage area and the winning action flag storage area, may correspond to the “number of logical products” described later.

  First, the main CPU 101 acquires logical product source data (for example, data in a symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation on the logical product source data and the logical product destination data (for example, data in the winning operation flag storage area), and stores the calculation result as the logical product destination data (S662).

  Next, the main CPU 101 adds 1 to the address of the logical product data to be acquired (S663). Next, the main CPU 101 adds 1 to the address of the logical product destination data to be referred to (S664).

  Next, the main CPU 101 subtracts 1 from the number of logical products (S665). Next, the main CPU 101 determines whether or not the number of logical products is “0” (S666).

  In S666, when the main CPU 101 determines that the number of logical products is not “0” (when S666 is NO), the main CPU 101 returns the process to the process of S661 and repeats the processes after S661. On the other hand, in S666, when the main CPU 101 determines that the number of logical products is “0” (in the case where S666 is YES), the main CPU 101 ends the logical product operation processing and stores the processing, for example, the drawing priority order storage. The process proceeds to S627 in the process (see FIG. 73).

[Withdrawal priority acquisition processing]
Next, with reference to FIGS. 78 to 80, a description will be given of the pull-in priority acquisition process performed in S627 in the pull-in priority storing process (see FIG. 73). FIG. 78 and FIG. 79 are flowcharts showing the procedure of the acquisition priority order acquisition process. FIG. 80A is a diagram illustrating an example of a source program for executing the later-described processing of S680 to S683 during the pull-in priority acquisition process, and FIG. 80B illustrates the later-described processing of S686 during the pull-in priority acquiring process. It is a figure which shows an example of the source program for performing.

  First, the main CPU 101 determines whether or not the right reel 3R (specific display column) is being checked (S671).

  In S671, when the main CPU 101 determines that it is not at the time of checking the right reel 3R (when S671 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, when the main CPU 101 determines in S671 that the right reel 3R is being checked (when S671 is YES), the main CPU 101 determines “ANY combination” as the symbol combination (winning combination) related to the internal winning combination. It is determined whether or not (predetermined symbol combination) is included (S672). Here, the “ANY combination” refers to a combination in which a winning is determined regardless of at least the stop design of the right reel 3R (a winning combination in which at least the stop design of the right reel 3R is an arbitrary design).

  In S672, when the main CPU 101 determines that “ANY combination” is not included in the symbol combination related to the internal winning combination (when S672 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S672, when the main CPU 101 determines that “ANY combination” is included in the symbol combination related to the internal winning combination (when S672 is YES), the main CPU 101 determines “ANY combination” in the winning action flag storage area. The storage area corresponding to “comb” is masked (S673). Specifically, the main CPU 101 sets “1” to a bit corresponding to “ANY combination” in the winning action flag storage area.

  After the process of S673, or when S671 or S672 is NO, the main CPU 101 adds “1” to the address of the last storage area as the address of the winning action flag storage area (see FIG. 22). Is set, stop prohibition data is set, and a winning action flag data length (data length of the winning action flag storage area: 7 bytes in this embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons for which a stop operation has been detected. The stop button operating state is acquired by referring to the operation stop button storage area (see FIG. 25).

  Next, the main CPU 101 subtracts 1 (-1 update) the address of the set winning operation flag storage area (S676). Next, the main CPU 101 generates winning request flag data from the set winning action flag storage area and the corresponding winning request flag storage area (see FIG. 22), and based on the generated winning request flag data A prohibited winning action position is generated (S677).

  Next, the main CPU 101 determines whether or not the stop operation position is a prohibited winning action position (S678).

  In S678, when the main CPU 101 determines that the stop operation position is not the prohibited winning action position (when S678 is NO), the main CPU 101 performs a process of S684 described later. On the other hand, when the main CPU 101 determines in S678 that the stop operation position is the prohibited winning operation position (when S678 is YES), the main CPU 101 has the value of the stop button operation counter being the value of the third stop. Whether or not (S679).

  In S679, when the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop (when S679 is YES), the main CPU 101 performs a process of S705 described later. On the other hand, when the main CPU 101 determines in S679 that the value of the stop button operation counter is not the value of the third stop (when S679 is NO), the main CPU 101 determines that the value of the stop button operation counter is the second stop. Whether it is a value or not is discriminated (S680).

  In S680, when the main CPU 101 determines that the value of the stop button operation counter is not the second stop value (when S680 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, when the main CPU 101 determines in S680 that the value of the stop button operation counter is the second stop value (when S680 is YES), the main CPU 101 determines whether or not the right reel 3R has stopped. Is discriminated (S681).

  When the main CPU 101 determines in S681 that the right reel 3R has been stopped (when S681 is YES), the main CPU 101 performs a process of S684 described later. On the other hand, when the main CPU 101 determines in S681 that the right reel 3R has not been stopped (NO in S681), the main CPU 101 determines that the hit request flag may be subject to interference “ANY role”. Or not (whether or not “ANY combination” is included in the symbol combination (winning combination) related to the internal winning combination) (S682).

  In S682, when the main CPU 101 determines that the hit request flag is not a flag that may receive the “ANY role” interference (YES in S682), the main CPU 101 performs the process of S684 described later. On the other hand, in S682, when the main CPU 101 determines that the hit request flag is a flag that may be subject to interference of “ANY role” (when S682 is NO), the main CPU 101 determines that the current check is “ANY”. It is determined whether or not it is time to check the hit request flag including “combination” (S683).

  In S683, when the main CPU 101 determines that the current check is a check of the hit request flag including “ANY role” (when S683 is YES), the main CPU 101 performs a process of S705 described later.

  On the other hand, when the main CPU 101 determines in S683 that the current check is not at the time of checking the hit request flag including “ANY role” (S683 is NO), S678 or S680 is NO, or S681. Alternatively, when S682 is YES, the main CPU 101 subtracts 1 from the winning operation flag data length (S684). Next, the main CPU 101 determines whether or not the winning action flag data length is “0” (S685).

  In S685, when the main CPU 101 determines that the winning action flag data length is not “0” (when S685 is NO), the main CPU 101 returns the process to the process of S676 and repeats the processes after S676.

  On the other hand, when the main CPU 101 determines in S685 that the winning action flag data length is “0” (when S685 is YES), the main CPU 101 performs a stop control pull-in request flag setting process (S686). . This process is performed by the main CPU 101 sequentially executing each process defined by the source program in FIG. 80B. Therefore, in this process, the AND operation process described with reference to FIG. 77 is performed. In the logical product calculation process executed in the process of S686, as described above, the data in the winning (withdrawal) request flag storage area is set to “logical product destination data”, and the data in the winning action flag storage area is In the “logical product source data”, the number of bytes “1” of the data length (1 byte) of the RT operation combination display flag is set in the “logical product number”. The RT action combination display flag is a storage area in which a symbol combination related to RT transition is defined in the winning action flag storage area. In this embodiment, only the storage area 7 is provided as shown in FIG. As described above, the number of bytes “7” that is the data length (7 bytes) of the winning request flag storage area and the winning action flag storage area may be set in the “logical product count”.

  Next, the main CPU 101 refers to a pull-in priority table address storage area (not shown) and obtains a pull-in priority table (not shown) (S687).

  Next, the main CPU 101 determines whether or not the data in the pull-in priority table stored at the currently set address is an end code (000H) (S688).

  In S688, when the main CPU 101 determines that the data in the pull-in priority order table stored at the currently set address is an end code (when S688 is YES), the main CPU 101 determines that S705 to be described later. Perform the process. On the other hand, when the main CPU 101 determines in S688 that the data in the drawing priority table stored at the currently set address is not an end code (when S688 is NO), the main CPU 101 A flag storage area is set (S689).

  Next, the main CPU 101 acquires pull-in priority data from the pull-in priority table based on the currently set address (S690). Next, the main CPU 101 sets a block counter in the pull-in priority table (S691). In this embodiment, in this process, the main CPU 101 sets “2” to the value of the block counter in the pull-in priority table.

  Next, the main CPU 101 sets the number of checks in the pull-in priority table, and adds 1 (+1 update) to the address of the pull-in priority table to be referred to (S692). In the present embodiment, in this process, the main CPU 101 sets “8” as an example to the number of checks in the pull-in priority table. Note that the number of checks in the pull-in priority table can be arbitrarily set in accordance with the number of bits of check data defined in the pull-in priority table.

  Next, the main CPU 101 acquires check data based on the updated address of the drawing priority table, and extracts a check bit from the check data (S693).

  Next, the main CPU 101 determines whether or not the value of the extracted check bit is “1” (S694).

  In S694, when the main CPU 101 determines that the value of the extracted check bit is not “1” (when S694 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, when the main CPU 101 determines in S694 that the value of the extracted check bit is “1” (when S694 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referenced. (+1 update), and based on the updated address, determination data is acquired from the pull-in priority table (S695).

  Next, the main CPU 101 determines based on the determination data acquired in S695 whether or not the currently acquired winning action flag data is a determination target (S696). In this process, the main CPU 101 compares the currently acquired winning action flag data with the determination data, determines whether or not the former corresponds to the latter, and the former corresponds to the latter. In this case, it is determined that the currently acquired winning action flag data is a determination target.

  In S696, when the main CPU 101 determines that the winning action flag data is not a determination target (when S696 is NO), the main CPU 101 performs a process of S699 described later. On the other hand, when the main CPU 101 determines in S696 that the winning operation flag data is the determination target (when S696 is YES), the main CPU 101 performs the update processing of the drawing priority data (S697). In this process, the main CPU 101 updates (overwrites) the currently set pull-in priority data with the pull-in priority data associated with the determination data acquired in S697.

  Next, the main CPU 101 performs check data update processing (S698). In this process, the main CPU 101 shifts the check data rightward by 1 bit (in the direction from bit 7 to bit 0). In this process, “0” is set in bit 7 of the check data after the shift.

  After the processing of S698, or when S694 or S696 is NO, the main CPU 101 determines whether or not there is a bit to be checked (bit in which “1” is set) in the check data (S699).

  In S699, when the main CPU 101 determines that there is no check target bit in the check data (when S699 is NO), the main CPU 101 performs a process of S702 described later. On the other hand, when the main CPU 101 determines in S699 that there is a bit to be checked in the check data (when S699 is YES), the main CPU 101 adds 1 to the address of the winning action flag storage area to be checked (+1 update) And 1 is subtracted from the number of checks (S700).

  Next, the main CPU 101 determines whether or not the number of checks is “0” (S701). In S701, when the main CPU 101 determines that the number of checks is not “0” (when S701 is NO), the main CPU 101 returns the process to the process of S698 and repeats the processes after S698.

  On the other hand, when the main CPU 101 determines in S701 that the number of checks is “0” (in the case where S701 is YES), the main CPU 101 sets the number of checks in the address of the winning action flag storage area that is currently referenced. The initial value “8” is added to update the address of the winning action flag storage area, and the value of the block counter is decremented by 1 (S702). Next, the main CPU 101 determines whether or not the value of the block counter is “0” (S703).

  In S703, when the main CPU 101 determines that the value of the block counter is not “0” (when S703 is NO), the main CPU 101 returns the process to the process of S692 and repeats the processes after S692.

  On the other hand, in S703, when the main CPU 101 determines that the value of the block counter is “0” (when S703 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referenced (+1 update). (S704). After the process of S704, the main CPU 101 returns the process to the process of S688, and repeats the processes after S688.

  Here, returning to the processing of S679, S683, or S688 again, if S679, S683, or S688 is YES, the main CPU 101 uses the pulling order data set at this time as the final pulling priority data. Set (S705). If S679 or S683 is YES, the main CPU 101 sets “0 (00H)” as final pull-in priority data. In this case, since the end code is assigned to the pull-in priority data “0 (00H)”, no pull-in data (stop prohibition) is set. After the process of S705, the main CPU 101 ends the pull-in priority order acquisition process, and moves the process to S628 in the pull-in priority order storing process (see FIG. 73).

  In the present embodiment, the pull-in priority acquisition process is performed as described above. Note that the “ANY role” pull-in priority handling process of S680 to S683 during the pull-in priority acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 80A. Is called. Among them, for example, the determination process of S683 is executed by a “JCP” instruction (predetermined determination instruction) on the source program. The “JCP” instruction is an instruction for executing an operation equivalent to a comparison instruction, and is a dedicated instruction code for the main CPU 101.

  For example, when the source code “JCP cc, A, n, e” is executed on the source program, the contents (stored data) of the A register are compared with the integer n, and the comparison result is the condition of cc. Then, the process is jumped to the address designated by e. In the “cc condition” of the “JCP” instruction, one of a carry flag state and a zero flag state in the flag register F is designated (see FIG. 11). For example, if “C” is specified for cc, the condition of cc means that the carry flag is “1” (ON state), and if “NC” is specified for cc, the condition of cc Means that the carry flag is “0” (off state). For example, if “Z” is specified for cc, the condition of cc means that the zero flag is “1” (ON state), and if “NZ” is specified for cc, The condition means that the zero flag is “0” (off state).

  As shown in FIG. 80A, when the “JCP” instruction is used on the source program of the “ANY role” pull-in priority handling process, the instruction relating to the address setting can be omitted (the instruction relating to the address setting is separately provided). Therefore, the processing efficiency of the “ANY role” pull-in priority handling process can be increased, and the capacity of the source program (the capacity of the main ROM 102) can be reduced.

  In addition, the stop control pull-in request flag setting process in S686 during the pull-in priority acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program in FIG. 80B. In the stop control pull-in request flag setting process of S686, as shown in FIG. 80B, an “LDQ” instruction for specifying an address using the Q register (extension register), which is a dedicated instruction code for the main CPU 101, and “CALLF” Instructions are used.

  Therefore, by using the “LDQ” instruction using the Q register (extension register) in the stop request pull-in request flag setting process in S686, the main ROM 102, the main RAM 103, and the memory map I / O are accessed by direct values. can do. In this case, an instruction relating to address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced. The “CALLF” instruction is a 2-byte instruction code as described above. Therefore, by using these instruction codes dedicated to the main CPU 101 in the stop control pull-in request flag setting process, the processing efficiency can be improved, and the limited capacity of the main RAM 103 can be effectively utilized. .

  Further, in the present embodiment, in the stop request pull-in request flag setting process of S686 during the priority pull-in order acquisition process, the jump destination logical product operation process address “SB_DAND_00” designated by the “CALLF” instruction is the above-described FIG. This is the same as the jump destination address specified by the “CALLF” instruction in the logical product operation process of S626 during the pull-in priority storage process described in (see FIG. 74). That is, in the present embodiment, the source program for executing the AND operation performed in the stop request pull-in request flag setting process in S686 during the priority pull-in order acquisition process is the logic performed in S626 during the pull-in priority storage process. It is the same as the source program for executing the product operation process, and the source program for the AND operation process is shared (modularized) in both processes of S686 and S626. In this case, since it is not necessary to separately provide a source program for the logical product operation process in both the processes of S686 and S626, the capacity of the source program (the capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  As described above, in the various processes during the priority pull-in order acquisition process of the present embodiment, the above-described various instruction codes dedicated to the main CPU 101 are used as appropriate, realizing the efficiency of the corresponding process and the reduction in the capacity of the source program. doing. As a result, in this embodiment, the efficiency of the program processing of the main control circuit 90 and the reduction of the capacity can be achieved, and it is possible to improve the gameability by utilizing the free space corresponding to the reduced capacity. It becomes.

[Reel stop control process]
Next, the reel stop control process performed in S213 in the main flow (see FIG. 54) will be described with reference to FIGS. FIG. 81 is a flowchart showing the procedure of the reel stop control process. FIG. 82 is a diagram showing an example of a source program for executing the later-described processing of S711 to S716 during the reel stop control processing, and FIG. 83 executes the later-described processing of S726 during the reel stop control processing. It is a figure which shows an example of the source program for this.

  First, the main CPU 101 performs a reel stop possible signal OFF process (S711). In this process, the main CPU 101 mainly performs a port output process of the reel stop possible signal OFF data. Further, this process is performed using an unspecified work area in the main RAM 103. Details of the reel stop enable signal OFF process will be described later with reference to FIG. 84 described later.

  Next, the main CPU 101 determines whether or not the rotation speeds of all the reels have reached a predetermined constant speed (whether or not it has become “constant speed”) (S712). In S712, when the main CPU 101 determines that the rotation speeds of all the reels are not “constant speed” (when S712 is NO), the main CPU 101 repeats the process of S712.

  On the other hand, when the main CPU 101 determines in S712 that the rotation speeds of all the reels have become “constant speed” (when S712 is YES), the main CPU 101 performs a reel stop enable signal ON process (S713). In this processing, the main CPU 101 mainly performs port output processing of the reel stop enable signal ON data. Further, this process is performed using an unspecified work area in the main RAM 103. Details of the reel stop possible signal ON process will be described later with reference to FIG. 85 described later.

  Next, the main CPU 101 determines whether or not a valid stop button has been pressed (S714).

  When the main CPU 101 determines in S714 that a valid stop button has not been pressed (in the case where S714 is NO), the main CPU 101 returns the process to the process of S713 and repeats the processes after S713. On the other hand, when the main CPU 101 determines in S714 that a valid stop button has been pressed (in the case where S714 is YES), the main CPU 101 updates the operation stop button storage area (see FIG. 25), and the stop button has not been pressed. The value of the operation counter is decremented by 1 (S715).

  Next, the main CPU 101 determines a search target reel from the operation stop button (S716). Further, in this process, an address (head address) setting process of the spinning control data storage area in which the reel control management information of the search target reel is stored is also performed (source code “LDQ IX, wR1_CTRL− (wR2_CTRL in FIG. 82). -WR1_CTRL) ").

  Next, the main CPU 101 performs a reel stop possible signal OFF process (S717). This process is performed using an unspecified work area of the main RAM 103, as in S711. Details of the reel stop enable signal OFF process will be described later with reference to FIG. 84 described later. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

  Next, the main CPU 101 performs reel stop selection processing (S719). Although a detailed description is omitted, in this process, the main CPU 101 performs the number of sliding pieces selection process.

  Next, the main CPU 101 determines a planned stop position based on the stop start position and the number of sliding pieces determined in S719, and stores the determined planned stop position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding frames to the stop start position, and sets the addition result as the planned stop position.

  Next, the main CPU 101 executes symbol code storage processing (S721). In this process, the symbol code corresponding to the scheduled stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel (S722). In this processing, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel based on the value of the stop button non-operating counter, and the value of the stop button non-operating counter is When it is “0”, it is determined that the reel to be controlled is the final stop reel.

  In S722, when the main CPU 101 determines that the reel to be controlled is not the final stop reel (when S722 is NO), the main CPU 101 performs a control change process (S723). In this process, the stop information group used for stopping the reel is updated when the stop position is at a specific stop position. Next, the main CPU 101 performs the pull-in priority storage process described with reference to FIG. 73 (S724).

  Next, the main CPU 101 performs standby interval remaining time standby processing (S725). In this process, the main CPU 101 performs a standby process until a predetermined reel stop interval time has elapsed. After the process of S725, the main CPU 101 returns the process to the process of S711, and repeats the processes after S711.

  Here, the process returns to S722 again, and when the main CPU 101 determines in S722 that the reel to be controlled is the final stop reel (when S722 is YES), the main CPU 101 energizes all reels. It is determined whether or not is in a stopped state (S726). In S726, when the main CPU 101 determines that the excitation of all the reels is not stopped (when S726 is NO), the main CPU 101 repeats the process of S726.

  On the other hand, when the main CPU 101 determines in S726 that the excitation of all the reels is in a stopped state (when S726 is YES), the main CPU 101 remains in the on state in which the stop button operated for the third stop is on. It is determined whether or not (the stop button has not been released) (S727). In S727, when the main CPU 101 determines that the stop button subjected to the third stop operation remains on (when S727 is YES), the main CPU 101 repeats the process of S727. On the other hand, when the main CPU 101 determines in S727 that the stop button for which the third stop operation has been performed is not in the on state (when S727 is NO), the main CPU 101 ends the reel stop control process and performs the process. The process proceeds to S214 in the main flow (see FIG. 54).

  In the present embodiment, the reel stop control process is performed as described above. Note that the processing of S711 to S716 during the reel stop control processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As shown in FIG. 82, in the reel stop control processing source program of this embodiment, the main CPU 101 instruction code, for example, an “LDQ” instruction for addressing using a Q register (extension register), “ The “CALLF” instruction is used.

  Therefore, by using such an instruction code dedicated to the main CPU 101 in the reel stop control process, it is possible to reduce the capacity of the source program for the reel control process and improve the processing efficiency of the reel stop control process. it can. That is, in the present embodiment, it is possible to increase the efficiency of the program processing speed and reduce the capacity in the main control circuit 90, and to utilize the free space of the main ROM 102 increased according to the reduced capacity, Can be increased.

  Further, the determination processing in S726 during the reel stop control processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As shown in FIG. 83, this processing is executed using “LDQ” instruction and “ORQ” instruction (predetermined OR operation instruction) on the source code.

  The “ORQ” instruction is an instruction code for performing an OR operation, and is a dedicated instruction code for the main CPU 101 for performing address designation using a Q register (extension register). For example, when the source code “ORQ (k)” is executed on the source program, the data stored in the Q register (upper address value) and 1-byte integer k (direct value: lower address value) are used. A logical OR operation is performed on the contents (stored data) of the memory at the specified address and the contents (stored data) of the A register, and the calculation result is stored in the A register.

  Therefore, in the determination process of S726 during the reel stop control process, first, when the source code “LDQ A, (.LOW.wR1_TIM)” in FIG. 83 is executed, the data stored in the Q register and the integer value “ . LOW.wR1_TIM ”is loaded into the A register at the address specified by“ LOW.wR1_TIM ”. In the present embodiment, the address of the area storing the excitation timer value of the first reel in the main RAM 103 is “F032h”. In the determination processing of S726 described above, the upper address value “F0h” of the address “wR1_TIM (F032h)” is set in advance in the Q register when the LDQ instruction is executed, and the lower value is set to the value of k (direct value). The address value (“.LOW.wR2_TIM” = 32h) is substituted.

  Next, when the source code “ORQ (.LOW.wR2_TIM)” in FIG. 83 is executed, the address “wR2_TIM () of the storage data (F0h) of the Q register and the excitation timer value of the second reel are stored. F03Dh) ”is obtained by performing an OR operation between the memory contents (excitation timer value of the second reel) at the address specified by the lower address value (3Dh) and the contents of the A register (excitation timer value of the first reel). The calculation result (combination result of the excitation timer value of the first reel and the excitation timer value of the second reel) is stored in the A register. Next, when the source code “ORQ (.LOW.wR3_TIM)” in FIG. 83 is executed, the address “wR3_TIM () of the storage data (F0h) in the Q register and the excitation timer value of the third reel are stored. F048h) ”lower address value (48h), the memory contents (third reel excitation timer value) and the A register contents (first reel excitation timer value and second reel excitation timer). OR operation with the value (combination result with value) is performed, and the operation result (combination result of the excitation timer values of the first to third reels) is stored in the A register.

  As described above, in the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extension register) are used in the reel (rotating cylinder) stop state check process. Therefore, by using these dedicated instruction codes for the main CPU 101, it is possible to access the main ROM 102, the main RAM 103, and the memory map I / O by direct values, and omit instructions related to address setting on the source program. Accordingly, the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  As described above, in the various processes during the reel stop control process of the present embodiment, the above-described various instruction codes dedicated to the main CPU 101 are used as appropriate, thereby realizing the efficiency of the corresponding process and the reduction of the capacity of the source program. ing. As a result, in this embodiment, the efficiency of the program processing of the main control circuit 90 and the reduction of the capacity can be achieved, and it is possible to improve the gameability by utilizing the free space corresponding to the reduced capacity. It becomes.

[Reel stop enable signal OFF processing]
Next, with reference to FIG. 84, the reel stop enable signal OFF process performed in S711 or S717 during the reel stop control process (see FIG. 81) will be described. FIG. 84 is a flowchart showing the procedure of reel stop possible signal OFF processing.

  First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S731). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S732).

  Next, the main CPU 101 saves the data set in all the registers (S733). Next, the main CPU 101 performs a reel stop enable signal OFF data setting process (S734).

  Next, the main CPU 101 performs non-standard port output processing (S735). In this process, the main CPU 101 generates and outputs OFF output data (output off mode data), which will be described later, based on the reel stop enable signal OFF data. This process is performed using an unspecified work area in the main RAM 103. Details of the non-standard port output processing will be described later with reference to FIG. 86 described later.

  Next, the main CPU 101 restores all register data saved in S733 (S736). Next, the main CPU 101 sets the address of the stack area saved in S731 in the stack pointer (SP) (S737).

  Then, after the process of S737, the main CPU 101 ends the reel stop possible signal OFF process. At this time, if the executed reel stop enable signal OFF process is the process of S711 during the reel stop control process (see FIG. 81), the main CPU 101 shifts the process to the process of S712 during the reel stop control process. On the other hand, when the executed reel stop enable signal OFF process is the process of S717 during the reel stop control process (see FIG. 81), the main CPU 101 shifts the process to the process of S718 during the reel stop control process.

[Reel stop enable signal ON process]
Next, with reference to FIG. 85, the reel stop possible signal ON process performed in S713 during the reel stop control process (see FIG. 81) will be described. FIG. 85 is a flowchart showing the procedure of reel stop enable signal ON processing.

  First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S741). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S742).

  Next, the main CPU 101 saves the data set in all the registers (S743). Next, the main CPU 101 refers to the operation stop button storage area (see FIG. 25) and acquires the stop button state (S744). Next, the main CPU 101 performs a reel stop enable signal ON data setting process (S745).

  Next, the main CPU 101 performs non-standard port output processing (S746). In this process, the main CPU 101 generates and outputs ON output data (output on mode data), which will be described later, based on the reel stop enable signal ON data. This process is performed using an unspecified work area in the main RAM 103. Details of the non-standard port output processing will be described later with reference to FIG. 86 described later.

  Next, the main CPU 101 restores all register data saved in S743 (S747). Next, the main CPU 101 sets the address of the stack area saved in S741 to the stack pointer (SP) (S748). After the process of S748, the main CPU 101 ends the reel stop enable signal ON process and shifts the process to the process of S714 in the reel stop control process (see FIG. 81).

[Non-standard port output processing]
Next, with reference to FIG. 86 and FIG. 87, the non-specified port output processing performed in S735 during the reel stop enable signal OFF process (see FIG. 84) and S746 during the reel stop enable signal ON process (see FIG. 85). explain. FIG. 86 is a flowchart showing the procedure of non-standard port output processing. FIG. 87 is a diagram showing an example of a source program for executing non-standard port output processing.

  First, the main CPU 101 determines whether or not the port output setting is the ON output mode (S751). In this process, the main CPU 101 determines that the port output setting is the ON output mode when the reel stop enable signal ON data is set, and when the reel stop enable signal OFF data is set. It is determined that the port output setting is not the ON output mode.

  In S751, when the main CPU 101 determines that the port output setting is the ON output mode (when S751 is YES), the main CPU 101 performs the process of S753 described later. On the other hand, when the main CPU 101 determines in S751 that the port output setting is not in the ON output mode (when S751 is NO), the main CPU 101 performs processing for generating OFF output data (output off mode data) (S752). ). In this process, among the ports (bits) that are currently in the output on state, the ports (bits) that are to be turned off are turned off, and the ports (bits) that are currently in the output off state are turned off. OFF output data for maintaining the state is generated.

  After the processing of S752 or when S751 is NO, the main CPU 101 performs processing for generating ON output data (output on mode data) (S753). In this process, among the ports (bits) that are currently in the output off state, the ports (bits) that are to be turned on are turned on, and the ports (bits) that are currently in the output on state are turned on. ON output data for maintaining the state is generated. Next, the main CPU 101 outputs the generated output data from the designated port (S754).

  Then, after the processing of S754, the main CPU 101 ends the non-standard port output processing. At this time, if the executed non-regulated port output process is the process of S735 during the reel stop enable signal OFF process (see FIG. 84), the main CPU 101 executes the process of S736 during the reel stop enable signal OFF process. Move to. On the other hand, if the executed non-regulated port output process is the process of S746 during the reel stop enable signal ON process (see FIG. 85), the main CPU 101 shifts the process to the process of S747 during the reel stop enable signal ON process. Move.

  In the present embodiment, the non-specified port output process is performed as described above. The non-specified port output processing described above is performed by the main CPU 101 sequentially executing each source code specified by the source program of FIG.

  Among them, the generation processing of the OFF output data in S752 during the non-regulated port output processing described above is to execute the source codes “XOR (HL)” and “AND (HL)” in FIG. 87 in this order. Done. The generation processing of the ON output data in S753 during the non-specified port output processing described above is performed by executing the source code “OR (HL)” in FIG.

  By performing such output data generation processing on the source program, the OFF output data generated in S752 even if the ON output data generation processing in S753 is performed after the OFF output data generation processing in S752. Does not change.

  For example, the port output setting is the OFF output mode, the output data indicating the non-standard port to be turned off in this processing is “000111011” (“1” is the bit to be turned off), and the non-standard port is currently set. When the output data (backup data) output to is “01010011” (“1” is currently an on-state bit), the data of bit 0, bit 1 and bit 5 of the backup data is changed from “1” to “1”. OFF output data for generating “0” is generated. In this case, first, when the source code “XOR (HL)” in FIG. 87 is executed, an exclusive OR operation between the output data “00010111” and the backup data “01010011” is performed, and the operation result is “ 01000100 "is obtained. Next, when the source code “AND (HL)” in FIG. 87 is executed, a logical product operation of the operation result “01000100” and the backup data “01010011” is performed, and the operation result “01000000” is used as OFF output data. Generated.

  After that, when the ON output data generation process of S753 (source code “OR (HL)” in FIG. 87) is executed, the calculation result “01000000” (OFF output data) is turned on in this process. An OR operation is performed on the output data “00000000” indicating the non-standard port to be set (the port output setting is the OFF output mode, so each bit of the output data is set to “0”). “01000000” is obtained, and the OFF output data does not change. Qualitatively, when the port output setting is the OFF output mode, the output for maintaining the port (bit) that is in the output ON state in the OFF output data in the ON output data generation processing in S753 is maintained in the ON state. Since the data is generated, the OFF output data generated in S752 does not change even if the ON output data generation processing in S753 is performed after the OFF output data generation processing in S752.

[Winning Search Processing]
Next, with reference to FIGS. 88 and 89, the winning search process performed in S214 in the main flow (see FIG. 54) will be described. FIG. 88 is a flowchart showing a procedure for winning search processing. FIG. 89 is a diagram showing an example of a source program for executing a winning search process.

  First, the main CPU 101 transfers and stores the data in each storage area stored in the symbol code storage area (see FIG. 27) to the corresponding storage area in the winning action flag storage area (see FIG. 22) (S761). . At the end of this process, the last address of the winning operation flag storage area is set in the DE register.

  Next, the main CPU 101 sets the address of the payout number data table (not shown) in the HL register (S762). Next, the main CPU 101 sets the number of payout number tables as the initial value of the winning search counter, and sets the initial value in the B register (S763).

  Next, the main CPU 101, based on the address set in the HL register, data of the number of medals to be paid out (in this embodiment, any one of 14, 13, 9, 7, 3, and 1). Is set in the C register, the determination target data is set in the A register, and "2" is added (+2 update) to the address set in the HL register (S764).

  Next, the main CPU 101 extracts the value of the determination bit from the medal payout number data set in the C register (S765). This determination bit is information indicating whether or not it is a determination target block for winning search. Next, the main CPU 101 determines whether the block is a determination target block based on the extracted determination bit value (S766). In this process, the main CPU 101 determines that the block is a determination target block when the value of the extracted determination bit is “1”.

  In S766, when the main CPU 101 determines that the block is not a determination target block (when S766 is NO), the main CPU 101 performs a process of S768 described later. On the other hand, when the main CPU 101 determines in S766 that the block is a determination target block (when S766 is YES), the main CPU 101 subtracts 1 from the address of the winning action flag storage area set in the DE register (- 1 update) (S767).

  After the process of S767 or when S766 is NO, the main CPU 101 extracts the data in the storage area specified by the address of the winning action flag storage area set in the DE register as the determination data (S768).

  Next, the main CPU 101 determines whether or not the determination result is a win based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, if the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a win.

  In S769, when the main CPU 101 determines that the result of the determination is not a win (when S769 is NO), the main CPU 101 performs a process of S776 described later. On the other hand, when the main CPU 101 determines in S769 that the result of the determination is a win (when S769 is YES), the main CPU 101 determines that the current game is three games (the number of medals bet is three). ) Is determined (S770).

  In S770, when the main CPU 101 determines that the current game is a three-game game (when S770 is YES), the main CPU 101 performs the process of S772 described later. On the other hand, when the main CPU 101 determines in S770 that the current game is not a three-game (when S770 is NO), the main CPU 101 pays out a two-game (a game with two medal bets). The number of sheets (2 sheets) is set in the C register (S771). In this embodiment, the number of games that can be started is three (see FIG. 18), so the process of S770 is always YES.

  After the processing of S771 or when S770 is YES, the main CPU 101 performs payout number update processing (S772). Specifically, the main CPU 101 adds the payout number of medals set in the C register to the current value of the winning number counter, and sets the value after the addition as the payout number.

  Next, the main CPU 101 determines whether or not the value of the payout number is less than the maximum payout number “14” (S773).

  In S773, when the main CPU 101 determines that the value of the payout number is less than the maximum payout number “14” (when S773 is YES), the main CPU 101 performs the process of S775 described later. On the other hand, when the main CPU 101 determines in S773 that the value of the payout number is not less than the maximum payout number “14” (NO in S773), the main CPU 101 sets the maximum payout number “14” as the payout number. (S774).

  After the processing of S774 or if S773 is YES, the main CPU 101 stores the payout number in the winning number counter (S775).

  After the processing of S775 or when S769 is NO, the main CPU 101 determines whether or not there is another winning (S776). When the main CPU 101 determines that there is another winning in S776 (when S776 is YES), the main CPU 101 returns the process to the process of S769 and repeats the processes after S769.

  On the other hand, when the main CPU 101 determines in S776 that there are no other winnings (when S776 is NO), the main CPU 101 subtracts 1 from the winning search counter (-1 update) (S777). Note that, when there is one active line as in the present embodiment, a plurality of small roles will not be won in duplicate, so the process of S776 is always NO.

  Next, the main CPU 101 determines whether or not the value of the winning search counter is “0” (S778).

  In S778, when the main CPU 101 determines that the value of the winning search counter is not “0” (when S778 is NO), the main CPU 101 returns the process to the process of S764 and repeats the processes after S764. On the other hand, when the main CPU 101 determines in S778 that the value of the winning search counter is “0” (in the case where S778 is YES), the main CPU 101 ends the winning search process, and the process proceeds to the main flow (FIG. 54), the process proceeds to S215.

  In the present embodiment, the winning search process is performed as described above. The winning search process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. Among these, the payout number and determination target data setting processing in S764 is performed by the main CPU 101 executing the source code “LDIN AC, (HL)”.

  For example, when the source code “LDIN ss, (HL)” is executed on the source program, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (added by 2). Therefore, when the source code “LDIN AC, (HL)” in FIG. 89 is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( The payout number and determination target data) are loaded into the AC register, and the address set in the HL register is updated by +2 (added by 2). In the process of S764, in accordance with the “LDIN” instruction, the payout number data is stored in the A register, the determination target data is stored in the C register, and the address set in the HL register is updated by +2.

  As described above, in the winning search process of the present embodiment, both the data load process and the address update process can be performed by one “LDIN” instruction. In this case, an instruction relating to address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  In addition, the medal counter value acquisition process referred to in the determination process of S770 during the above-described winning search process, the winning sheet counter value acquisition process referred to in the process of S772, and the winning number counter executed in the process of S775. As shown in FIG. 89, all the storage (update) processes are executed by an “LDQ” instruction (instruction code dedicated to the main CPU 101) for specifying an address using a Q register (extended register). Therefore, in the winning search process of the present embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values by using the “LDQ” instruction. A command related to the setting can be omitted (there is no need to separately provide a command related to the address setting), and accordingly, the capacity of the source program (used capacity of the main ROM 102) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  Further, the determination process in S769 during the above-described winning search process is executed by a “JSLAA” instruction (predetermined determination instruction) on the source program as shown in FIG. The “JSLAA” instruction is an instruction for executing an operation equivalent to a left shift (SLA) instruction.

  For example, when the source code “JSLAA cc, e” is executed on the source program, if the condition of cc is satisfied, the process is jumped to the address specified by e. The “cc condition” defined by the “JSLAA” instruction specifies the state of the carry flag in the flag register F. For example, if “C” is specified for cc, the condition of cc means that the carry flag is “1” (ON state), and if “NC” is specified for cc, the condition of cc Means that the carry flag is “0” (off state). Therefore, in the source code “JSLAA NC, MN_CKLN — 06” in FIG. 89, if the carry flag is “0” (off state), the process jumps to the address specified by “MN_CKLN — 06”.

  Further, the determination processing of S770 and S773 during the winning search processing described above is executed by the “JCP” instruction on the source program as shown in FIG. As described above, the “JCP” instruction is an instruction for executing an operation corresponding to the comparison instruction, and is a dedicated instruction code for the main CPU 101.

  Therefore, when the above-described “JSLAA” instruction and “JCP” instruction are used in the source program for winning search processing, the instruction for address setting can be omitted (the instruction for address setting needs to be provided separately). Therefore, the capacity of the source program (capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Illegal hit check processing]
Next, the illegal hit check process performed in S215 in the main flow (see FIG. 54) will be described with reference to FIGS. FIG. 90 is a flowchart showing the procedure of the illegal hit check process. FIG. 91 is a diagram showing an example of a source program for executing illegal hit check processing. The illegal hit is a lottery in the internal lottery process (see FIG. 64) and based on the internal winning combination stored in the winning request flag storage area in the symbol setting process, the left reel 3L, the middle reel 3C and the right reel 3R. Is a term indicating that a combination of symbols that cannot be established in (i.e., a combination of symbols that are not permitted to be stopped) is stopped on the active line (design combination is not established).

  First, the main CPU 101 sets the address of the winning action flag storage area (see FIG. 22) (S781). Next, the main CPU 101 sets the size (number of bytes, “7” in this embodiment) of the winning action flag storage area to the value of the check counter (S782).

  Next, the main CPU 101, based on the address of the currently set winning action flag storage area, stores the internal winning combination stored in the storage area in the winning request flag storage area (internal winning combination storage area) corresponding to the address. (Hit request flag data) is acquired (S783). Next, the main CPU 101 synthesizes the winning combination data (winning operation flag data) stored at the address of the currently set winning operation flag storage area and the internal winning combination data (winning request flag data) ( S784).

  In this composition process, first, the main CPU 101 obtains an exclusive OR of the winning combination data (winning operation flag data) and the internal winning combination data (winning request flag data) (source program shown in FIG. 91). Source code "XOR (HL)"). Next, the main CPU 101 obtains a logical product of the obtained exclusive OR calculation result and winning combination data (winning operation flag data) (source code “AND (HL)” in the source program shown in FIG. 91). ), The calculation result of the logical product is taken as the synthesis result. If an illegal hit error has not occurred, the value of the synthesis result is “0”.

  Next, the main CPU 101 determines whether an illegal hit error has occurred based on the result of the synthesis process in S784 (S785).

  In S785, when the main CPU 101 determines that an illegal hit error has not occurred (when S785 is NO), the main CPU 101 updates the address of the winning action flag storage area to be referred to by +1 (S786). Next, the main CPU 101 subtracts 1 from the value of the check counter (S787). Next, the main CPU 101 determines whether or not the value of the check counter is “0” (S788).

  In S788, when the main CPU 101 determines that the value of the check counter is not “0” (when S788 is NO), the main CPU 101 returns the process to the process of S783 and repeats the processes after S783. On the other hand, in S788, when the main CPU 101 determines that the value of the check counter is “0” (when S788 is YES), the main CPU 101 ends the illegal hit check process, and the process proceeds to the main flow (FIG. 54), the process proceeds to S216.

  Here, returning to the processing of S785 again, when the main CPU 101 determines in S785 that an illegal hit error has occurred (in the case where S785 is YES), the main CPU 101 performs error processing described with reference to FIG. (S789). By this process, the two characters “EE” indicating the occurrence of the illegal hit error are displayed as error information on the 2-digit 7-segment LED (used for displaying the number of payouts and for error display) included in the information display 6. Error display data is output. The occurrence state (error state) of the illegal hit error is canceled by pressing the reset switch 76 (see FIG. 7).

  Next, the main CPU 101 clears the value of the winning number counter and the data in the winning request flag storage area (S790). After the process of S790, the main CPU 101 ends the illegal hit check process, and moves the process to the process of S216 in the main flow (see FIG. 54).

  In the present embodiment, the illegal hit check process is performed as described above. The illegal hit check process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  In this embodiment, as shown in FIG. 22, the structure of the winning action flag storage area (display combination storage area) is the same as that of the winning request flag storage area (internal winning combination storage area). The winning request flag storage area and the winning action flag storage area arranged in the main RAM 103 during the combination process of the combination of the storage area and the internal winning combination can be configured in the same configuration. Therefore, the calculation result of S784 in the illegal hit check process of the present embodiment (the result of combining the winning combination data and the internal winning combination data) is, as described above, the winning combination data and the internal It is obtained by simply ANDing (executing with an “AND” instruction) with the winning data. As a result, in this embodiment, the illegal hit check process can be streamlined and simplified, the free capacity of the main control program can be secured (increased), and the increased free capacity can be used to increase game play. It becomes possible to increase.

[Winning check / medal payout processing]
Next, with reference to FIG. 92 and FIG. 93, the winning check / medal payout process performed in S216 in the main flow (see FIG. 54) will be described. FIG. 92 is a flowchart showing the procedure of the winning check / medal payout process. FIG. 93 is a diagram showing an example of a source program for executing the processes of S804 to S808 described later during the winning check / medal payout process.

  First, the main CPU 101 performs a winning operation command generation process (S801). In this process, the main CPU 101 generates type data and various communication parameters included in the winning action command transmitted to the sub control circuit 200. The winning action command includes a parameter for specifying a winning action flag (display combination) and the like.

  Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 44 (S802). With this process, the winning operation command data is stored in the communication data storage area (see FIG. 47B) provided in the main RAM 103. The winning operation command is transmitted from the main control circuit 90 to the sub-control circuit 200 by communication data transmission processing in the interrupt processing described with reference to FIG.

  Next, the main CPU 101 determines whether or not the value of the winning number counter is “0” (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is “0” (in the case of YES determination in S803), the main CPU 101 ends the winning check / medal payout process, and the process proceeds to the main flow ( The process proceeds to S217 in FIG.

  On the other hand, in S803, when the main CPU 101 determines that the value of the winning number counter is not “0” (NO in S803), the main CPU 101 determines that the number of credits (stored number) of medals is the upper limit number (the number of books). It is determined whether or not the number is 50 or more in the embodiment (S804).

  In S804, when the main CPU 101 determines that the number of credits of the medal is not equal to or greater than the upper limit (when S804 is NO), the main CPU 101 adds “1” to the value of the credit counter (+1 update) ( S805). The added credit counter value is displayed by a two-digit 7-segment LED (not shown) for displaying the number of stored sheets included in the information display 6. Next, the main CPU 101 performs a medal payout number check process (S806). Details of the medal payout number check process will be described later with reference to FIG. 94 described later.

  Next, the main CPU 101 determines whether or not the medals have been paid out (S807). When the main CPU 101 determines in S807 that the payout of medals has ended (when S807 is YES), the main CPU 101 ends the winning check / medal payout process, and the process is in the main flow (see FIG. 54). The process proceeds to S217.

  On the other hand, when the main CPU 101 determines in S807 that the payout of medals has not ended (when S807 is NO), the main CPU 101 performs payout interval waiting processing (S808). In this process, the main CPU 101 waits until a preset medal payout interval time (in this embodiment, 60.33 msec: 54 cycles of an interrupt process (1.1172 msec cycle) described later with reference to FIG. 100). Wait. After the process of S808, the main CPU 101 returns the process to the process of S803 and repeats the processes after S803.

  Here, returning to the processing of S804 again, when the main CPU 101 determines in S804 that the number of credits of medals is equal to or greater than the upper limit number (50) (when S804 is YES), the main CPU 101 A medal payout process is performed (S809). Through this process, one medal is paid out. After the processing of S809, the main CPU 101 ends the winning check / medal payout processing, and moves the processing to S217 in the main flow (see FIG. 54).

  In the present embodiment, the winning check / medal payout process is performed as described above. Note that the processing of S804 to S808 during the above-described winning check / medal payout processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG.

  In this embodiment, when the payout operation is continued after the credit counter is updated (+1), the main CPU 101 performs a wait (payout interval waiting) process for 60.33 ms in the process of S808. On the source program, the main CPU 101 executes the source codes “LD BC, cTM_PAYC” and “RST SB_W1BC_00” in this order. In this way, in the winning check / medal payout process, when the payout operation is continued after the credit counter is updated (+1), when waiting for 60.33 ms (waiting for payout interval) is performed, useless waiting time is reduced. Can reduce the mental burden of the player.

[Medal payout number check process]
Next, with reference to FIG. 94 and FIG. 95, the medal payout number check process performed in S806 during the winning check / medal payout process (see FIG. 92) will be described. FIG. 94 is a flowchart showing the procedure of the medal payout number check process. FIG. 95A is a diagram showing an example of a source program for executing the later-described processing of S811 to S814 during the medal payout number check process, and FIG. 95B shows later-described S816 and the medal payout number check process during the medal payout number check process. It is a figure which shows an example of the source program for performing the process of S817.

  First, the main CPU 101 adds “1” to the value of the medal OUT counter (+1 update) (S811). The medal OUT counter is a counter for counting the number of medals paid out. Next, the main CPU 101 adds “1” to the value of the payout number counter (+1 update) (S812). The payout number counter is a counter for counting the number of medals to be paid out.

  Next, the main CPU 101 performs a payout number 7 SEG display process (S813). In this process, the main CPU 101 performs a control process for displaying the value of the payout number counter by a 2-digit 7-segment LED (not shown) for displaying the payout number included in the information display 6.

  Next, the main CPU 101 performs update processing of the combination end number counter (S814). The consecutive end number counter is a counter for counting the remaining number of medals to be paid out corresponding to the winning combination. In this process, the main CPU 101 compares the value of the consecutive end number counter with its lower limit “0”, and when the value of the end of consecutive number counter is greater than the lower limit “0”, The counter value is decremented by 1 (-1 is updated), and when the value of the combination end number counter is equal to or lower than the lower limit “0”, the value of the combination end number counter is held at “0”.

  Next, the main CPU 101 subtracts 1 (updates -1) the value of the winning number counter (S815).

  Next, the main CPU 101 performs a credit information command generation process (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command transmitted to the sub control circuit 200. The credit information command includes a parameter for specifying the number of medals for credit.

  Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 44 (S817). By this processing, the credit information command data is stored in a communication data storage area (see FIG. 47B) provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub-control circuit 200 by communication data transmission processing in the interrupt processing described with reference to FIG. After the process of S817, the main CPU 101 ends the medal payout number check process, and shifts the process to the process of S807 in the winning check / medal payout process (see FIG. 92).

  In the present embodiment, the medal payout number check process is performed as described above. Note that the processing of S811 to S814 during the above-described medal payout number check processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 95A. Among them, the update processing of the combination end number counter in S814 is executed by the “DCPLD” command (predetermined update command) in FIG. 95A. The “DCPLD” instruction is an instruction code dedicated to the main CPU 101.

  For example, when the source code “DCPLD (HL), n” is executed on the source program, the contents (stored data) of the memory at the address specified by the HL register are compared with the integer n, and the contents of the memory are If it is larger than the integer n, 1 is subtracted from the contents of the memory, and if the memory content is less than or equal to the integer n, the integer n is stored in the memory at the address specified by the HL register. Therefore, when the source code “DCPLD (HL), 0” in FIG. 95A is executed, the contents of the memory at the address specified by the HL register (value of the consecutive end number counter) and the integer 0 (lower limit) Are compared, and if the memory content (the value of the combination end number counter) is larger than the integer 0, the memory content is decremented by 1, and if the memory content is less than or equal to the integer 0, the memory content “0” is set to (the value of the counter end number counter). In other words, if the current value of the consecutive end number counter is greater than “0”, the update process of the consecutive end number counter is performed, and if the current end of number counter value is “0” or less. Then, a process of holding the value of the combination end number counter at “0” is performed.

  As described above, in the process of S814 during the medal payout number check process, the number of consecutively completed sheets is determined by one “DCPLD” command (a command that combines the lower limit determination command of the number management counter and the determination branch command). Both the counter update (subtraction) process and the process of holding the value of the consecutive end number counter at “0” can be executed. In this case, there is no need to provide an instruction code for executing both processes separately. For example, the determination branch instruction code for determining whether or not the value of the consecutive end number counter is “0” can be omitted. Therefore, in the medal payout number check process according to the present embodiment, the capacity of the source program (usage capacity of the main ROM 102) can be reduced, and a free capacity can be secured (increased) in the main ROM 102. It is possible to improve the playability by utilizing the free space.

  Also, the processing of S816 and S817 during the above-described medal payout number check processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 95B.

  Among them, in the process of S816, as shown in FIG. 95B, the communication parameter 1 of the credit information command is set with the value of the payout number counter via the L register, and the communication parameter 5 is credited via the C register. The counter value is set. However, values (undefined values) stored in the H register, E register, and D register at the present time are set in the other communication parameters 2 to 4 constituting the credit information command. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[Bonus check processing]
Next, with reference to FIG. 96, the bonus check process performed in S217 in the main flow (see FIG. 54) will be described. FIG. 96 is a flowchart showing the procedure of the bonus check process.

  First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S821). That is, the main CPU 101 determines whether or not the current gaming state is the BB gaming state or the MB gaming state. In S821, when the main CPU 101 determines that the current gaming state is not a bonus state (when S821 is NO), the main CPU 101 performs a process of S826 described later.

  On the other hand, when the main CPU 101 determines in S821 that the current gaming state is the bonus state (when S821 is YES), the main CPU 101 counts the number of medals that can be paid out during the bonus state. The payout number of medals paid out in the winning check / medal payout process is subtracted from the value of the bonus payout number counter (S822).

  Next, the main CPU 101 determines whether or not the value of the bonus bonus payout counter is less than “0” (S823). When the main CPU 101 determines in S823 that the value of the bonus payout counter is not less than “0” (when S823 is NO), the main CPU 101 determines that the current gaming state is the BB gaming state. The state (RB in operation) is maintained, and if the current game state is the MB game state, a process of maintaining the CB game state (CB in operation) is performed (S824). Specifically, in the gaming state flag storage area (see FIG. 24), when “1” is stored in bit 0 (BB gaming state), “1” is always set in bit 1 (RB gaming state). When “1” is stored in bit 2 (MB gaming state), “1” is always stored in bit 3 (CB gaming state). Thus, during the BB gaming state (BB operation), the RB gaming state (RB operation) is always controlled, and during the MB gaming state (MB operation), the CB gaming state (CB operation) is always controlled. The Then, after the process of S824, the bonus check process is terminated, and the process proceeds to the process of S218 in the main flow (see FIG. 54).

  On the other hand, when the main CPU 101 determines in S823 that the value of the bonus payout number counter is less than “0” (when S823 is YES), the main CPU 101 performs a bonus end time process (S825). In this process, the main CPU 101 clears various information in the bonus state (for example, at the end of the BB gaming state, the BB gaming state flag and the RB gaming state flag are turned off (“0” cleared), and MB At the end of the gaming state, the MB gaming state flag and the CB gaming state flag are turned off ("0" cleared), and at the end of the BB gaming state, all the RT state flags are set to the off state. (In other words, the RT state is changed to the RT0 state). And after the process of S825, a bonus check process is complete | finished and a process is moved to the process of S218 in a main flow (refer FIG. 54).

  Here, returning to the processing of S821 again, if S821 is NO, the main CPU 101 determines whether BB or MB is established (S826). That is, the main CPU 101 determines whether or not a symbol combination of BB or MB (a symbol combination of “C_BB” or “C_MB”) is displayed in the current game. In S826, when the main CPU 101 determines that BB or MB has not been established (NO in S826), the main CPU 101 ends the bonus check process, and the process proceeds to S218 in the main flow (see FIG. 54). Move on to processing.

  On the other hand, when the main CPU 101 determines in step S826 that BB or MB has been established (YES in step S826), the main CPU 101 sets “144” as the value of the bonus payout number counter (S827). Next, the main CPU 101 determines whether or not MB is established (S828). In S828, when the main CPU 101 determines that MB is not established (that is, BB is established) (when S828 is NO), the main CPU 101 performs processing of S830 described later.

  On the other hand, when the main CPU 101 determines in S828 that MB has been established (that is, BB has not been established) (in the case where S828 is YES), the main CPU 101 sets “13 Is set (S829). That is, the main CPU 101 overwrites the value of the bonus payout number counter from “144” to “13”. As a result, in this embodiment, the BB gaming state (in BB) ends when more than “144” medals are paid out, and the MB gaming state (in MB) exceeds “13” medals. It is set to end when there is a payout. Note that the value of the bonus payout number counter represents an example of the present embodiment, and this value can be set by varying as appropriate.

  Next, the main CPU 101 performs a bonus start process (S830). In this process, for example, the main CPU 101 sets a bonus state in the gaming state of the next game (for example, at the start of the BB gaming state, the BB gaming state flag and the RB gaming state flag are turned on ("1" is set). When the MB gaming state is started, various processes necessary for starting the bonus operation such as turning on the MB gaming state flag and the CB gaming state flag (setting “1”) are performed. Then, after the process of S830, the main CPU 101 ends the bonus check process and shifts the process to the process of S218 in the main flow (see FIG. 54).

[RT check processing]
Next, the RT check process performed in S218 in the main flow (see FIG. 54) will be described with reference to FIG. FIG. 97 is a flowchart showing the procedure of the RT check process.

  First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S841). That is, the main CPU 101 determines whether or not the current gaming state is the BB gaming state or the MB gaming state. In S841, when the main CPU 101 determines that the current gaming state is a bonus state (when S841 is YES), the main CPU 101 ends the RT check process, and the process is in the main flow (see FIG. 54). The process proceeds to S219.

  On the other hand, when the main CPU 101 determines in S841 that the current gaming state is not the bonus state (when S841 is NO), the main CPU 101 determines whether or not the RT state is the RT4 state (S842). . In S842, when the main CPU 101 determines that the RT state is the RT4 state (when S842 is YES), the main CPU 101 ends the RT check process, and the process proceeds to S219 in the main flow (see FIG. 54). Move on to processing.

  On the other hand, when the main CPU 101 determines in step S842 that the RT state is not the RT4 state (if NO in step S842), the main CPU 101 determines whether or not the symbol combination “bell spilled” is displayed (step S842). S843). That is, the main CPU 101 determines whether or not one of the symbol combinations “S_RT1 transition A”, “S_RT1 transition B”, and “S_RT1 transition C” is displayed on the active line. In S843, when the main CPU 101 determines that the symbol combination of “bell spilling” is displayed (when S843 is YES), the main CPU 101 performs the process of S845 described later.

  On the other hand, when the main CPU 101 determines in S843 that the symbol combination of “bell spilled eyes” has not been displayed (when S843 is NO), the main CPU 101 displays the symbol combination of “RT1 transition lip”. It is determined whether or not (S844). That is, the main CPU 101 determines whether or not one of the symbol combinations “S_RT1 Lip A” and “S_RT1 Lip B” is displayed on the active line. In S844, when the main CPU 101 determines that the symbol combination “RT1 transition lip” is not displayed (when S844 is NO), the main CPU 101 performs the process of S846 described later.

  When the main CPU 101 determines in S843 that the symbol combination “bell bell spill” is displayed (when S843 is YES), and in S844, the main CPU 101 displays the symbol combination “RT1 transition lip”. When it is determined that the determination has been made (in the case where S844 is YES), the main CPU 101 sets the RT1 state flag to the on state (S845). With this process, when the RT state is another RT state, the RT state is shifted to the RT1 state. After the process of S845, the main CPU 101 ends the RT check process and moves the process to the process of S219 in the main flow (see FIG. 54).

  Here, returning to the processing of S844 again, if S844 is NO, the main CPU 101 determines whether or not the symbol combination “RT2 transition lip” is displayed (S846). That is, the main CPU 101 determines whether or not the symbol combination “C_RT2 Lip” is displayed on the active line. In S846, when the main CPU 101 determines that the symbol combination “RT2 transition lip” has not been displayed (when S846 is NO), the main CPU 101 performs processing in S848 described later.

  On the other hand, when the main CPU 101 determines in S846 that the symbol combination “RT2 transition lip” is displayed (YES in S846), the main CPU 101 sets the RT2 state flag to the on state (S847). With this process, when the RT state is another RT state, the RT state is shifted to the RT2 state. After the process of S847, the main CPU 101 ends the RT check process, and moves the process to S219 in the main flow (see FIG. 54).

  Here, the process returns to S846 again, and when S846 is NO, the main CPU 101 determines whether or not the symbol combination “RT3 transition lip” is displayed (S848). That is, the main CPU 101 determines whether or not one of the symbol combinations “S_RT3 Lip”, “C_SP_CL Lip”, “C_SP_XU Lip”, and “C_SP_XD Lip” is displayed on the active line. In S848, when the main CPU 101 determines that the symbol combination “RT3 transition lip” has not been displayed (NO in S846), the main CPU 101 ends the RT check process, and the process proceeds to the main flow (FIG. 54). The process proceeds to S219.

  On the other hand, when the main CPU 101 determines that the symbol combination “RT3 transition lip” is displayed in S848 (when S848 is YES), the main CPU 101 sets the RT3 state flag to the on state (S849). By this process, when the RT state is another RT state, the RT state is shifted to the RT3 state. After the process of S849, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 54).

[Control processing by state at the end of the game]
Next, with reference to FIG. 98, a description will be given of the game end state control process performed in S219 in the main flow (see FIG. 54). FIG. 98 is a flowchart showing the procedure of the state-by-state control process at the end of the game.

  First, the main CPU 101 determines whether or not the current game is in ART (see FIG. 14) (S861). In S861, when the main CPU 101 determines that the current game is not in ART (when S861 is NO), the main CPU 101 performs processing of S865 described later.

  On the other hand, when the main CPU 101 determines in S861 that the current game is in ART (when S861 is YES), the main CPU 101 determines whether or not the current game is in a continuous challenge (see FIG. 14). A determination is made (S862). In S862, when the main CPU 101 determines that the current game is in a continuous challenge (in the case where S862 is YES), the main CPU 101 performs an end-of-continuation challenge process (S863). The details of the end-of-continuation challenge process will be described later with reference to FIG. Then, after the process of S863, the main CPU 101 ends the control process according to the state at the end of the game, and moves the process to S201 of the main flow (see FIG. 54).

  On the other hand, when the main CPU 101 determines in S862 that the current game is not in a continuous challenge (in the case where S862 is NO), the main CPU 101 performs other state-specific control processing during the ART game (S864). In this other control process according to the state at the end of the game during ART, for example, when a BB winning (operation) occurs, a process of shifting from the next game to the BB CP special zone is performed. Then, after the process of S864, the main CPU 101 ends the control process according to the state at the end of the game, and moves the process to S201 of the main flow (see FIG. 54).

  Here, returning to the processing of S861 again, if S861 is NO, the main CPU 101 performs other normal state control processing by state (S865). In the other normal state control process at the end of the game, for example, when a BB win (actuation) is made, a process of shifting from the next game to the BB history special zone is performed. Then, after the process of S865, the main CPU 101 ends the control process according to the state at the end of the game, and moves the process to S201 of the main flow (see FIG. 54).

[Processing at the end of a continuous challenge]
Next, with reference to FIG. 99, the continuous challenge end process performed in S863 in the game end state control process (see FIG. 98) will be described. FIG. 99 is a flowchart showing a procedure of processing at the end of continuous challenge.

  First, the main CPU 101 determines whether or not the promotion chance activation flag is on (S871). In S871, when the main CPU 101 determines that the promotion chance activation flag is not on (when S871 is NO), the main CPU 101 performs the process of S874 described later.

  On the other hand, when the main CPU 101 determines in S871 that the promotion chance activation flag is on (when S871 is YES), the main CPU 101 sets a promotion chance (S872). That is, the main CPU 101 performs control to shift from the next unit game to a promotion chance. Next, the main CPU 101 sets a continuation challenge as a pre-start state (S873). In other words, the main CPU 101 stores information for performing control to shift to the continuous challenge again when the transferred promotion chance ends. After the process of S873, the main CPU 101 ends the process at the end of the continuous challenge, and moves the process to S201 of the main flow (see FIG. 54).

  Here, returning to the process of S871 again, if S871 is NO, the main CPU 101 determines whether or not CP is 0 (S874). That is, the main CPU 101 determines whether or not all acquired CPs are consumed in the continuous challenge. In S874, when the main CPU 101 determines that the CP is not 0 (when S874 is NO), the main CPU 101 ends the process at the end of the continuous challenge, and the process is the main flow (see FIG. 54). To S201.

  On the other hand, when the main CPU 101 determines that the CP has become 0 in S874 (when S874 is YES), the main CPU 101 determines whether or not the ART game number counter is 0 (S875). That is, the main CPU 101 determines whether or not the number of ART games is added in the continuation challenge. In S875, when the main CPU 101 determines that the ART game number counter is not 0 (when S875 is NO), the main CPU 101 performs the process of S878 described later.

  On the other hand, when the main CPU 101 determines that the ART game number counter is 0 in S875 (when S875 is YES), the main CPU 101 determines whether or not the ART stock counter is 0 (S876). . That is, the main CPU 101 determines whether there is an ART stock. In S876, when the main CPU 101 determines that the ART stock counter is not 0 (when S876 is NO), the main CPU 101 performs a process of subtracting “1” from the ART stock counter (S877).

  Next, the main CPU 101 performs an ART transition initial setting process (S878). In this ART transition process setting process, if the number of ART games is added in the continuous challenge, a process for returning to the normal ART of the set is performed with the number of ART games, and the number of ART games is added in the continuous challenge. If not, a process for starting the next set of normal ART is performed. In this case, the promotion lottery for the promotion chance can be performed in this process. After the process of S878, the main CPU 101 ends the process at the end of the continuous challenge, and moves the process to S201 of the main flow (see FIG. 54).

  On the other hand, when the main CPU 101 determines that the ART stock counter is 0 in S876 (when S876 is YES), the main CPU 101 performs normal transition initial setting processing (S879). In the normal transition initial setting process, the game state is shifted in the normal state, the lottery at the end of the normal mode ART is performed, and the determined normal mode is set. After the process of S879, the main CPU 101 ends the process at the end of the continuous challenge, and moves the process to S201 of the main flow (see FIG. 54).

[Interrupt processing under the control of the main CPU (1.1172 msec)]
Next, an interrupt process performed by the main CPU 101 at a cycle of 1.1172 msec will be described with reference to FIG. FIG. 100 is a flowchart showing the procedure of interrupt processing. 1. Interrupt processing repeatedly executed at a period of 1172 msec is generated based on the output timing of the time-out signal of the timer circuit 113 set in the initialization processing (see S2 in FIG. 36) of the timer circuit 113 (PTC). This is a process executed when an interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

  First, the main CPU 101 performs a register saving process (S901). Next, the main CPU 101 performs input port check processing (S902). In this process, signals input from various switches such as a stop switch are checked.

  Next, the main CPU 101 performs a reel control process (S903). In this process, the main CPU 101 starts rotation of the left reel 3L, the middle reel 3C, and the right reel 3R when the start of rotation of all reels is requested, and thereafter, each reel rotates at a constant speed. Three stepping motors are driven and controlled. When the number of sliding symbols is determined, the main CPU 101 updates the symbol counter of the corresponding reel by the number of sliding symbols. Then, the main CPU 101 waits for the updated symbol counter to match the value corresponding to the planned stop position (the symbol at the planned stop position reaches the area on the effective line of the display window), and The corresponding stepping motor is driven and controlled so that the rotation is decelerated and stopped.

  Next, the main CPU 101 performs communication data transmission processing (S904). In this processing, various commands stored in the communication data storage area are mainly transmitted to the sub control circuit 200 via the first serial communication circuit 114 (see FIG. 9) of the main control circuit 90. After transmitting a command to the sub control circuit 200, the main CPU 101 subtracts and updates the communication data pointer by one packet (not shown), and clears the transmitted command data in the communication data storage area. If a plurality of command data is stored in the communication data storage area, the command data is transmitted to the sub-control circuit 200 in the oldest stored order. When no command data is stored in the communication data storage area, that is, when the value of the communication data pointer is “0”, a no-operation command is generated and transmitted to the sub-control circuit 200. Next, the main CPU 101 performs inserted medal passage check processing (S905). In this process, the main CPU 101 checks whether or not the inserted medal has passed through the selector 66 based on the detection result (medal sensor input state) of the medal sensor (not shown). Next, the main CPU 101 performs a WDT restart process (S906).

  Next, the main CPU 101 performs a 7-segment LED drive process (S907). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display 6 and displays, for example, the number of medals paid out, the number of credits, stop button pressing order data, and the like. The details of the 7-segment LED drive process will be described later with reference to FIG.

  Next, the main CPU 101 performs timer update processing (S908). In this processing, the main CPU 101 performs count (subtraction) processing for various timers that have been set. Details of the timer update process will be described later with reference to FIG.

  Next, the main CPU 101 performs error detection processing (S909). Next, the main CPU 101 performs a door open / close check process (S910). In the door open / close check process, the main CPU 101 checks the open / closed state of the front door 2b (see FIG. 2) by checking the on / off (door closed) / off (door open) state of the door open / close monitoring switch 67.

  Next, the main CPU 101 performs a test firing test signal control process (S911). In this processing, control processing is performed when various test signals are output to the testing machine via the second interface boat or the like. Further, this process is executed by using an unspecified work area (see FIG. 12C) of the main RAM 103. In the present embodiment, this process is also performed at times other than during the test firing test (after the pachislot 1 is installed in the amusement store). At this time, the main control board 71 is connected via the second interface boat or the like. Since it is not connected to a testing machine, various test signals are generated but not output. Details of the test test signal control process will be described later with reference to FIG.

  Next, the main CPU 101 performs a register restoration process (S912). Then, after the process of S912, the main CPU 101 ends the interrupt process.

[7-segment LED drive processing]
Next, the 7-segment LED drive process performed in S907 during the interrupt process (see FIG. 100) will be described with reference to FIGS. FIG. 101 is a flowchart showing the procedure of 7-segment LED drive processing. FIG. 102A is a diagram illustrating an example of a source program for executing the processing of S923 to S925 described later during the 7-segment LED driving process, and FIG. 102B illustrates S931 to be described later during the 7-segment LED driving process. It is a figure which shows an example of the source program for performing the process of S936.

  First, the main CPU 101 adds “1” to the value of the interrupt counter (+1 update) (S921). Next, the main CPU 101 determines whether or not the value of the interrupt counter is an odd number (S922).

  In S922, when the main CPU 101 determines that the value of the interrupt counter is not an odd number (in the case where S922 is NO), the main CPU 101 ends the 7-segment LED driving process, and the process is interrupted (see FIG. 100). ) In S908. That is, in this embodiment, the 7-segment LED driving process is performed every two interrupt cycles. In this embodiment, the example in which the 7-segment LED driving process is executed when the interrupt counter value is an even number has been described. However, the present invention is not limited to this, and the 7-segment LED drive process is performed when the interrupt counter value is an odd number. The LED driving process may be executed, or the execution timing of the 7-segment LED driving process may be determined using the quotient or the remainder when the value of the interrupt counter is divided by an arbitrary integer.

  On the other hand, when the main CPU 101 determines in S922 that the value of the interrupt counter is an odd number (when S922 is YES), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets the address of the push order display data storage area for storing the push order display data output to each cathode of the 7-segment LED (S924).

  Next, the main CPU 101 performs 7-segment display data generation processing (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. Details of the 7-segment display data generation processing will be described later with reference to FIG. 103 described later.

  Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets an address of a credit display data storage area for storing credit display data output to each cathode of the 7-segment LED (S927).

  Next, the main CPU 101 performs a 7-segment display data generation process (S928). In this process, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. Details of the 7-segment display data generation processing will be described later with reference to FIG. 103 described later.

  Next, the main CPU 101 sets an address of a 7-segment common counter storage area for storing a value of a 7-segment common counter described later (S929). Next, the main CPU 101 adds “1” to the value of the 7-segment common counter (+1 update) (S930). In this process, when the updated 7-segment common counter value is “8”, the main CPU 101 sets the 7-segment common counter value to “0”. In the present embodiment, since the 7-segment LED is dynamically controlled, the value of the 7-segment common counter is updated every 8 cycles.

  Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and the address of the target cathode data storage area (the target storage area in the push order display data storage area or the credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This process is performed to turn off the 7-segment LED and eliminate the influence of afterimages.

  Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

  Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). Then, after the process of S936, the main CPU 101 ends the 7-segment LED drive process, and shifts the process to the process of S908 in the interrupt process (see FIG. 100).

  In the present embodiment, the 7-segment LED driving process is performed as described above. Note that the processing of S923 to S925 during the 7-segment LED driving process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 102A. Further, the processing of S931 to S936 during the 7-segment LED driving processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 102B.

  Among them, the output processing of each 7-segment output data in S936 is executed by one source code “LD (cPA_SEGCOM), BC” as shown in FIG. 102B. Therefore, in the 7-segment LED driving process of the present embodiment, 7-segment common output (selection) data and 7-segment cathode output data are output simultaneously when dynamic lighting control is performed on a 2-digit 7-segment LED. That is, in the 7-segment LED dynamic lighting control when carrying out the push order navigation on the instruction monitor, and in the 7-segment LED dynamic lighting control when displaying credit information with the 2-digit 7-segment LED, the 7-segment common output ( Selection) data and 7-segment cathode output data are output simultaneously.

  In this case, the number of instruction codes necessary for dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Therefore, it becomes possible to improve game playability. In this embodiment, an example in which a 7-segment drive circuit (not shown) that performs 7-segment LED drive processing is configured by a cathode common circuit and controlled by the cathode has been described. However, the present invention is not limited to this, The segment drive circuit may be configured by an anode common circuit, and the 7-segment LED may be controlled by the anode.

  In addition, the navigation data acquisition process of S923 and the address setting process of the push display data storage area of S924 during the 7-segment LED driving process described above are both performed using a Q register (extension register) as shown in FIG. 102A. This is executed by an “LDQ” instruction (instruction code dedicated to the main CPU 101) for specifying an address. Therefore, in the 7-segment LED driving process of this embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values by using the “LDQ” instruction. The command for address setting can be omitted (there is no need to separately provide the command for address setting), and accordingly, the capacity of the source program (capacity of the main ROM 102) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[7-segment display data generation processing]
Next, the 7-segment display data generation process performed in S925 and S928 in the 7-segment LED drive process (see FIG. 101) will be described with reference to FIGS. FIG. 103 is a flowchart showing the 7-segment display data generation processing procedure. FIG. 104 is a diagram illustrating an example of a source program for executing the 7-segment display data generation process. FIG. 105 is a diagram showing an example of the configuration of a 7-segment cathode table that is actually referred to on the source program of the 7-segment display data generation process.

  Note that “display data”, which will be described later, generated in the 7-segment display data generation process performed in S925 in the 7-segment LED drive process (see FIG. 101) corresponds to the push order display data, 101), “display data” described later generated in the 7-segment display data generation process performed in S928 corresponds to the credit display data.

  First, the main CPU 101 divides the display data set in the cathode data storage area by “10”, obtains the quotient value of the division result as the display data of the upper digits of the 2-digit 7-segment LED, and divides the data. The remainder of the result is acquired as display data for the lower digits (S941). Next, the main CPU 101 determines whether or not to perform upper digit display based on the acquired upper digit display data (S942).

  In S942, when the main CPU 101 determines to display the upper digits (when S942 is YES), the main CPU 101 performs the process of S944 described later. On the other hand, when the main CPU 101 determines in S942 that the upper digit display is not performed (when S942 is NO), the main CPU 101 sets no upper digit display (S943).

  After the processing of S943 or when S942 is YES, the main CPU 101 refers to the 7-segment cathode table (see FIG. 163) and acquires the display data of the upper digits (S944). Next, the main CPU 101 stores the acquired upper digit display data in the upper digit display data storage area (not shown) (S945).

  Next, the main CPU 101 refers to the 7-segment cathode table (see FIG. 105) and acquires display data for the lower digits (S946). Next, the main CPU 101 stores the acquired lower-digit display data in a lower-digit display data storage area (not shown) (S947).

  After the process of S947, the main CPU 101 ends the 7-segment display data generation process. At this time, if the executed 7-segment display data generation process is the process of S925 during the 7-segment LED drive process (see FIG. 101), the main CPU 101 shifts the process to the process of S926 during the 7-segment LED drive process. Move. On the other hand, when the executed 7-segment display data generation process is the process of S928 during the 7-segment LED drive process (see FIG. 101), the main CPU 101 shifts the process to the process of S929 during the 7-segment LED drive process. .

  In the present embodiment, the 7-segment display data generation process is performed as described above. The 7-segment display data generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

[Timer update processing]
Next, the timer update process performed in S908 during the interrupt process (see FIG. 100) will be described with reference to FIGS. FIG. 106 is a flowchart showing the timer update process. FIG. 107 is a diagram showing an example of a source program for executing the processes of S951 to S954 described later during the timer update process.

  First, the main CPU 101 sets an update start address of a 2-byte timer storage area (not shown) in the HL register, and sets a 2-byte timer number in the B register (S951).

  Next, the main CPU 101 compares the number of 2-byte timers with the lower limit value “0”. When the number of 2-byte timers is greater than the lower limit value “0”, the main CPU 101 subtracts 1 from the 2-byte timer number (-1 update). If the 2-byte timer number is less than or equal to the lower limit “0”, the 2-byte timer number is held at “0” (S952). Further, in the process of S952, the main CPU 101 subtracts 2 (-2 update) the update start address of the 2-byte timer storage area set in the HL register.

  Next, the main CPU 101 subtracts 1 (updates -1) the 2-byte timer number set in the B register (S953). Next, the main CPU 101 determines whether or not the number of 2-byte timers set in the B register is “0” (S954).

  In S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is not “0” (when S954 is NO), the main CPU 101 returns the process to the process of S952, and after S952 Repeat the process.

  On the other hand, when the main CPU 101 determines in S954 that the number of 2-byte timers set in the B register is “0” (when S954 is YES), the main CPU 101 stores the 1-byte timer storage area in the HL register. The update start address is set, and the 1-byte timer number is set in the B register (S955).

  Next, the main CPU 101 compares the number of 1-byte timers with the lower limit value “0”. When the number of 1-byte timers is larger than the lower limit value “0”, the main CPU 101 subtracts 1 (1 update) the number of 1-byte timers. If the number of 1-byte timers is less than or equal to the lower limit “0”, the number of 1-byte timers is held at “0” (S956). Further, in the process of S956, the main CPU 101 subtracts 1 (-1 update) the update start address of the 1-byte timer storage area set in the HL register.

  Next, the main CPU 101 subtracts 1 (-1 update) the number of 1-byte timers set in the B register (S957). Next, the main CPU 101 determines whether or not the number of 1-byte timers set in the B register is “0” (S958).

  In S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is not “0” (when S958 is NO), the main CPU 101 returns the process to the process of S956, and after S956 Repeat the process.

  On the other hand, when the main CPU 101 determines in S958 that the number of 1-byte timers set in the B register is “0” (when S958 is YES), the main CPU 101 performs electromagnetic counter control processing (S959). ). In this process, an output control process when a signal indicating IN / OUT of medals is output to the external concentration terminal board 47 is performed. After the process of S959, the main CPU 101 ends the timer update process and shifts the process to the process of S909 during the interrupt process (see FIG. 100).

  In the present embodiment, the timer update process is performed as described above. Note that the processing of S951 to S954 (2-byte timer update processing) during the timer update processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG.

  Among them, the process of S952 (2-byte timer update process) is executed by the “DCPWLD” instruction (predetermined update instruction) in FIG. The “DCPWLD” instruction is an instruction code dedicated to the main CPU 101.

  On the source program, for example, when the source code “DCPWLD (HL), n” is executed, the memory content (stored data) for 2 bytes from the address specified by the HL register is compared with the integer n, If the memory content for 2 bytes is larger than the integer n, 1 is subtracted from the memory content for 2 bytes. If the memory content for 2 bytes is less than or equal to the integer n, it is specified by the HL register. An integer n is stored in a 2-byte memory from the address.

  Therefore, in the source code “DCPWLD (HL), 0” in FIG. 107, the memory contents for 2 bytes (the number of 2-byte timers) and the integer “0” (lower limit value) from the address specified by the HL register When the contents of the memory for 2 bytes are larger than the integer “0”, the contents of the memory for 2 bytes are decremented by 1 and the contents of the memory for 2 bytes are less than the integer “0”. “0” is set in the memory contents of 2 bytes. That is, when the current 2-byte timer number is larger than “0”, the 2-byte timer update process is performed. When the current 2-byte timer number is “0” or less, the 2-byte timer number is “0”. Is held.

  As described above, in the timer update process of the present embodiment, both the update (subtraction) process of the timer number and the process of holding the timer number to “0” are executed by the “DCPWLD” instruction that is the instruction code dedicated to the main CPU 101. can do. In this case, there is no need to provide an instruction code for executing both processes separately. Also, the decision branch instruction code for determining whether or not the number of timers is “0” can be omitted. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Therefore, it becomes possible to improve game playability. In this embodiment, an example in which the “DCPWLD” instruction is used only in the update process of the 2-byte timer has been described. However, the present invention is not limited to this, and the “DCPWLD” instruction is also used in the update process of the 1-byte timer. May be used.

[Trial test signal control processing (not specified)]
Next, with reference to FIG. 108, the test firing test signal control process performed in S911 during the interrupt process (see FIG. 100) will be described. FIG. 108 is a flowchart showing the procedure of the test test signal control process.

  First, the main CPU 101 saves the address of the stack area of the main RAM 103 (S961). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S962). Next, the main CPU 101 saves data in all registers (S963).

  Next, the main CPU 101 performs a rotating brake signal generation process (S964). In this process, the main CPU 101 generates and outputs a rotation control signal (drive signal) for each reel that is output to the testing machine via the second interface boat or the like. Note that details of the rotation brake signal generation processing will be described later with reference to FIG. 109 described later.

  Next, the main CPU 101 performs a special signal control process (S965). In this process, the main CPU 101 performs an output process of a bonus (special prize) ON / OFF signal (test signal) output to the testing machine. Details of the special signal control process will be described later with reference to FIG. 110 described later.

  Next, the main CPU 101 performs a conditional device signal control process (S966). In this process, the main CPU 101 performs a control signal output process corresponding to the state of the conditional device signal control flag. Details of the condition device signal control processing will be described later with reference to FIGS. 111 and 112 described later.

  Next, the main CPU 101 performs a process for restoring the data of all registers saved in the process of S963 (S967). Next, the main CPU 101 sets the address of the stack area saved in the process of S961 in the stack pointer (SP) (S968). Then, after the process of S968, the main CPU 101 ends the test firing test signal control process, and shifts the process to the process of S912 in the interrupt process (see FIG. 100).

[Rotating brake signal generation processing]
Next, with reference to FIG. 109, the rotating drum braking signal generation process performed in S964 in the test fire test signal control process (see FIG. 108) will be described. FIG. 109 is a flowchart showing the procedure of the rotation brake signal generation process.

  First, the main CPU 101 sets a spinning cylinder control data storage area (not shown) in an unspecified work area (S971). Next, the main CPU 101 sets “3” as the number of reels, and clears the spinning cylinder control signal and its generation state (1 byte data) (S972).

  Next, the main CPU 101 determines whether or not the rotation control data is “less than stopped” data (S973). Note that the “less than stop” rotation control data here refers to rotation control data other than the rotation control data for stopping the reel, that is, rotation control data (acceleration for rotating the reel). Preparation, acceleration, waiting for constant speed, waiting for constant speed, and waiting for stop start position).

  In S973, when the main CPU 101 determines that the rotation control data is “less than stopped” data (when S973 is YES), the main CPU 101 performs the process of S975 described later. On the other hand, in S973, when the main CPU 101 determines that the rotation control data is not “less than stopped” data (when S973 is NO), the main CPU 101 determines that the rotation control data is “end of static hold control”. It is determined whether or not the data is “S” (S974). Note that the “rotation control data” of “end of static hold control” here is the rotation control data indicating the all-phase all-stop state of the reels.

  In S974, when the main CPU 101 determines that the spinning cylinder control data is “end of static hold control” (when S974 is YES), the main CPU 101 performs the process of S976 described later. On the other hand, in S974, when the main CPU 101 determines that the rotation control data is not “end of the static hold control” (when S974 is NO), or when S973 is YES, the main CPU 101 Bit 3 of the rotation control signal generation state (1-byte data) is turned on (“1”) (S975).

  After the process of S975 or when S974 is NO, the main CPU 101 shifts the data of each bit in the generated state by one bit to the right (in the direction from bit 7 to bit 0) (S976). Next, the main CPU 101 updates the address of the spinning cylinder control data storage area to the address of the next reel to be controlled (S977).

  Next, the main CPU 101 subtracts 1 from the number of reels (S978). Next, the main CPU 101 determines whether or not the number of reels is “0” (S979).

  In S979, when the main CPU 101 determines that the number of reels is not “0” (when S979 is NO), the main CPU 101 returns the process to the process of S973 and repeats the processes after S973.

  On the other hand, when the main CPU 101 determines in S979 that the number of reels is “0” (in the case where S979 is YES), the main CPU 101 sends the generated state data to the testing machine via the rotating brake signal output port. To the first interface board 301 (see FIG. 7) (S980). Then, after the processing of S980, the main CPU 101 ends the rotation brake signal generation processing and shifts the processing to the processing of S965 in the test firing test signal control processing (see FIG. 108).

[Special signal control processing]
Next, with reference to FIG. 110, the special signal control process performed in S965 in the test fire test signal control process (see FIG. 108) will be described. FIG. 110 is a flowchart showing a procedure of a special signal control process.

  First, the main CPU 101 refers to the gaming state flag storage area (see FIG. 24) and acquires a gaming state flag (S991). Next, the main CPU 101 determines whether or not the gaming state is an RB gaming state (S992).

  In S992, when the main CPU 101 determines that the gaming state is the RB gaming state (when S992 is YES), the main CPU 101 sends an ON signal from the RB signal port for the test signal to the first interface for the testing machine. The data is output to the board 301 (see FIG. 7) (S993). On the other hand, when the main CPU 101 determines in S992 that the gaming state is not the RB gaming state (when S992 is NO), the main CPU 101 sends an OFF signal from the RB signal port for the test signal to the first for testing machine. The data is output to the interface board 301 (see FIG. 7) (S994).

  After the processing of S993 or S994, the main CPU 101 refers to the gaming state flag storage area (see FIG. 24) and determines whether or not the gaming state is the BB gaming state (S995).

  In S995, when the main CPU 101 determines that the gaming state is the BB gaming state (when S995 is YES), the main CPU 101 sends an ON signal from the BB medium signal port for the test signal to the first interface for the testing machine. The data is output to the board 301 (see FIG. 7) (S996). On the other hand, when the main CPU 101 determines in S995 that the gaming state is not the BB gaming state (when S995 is NO), the main CPU 101 sends an OFF signal from the BB medium signal port for the test signal to the first for testing machine. The data is output to the interface board 301 (see FIG. 7) (S997).

  Then, after the process of S996 or S997, the main CPU 101 ends the special signal control process, and shifts the process to the process of S966 in the trial test signal control process (see FIG. 108).

  In the present embodiment, since the CB gaming state and the MB gaming state are further provided (see FIG. 24), the same processing as described above may be performed in the RB gaming state and the MB gaming state. .

  Specifically, after the processing of S998, the main CPU 101 determines whether or not the gaming state is the CB gaming state, and when the main CPU 101 determines that the gaming state is the CB gaming state, When the ON signal is output from the CB medium signal port to the first interface board 301 for the testing machine (see FIG. 7), when it is determined that the gaming state is not the CB gaming state, the OFF signal is output from the CB medium signal port for the test signal You may make it output to the 1st interface board 301 for test machines (refer FIG. 7).

  After the processing, the main CPU 101 determines whether or not the gaming state is the MB gaming state, and when the main CPU 101 determines that the gaming state is the MB gaming state, an MB medium signal port for the test signal On the other hand, when it is determined that the gaming state is not the MB gaming state, the OFF signal is sent from the MB middle signal port for the testing machine to the testing machine first interface board 301 (see FIG. 7). One interface board 301 (see FIG. 7) may be output.

  However, in the present embodiment, the MB gaming state lasts for only two games at the maximum (see FIG. 96), so in this case, the CB gaming state and the MB gaming state are provided. Even in such a case, an ON signal or an OFF signal may not be output from the test signal signal port to the first testing machine interface board 301 (see FIG. 7).

  In the present embodiment, since the RB gaming state and the BB gaming state, and the CB gaming state and the MB gaming state are not operated at the same time, whether or not the CB gaming state is operating. In the case of outputting a signal indicating that, an ON signal or an OFF signal is output using a signal port during RB as a signal port for a test signal, and a signal indicating whether or not the MB gaming state is operating is output. In this case, an ON signal or an OFF signal may be output using a BB medium signal port as a test signal signal port.

[Condition device signal control processing]
Next, with reference to FIG. 111 and FIG. 112, the condition device signal control process performed in S966 in the test firing test signal control process (see FIG. 108) will be described. 111 and 112 are flowcharts showing the procedure of the conditional device signal control process.

  First, the main CPU 101 determines whether or not the conditional device signal control flag is in the initial state (S1001). In S1001, when the main CPU 101 determines that the condition device signal control flag is in the initial state (when S1001 is YES), the main CPU 101 ends the condition device signal control process, and the process is a test firing test signal control process. The process proceeds to S967 in (see FIG. 108).

  On the other hand, when the main CPU 101 determines in S1001 that the condition device signal control flag is not in the initial state (when S1001 is NO), the main CPU 101 determines that the condition device signal control flag indicates that the re-game state identification signal is on. It is determined whether or not it is to be shown (S1002).

  In S1002, when the main CPU 101 determines that the conditional device signal control flag indicates the ON state of the re-playing state identification signal (when S1002 is YES), the main CPU 101 serves the conditional device signal control state. The on state of the object condition apparatus signal is set (S1003). Next, the main CPU 101 outputs information on the RT state from the condition device 1-6 signal port to the first interface board 301 for tester (see FIG. 7) (S1004). After the process of S1004, the main CPU 101 ends the condition device signal control process, and moves the process to the process of S967 in the test firing test signal control process (see FIG. 108).

  On the other hand, when the main CPU 101 determines in S1002 that the conditional device signal control flag does not indicate the ON state of the re-playing state identification signal (when S1002 is NO), the main CPU 101 determines that the conditional device signal control flag is It is determined whether or not the re-playing state identification signal indicates an off state (S1005).

  In S1005, when the main CPU 101 determines that the conditional device signal control flag indicates the off state of the re-playing state identification signal (when S1005 is YES), the main CPU 101 detects the conditional device 1-8 signal port. The OFF signal is output to the first interface board 301 for testing machine (see FIG. 7) (S1006). After the process of S1006, the main CPU 101 ends the condition device signal control process, and moves the process to the process of S967 in the test firing test signal control process (see FIG. 108).

  On the other hand, when the main CPU 101 determines in S1005 that the conditional device signal control flag does not indicate the off state of the re-gaming state identification signal (when S1005 is NO), the main CPU 101 indicates that the conditional device signal control state is It is determined whether or not the accessory condition device signal is in an ON state (S1007).

  In S1007, when the main CPU 101 determines that the condition device signal control state is the ON state of the accessory condition device signal (when S1007 is YES), the main CPU 101 receives the special prize winning from the condition devices 1 to 8 signal port. The number information is output to the first interface board 301 for tester (see FIG. 7), and at this time, the ON signal is output from the condition device 8 signal port to the first interface board 301 for tester (see FIG. 7) (see FIG. 7). S1008). Next, the main CPU 101 sets a predetermined waiting time (24.58 ms in this embodiment) to the conditional device signal output waiting timer (S1009). Next, the main CPU 101 sets the condition device signal output waiting state to the condition device signal control state (S1010). After the process of S1010, the main CPU 101 ends the condition device signal control process, and moves the process to the process of S967 in the test firing test signal control process (see FIG. 108).

  On the other hand, when the main CPU 101 determines in S1007 that the condition device signal control state is not the ON state of the accessory condition device signal (when S1007 is NO), the main CPU 101 determines that the condition device signal control state is the condition device signal. It is determined whether or not the output is waiting (S1011).

  In S1011, when the main CPU 101 determines that the condition device signal control state is the condition device signal output waiting state (when S1011 is YES), the main CPU 101 sets the value of the condition device signal output waiting timer to “0”. Is determined (S1012).

  In S1012, when the main CPU 101 determines that the value of the conditional device signal output waiting timer is not “0” (when S1012 is NO), the main CPU 101 ends the conditional device signal control processing and performs the test test. The process proceeds to S967 in the signal control process (see FIG. 108). On the other hand, when the main CPU 101 determines in S1012 that the value of the conditional device signal output waiting timer is “0” (when S1012 is YES), the main CPU 101 enters the small device condition device in the conditional device signal control state. The signal on state or the condition device signal off state is set (S1013). Then, after the process of S1013, the main CPU 101 ends the condition device signal control process, and shifts the process to the process of S967 in the test firing test signal control process (see FIG. 108).

  Here, returning to the processing of S1011 again, in S1011, when the main CPU 101 determines that the condition device signal control state is not a condition device signal output waiting state (when S1011 is NO), the main CPU 101 It is determined whether or not the device signal control state is the ON state of the small role condition device signal (S1014).

  In S1014, when the main CPU 101 determines that the condition device signal control state is the ON state of the small role condition device signal (when S1014 is YES), the main CPU 101 starts the small role from the condition devices 1 to 8 signal port. Information of a winning number (for example, a winning number defined in advance as a winning number included in the winning number (see FIGS. 16 and 17)) is output to the first interface board 301 for testing machine (see FIG. 7), At this time, an ON signal is output from the condition device 7 signal port to the first interface board 301 for tester (see FIG. 7) (S1015). Next, a predetermined waiting time (24.58 ms in this embodiment) is set to the conditional device signal output waiting timer (S1016). Next, the main CPU 101 sets the condition device signal output waiting state to the condition device signal control state (S1017). Then, after the process of S1017, the main CPU 101 ends the condition device signal control process, and shifts the process to the process of S967 in the test firing test signal control process (see FIG. 108).

  On the other hand, when the main CPU 101 determines in S1014 that the condition device signal control state is not the ON state of the small role condition device signal (when S1014 is NO), the main CPU 101 turns OFF from the condition devices 1 to 8 signal port. The signal is outputted to the first interface board 301 for tester (see FIG. 7) (S1018). After the process of S1018, the main CPU 101 ends the condition device signal control process, and moves the process to the process of S967 in the test firing test signal control process (see FIG. 108).

<Description of operation of sub-control circuit>
Next, contents of various processes executed by the sub CPU 201 of the sub control circuit 200 using a program will be described with reference to FIGS. 113 to 122.

[Sub CPU power-on processing]
First, referring to FIG. 113, the power-on process of the sub CPU 201 will be described. FIG. 113 is a flowchart showing the procedure of the power-on process.

  First, when the power of the sub CPU 201 is turned on, a sub CPU initial setting process is executed (S1101). In this processing, for example, initialization processing of the sub CPU 201, initialization processing of connected devices (IC (Integrated Circuit), LSI (Large-scale Integration), etc.), initialization processing of the memory (DRAM), OS (Operating System) The initialization process is performed.

  Next, the sub CPU 201 issues an accessory control task activation request as a subtask activation request (S1102). The “act” here refers to an effect device that produces an effect by a physical operation. In the present embodiment, when the effect device is provided and an effect using the effect device can be executed, The operation of the rendering device is controlled by the accessory control task. For example, in the power-on process of the sub CPU, the accessory control task is executed when an accessory control task request is generated from the OS in response to an activation request for the accessory control task by the sub CPU 201.

  Next, the sub CPU 201 makes a startup request for the lamp control task described above (S1103). Next, the sub CPU 201 makes an activation request for the above-described sound control task (S1104).

  Next, the sub CPU 201 makes a request for starting the main board communication task described above (S1105). The main board communication task is executed, for example, when a main board communication task request is generated from the OS in response to an activation request for the main board communication task by the sub CPU 201 in the power-on process of the sub CPU. Details of the main board communication task will be described later with reference to FIG.

Next, the sub CPU 201 makes a startup request for the animation task described above (S1106). The animation task is executed when, for example, an animation task request is generated from the OS in response to an animation task activation request from the sub CPU 201 in the power-on process of the sub CPU. In addition, the animation task is repeated at a cycle of 33 msec including the processing time in order to control the image display operation of the display device 11 (projector mechanism 211) and / or the sub display device 18, for example.
I will do it.

  Next, the sub CPU 201 performs backup recovery processing (S1107). In this process, the sub CPU 201 stores various game data (game state data, ART game number, ART stock number, CP, etc.) stored in an SRAM (static RAM) and various history data as work DARM (dynamic). RAM). By this processing, the content of the effect in the pachislot 1 can be returned to the state before the power interruption. Then, after the processing of S1107, the sub CPU 201 ends the power-on processing.

[Sub CPU power interruption processing]
Next, the power interruption processing of the sub CPU 201 will be described with reference to FIG. This process is, for example, an interrupt process that is executed when an abnormality such as a power interruption occurs. In addition, FIG. 114 is a flowchart which shows the procedure of a power interruption interrupt process.

  When power interruption (reduction of power supply voltage) occurs, the sub CPU 201 performs backup creation processing (S1111). In this process, the sub CPU 201 copies various data to be held from the DRAM to the SRAM when power interruption is detected. That is, the sub CPU 201 performs a process opposite to the above-described backup recovery process (S1107 during the power-on process). With this processing, even if the data is destroyed, correct data is saved as backup data.

[Main board communication task]
Next, the main board communication task executed by the sub CPU 201 will be described with reference to FIG. FIG. 115 is a flowchart showing the procedure of the main board communication task.

  First, the sub CPU 201 performs reception check of the command transmitted from the main control circuit 90, and acquires command registration data (S1121). Next, the sub CPU 201 extracts the type of the received command (S1122). In this embodiment, command data is composed of 8-byte data, and the first byte of data indicates the type of command.

  Next, the sub CPU 201 determines whether or not the command type is a specified type (S1123).

  In this embodiment, the command type is associated with one of a plurality of predetermined codes, and when the game is operating normally, the command type is one of the codes within the regulations. Become. Therefore, in the process of S1123, if the type of the received command is one of the codes within the specification, the sub CPU 201 determines that the command type is valid (specified type). On the other hand, if the command type is an unspecified code, the sub CPU 201 determines that some abnormality (including an illegal act) has occurred during the game, and determines that the command type is invalid.

  In S1123, when the sub CPU 201 determines that the command type is not the specified type (when S1123 is NO), the sub CPU 201 returns the process to S1121 and repeats the processes after S1121. On the other hand, when the sub CPU 201 determines in S1123 that the command type is the specified type (when S1123 is YES), the sub CPU 201 stores the message in the message queue based on the received command ( S1124). The message queue is a mechanism for exchanging information between processes. Then, after the processing of S1124, the sub CPU 201 returns the processing to S1121, and repeats the processing after S1121.

  Although not shown in the figure, when a message (that is, information included in each parameter of the received command) is stored in the message queue, the sub CPU 101 extracts the message (that is, each received command). The information contained in the parameter is acquired), and processing (processing upon receiving various commands) according to the command type and the content of the command is executed. For example, the processes shown in FIGS. 116 and 118 to 122 described later show an example of the command reception process.

[Sub-side navigation control processing]
Next, the sub-side navigation control process will be described with reference to FIG. FIG. 116 is a flowchart showing a procedure of sub-side navigation control processing.

  First, the sub CPU 201 determines whether or not navigation data has been acquired (S1131). The sub CPU 201 acquires navigation data determined by the main control board 71 from the start command data received from the main control board 71. Therefore, in the process of S1131, the sub CPU 201 determines whether navigation data is included in the received start command data.

  In the present embodiment, the determined navigation data is included in the start command data, but the navigation data transmission mode is not limited to this. For example, the main CPU 101 generates and stores specific state command data including at least navigation data only in a specific state where navigation data needs to be transmitted (for example, during ART), and the sub CPU 201 stores the specific state command data. It may be determined whether or not navigation data is included therein.

  When the sub CPU 201 determines that the navigation data has been acquired in S1131 (when S1131 is YES), the sub CPU 201 sets the sub navigation data corresponding to the navigation data (S1132). For example, when the sub CPU 201 acquires the navigation data “4”, the navigation data for notifying the push order “left, middle, right” as the sub-side navigation data is set in this process. As a result, the contents of the stop operation can be notified on both the main side and the sub side. Then, after the process of S1132, the sub CPU 201 ends the sub-side navigation control process.

  On the other hand, when it is determined in S1131 that the sub CPU 201 has not acquired navigation data (NO in S1101), the sub CPU 201 determines whether navigation (notification of stop operation) is necessary. (S1133). When the sub CPU 201 determines that navigation is not necessary in S1133 (when S1133 is NO), the sub CPU 201 ends the sub-side navigation control process.

  On the other hand, when the sub CPU 201 determines that the navigation is necessary in S1133 (when S1133 is YES), the sub CPU 201 sets sub-side navigation data corresponding to various lottery results (S1134). For example, when the sub CPU 201 is in an ART gaming state and an internal winning combination that is not a push order is determined, in order to enhance the effect, the sub CPU 201 provides effect data for notifying the contents of the stop operation alone. Can be determined. Then, after the process of S1134, the sub CPU 201 ends the sub-side navigation control process.

[Player registration process]
Next, the player registration process will be described with reference to FIG. FIG. 117 is a flowchart showing the procedure of the player registration process.

  First, the sub CPU 201 determines whether or not a registration operation has been accepted (S1141). For example, when the operation of the registration button 222b is accepted on the menu screen 222 (see FIG. 5B) of the sub display device 18 and a predetermined operation is accepted on the registration screen (not shown) displayed in that case, the sub CPU 201 performs the registration operation. Is determined to have been accepted.

  When the sub CPU 201 determines in S1141 that the registration operation has been accepted (in the case where S1141 is YES), the sub CPU 201 sets a player registration state (S1142). In the situation where the player registration state is set, the sub CPU 201 sets the sub display device 18 so that the game information screens 223, 224, and 225 (see FIGS. 5C to 5E) can be displayed on the sub display device 18. Control the display screen. Then, after the process of S1142, the sub CPU 201 ends the player registration process.

  On the other hand, when it is determined in S1141 that the sub CPU 201 has not accepted a registration operation (when S1141 is NO), the sub CPU 201 determines whether or not a registration deletion operation has been accepted (S1143). For example, when a specific operation is accepted on the registration screen of the sub display device 18, the sub CPU 201 determines that a registration deletion operation has been accepted.

  When the sub CPU 201 determines in S1143 that the registration deletion operation has not been accepted (NO in S1113), the sub CPU 201 ends the player registration process.

  On the other hand, when it is determined in S1143 that the sub CPU 201 has accepted the registration deletion operation (YES in S1143), the sub CPU 201 clears the player registration state (S1144). In the situation where the player registration state is cleared, the sub CPU 201 causes the sub display device 18 so that the game information screens 223, 224, and 225 (see FIGS. 5C to 5E) cannot be displayed on the sub display device 18. Control the display screen. Then, after the process of S1144, the sub CPU 201 ends the player registration process.

[History management processing]
Next, the history management process will be described with reference to FIG. FIG. 118 is a flowchart showing the procedure of history management processing.

  First, the sub CPU 201 acquires a game result from various command data received from the main control board 71 (S1151). For example, in this process, the sub CPU 201 can grasp the type of the combination determined as the internal winning combination from the start command data. Further, for example, in this process, the sub CPU 201 can grasp the symbol combination displayed from the winning action command data (that is, whether or not a winning combination is determined as an internal winning combination). Further, for example, in this process, the sub CPU 201 can grasp the current gaming state and the transition state of the gaming state from the start command data or the like.

  Next, the sub CPU 201 performs a game history update process based on the acquired game result (S1152). By this process, the sub CPU 201, for example, based on the game results acquired from the various command data, for example, the number of games (number of games), bonus times, ART times, CZ times, CZ success times, promotion chance times, specialized zones ( It is possible to manage various game histories such as the number of BB CP special zones and double special zones), the number of wins of each combination, and the winning probability. Then, after the processing of S1152, the sub CPU 201 ends the history management processing.

[Direction determination processing]
Next, the effect determination process will be described with reference to FIG. FIG. 119 is a flowchart showing the procedure of the effect determination process. This effect determination process shows an example of a command reception process when the start command data transmitted from the main control board 71 is received.

  First, the sub CPU 201 acquires information on each parameter from the received command and updates the game information (S1161). For example, the sub CPU 201 compares information on the current gaming state with information on the gaming state before one game, and stores the gaming information indicating that there is a change in the gaming state. Further, for example, the sub CPU 201 compares the current mode information with the information of the mode before one game, and stores the game information to that effect if there is a change in the mode.

  Next, the sub CPU 201 determines whether or not the current gaming state is in a promotion chance (S1162). In S1162, when the sub CPU 201 determines that the current gaming state is a promotion chance (when S1162 is YES), the sub CPU 201 performs an effect determination process during the promotion chance (S1163). In this process, the sub CPU 201 performs a process of determining the production contents during the promotion chance. The details of the promotion chance mid-stage effect determination process will be described later with reference to FIG. 120 described later. Then, after the process of S1163, the sub CPU 201 ends the effect determination process.

  On the other hand, when the sub CPU 201 determines in S1162 that the current gaming state is not being promoted (when S1162 is NO), the sub CPU 201 determines whether or not the current gaming state is ART. (S1164). In S1164, when the sub CPU 201 determines that the current gaming state is ART (when S1164 is YES), the sub CPU 201 determines that the state of art during the ART (various effects gaming state (zone), various internal states). Etc.) and the game pattern such as the internal winning combination, the effect pattern during the ART is determined (S1165). Then, after the process of S1165, the process of S1167 described later is performed.

  On the other hand, when the sub CPU 201 determines in S1164 that the current gaming state is not in ART (when S1164 is NO), the sub CPU 201 determines that the non-ART effect state (various effect game states (zones), various A normal production pattern is determined according to game information such as an internal state or the like and an internal winning combination (S1166).

  Next, the sub CPU 201 determines whether or not the determined effect pattern is a special effect prohibited effect pattern (S1167). Here, since the special effect is executed when all the reels 3L, 3C, 3R are stopped, the predetermined effect pattern is that all the reels 3L, 3C, 3R are stopped. When a specific effect is sometimes executed, the effect pattern becomes a special effect prohibited effect pattern in which the special effect and the effect timing compete. That is, in this process, the sub CPU 201 determines whether or not the determined effect pattern is such an effect pattern.

  In S1167, when the sub CPU 201 determines that the determined effect pattern is a special effect prohibited effect pattern (when S1167 is YES), the sub CPU 201 ends the effect determination process.

  On the other hand, when the sub CPU 201 determines in S1167 that the determined effect pattern is not a special effect prohibited effect pattern (when S1167 is NO), the sub CPU 201 performs special effect reservation processing (S1168). In this process, the sub CPU 201 performs a process of determining whether or not to reserve a special effect according to the determination value for the special effect lottery. Details of the special effect reservation process will be described later with reference to FIG. 121 described later. Then, after the process of S1168, the sub CPU 201 ends the effect determination process.

[Direction decision processing during promotion chance]
Next, with reference to FIG. 120, the effect determination process during the promotion chance performed in S1163 of the effect determination process (see FIG. 119) will be described. FIG. 120 is a flowchart showing the procedure of the effect determination process during the promotion opportunity.

  First, the sub CPU 201 determines whether or not the continuation number counter is 0 (S1171). That is, the sub CPU 201 determines whether or not it is the first game in the promotion chance. In S1171, when the sub CPU 201 determines that the continuation counter is not 0 (when S1171 is NO), the sub CPU 201 performs the process of S1175 described later.

  On the other hand, when the sub CPU 201 determines in S1171 that the continuation number counter is 0 (YES in S1171), the sub CPU 201 determines whether or not the next game is a continuation success (S1172). That is, the sub CPU 201 determines whether or not the result of the continuous lottery (or continuous security lottery) by the main CPU 101 is a win.

  In S1172, when the sub CPU 201 determines that the next game is not successfully continued (when S1172 is NO), the sub CPU 201 determines an effect pattern to be displayed according to the number of times of continuation (no reviving pattern) (S1173). ). By this processing, for example, after the start of the second game, it is notified that the promotion chance ends at the first game and the number of ART games is fixed at “111”. Then, after the processing of S1173, the sub CPU 201 ends the effect determination processing during the promotion chance.

  On the other hand, when the sub CPU 201 determines in S1172 that the next game is a continuation success (when S1172 is YES), the sub CPU 201 displays according to the number of continuations, or the next continuation confirmation display (no revival pattern). The effect pattern to perform is determined (S1174). With this process, for example, when displaying according to the number of times of continuation, it is notified that the promotion chance has continued after the start of the second game and the number of ART games has been increased to “222”. In addition, for example, when the next continuation confirmation display (without the restoration pattern) is performed (that is, when the continuation is successful until the third game), the promotion chance continues after the start of the second game, and the number of ART games Is reported to have been added to “222”, and at the end of the second game, the number of ART games exceeds “222” (for example, “223”), so that the third game You will be notified that your promotion chance will continue. Then, after the processing of S1174, the sub CPU 201 ends the effect determination processing during the promotion chance.

  When the sub CPU 201 determines in S1171 that the continuation counter is not 0 (NO in S1171), the sub CPU 201 determines whether or not the game is a continuation success (S1175). When the sub CPU 201 determines in S1175 that the game is not continued successfully (when S1175 is NO), the sub CPU 201 determines an effect pattern for displaying the number of acquired ART games (S1176). By this processing, for example, at the end of the game (or after the start of the next game), it is notified that the promotion chance has ended in the game and that the number of ART games has been determined by the number of games corresponding to the game. . Then, after the process of S1176, the sub CPU 201 ends the effect determination process during the promotion chance.

  On the other hand, when the sub CPU 201 determines in S1175 that the game is a continuation success (when S1175 is YES), the sub CPU 201 determines whether or not the next game is a continuation success (S1177). In S1177, when the sub CPU 201 determines that the next game is not successfully continued (when S1177 is NO), the sub CPU 201 determines an effect pattern to be displayed (with a resurrection pattern) according to the number of continuations (S1178). ). By this process, for example, after the start of the next game, it is notified that the promotion chance has continued and the number of ART games has been increased to the number of games corresponding to the next game. Also, for example, after the end of the game (or after the start of the next game), once the promotion chance is finished for the game and it is once informed that the number of ART games is determined by the number of games corresponding to the game The revival effect is performed, and after the start of the next game, the promotion chance is continued, and it is notified that the number of ART games has been increased to the number of games corresponding to the next game. This notification mode corresponds to a revival pattern. Then, after the processing of S1178, the sub CPU 201 ends the effect determination processing during the promotion chance.

  On the other hand, when the sub CPU 201 determines in S1177 that the next game is a continuation success (when S1177 is YES), the sub CPU 201 determines whether or not the continuation confirmation display (next continuation confirmation display) has been performed in the previous game. Is discriminated (S1179). In S1179, when the sub CPU 201 determines that the continuation confirmation display (next continuation confirmation display) has not been performed in the previous game (when S1179 is NO), the sub CPU 201 performs display according to the number of continuations, or next time. An effect pattern for performing continuous confirmation display (with a restoration pattern) is determined (S1180). Then, after the processing of S1180, the sub CPU 201 ends the effect determination processing during the promotion opportunity.

  On the other hand, in S1179, when the sub CPU 201 determines that the continuation confirmation display (next continuation confirmation display) has been performed in the previous game (when S1179 is YES), the sub CPU 201 displays according to the number of continuations, or next time. An effect pattern for performing continuous confirmation display (without a restoration pattern) is determined (S1181). Then, after the process of S1181, the sub CPU 201 ends the effect determination process during the promotion chance.

  That is, when the continuation confirmation display (next continuation confirmation display) is performed in the previous game, the sub CPU 201 selects the effect pattern so that the revival pattern cannot be selected in the game, and the continuation confirmation is performed in the previous game. When the display (next continuous confirmation display) is not performed, the effect pattern is selected so that the revival pattern can be selected in the game. Thereby, the content of the effect of the effect performed can be matched.

[Special effects reservation process]
Next, with reference to FIG. 121, the special effect reservation process performed in S1168 of the effect determination process (see FIG. 119) will be described. FIG. 121 is a flowchart showing the procedure of special effect reservation processing.

  First, the sub CPU 201 determines whether or not a mode transition has occurred in the game (S1191). When the sub CPU 201 determines in S 1191 that a mode transition has occurred in the game (YES in S 1191), the sub CPU 201 clears the special effect reservation parameter to 0 (S 1192). That is, when execution of a special effect is reserved, if the mode transition occurs before the special effect is executed, the sub CPU 201 performs processing for temporarily canceling the reserved special effect.

  After the processing of S1192, and in S1191, when the sub CPU 201 determines that no mode transition has occurred in the game (when S1191 is NO), the sub CPU 201 sets the special effect reservation parameter to “1” or more. It is determined whether or not there is (S1193). That is, the sub CPU 201 determines whether or not the execution of the special effect is reserved. In S1193, when the sub CPU 201 determines that the special effect reservation parameter is “1” or more (when S1193 is YES), the sub CPU 201 performs the process of S1196 described later.

  On the other hand, when the sub CPU 201 determines in S1193 that the special effect reservation parameter is not “1” or more (when S1193 is NO), the sub CPU 201 sets a determination value (see FIG. 34) for the special effect lottery. Then, a special effect reservation lottery is performed based on the determination value and the internal winning combination, and the lottery result is set as a special effect reservation parameter (S1194). For example, the sub CPU 201 determines the special effect reservation parameter based on the normal special effect reservation lottery table (see FIG. 35) in normal time.

  Next, the sub CPU 201 determines whether or not the special effect reservation parameter is “1” or more (S1195). In S1195, when the sub CPU 201 determines that the special effect reservation parameter is not “1” or more (when S1195 is NO), the sub CPU 201 ends the special effect reservation process.

  On the other hand, when the sub CPU 201 determines that the special effect reservation parameter is “1” or more in S1195 (when S1195 is YES), and in S1193 described above, the sub CPU 201 sets the special effect reservation parameter to “1”. When it is determined that it is equal to or greater than the above (when S1193 is YES), the sub CPU 201 determines whether or not “normal lip” has been won (S1196). The “normal lip” here does not indicate only “F_normal lip” but includes a replay role that can be normally established in a non-ART gaming state (for example, RT1 lip, RT2 lip, and RT3 lip). Means. Alternatively, this means that the combination of symbols of “S_TL Lip” is allowed to be derived in the non-ART gaming state (see FIGS. 19 to 21).

  When the sub CPU 201 determines in S1196 that the “normal lip” has not been won (when S1196 is NO), the sub CPU 201 ends the special effect reservation process.

  On the other hand, when it is determined in S1196 that the sub CPU 201 has won the “normal lip” (when S1196 is YES), the sub CPU 201 turns on the special effect execution flag (S1197) and ends the special effect reservation process. To do. When the sub CPU 201 determines that “normal lip” has been won in S1196 (when S1196 is YES), the sub CPU 201 further determines whether the determined effect pattern is a special effect prohibited effect pattern. If it is determined whether or not the determined effect pattern is the effect pattern for which the special effect is prohibited, the special effect execution flag may not be turned on.

[Special effect execution processing]
Next, with reference to FIG. 121, the special effect execution process will be described. FIG. 121 is a flowchart showing the procedure of the special effect execution process. This special effect execution process shows an example of a command reception process when the winning action command data transmitted from the main control board 71 is received.

  First, the sub CPU 201 determines whether or not the special effect execution flag is on (S1201). In S1201, when the sub CPU 201 determines that the special effect execution flag is not on (when S1201 is NO), the sub CPU 201 ends the special effect execution process.

  On the other hand, when the sub CPU 201 determines in S1201 that the special effect execution flag is on (when S1201 is YES), the sub CPU 201 executes the special effect according to the value of the special effect reservation parameter (S1202). ).

  Next, the sub CPU 201 turns off the special effect execution flag (S1203), clears the special effect reservation parameter to 0 (S1204), and ends the special effect execution process.

  As described above, the pachislot machine 1 of the present embodiment has a plurality of specific internal states (for example, the normal mode), and executes a predetermined effect (for example, a special effect) when the specific internal state has changed. When a predetermined execution condition is established, a predetermined effect is executed.

  For example, when there are a plurality of lottery states having different transition probabilities to the advantageous state (for example, during ART) as the plurality of specific internal states, the lottery state becomes an advantageous lottery state, or the advantageous state If there is a precursor state where the transition to the state is awaited, execution of a predetermined effect is reserved when the precursor state is reached.

  Then, when a predetermined display result (for example, a combination of symbols of “S_TL Lip”) is derived (that is, when a predetermined internal winning combination (for example, “Normal Lip”) is established), a predetermined effect is executed. It is configured to be. In other words, every time a predetermined display result is derived, the player can expect whether or not a predetermined effect will be executed, and a unit game with a change in a specific internal state and a predetermined effect will be executed. The unit game to be played can be different. Therefore, when there are a plurality of specific internal states, various specific internal state suggestions can be provided.

[Example display during promotion chance]
Next, an example of the effect display during the promotion chance will be described with reference to FIGS. FIG. 123 is a diagram illustrating a display example of pattern 1 as an example of the effect display during the promotion chance, and FIG. 124 is a diagram illustrating a display example of pattern 2 as an example of the effect display during the promotion chance. FIG. 125 is a diagram illustrating a display example of the pattern 3 as an example of the effect display during the promotion chance.

(Pattern 1)
FIG. 123 shows an example of effect display in a pattern (pattern 1) in which the promotion chance ends in the first game (first game).

  First, when the promotion chance start lock effect or the promotion chance expectation lock effect (success) is being executed, the sub CPU 201 displays that it has shifted to the promotion opportunity and displays 50 games of the initial ART game number (1G). Locked at eye start).

  Next, the sub CPU 201 finishes the promotion chance start lock effect or the promotion chance expectation lock effect (success), starts the first game (first game), and ends the first game (first game). It is displayed that the number of ART games has been added to 111 games at an arbitrary timing until the game is started (1G start to 1G complete stop).

  Next, the sub CPU 201 starts the second game (second game), ends the promotion chance at an arbitrary timing after the start of the second game (second game), and the number of ART games is 111 games. The confirmation is displayed (from the 2G start to the 2G start). Note that it may be at the end of the first game (first game) that the promotion chance ends and the ART game number is confirmed to be 111 games.

  Thus, in pattern 1, display according to the number of continuations (no restoration pattern) is performed (see FIG. 120).

(Pattern 2)
FIG. 124 shows an example of effect display in a pattern (pattern 2) in which the promotion chance ends at the third game (third game).

  First, when the promotion chance start lock effect or the promotion chance expectation lock effect (success) is being executed, the sub CPU 201 displays that it has shifted to the promotion opportunity and displays 50 games of the initial ART game number (1G). Locked at eye start). Since this display is the same as that in FIG. 123, the illustration is omitted in FIG.

  Next, the sub CPU 201 finishes the promotion chance start lock effect or the promotion chance expectation lock effect (success), starts the first game (first game), and ends the first game (first game). It is displayed that the number of ART games has been added to 111 games at an arbitrary timing until the game is started (1G start to 1G complete stop).

  At this time, in pattern 2, it is determined that the promotion chance continues until the third game (third game).

  Next, the sub CPU 201 indicates that the number of ART games has been added to the 223 game at an arbitrary timing until the second game (second game) starts and the second game (second game) ends. Is displayed (2G start to 2G all stop). Here, in the present embodiment, the number of ART games is increased to 223 games because the number of ART games is added with a certain rule of 111 games, 222 games, 333 games,... The indication of the addition is an irregular display.

  By this irregular display, it is notified that the promotion chance continues until the third game (third game). That is, by displaying the number of ART games “223” that exceeds the number of ART games “222” to be added originally, the number of ART games to be added exceeds “222” (that is, the promotion chance is the third time The game (the third game) is continued and the number of ART games “333” can be acquired at least) is notified. In this pattern 2, “223” exceeding the ART game number “222” is displayed as an example of the irregular display described above. However, the display is not limited to this. For example, “223” to “332” are displayed. Any value can be displayed within the range of "". That is, when the above-described irregular display is performed, the number of ART games that can be added when the promotion chance continues until the second game (second game) is exceeded, and the promotion chance is the third game (third game). Any value can be displayed as long as the value is less than the number of ART games that can be added when the game continues. Further, this value may be determined by lottery.

  At this time, if it is determined in pattern 2 that the promotion chance continues until the fourth game (fourth game), the promotion chance continues until the fourth game (fourth game). A relatively large value may be displayed as compared to the case where it is not determined to do so. Alternatively, a relatively large value may be easily determined by lottery.

  Next, the sub CPU 201 indicates that the number of ART games has been added to the 333 game at an arbitrary timing from the start of the third game (third game) to the end of the third game (third game). Is displayed (3G start to 3G all stop).

  Next, the sub CPU 201 starts the fourth game (fourth game), ends the promotion chance at an arbitrary timing after the fourth game (fourth game) starts, and the number of ART games is 333 games. The confirmation is displayed (from the 4G start to the 4G start). It may be displayed at the end of the third game (third game) that the promotion chance ends and that the number of ART games is confirmed in 333 games is displayed.

  Thus, in pattern 2, display according to the number of continuations (no restoration pattern) is performed (in this case, display according to the number of continuations (with restoration pattern) may be performed), and then the next time The continuation confirmation display is performed, and then the display according to the number of continuations (without the restoration pattern) is performed, and then the acquired ART game number display is performed (see FIG. 120).

(Pattern 3)
FIG. 125 shows an example of effect display in a pattern (pattern 3) in which the promotion chance ends in the second game (second game).

  First, when the promotion chance start lock effect or the promotion chance expectation lock effect (success) is being executed, the sub CPU 201 displays that it has shifted to the promotion opportunity and displays 50 games of the initial ART game number (1G). Locked at eye start). Since this display is the same as that in FIG. 123, the illustration is omitted in FIG.

  Next, the sub CPU 201 finishes the promotion chance start lock effect or the promotion chance expectation lock effect (success), starts the first game (first game), and ends the first game (first game). It is displayed that the number of ART games has been added to 111 games at an arbitrary timing until the game is started (1G start to 1G complete stop).

  Next, the sub CPU 201 starts the second game (second game), ends the promotion chance at an arbitrary timing after the start of the second game (second game), and the number of ART games is 111 games. The confirmation is temporarily displayed (from the 2G start to the 2G start). However, at any timing until the end of the second game (second game) (for example, when the second game is completely stopped), the promotion chance is actually continuing, and the number of ART games is added to 222 games. (2G full stop to 2G full stop).

  Next, the sub CPU 201 starts the third game (third game), finishes the promotion chance at an arbitrary timing after the third game (third game) starts, and the number of ART games is 222 games. The confirmation is displayed (from the 3G start to the 3G start).

  As described above, in pattern 3, display according to the number of continuations (without the revival pattern) is performed (in this case, display according to the number of continuations (with the revival pattern may be performed) may be performed), and then continue. Display according to the number of times (there is a resurrection pattern) is performed, and then the number of acquired ART games is displayed (see FIG. 120).

  As described above, the pachislot machine 1 of the present embodiment has a specific state (for example, promotion chance) in which the game period in the advantageous state (for example, during ART) is extended, and in this specific state, each time the game continues. The game period in the advantageous state is extended. Moreover, it is comprised so that it can determine beforehand whether it continues about the game of the continuous multiple times in a specific state. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  In the pachi-slot 1 of the present embodiment, in the current game in the specific state, when it is determined to continue the game in the specific state until the next game, and to continue the game in the specific state until the next game. It is configured such that the effect executed in the next game can be made different from the case where is determined.

  For example, if it is not determined to continue the game in the specific state until the next game, the advantage that is extended based on the fact that the specific state has continued until the game in the next game When it is decided to continue the game in the specific state until the next game, while the game period of the state is informed, the specific state has continued until the game as the second effect in the next game The game period exceeding the advantageous game period extended based on the game period is notified.

  By comprising in this way, it can notify definitively that a specific state continues, ie, the game period of an advantageous state is further extended, and the interest of a game can be improved more. Moreover, while notifying specifically the game period of the advantageous state added, it is alert | reported that a specific state continues by the contradiction of the aspect, Therefore The interest of a game can be improved more.

[Numerical fluctuation display control]
Next, with reference to FIG. 126, the numerical value fluctuation display control in the pachi-slot 1 of the present embodiment will be described. FIG. 126A shows an example of the specified time in the numerical value change display, and FIG. 126B shows an example of the numerical value change display control when an additional number of ART games occurs in the ART gaming state. These show an example of numerical value fluctuation display control in the ART gaming state when the pachislot 1 is disconnected due to a power failure and then restored and the pachislot 1 returns to the state before the interruption.

  In the pachi-slot 1 of the present embodiment, when various numerical values displayed on the display device 11 (and / or the sub display device 18) are changed during the game, the numerical values before the change are sequentially changed within the range of the specified time. Thus, it is possible to execute numerical value fluctuation display (for example, count-up display or count-down display) for displaying the numerical value after fluctuation.

  And as shown to FIG. 126A, the regulation time for which numerical fluctuation display is performed is prescribed | regulated according to the applicable item (numeric value which is the object of fluctuation).

  For example, when the ART stock is added in the special zone (CP special zone in BB, double special zone) (the number of ART stocks in the special zone), since the specified time is not specified, the numerical value change display Is not performed, and the numerical display of the ART stock number is promptly switched to the numerical display after fluctuation.

  Also, for example, when CP is added (subtracted) (CP counter), when CP is added in a special zone (CP special zone in BB, double special zone) (number of CPs acquired in the special zone) ) Defines a specified time “200 ms”, and the numerical value display is sequentially counted up (or counted down) within the specified time range, and then switched to the numerical value display after fluctuation. .

  Further, for example, when the number of ART games is added (subtracted) (ART remaining game number), the number of remaining games (guaranteed game number) in the double specialized zone is added (subtracted) in the specialized zone (double specialized zone). ) (Remaining number of games in the special zone), the specified time “500 ms” is specified, and the numerical display is sequentially counted up (or counted down) within this specified time, and then fluctuates. It is designed to switch to the later numerical display. In the “ART remaining game count”, when normal ART starts (that is, at the start of one set), a numerical display of the initial number of ART games (or the number of ART games given in the continuous challenge) is displayed. Includes the case to do. Further, the “number of remaining games in the special zone” includes a case where a numerical value of the number of guaranteed games is displayed when the double special zone starts.

  Further, for example, when the number of times of transition from the non-ART gaming state to the ART gaming state is added (ART initial number of times), or when the number of times of transition to normal ART is added (ART number), the specified time “1000 ms The numerical value display is sequentially counted up (or counted down) within the specified time range, and then the numerical value display after the change is switched.

  Here, as shown in FIG. 126B, in the ART gaming state, when the current number of ART games is “40” and “remaining 40 games” is displayed, the number of ART games “10” is added. In the case where the game is performed, the control is performed so that the numerical display indicating “40 remaining games” is sequentially changed and displayed within the specified time “500 ms”, and then the number of ART games “50” after the change is displayed. “Remaining 50 games” is displayed.

  On the other hand, as shown in FIG. 126C, after the pachislot 1 is disconnected due to a power failure in the ART gaming state, when the power is restored and the pachislot 1 returns to the state before the interruption, “0 game remaining” is displayed as an initial display. After that, when the restoration process is completed, “remaining 50 games” for displaying the current ART game number “50” is promptly displayed. In other words, in this case, the numerical display indicating “0 games remaining” is sequentially changed and displayed to display “50 games remaining”.

  In this case, the trigger for switching the initial display “0 remaining games” to “50 remaining games” may be, for example, that a specific command (for example, the above-described game return command) is transmitted from the main control circuit 90. .

  Further, the initial display “0 remaining games” may not be displayed until the restoration process is completed or until the above-described specific command is transmitted from the main control circuit 90.

  Further, the value (initial value) displayed in the initial display is not limited to “0”, and may be an arbitrary value. For example, “50”, which is the initial number of ART games, may be displayed, or a value (for example, “9999”) that the player can clearly recognize as the initial display may be displayed.

  Note that the corresponding item (the numerical value subject to fluctuation) in FIG. 126A is merely an example, and the prescribed time is prescribed in the other relevant items (numeric values subject to fluctuation), and numerical fluctuation display control is performed. It may be performed.

  For example, even when the cumulative number of medals acquired in the ART gaming state (the number of acquired medals during ART) is added (subtracted), a predetermined specified time may be specified and numerical value variation display control may be performed. . In this case, different prescribed times may be set according to the number of medals to be paid out (that is, according to the display combination).

  Further, the “number of medals acquired during ART” may be subjected to numerical value display control even when a replay combination is established. Here, the replay combination does not pay out medals (see FIG. 18), but actually, for example, the replay combination is equivalent to the case where three medals are paid out. Therefore, when a replay role is established, a numerical value change display is added to which “three medals acquired during ART” is added at the end of the game, and “MART acquired during ART” is displayed at the start of the next game (for example, at the start operation). You may make it perform the numerical fluctuation display by which three "number" is subtracted.

  On the other hand, when the replay role is established, the “art medal acquisition number” is not changed at the end of the game, and the “art medal acquisition number” is also set at the next game start (for example, at the start operation). It can also be made not to fluctuate.

  In this embodiment, any of these methods can be adopted. Further, in the present embodiment, for a normal replay combination (for example, RT3 lip) in the ART gaming state, the numerical fluctuation display of “number of medals acquired during ART” is not performed, and a specific replay combination (for example, “ For “F_SP Lip A” to “F_SP Lip C”, etc., it is also possible not to display the numerical change display of “the number of acquired medals during ART”.

  As for the “number of medals during ART”, when the technique of displaying the numerical value change is adopted when the replay role is established, as in the case of the “number of remaining ARTs”, the normal “medal during ART” When it is the display fluctuation timing of “acquired number”, the numerical value change display is performed, and when it is the display fluctuation timing of “number of acquired medals during ART” at the time of power interruption, the numerical value fluctuation display is not performed. Can be configured.

  As described above, in the pachislot machine 1 according to the present embodiment, when a predetermined numerical value (for example, the value of the ART game number counter) fluctuates, the predetermined numerical value is displayed before the changed predetermined numerical value is displayed. Although it is configured so that the effect of presentation is increased by displaying it fluctuating over a predetermined period, if it returns to the state before the power interruption after a power interruption occurs in the gaming machine, the fluctuation display is not performed. The predetermined numerical value after the change (that is, the current) is displayed.

  For example, when a predetermined numerical value corresponds to the remaining game period in a specific gaming state (for example, during ART), and the remaining game period fluctuates, the remaining game period is usually set to a predetermined period ( For example, after the variable display is performed over 500 ms), the remaining game period after the change is displayed. However, when a power failure occurs in the gaming machine and then returns to the state before the power failure, the variable display is performed. Without change, the remaining (ie, current) remaining game period is displayed.

  In other words, at the time of power interruption recovery, control for returning to a gameable state is given priority over control for enhancing the effect. Therefore, it is possible to appropriately restore the content of the performance when the power interruption is restored.

  Further, in the pachislot machine 1 of this embodiment, the control circuit (display control means) side that controls the effects in conjunction with the return to the game-ready state on the control circuit (game control means) side that controls the progress of the game. However, it is configured to be able to return to a game-ready state. At that time, the display of the predetermined numerical value is configured to be switched from the initial value to the current numerical value. Therefore, with a simple configuration, it is possible to notify that the gaming machine returns to a playable state, and it is possible to return the content of the production more appropriately when power is restored.

  So far, the gaming machine according to the present embodiment has been described. And from this embodiment, the technical idea (namely, invention which concerns on this embodiment) as shown at least below can be grasped | ascertained as an example. However, these technical ideas are not limited to those described in the present embodiment, and various changes and modifications can be made. Further, a plurality of technical ideas (a part thereof, that is, including a part of the configuration of the invention according to the present embodiment) can be combined into another technical idea, or a certain technical idea A part of the idea can be used as another technical idea. In addition, a technical idea that is subordinately described in a certain technical idea may be an independent technical idea, or may be subordinated in another technical idea.

  In this embodiment, a pachislot machine has been described as an example of a gaming machine, but this is not intended to limit the invention according to this embodiment. For example, all the inventions according to the present embodiment, except for the case described in the present embodiment, which has a pachislot-specific configuration such as a configuration related to reel control when a stop operation is performed or a configuration related to setting change and confirmation, It can also be applied to a game machine called “pachinko”. For example, checksum generation and determination processing, various processing using an instruction code dedicated to the main CPU 101 (address designation processing using a Q register, soft timer update processing, 7 segment LED drive processing, communication data generation and storage processing, etc. ), Features such as various processes using the non-standard ROM area and non-standard RAM area are also suitable for the pachinko machine.

  That is, the invention according to the present embodiment performs an internal lottery (determination of whether or not to win) based on the fact that a predetermined variation start condition is satisfied (for example, the game ball has passed through the starting region) Variable display is started (identification information is variably displayed), and variable display is stopped (identification information is stopped and displayed) when a predetermined variation end condition is satisfied (for example, the variation time has ended). A pachinko that can be shifted to a special game state (winning game state) based on a predetermined display result being derived, a pachinko that includes game control means for controlling the progress of these games, and an effect display An effect display means for controlling the effect display means, and an effect display control means for controlling the effect display means. The effect display means performs variable display and stop display of decorative symbols according to variable display, and other effect tables. It can be applied to a pachinko to perform.

  Similarly, a slot machine that uses a game ball as a game medium, an enclosed game machine that encloses the game medium and electronically adds game value, and a management frame that can be used and managed by multiple manufacturers in common. The invention can also be applied to other gaming machines such as a gaming machine called a management-type gaming machine in which a gaming board can be mounted in the management frame.

  Further, for example, the various counters and various timers managed by the control of the main CPU 101 or the sub CPU 201 shown in the present embodiment can be managed in a range not departing from the gist of the invention according to the present embodiment. It can be changed as appropriate. For example, various counters and various timers managed by “addition” may be managed by “subtraction”, and various counters and various timers managed by “subtraction” may be “addition”. It is good also as managed by. In this case, for example, the determination of whether or not “to be greater than or equal to” is read as the determination of whether or not it is “less than or equal to”, and the determination of whether or not “exceeds” is “less than”. It is assumed that the determination of whether or not the value has become a predetermined value is read as the determination of whether or not the value is “0”.

  Further, for example, various data such as various counters, various flags, and various timers managed by the control of the main CPU 101 shown in the present embodiment are within the scope not departing from the gist of the invention according to the present embodiment. The various data managed by the control of the sub CPU 201 may be managed by the control of the main CPU 101 without departing from the gist of the invention according to the present embodiment. It is good.

  In addition, for example, various control states managed by the control of the main CPU 101 and internal control states such as various effect game states shown in the present embodiment are within the scope of the invention according to the present embodiment. However, the state relating to various effects managed by the control of the sub CPU 201 may be managed by the control of the main CPU 101 without departing from the gist of the invention according to the present embodiment. It may be done.

[Middle MB production]
In the pachi-slot 1 of the present embodiment, in a gaming state different from the special gaming state (for example, the MB gaming state), a specific combination (for example, “F_black BAR”) that triggers an advantageous state (for example, during ART) In the special gaming state, the winning probability and the execution probability of a specific lock effect that triggers the advantageous state are configured to have the same probability (for example, 8/65536). In other words, an advantageous operation trigger can be obtained with a certain probability regardless of which gaming state the gaming state is. Therefore, the interest of the game can be improved.

  Further, in the pachislot 1 of the present embodiment, when a specific lock effect is executed in a special game state (for example, MB game state), a combination of symbols (for example, “C_black BAR”) related to a specific role is performed. The combination of symbols) is configured to temporarily stop. In other words, if a combination of symbols relating to a specific combination is displayed regardless of which gaming state the gaming state is, the player can be made aware that the trigger for the advantageous state has been established. ing. Therefore, for example, even in a special gaming state, even when there are restrictions on the determination of the internal winning combination and the reel stop control, the player can easily perceive that the operation trigger of the advantageous state has been established. In addition, the interest of the game can be improved.

  In addition, in this embodiment, although the privilege given when a specific combination is won and when a specific lock effect is executed is described as an advantageous operation trigger, Without being limited, the privilege to be granted may be another privilege. For example, a specific right (for example, CP) may be given, or a player's portable terminal that allows the display device 11 and / or the sub display device 18 to acquire a privilege image (or other privilege). It is also possible to display a two-dimensional code that can be read by.

  In the present embodiment, a specific lock effect can be executed only in a special game state (for example, MB game state). However, the present invention is not limited to this. For example, the specific lock effect is also specified in the following cases. It is good also as what can perform this lock production.

  For example, when at least one of a plurality of reels is provided with another special gaming state (for example, CB gaming state) in which the maximum number of sliding symbols is reduced from four symbols to one symbol Similarly, in the special game state, a specific lock effect may be executed.

  In addition, for example, the maximum number of sliding symbols for all of the plurality of reels is four symbols, but when winning a specific combination, it becomes a specific combination in relation to another internal winning combination (for example, BB). Similarly, a specific lock effect may be executed even in a gaming state (for example, the RT4 state in the present embodiment, see FIG. 20) in which such symbol combinations cannot be displayed or are difficult to display. In this case, when a specific combination (for example, “F_black BAR”) is won without performing lottery as to whether or not a specific lock effect is executed, the specific lock effect is executed. You can also

  Also, for example, when a specific combination is configured as a replay combination, a specific lock effect cannot be executed in a gaming state (for example, an RT1 state to an RT3 state) in which the specific combination as the replay combination can be won. In a gaming state where the specific combination cannot be won (for example, the RT0 state and the RT4 state), a specific lock effect may be executed.

  Also, for example, when a specific combination is configured as a bonus combination, a specific lock effect cannot be executed in a gaming state where the specific combination as the bonus combination can be won (for example, the RT0 state to the RT3 state). In a gaming state where a specific combination cannot be won (for example, an RT4 state), a specific lock effect may be executed.

  In addition, for example, when a specific combination can be won by a predetermined number of insertions (for example, 3), but not at a specific insertion number (for example, 2), a predetermined number of medals are inserted. In a game, a specific lock effect may not be executed, and a specific lock effect may be executed in a game in which a specific number of medals are inserted.

  In addition, for example, a combination of symbols related to a specific combination can be easily displayed with a predetermined number (for example, 3), but it is difficult to display with a specific number (for example, 2). In some cases, a specific lock effect cannot be executed in a game in which a predetermined number of inserted medals are inserted, and a specific lock effect can be executed in a game in which a specific inserted number of medals are inserted. It may be.

  That is, this technical idea is that a specific lock effect can be executed in a unit game (or game state) in which a specific role can be won or a combination of symbols related to the specific role can be displayed (or easy to display). On the other hand, in a unit game (or game state) in which a specific combination cannot be won or a combination of symbols related to the specific combination cannot be displayed (or difficult to display), a specific lock effect can be executed. By this, all the forms which can eliminate the unfair feeling which concerns on privilege provision between game states are included. That is, the present invention can be applied to all cases where a predetermined privilege is not given (or difficult to be given) due to lottery restrictions or stop control restrictions.

[Continuous challenge]
In the pachislot machine 1 of the present embodiment, the advantageous state (for example, during ART) is configured to include a first advantageous state (for example, normal ART) and a second advantageous state (for example, continuous challenge). In the second advantageous state, it is configured to be able to grant a plurality of specific rights (for example, CP) for adding the number of games in the first advantageous state and performing lottery (deciding whether to extend the game period). ing.

  In addition, when the specific right is granted when the first advantageous state ends, the state is shifted to the second advantageous state, and in the second advantageous state, the specific right is consumed and the first advantageous state is consumed. When the number of games is added, a lottery (deciding whether or not to extend the game period) is performed, and when the winning lottery is won (when it is determined to extend the game period), the first advantageous state is continued. It is configured to be able to.

  If a plurality of specific rights have been acquired, the specific rights will not be wasted and all will be added to the number of games in the first advantageous state (determination of whether to extend the game period) ). Therefore, in the second advantageous state, not only is it determined whether or not to continue the advantageous state, but also a possibility that a large number of games can be added at a time can be created. A variety of characteristics can be achieved, and the fun of the game can be improved.

  In the present embodiment, the second advantageous state is also an advantageous state (ART gaming state), and information on a stop operation that is advantageous to the player can be notified. Therefore, the specific right substantially has the advantageous state. Acts as an extension. In other words, since the second advantageous state continues until all the specific rights are consumed, it is possible to extend the second advantageous state itself as the number of specific rights acquired increases. Therefore, this also makes it possible to make a variety of games related to the continued advantageous state.

  Further, in the present embodiment, in the second advantageous state, it is assumed that a predetermined effect corresponding to the number of specific rights acquired is performed, and a display result in the game in which the predetermined effect is performed (as a premise thereof) Whether or not the game period of the first advantageous state is extended is determined based on the internal lottery result) (see FIG. 71), but whether or not the game period of the first advantageous state is extended. The manner in which is determined is not limited to this.

  For example, the number of specific rights acquired is the game period of the second advantageous state (that is, the number of continuing games), and in the second advantageous state, an internal winning combination (for the number of specific rights acquired) And / or the display result), it may be determined (lottery) whether or not the game period of the first advantageous state is extended. Further, regardless of the internal winning combination (and / or display result), it may be determined (lotted) whether or not the game period of the first advantageous state is extended with a certain probability. In this case, if the game period of the first advantageous state is not extended even after a predetermined number of lotteries, a relief measure is provided such as increasing the probability that the game period of the first advantageous state will be extended. You may do it.

  In addition, for example, in the second advantageous state, at least a part of the stop operation information is not notified, and when the internal winning combination is the push order, the stop operation is performed in the push order that is advantageous to the player. If the internal winning combination is not the push order when performed, the game period of the first advantageous state is extended when the stop operation is performed in the push order that matches the push order determined by the lottery. May be determined. Alternatively, when a specific internal winning combination that allows display of any of a plurality of specific symbols alternatively arranged so that they cannot be aimed at the same time is determined on the symbol arrangement of a specific reel It is determined that the game period of the first advantageous state is extended when a stop operation is performed at a timing at which a symbol can be displayed (that is, when this specific internal winning combination can be established) You may be made to do.

  Further, for example, it may be determined (lottery) whether or not the game period of the first advantageous state is extended by consuming specific rights acquired at once. In this case, the greater the number of specific rights acquired, the higher the probability of determining that the game period of the first advantageous state will be extended. In this case, the lottery may be performed when the first advantageous state ends without defining the second advantageous state as the gaming state.

  Further, for example, when the number of specific rights acquired is a predetermined number (for example, 10) or more, it may be determined that the game period of the first advantageous state is necessarily extended. . In this case, all of the acquired specific rights may be consumed, or the specific number of rights consumed by lottery may be determined.

  Further, in the present embodiment, basically, the transition to the second advantageous state is made when the first advantageous state ends, but the transition timing (transition opportunity) of the second advantageous state is not limited to this. .

  For example, in the first advantageous state (or another advantageous state), the transition to the second advantageous state may be made based on the establishment of a predetermined transition opportunity. This predetermined transition opportunity corresponds to the second advantageous state when, for example, the first advantageous state (or other advantageous state) and the second advantageous state are configured to play a game in different RT states. It is only necessary to transition to the RT state. Note that the transition to the RT state corresponding to the second advantageous state is made when a predetermined combination of symbols is displayed by stopping operation in an appropriate pressing order when a predetermined pressing order is won. In this case, in the first advantageous state (or other advantageous state), whether or not to notify the stop operation information for displaying the predetermined symbol combination (that is, whether to shift to the second advantageous state) is determined by lottery. It may be determined.

  In addition, for example, the predetermined transition opportunity may be that a lottery is performed to determine whether or not to shift to the second advantageous state in the first advantageous state (or another advantageous state), and this lottery is won. In this case, when it is decided to shift to the second advantageous state, it may be immediately shifted to the second advantageous state, or may be shifted to the second advantageous state via a predetermined precursor state. May be. In addition, the predetermined sign state may be until the predetermined push order described above is won.

  Further, for example, in the advantageous state, the specific number of rights acquired is not clearly indicated to the player, and when the first advantageous state ends, the fact that the advantageous state has ended is displayed and the player is once in the normal gaming state. If a specific right has been acquired in the advantageous state after displaying, the second is passed through the specific precursor state (or from the next game in which the first advantageous state is displayed). You may make it transfer to an advantageous state. Further, the actual gaming state may be subjected to transition control in the order of the first advantageous state (“normal ART”), the normal gaming state (“normal time”), and the second advantageous state (“continuation challenge”). Note that this specific precursor state may be until the predetermined push order is won. In this case, even after the advantageous state has ended (or after the fact that the advantageous state has ended is displayed), the possibility of shifting to the second advantageous state can remain, so that the game It is possible to maintain the player's expectation and to prevent the player from stopping the game and reducing the operating rate of the gaming machine.

  Further, in the present embodiment, an object whose game period can be extended in the second advantageous state is the game period of the first advantageous state, but an object whose game period can be extended in the second advantageous state is not limited thereto. .

  For example, in the second advantageous state, it is determined whether or not to extend the game period of another advantageous state (for example, “promotion chance”, “double specialization zone”, or “continuation challenge” itself). May be. In addition, for example, when the second advantageous state (“continuation challenge”) can be transferred from any of the other advantageous states (for example, “promotion chance”, “double specialized zone”, and “normal ART”). In the second advantageous state, it may be determined whether or not to extend the game period of the advantageous state before the transition (pre-start state).

  In other words, this technical idea makes it possible to grant a specific right in the advantageous state, and consumes the granted specific right at a predetermined time of the advantageous state (for example, when the advantageous state ends). By deciding whether or not to extend the game period, all forms that can improve the interest related to continuing the advantageous state are included.

  Further, in pachinko (which may be the above-described enclosed game machine or management game machine, the same applies hereinafter), as an advantageous state, for example, when it is determined whether or not a win is determined, A high-probability state (probability change state) in which the probability to be determined is high, a movable member (for example, an electric device) for assisting (that is, supporting) that a game ball easily passes (wins) a specific starting area. The electric support state (high) that increases the operation probability (opening probability) of the operation pattern (opening pattern) or increases the probability that the operation pattern (opening pattern) becomes an advantageous operation pattern (opening pattern) than usual. (Base state), the time until the variable display stops (fluctuation time) can be shortened more easily than usual, so that more games can be played in a short time, game balls pass through a specific area When a winning is determined by (V winning), a movable member is provided so that it is difficult or easy to pass the game ball to the specific area, and the movable member is used for the game ball to the specific area. A gaming state that increases the operation probability (opening probability) to operate so as to facilitate the passage of the game, or increases the probability that the operation pattern (opening pattern) becomes an advantageous operation pattern (opening pattern) than usual, And other advantageous conditions may be employed.

  For example, when a limit (limiter) is provided for the number of consecutive hits in the high probability state (probability variation state) described above, the number of consecutive hits is subtracted or initialized (0) based on a specific right. It may be possible to extend the advantageous state by performing a clearing process.

  In pachinko, a specific right can be given as specific control data when it is detected that a game ball has passed (winning) the above-mentioned various areas or other areas. The lottery is performed based on the lottery result, and can be given as specific control data based on the lottery result.

  Further, in the pachinko machine, a specific right may be that the above-described opening of the movable member (or an advantageous opening pattern) is selected, or a right to variably display the identification information (for example, also called holding information or holding ball) May be a specific right.

  In addition, in the pachinko, a predetermined member capable of physically retaining (holding) the game ball rolling in the game area at a predetermined position is provided, and the retention (holding) of the game ball retained (held) by the predetermined member is provided. ) Is released, and whether or not the advantageous game period is extended may be determined depending on whether or not the game ball passes a specific area. Thereby, the interest about continuation of an advantageous state can be improved, improving the pachinko peculiar interest to enjoy the motion of the rolling game ball.

[CP priority digestion]
In the pachislot machine 1 of the present embodiment, the advantageous state (for example, during ART) is configured to include a first advantageous state (for example, normal ART) and a second advantageous state (for example, continuous challenge). Perform a first right (for example, ART stock) to continue the first advantageous state, and add lottery (determination of whether to extend the game period) of the number of games in the first advantageous state in the second advantageous state Therefore, the second right (for example, CP) can be granted.

  Then, when the first advantageous state ends, if both the first right and the second right are granted, control is performed so as to give priority to shifting to the second advantageous state. Has been. That is, the second right is digested in preference to the first right.

  In this case, in the second advantageous state, when the second right is consumed and the number of games in the first advantageous state is added and a lottery (determination of whether to extend the game period) is performed, and the additional lottery is won ( If it is decided to extend the game period), the first advantageous state can be continued without consuming the first right, and if the winning lottery is not won (the game period can be extended) The first advantageous state can be continued by consuming the first right even if it is not determined. Therefore, while ensuring the sense of security related to the continuation of the advantageous state, it is possible to make a variety of games and improve the interest of the game.

  In addition, when the first advantageous state ends, the first advantageous state is continued by the consumption of the second right or the consumption of the first right even if the state is shifted to the second advantageous state. Since the possibility can remain, the expectation regarding the continuation of the advantageous state can be maintained.

  It is possible to acquire a plurality of second rights in an advantageous state, and when a plurality of second rights are acquired, the second right is not wasted, It is configured to be used for an additional lottery (determination of whether or not to extend the game period) for the number of games in the first advantageous state. Therefore, in the second advantageous state, it is possible not only to determine whether or not to continue the advantageous state, but also to create a possibility that a large number of games can be added at one time. Can improve the interest of the game.

  In the present embodiment, when the second right is prioritized over the first right and the game period of the first advantageous state is extended by the acquired second right, The first advantageous state is not continued and the first advantageous state is continued, but when the priority of the second right over the consumption of the first right is given, the mode of extending the advantageous gaming period is Not limited to.

  For example, even when the game period of the first advantageous state is extended by consumption of the second right, the first right is also consumed to extend the game period of the first advantageous state, and this second advantage In the state, a larger number of games may be added (a longer game period is extended).

  Specifically, if the first right is granted when the game period extended in the second advantageous state is less than the predetermined game period, the first right is also consumed, A game period longer than the game period may be extended. For example, if the predetermined game period is 50 games, which is one set of basic game periods, and the game period of 30 games is extended based on the second right in the second advantageous state. When the second advantageous state ends, the game period of 50 games is extended based on the first right (ie, consuming 1 ART stock), and the game period of 80 games is generally extended. That may be displayed to the player to that effect.

  In this case, the predetermined game period may be set as a game period different from one set of basic game periods. For example, when the predetermined game period is 100 games, when the game period of 50 games is extended based on the second right in the second advantageous state, the second advantageous state ends. In addition, based on the first right (ie, consuming 1 ART stock), the game period of 50 games has been extended, and the game period of 100 games has been extended as a whole. If the game period of 100 games is extended based on the rights of 2, the first right is not consumed, the game period of 100 games is extended, and the second advantageous state is If the game period is not extended based on the right of 2, the game period of 100 games may be extended based on the first right (that is, consuming 2 ART stocks).

  In this case, in the advantageous state, the acquired first right and the second right should not be specified, and in the second advantageous state, the lottery result based on the second right should not be specified. When shifting (returning) from the second advantageous state to the first advantageous state, it is not clearly indicated which rights have been consumed, and simply 100 games (or 50 or more games in the above-mentioned other examples) ) Is added (extended) may be displayed to the player. In this way, it is possible to make it difficult to understand what rights have been consumed and the transition to the first advantageous state (return), so that the gameability relating to the continuation of the advantageous state is made more diverse. Can do.

  The predetermined game period described above is not limited to the example described above, and can be set arbitrarily. For example, the average winning probability of the first right (eg, ART stock), the average winning probability of the second right (eg, CP), or the first right and the second The reciprocal of the average winning probability of the right may be set as a predetermined game period. In this way, in the first advantageous state that has shifted (returned) from the second advantageous state, at least one player is expected to be able to acquire the first right and / or the second right. Can improve the interest of the game.

  Further, in the second advantageous state, when it is determined that the game period exceeding the above-described predetermined game period is extended, not all of them are displayed when shifting (returning) to the first advantageous state, A part of the game period is displayed, and the remaining game period is displayed at an arbitrary timing during the first advantageous state (for example, when the display indicating that the first advantageous state ends). Also good. That is, the timing at which the extended game period is displayed to the player in the second advantageous state can be arbitrarily set.

  In addition, as described above, when a certain limit (limiter) is provided for the continuation of the advantageous section advantageous to the player, and when the state shifts to the second advantageous state just before the end of this advantageous section, In the second advantageous state, it may not be possible to extend the game period exceeding the limit, or even if the game period is extended beyond the limit, the limit is exceeded. A message indicating that the game period has been extended may not be displayed.

  In the present embodiment, when the predetermined game period is extended in the second advantageous state, a signal indicating that is sent to an external gaming device (for example, the external concentration terminal board 47). , Data display, game medium lending device, hall management device, etc.). Thereby, it can be made to recognize appropriately also in the external game device that the advantageous state continued.

  That is, this technical idea makes it possible to grant, in the advantageous state, the first right to decide to extend the advantageous state and the second right to decide whether or not to extend the advantageous state. Continuation of the advantageous state by determining whether or not to extend the gaming period of the advantageous state based on the first right and the second right at a predetermined time of the state (for example, when the advantageous state ends) It includes all forms that can improve the interest of

[Promotion chance]
The pachislot machine 1 of the present embodiment has a specific state (for example, promotion chance) in which the game period of the advantageous state (for example, during ART) is extended, and in this specific state, the game in the advantageous state every time the game continues. The period is configured to be extended. Moreover, it is comprised so that it can determine beforehand whether it continues about the game of the continuous multiple times in a specific state. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  In the pachi-slot 1 of the present embodiment, in the current game in the specific state, when it is determined to continue the game in the specific state until the next game, and to continue the game in the specific state until the next game. It is configured such that the effect executed in the next game can be made different from the case where is determined.

  For example, if it is not determined to continue the game in the specific state until the next game, the advantage that is extended based on the fact that the specific state has continued until the game in the next game When it is decided to continue the game in the specific state until the next game, while the game period of the state is informed, the specific state has continued until the game as the second effect in the next game The game period exceeding the advantageous game period extended based on the game period is notified.

  By comprising in this way, it can notify definitively that a specific state continues, ie, the game period of an advantageous state is further extended, and the interest of a game can be improved more. Moreover, while notifying specifically the game period of the advantageous state added, it is alert | reported that a specific state continues by the contradiction of the aspect, Therefore The interest of a game can be improved more.

  In addition, in this embodiment, although the specific state demonstrates the aspect by which the game period of an advantageous state is extended whenever the game in the specific state continues, a privilege is obtained by the game in a specific state continuing. The mode given is not limited to this.

  For example, it is possible to shift from a normal gaming state (for example, during non-ART) to a specific state, and a predetermined number of points (specific numerical value) is given each time the game continues in the specific state, and the number of points given is determined in advance When the number of points obtained (or determined by lottery) is reached (when a predetermined achievement condition is satisfied), a privilege of shifting to an advantageous state may be given. In this case, an effect pattern (see FIGS. 72 and 123 to 125) corresponding to the number of points to be given may be determined.

  In this case, in the specific state, there is a predetermined number of points (or determined by lottery), and each time the game continues in the specific state, a predetermined number of points (specific numerical value) When the number of points becomes 0 (when a predetermined achievement condition is satisfied), a privilege of shifting to an advantageous state may be given.

  In these cases, the number of games in the advantageous state may be added (the game period in the advantageous state is extended) when a predetermined achievement condition is satisfied in the specific state shifted from the advantageous state.

  In addition, as described above, when a specific numerical value is decreased every time a game continues in a specific state and an effect corresponding to that is performed, for example, in the specific state, a battle effect between a teammate character and an enemy character When the enemy character's hit points (predetermined achievement conditions) are displayed and the game continues, the teammate character is attacked and the damage corresponding to the attack (specific (Numerical value) is reduced from the hit point. At this time, if it is determined that the specific state will continue until the next game, in the next game, a value corresponding to the damage larger than the damage corresponding to the normal attack is reduced from the hit point ( The next continuation confirmation display) may be performed. Thereby, like this embodiment, it can alert | report that a specific state continues until the next game, and it can suppress that a production | generation becomes monotonous by giving a variation to the change of a numerical display. Can do.

  Note that whether or not the predetermined achievement condition is satisfied may be determined in advance before the specific state starts or when the specific state starts. In addition, it may be determined in advance whether or not a predetermined achievement condition is satisfied and at what timing (for example, in which game in a specific state) it is satisfied. In this case, either the display corresponding to the number of continuations or the next continuation confirmation display may be performed depending on at which timing a predetermined achievement condition is satisfied.

  In pachinko, for example, a big hit gaming state (first specific state) with 5 rounds, a big hit gaming state (second specific state) with 10 rounds, and a round number of 15 rounds. When a big hit gaming state (third specific state) is provided, at the start of the fifth round (or during execution of the fifth round) and at the start of the tenth round (or execution of the tenth round) In the fifth round of the second specific state, it is possible to increase the rank as the second effect. As an effect, the next continuation confirmation display may be performed by displaying the number of rounds “6”. In the 10th round of the third specific state, As a rank-up rendition of as 2 of production, it may be continuously determined display next time is carried out by displaying the number of rounds "11". In other cases, the actual number of rounds may be displayed so that display according to the number of continuations (first effect) may be performed.

  In other words, this technical idea is advantageous to the player whenever a game in a specific state continues in a specific state, and it is possible to determine in advance until a predetermined time how long a game in a specific state will continue. In addition, all forms that can improve the interest of the game by changing the effect to be performed according to the determination are included.

[Special production]
In the pachi-slot 1 of the present embodiment, there is a plurality of specific internal states (for example, normal mode), and when there is a change in the specific internal state, it is reserved to execute a predetermined effect (for example, a special effect) After that, when a predetermined execution condition is satisfied, a predetermined effect is executed.

  For example, when there are a plurality of lottery states having different transition probabilities to the advantageous state (for example, during ART) as the plurality of specific internal states, the lottery state becomes an advantageous lottery state, or the advantageous state If there is a precursor state where the transition to the state is awaited, execution of a predetermined effect is reserved when the precursor state is reached.

  Then, when a predetermined display result (for example, a combination of symbols of “S_TL Lip”) is derived (that is, when a predetermined internal winning combination (for example, “Normal Lip”) is established), a predetermined effect is executed. It is configured to be. In other words, every time a predetermined display result is derived, the player can expect whether or not a predetermined effect will be executed, and a unit game with a change in a specific internal state and a predetermined effect will be executed. The unit game to be played can be different. Therefore, when there are a plurality of specific internal states, various specific internal state suggestions can be provided.

  As described in the present embodiment, a probability (see FIGS. 16 to 21) that a predetermined display result (for example, a combination of symbols of “S_TL Lip”) can be derived, that is, a predetermined execution condition is satisfied. The probability is higher than the probability that the normal mode shifts to the advantageous mode (see FIG. 29), that is, the probability that the lottery state becomes the advantageous lottery state. Thereby, the frequency of the game in which the specific internal state can be suggested can be increased, and the player's expectation can be maintained.

  Further, in the present embodiment, the aspect in which the predetermined execution condition is satisfied by deriving the predetermined display result is described, but the aspect in which the predetermined execution condition is satisfied is not limited thereto.

  For example, when a special effect execution lottery is performed based on a game state or an internal winning combination and a special effect execution lottery is won, a predetermined execution condition may be established. Also, for example, when a display result other than the predetermined display result described in the present embodiment (for example, a combination of symbols of “S_TL Lip”) is derived, the predetermined execution condition may be satisfied.

  Further, for example, when a specific operation is performed on the touch sensor 19, a predetermined execution condition may be established. Further, for example, a separate operation button (not shown) may be provided, and a predetermined execution condition may be established when a specific operation is performed on the operation button. In addition, for example, when a specific operation is performed on the start lever 16 or the stop buttons 17L, 17C, and 17R, a predetermined execution condition may be satisfied. Further, in these cases, it is urged to perform a specific operation, and whether or not to perform the specific instruction effect indicating the procedure of the specific operation is determined based on the determination value for the special effect and the value of the special effect reservation parameter. It is good also as what establishes predetermined | prescribed execution conditions, when a lottery is performed and specific instruction | indication effect is performed based on this lottery result and specific operation is performed.

  That is, this technical idea has a plurality of specific internal states, makes it possible to perform a predetermined effect that suggests the specific internal state, and determines whether or not the predetermined effect can be executed, By determining whether or not to execute the production, it is possible to include all forms that can make various suggestions of the specific internal state.

[Numerical fluctuation display control]
In the pachislot machine 1 of this embodiment, when a predetermined numerical value (for example, the value of the ART game number counter) fluctuates, the predetermined numerical value fluctuates over a predetermined period before the changed predetermined numerical value is displayed. Although it is configured to increase the production effect by being displayed, when the power failure occurs in the gaming machine, when returning to the state before the power interruption, without displaying the fluctuation, It is configured to display a predetermined numerical value (that is, current).

  For example, when a predetermined numerical value corresponds to the remaining game period in a specific gaming state (for example, during ART), and the remaining game period fluctuates, the remaining game period is usually set to a predetermined period ( For example, after the variable display is performed over 500 ms), the remaining game period after the change is displayed. However, when a power failure occurs in the gaming machine and then returns to the state before the power failure, the variable display is performed. Without change, the remaining (ie, current) remaining game period is displayed.

  In other words, at the time of power interruption recovery, control for returning to a gameable state is given priority over control for enhancing the effect. Therefore, it is possible to appropriately restore the content of the performance when the power interruption is restored.

  In conjunction with the return to the game-enabled state on the control circuit (game control means) side that controls the progress of the game, the game can also return to the game-ready state on the control circuit (display control means) side that controls the effects. It is configured to be able to. At that time, the display of the predetermined numerical value is configured to be switched from the initial value to the current numerical value. Therefore, with a simple configuration, it is possible to notify that the gaming machine returns to a playable state, and it is possible to return the content of the production more appropriately when power is restored.

  As described in the present embodiment, the predetermined numerical value can be applied to any numerical value as long as it is a numerical value relating to a game. However, the predetermined numerical value is a numerical value related to the game, and is particularly preferably a numerical value necessary for the progress of the game.

  Further, in the present embodiment, a case has been described in which a specific numerical value fluctuation display is not performed when a power failure occurs in a gaming machine and then returns to the state before the power interruption. The mode of not performing is not limited to this.

  For example, even when the gaming machine returns to a state in which a game can be played after a setting change or setting confirmation, a specific numerical value fluctuation display may not be performed. In particular, in the setting confirmation scene, it is necessary to quickly return to the state before the setting confirmation after the setting confirmation is completed, so that the production content can be appropriately restored at the time of the setting confirmation. It is thought that you can.

  That is, this technical idea includes all forms in which the contents of the production can be appropriately restored in a scene where priority is given to the control for returning to a game-ready state.

[Game history display function]
In the pachi-slot 1 of the present embodiment, a sub display device 18 is provided separately from the display device 11 (projector mechanism 211 and display unit 212), and various information useful to the player is displayed by the sub display device 18. For example, as shown in FIGS. 5A to 5E, a top screen 221 representing an outline game history, a menu screen 222 capable of various operations on the pachislot 1, and game information screens 223, 224, and 225 representing a detailed game history are displayed as sub-display devices. 18 can be displayed.

  Further, the pachislot machine 1 of the present embodiment has a function of enabling registration of a player who performs a game and a function of providing a unique service to the registered player via the sub display device 18. For example, in this embodiment, when the player registration is not accepted, the game information screens 223, 224, and 225 showing the detailed game history are not displayed on the sub display device 18, but the player registration is not performed. If it is received, the game information screens 223, 224, and 225 showing the detailed game history are displayed on the sub display device 201. Making it possible to confirm a more detailed game history leads to an improvement in the convenience of the player. Therefore, in the present embodiment, the convenience can be improved when registration of the player is accepted.

  Further, in the pachislot machine 1 of the present embodiment, the sub display device 18 is provided separately from the display device 11 that produces effects. The sub display device 18 is controlled by the sub control board 72 (sub CPU 201) via the liquid crystal relay board 87. Moreover, the display unit 212 which comprises the display apparatus 11 is controlled by the sub control board 72 (sub CPU201) via the accessory relay board | substrate (not shown). Therefore, in the present embodiment, the sub display device 18 can be controlled separately from the display device 11. Specifically, the display screen of the sub display device 18 can be switched even during the game (that is, during the performance of the display device 11). Therefore, even during the game, the player can acquire various information by switching the display of the sub display device 18 without interfering with the effect performed by the display device 11.

  Further, in the display device 11 of the pachislot machine 1 of the present embodiment, a planar image display is used by switching a plurality of screen mechanisms (display units 212) that cause an image to appear by irradiation of irradiation light from the projector mechanism 211. When performing an effect, an effect using an image display with a sense of depth (stereoscopic effect), and an effect using a curved image display, the effect can be remarkably enhanced. However, such a display form of information is not suitable for displaying information that is not related to an effect such as a game history during the effect. Therefore, in the pachi-slot 1 of the present embodiment, information that is not related to the effect can be displayed on the sub display device 18 provided separately from the display device 11, so that the effect of the effect is not impaired and the game Various information such as history can be displayed appropriately.

  By the way, in a general pachislot machine, when viewed from the player side, a medal slot 14 is provided on the right side of the pedestal portion 13, and bet buttons 15 a and 15 b and a start lever 16 are provided on the left side of the pedestal portion 13. Therefore, usually, when the game is advanced, the player operates the operation unit on the right side or the left side (side) of the pedestal unit 13.

  On the other hand, in the pachislot machine 1 of the present embodiment, the sub display device 18 is provided on the side (left side) of the surface standing upright from the pedestal portion 13, and the sub display device 18 is displayed on the screen of the sub display device 18. A touch sensor 19 for switching the display screen is provided. Therefore, in this embodiment, the sub display device 18 and the input device (touch sensor 19) for controlling the display are provided at a place where the player's hand is located during the game. Can be improved. In particular, as in this embodiment, when the sub display device 18 with the touch sensor 19 is provided on the surface of the pedestal portion 13 that is erected from the horizontal plane, the player places his / her hand on the pedestal portion 13. However, the sub display device 18 can be operated. In this case, not only the operability of the player is improved, but also the fatigue of the player accompanying the operation can be reduced, and as a result, an improvement in the operating rate can be expected.

[Non-standard ROM area and non-standard RAM area]
In the pachi-slot 1 of the present embodiment, as shown in FIG. 12B, various programs and various types used for various processes (various processes that do not affect the game characteristics) that are not directly related to the game performance of the game performed by the player. Data (table) is stored in a non-specified ROM area located at an address different from the game ROM area in the main ROM 102.

  In such a configuration of the main ROM 102, programs and data that are not necessary for the game itself actually performed by the player are placed in the ROM area (non-regulated ROM area) where it is impossible to place a program or the like according to conventional rules. can do. Therefore, in the present embodiment, it is possible to avoid compression of the capacity of the game ROM area in the main ROM 102 of the main control board 71, and it is possible to improve the expandability of programs and tables in the main ROM 102.

[Processing at power-on (reset interrupt)]
In the power-on (reset interrupt) process of the pachislot machine 1 according to the present embodiment, as shown in FIG. 36, the first 1.1172 ms cycle interrupt process is performed immediately after power recovery (before the sum check) (S7 and S8). ), A no-operation command is transmitted from the main control circuit 90 to the sub-control circuit 200. In this way, by permitting the interrupt processing immediately after the power is restored, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

  Further, the communication parameters 1 to 5 constituting the no-operation command transmitted immediately after the power is restored are set with the data stored in the L register, H register, E register, D register and C register, respectively, when the power is restored. Is done. Therefore, in the present embodiment, the sum value (BCC) of the no-operation command transmitted in the interrupt process immediately after the power recovery can be made different every time the power is recovered, thereby suppressing illegal acts such as goto. it can.

  Furthermore, the control for displaying the error code “rr” on the 2-digit 7-segment LED in the information display 6 performed in the process of S13 during the process of turning on the power (reset interrupt) is performed by one “LDW”. ”Command (predetermined read command), the 7-segment common output (selection) data output operation to the 2-digit 7-segment LED and the 7-segment cathode output data output operation are performed simultaneously (see FIG. 37C). That is, in the pachislot machine 1 of the present embodiment, when the 2-digit 7-segment LED is dynamically controlled in the power-on (reset interrupt) process, the 7-segment common output (selection) data and the 7-segment cathode output data are Output simultaneously.

  In this case, the number of instruction codes necessary for dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Thus, the playability can be improved.

[Game return processing]
In the game return process of the pachi-slot 1 of this embodiment, as shown in FIG. 38, while ensuring the input / output state of each port at the time of power interruption at the time of power recovery, The reel control management information is acquired when the power is restored, and processing necessary for starting the reel re-rotation is also performed (see S25 to S32). Therefore, in this embodiment, even when the power is restored from the power interruption during the reel rotation, the reel re-rotation control can be stably performed, and the player is not discomforted.

  Moreover, the pachislot 1 of this embodiment is provided with the microprocessor 91 with the security function for game machines as mentioned above. The microprocessor 91 is provided with various kinds of instruction codes (instruction codes dedicated to the main CPU 101) specific to the microprocessor 91 that can be defined in the source program, and the instruction codes dedicated to the main CPU 101 are used in various processes. As a result, processing efficiency and program capacity can be reduced.

  For example, in the game return process, as shown in FIG. 38, the “LDQ” instruction, which is one of the instruction codes dedicated to the main CPU 101, is used on the source program. The “LDQ” instruction is an instruction code for performing address designation using a Q register (extension register), and can access the main ROM 102, the main RAM 103, and the memory map I / O as direct values as described above. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program for the game return process (the capacity used for the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Setting change confirmation process]
In the setting change confirmation process of the pachi-slot 1 of this embodiment, as shown in FIG. 41A, the “BITQ” instruction and the “SETQ” instruction (predetermined instructions), which are instruction codes dedicated to the main CPU 101, are used on the source program. . Each of the “BITQ” instruction and the “SETQ” instruction is an instruction code for specifying an address using a Q register (extension register). When these instruction codes are used, the main RAM 103 is a direct value as described above. And the memory map I / O can be accessed. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to increase the free space of the main ROM 102 and to increase the processing speed.

  Also, the setting change command (initialization command) generation and storage process performed at the time of setting change / setting confirmation in S46 and at the time of setting change / setting confirmation end in S57 during the setting change confirmation process is as shown in FIGS. 41A and 41B. In addition, it is executed by a “CALLF” instruction which is an instruction code dedicated to the main CPU 101 on the source program. The jump destination address designated by the “CALLF” instruction in S46 is the same as the jump destination address designated by the “CALLF” instruction in S57. That is, in the present embodiment, a setting change command (initialization command) generation and storage process to be transmitted to the sub-control circuit 200 at the time of setting change (when a gaming machine is started), at the time of setting check start (during normal operation), and at the end of setting check Are the same as each other, and the source program is shared (modularized) in both processes of S46 and S57.

  In this case, since it is not necessary to provide a source program for generating and storing the setting change command separately in both the processes of S46 and S57, the capacity of the source program (the capacity of the main ROM 102) can be reduced correspondingly. it can. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Setting change command generation and storage processing]
In the setting change command generation / storage processing of the pachi-slot 1 of the present embodiment, as shown in FIG. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), communication parameters 3 and 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side. New information is set in the communication parameter. On the other hand, the other communication parameters 1, 2, and 4 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side. And 4 are set to values currently stored in the L register, H register, and D register, respectively. Therefore, the values of the communication parameters 1, 2, and 4 when the setting change command (initialization command) is transmitted are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[Communication data storage processing]
In the communication data storing process of the pachi-slot 1 of this embodiment, as shown in FIG. 44, the data stored in the A register is set as the type data of the communication command, and the L register, H register, E register, D register, and C The data stored in the register is set as communication parameters 1 to 5 of the communication command, and the data stored in the B register is set as gaming state flag data of the communication command. That is, in this embodiment, when creating communication data (command data) of one packet (8 bytes), various parameters are transferred from the register and stored in a communication data temporary storage area (communication buffer).

  In this case, when command data including an unused parameter is created, the value of the unused parameter becomes an indefinite value every time it is created. That is, in command data including unused parameters, even if there is command data of the same type and the values of the used parameters are the same, the command data sum value (BCC data) can be changed every time the command is created. . Therefore, in this embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress illegal acts such as goto, and it is necessary to add unnecessary goth countermeasure processing. Therefore, it is possible to suppress the compression of the program capacity of the main control circuit 90 due to the addition of the anti-going process.

[Communication data pointer update processing]
In the communication data pointer update process of the pachislot 1 of the present embodiment, as shown in FIG. 47A, an “ICPLD” instruction that is an instruction code dedicated to the main CPU 101 is used on the source program.

  In the communication data pointer update process, the “ICPLD” instruction is an instruction code in which the upper limit determination instruction of the transmission buffer and the determination branch instruction are integrated. Therefore, an instruction code for executing each instruction process separately is provided. There is no need to provide it. Therefore, by using the “ICPLD” instruction, it is possible to reduce the capacity of the source program for the communication data pointer update process (the capacity used by the main ROM 102). As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Checksum generation processing and sumcheck processing]
In the pachi-slot 1 of this embodiment, in the checksum generation process (not specified) performed at the time of power interruption, as shown in FIG. 49, the checksum is calculated by sequentially adding data in the main RAM 103. On the other hand, in the sum check process (not specified) performed when the power is turned on (when the power is restored), as shown in FIG. 51, the check sum value generated when the power interruption occurs is stored in the main RAM 103 when the power is restored. The data is sequentially subtracted, and whether or not an abnormality has occurred is determined based on whether or not the final subtraction result is “0”. In other words, in the present embodiment, the checksum generation process when power interruption occurs is performed by the addition method, and the checksum determination process when power is restored is performed by the subtraction method.

  When such checksum generation processing and determination processing are employed, it is not necessary to generate the checksum again when the power is restored and to check the checksum with the checksum when the power interruption occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, in the main ROM 102, it is possible to secure (increase) the free space corresponding to the omission of the collation instruction code, and it is possible to improve the gameability by utilizing the increased free space. Become.

[Medal reception / start check processing]
In the medal acceptance / start check process of the pachi-slot 1 of this embodiment, as shown in FIG. 55, a setting change confirmation process (the process of S233) is performed, but this process is executed regardless of the gaming state. Therefore, in this embodiment, even if the gaming state is a bonus state (special prize operating state), the set value and the hall menu (various history data (error, power interruption history, etc.)) can be confirmed, Can be suppressed.

[Medal insertion processing]
In the medal insertion process of the pachi-slot 1 of the present embodiment, as shown in FIG. 57, in the process of S244, the LED lighting data for displaying the number of medal insertions is generated not by the loop process referring to the table but by the calculation process. . Specifically, a series of source codes “LD A, L” to “OR L” in the source program shown in FIG. 58 are sequentially executed to generate LED lighting data for displaying the number of inserted medals.

  When the LED lighting data for displaying the number of inserted medals is generated by calculation processing, the free space in the table area of the main ROM 102 can be increased and the increase in the program capacity can be minimized. That is, in the medal insertion process of the present embodiment, the medal insertion LED display process can be made more efficient, the free capacity of the main ROM 102 is secured (increased), and the increased free area is utilized to increase the game performance. Can be increased.

[Medal insertion check process]
In the medal insertion check process (see FIG. 59) of the pachi-slot 1 of the present embodiment, the normal change value generation process of the medal sensor input state in S257 is performed by an arithmetic process, not a process of obtaining with reference to a table. Specifically, the medal sensor input state normal change value is calculated by sequentially executing the source code “RLA” and “AND cBX_MDINSW” in the source program shown in FIG.

  By changing the detection process of the change state of the medal sensor input state from the table reference process to the calculation process, the free space in the table storage area of the main ROM 102 can be increased and the increase in the program capacity can be minimized. it can. Therefore, by adopting the processing method described above, it is possible to increase the efficiency of the detection process of the change state of the medal insertion sensor state, and it is possible to improve the gameability by utilizing the increased free space in the main ROM 102. it can.

[Internal lottery processing]
In the internal lottery process (see FIG. 64) of the pachi-slot 1 of this embodiment, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 65A. As a result of the execution of the “LDIN” instruction, in the processing of S305, determination data is stored in the A register and a request flag status is stored in the C register. Further, by executing the “LDIN” instruction, the address set in the HL register is updated by +2 (added by 2).

  That is, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed with one instruction code ("LDIN" instruction). In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  In addition, the addition processing of the set value data (any one of 0 to 5) in S309 of the internal lottery processing is performed by the main CPU 101 using the source codes “MUL A, 6” and “ADDQ A, (.LOW.wWAVENUM) in FIG. 65B. ) "In this order.

  The “MUL” instruction is an instruction code for multiplication processing dedicated to the main CPU 101, and the execution of this instruction is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, in the pachislot machine 1 of the present embodiment, an arithmetic dedicated circuit (arithmetic circuit 107) for executing multiplication processing and division processing on the source program is provided, so that the efficiency of the multiplication processing and division processing is improved. Can do.

  The “ADDQ” instruction (predetermined addition instruction) is an instruction code dedicated to the main CPU 101, and is an instruction code for performing address designation using the Q register (extension register). By using this “ADDQ” instruction, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values. Therefore, by using the “ADDQ” instruction, an instruction relating to address setting can be omitted on the source program of the internal lottery process, and the capacity of the source program (usage capacity of the main ROM 102) is reduced correspondingly. Can do. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Design code acquisition processing]
In the symbol code acquisition process (see FIG. 75) of the pachi-slot 1 of the present embodiment, the data related to winning is compressed / decompressed according to the processing procedure described in S647 to S649, and the instruction dedicated to the main CPU 101 in the process By using a code (“CALLF” instruction or the like), it is possible to improve the efficiency of compression / decompression processing of data related to winning, and to effectively utilize the limited capacity of the main RAM 103.

  In the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address specified by the “CALLF” instruction is the compression executed in the symbol setting process (see S205 of FIG. 54). In the data storage process (not shown), it is the same as the jump destination address specified by the “CALLF” instruction. That is, in the present embodiment, the source program for executing the compressed data storage process is shared (modularized) in both the symbol code acquisition process and the symbol setting process. In this case, since it is not necessary to provide a source program for compressed data storage processing separately in each process, the capacity of the source program (usable capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Withdrawal priority acquisition processing]
In the pull-in priority acquisition process (see FIGS. 78 and 79) of the pachislot 1 of the present embodiment, the determination process of S683 during the pull-in priority corresponding process of “ANY role” is a command code dedicated to the main CPU 101 on the source program. It is executed by a certain “JCP” instruction (comparison instruction) (see FIG. 80A).

  When the “JCP” instruction is used in the “ANY role” pull-in priority processing, the address setting command can be omitted as described above. The processing efficiency of the processing can be increased, and the capacity of the source program (used capacity of the main ROM 102) can be reduced.

  Further, in the stop request pull-in request flag setting process in S686 during the pull-in priority acquisition process, as shown in FIG. 80B, the Q register (extended register), which is a dedicated instruction code for the main CPU 101, is used in the source program. An “LDQ” instruction and “CALLF” instruction for addressing are used.

  Therefore, in the stop control pull-in request flag setting process of S686, by using the “LDQ” instruction, an instruction for address setting can be omitted on the source program, and the capacity of the source program (use of the main ROM 102) can be omitted. Capacity) can be reduced. The “CALLF” instruction is a 2-byte instruction code as described above. Therefore, by using these instruction codes dedicated to the main CPU 101 in the stop control pull-in request flag setting process, the processing efficiency can be improved, and the limited capacity of the main RAM 103 can be effectively utilized. .

  Further, in the present embodiment, in the stop request pull-in request flag setting process in S686 during the priority pull-in order acquisition process, the address of the logical product operation process of the jump destination specified by the “CALLF” instruction is the pull-in priority storage process ( This is the same as the jump destination address designated by the “CALLF” instruction in the logical product operation process of S626 in FIG. 73 (see FIG. 74). That is, in this embodiment, the source program for executing the AND operation processing is shared (modularized) in both the priority pull-in order acquisition process and the pull-in priority order storage process.

  In this case, since it is not necessary to provide a source program for logical product operation processing separately in both the priority pull-in order acquisition process and the pull-in priority order storage process, the capacity of the source program (the capacity used in the main ROM 102) correspondingly. Can be reduced. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Reel stop control process]
In the reel stop control process (see FIG. 81) of the pachislot machine 1 of the present embodiment, in the processes of S711 to S715, as shown in FIG. An “LDQ” instruction and a “CALLF” instruction are used.

  Therefore, in this embodiment, by using these instruction codes dedicated to the main CPU 101, it is possible to reduce the capacity of the source program of the reel control process and improve the processing efficiency of the reel stop control process. That is, in this embodiment, it is possible to increase the efficiency of the program processing speed and reduce the capacity in the main control circuit 90, and to utilize the free area of the main ROM 102 that increases according to the reduced capacity, Can be increased.

  Further, in the determination processing of S726 (reel (rotating drum) stop state check processing) during the reel stop control processing, as shown in FIG. 83, the “LDQ” instruction and “ORQ” instruction (Q An instruction code dedicated to the main CPU 101 that performs addressing using a register (extended register) is used.

  Therefore, in the present embodiment, an instruction for address setting can be omitted on the source program of the reel stop control process, and the capacity of the source program (usable capacity of the main ROM 102) can be reduced accordingly. . As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Winning Search Processing]
In the payout search process (see FIG. 88) of the pachislot 1 of the present embodiment, the “LDIN” instruction is used on the source program as shown in FIG. 89 in the payout number and determination target data setting process of S764.

  Therefore, in the winning search process of this embodiment, both the data load process and the address update process can be performed by one “LDIN” instruction. In this case, an instruction relating to address setting can be omitted from the source program of the winning search process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  Further, the medal counter value acquisition process referred to in the determination process of S770 during the winning search process, the winning sheet counter value acquisition process referred to in the process of S772, and the winning number counter stored in the process of S775 ( In each of the (update) processing, as shown in FIG. 89, an “LDQ” instruction for specifying an address using a Q register (extended register) is used. Therefore, in the winning search process of the present embodiment, an instruction relating to address setting can be omitted on the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  Furthermore, in the determination process of S769 during the winning search process, as shown in FIG. 89, the “JSLAA” instruction is used in the source program, and in the determination processes of S770 and S773, the “JCP” instruction is used. When the “JSLAA” instruction and the “JCP” instruction are used on the source program of the winning search process, as described above, the address setting instruction can be omitted, and the capacity of the source program (main ROM 102) Used capacity) can be reduced. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Illegal hit check processing]
In this embodiment, as shown in FIG. 22, the configuration of the winning action flag storage area (display combination storage area) is the same as that of the winning request flag storage area (internal winning combination storage area). Therefore, in the arithmetic processing of S784 in the illegal hit check processing of the present embodiment, the winning combination data and the internal winning combination data are simply ANDed (“AND” instruction) on the source program (see FIG. 91). Just execute it, you can get the result of combining the winning combination data and the internal winning combination data.

  Therefore, in this embodiment, the illegal hit check process can be made efficient and simplified, and as a result, the free space of the main control program can be secured, and the free space is used to improve the game performance. be able to.

[Winning check / medal payout processing]
In the winning check / medal payout process (see FIG. 92) of the pachislot 1 of the present embodiment, when the payout operation is continued after the credit counter is updated (+1), a wait of 60.33 ms (payout interval) in the process of S808. Wait) processing is performed. In this case, useless waiting time can be reduced, and the mental burden on the player can be reduced.

[Medal payout number check process]
In the update processing of the combination end number counter in S814 during the medal payout number check process (see FIG. 94) of the pachislot 1 of this embodiment, as shown in FIG. 95A, the instruction code dedicated to the main CPU 101 is displayed on the source program. A “DCPLD” instruction is used.

  In the process of S814, the “DCPLD” instruction is an instruction code in which the lower limit determination instruction of the number management counter and the determination branch instruction are integrated. Both processes for holding the value of the counter at “0” can be executed. In this case, there is no need to provide an instruction code for executing both processes separately. Therefore, in the medal payout number check process according to the present embodiment, the capacity of the source program (usage capacity of the main ROM 102) can be reduced, and a free capacity can be secured (increased) in the main ROM 102. The free space can be used to improve gameplay.

  In the process of S816 during the medal payout number check process, as shown in FIG. 95B, the payout number counter value is set in communication parameter 1 of the credit information command, and the credit counter value is set in communication parameter 5. Is done. However, values stored in the H register, E register, and D register at the present time are set in the other communication parameters 2 to 4 (unused parameters) constituting the credit information command. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[7-segment LED drive processing]
The output processing of the 7-segment common output (selection) data and the 7-segment cathode output data performed in S936 during the 7-segment LED driving process (see FIG. 101) of the pachislot 1 of this embodiment is performed as shown in FIG. It is executed by the code “LD (cPA_SEGCOM), BC”. That is, in the present embodiment, in the 7-segment LED driving process, the 7-segment common output data and the 7-segment cathode output data are simultaneously output when dynamic lighting control is performed on the 2-digit 7-segment LED. This output control is also performed when the push order display data is displayed on the instruction monitor in the information display 6.

  In this case, the number of instruction codes necessary for dynamic lighting control of the 7-segment LED can be reduced on the source program of the 7-segment LED driving process. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Thus, the playability can be improved.

[Timer update processing]
In the process of S952 (2-byte timer update process) in the timer update process (see FIG. 106) of the pachislot 1 of this embodiment, as shown in FIG. 107, the instruction code dedicated to the main CPU 101 is “ DCPWLD "instruction is used.

  When the “DCPWLD” instruction is executed in the timer update process, both the update (subtraction) process of the timer number (2-byte timer number) and the process of holding the timer number at “0” are executed as described above. Can do. In this case, there is no need to provide an instruction code for executing both processes separately. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Thus, the playability can be improved.

<Appendix (Summary of the Invention of the Present Embodiment)>
[A gaming machine of the first invention]
In a conventional gaming machine, for at least one reel, when the stop operation is performed, the maximum number of symbol movements (hereinafter referred to as “the number of sliding symbols”) until the symbol stops is set as the first symbol number ( For example, instead of reducing the number of 4 symbols) to a second number of symbols (for example, 1 symbol) that is less than the first number of symbols, all the small roles are won regardless of the lottery result. It is known that a specific special gaming state (MB gaming state) for processing can be activated (see, for example, Japanese Patent Application Laid-Open No. 2007-117497).

  By the way, in such a gaming machine, for example, when it is intended to adopt that a specific small role is determined as an internal winning combination as an operation trigger of ART which is an advantageous state advantageous to the above-mentioned player, During a specific special game state, it is difficult to obtain an ART trigger or it is difficult to obtain it, so the interest of a specific special game state that should be advantageous to the player is reduced. There was a problem of doing.

  1st invention was made in order to solve the said subject, and even if it is in a specific special game state, by enabling it to obtain the operation opportunity of an advantageous state like other game states, It is an object of the present invention to provide a gaming machine that can improve the fun of gaming.

The gaming machine of the first invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
When the symbol variation display is stopped by the symbol variation stop control means and a special symbol combination (for example, “C_MB” symbol combination) is displayed, control is performed to a special gaming state (for example, MB gaming state). Special gaming state control means (for example, bonus check processing by the main CPU 101);
When a predetermined condition is established, an advantageous state control means (for example, the main CPU 101) that controls the advantageous state (for example, during ART) advantageous to the player;
A lock effect determining means (for example, the main CPU 101) for determining whether or not to execute a specific lock effect (for example, an MB medium lock effect) in the special gaming state,
In the special gaming state, when a stop operation is performed by the player, the symbol variation stop control means sets the maximum number of symbol movements for at least one display row (for example, the reel 3R), A gaming state in which the number of symbols of 1 (for example, 4 symbols) is reduced to a second number of symbols (for example, 1 symbol) that is less than the first number of symbols,
The predetermined condition is that, in a gaming state different from the special gaming state, a specific winning combination (for example, “F_black BAR”) is determined as an internal winning combination by the internal winning combination determining means, and the special gaming state In the above, the execution of the specific lock effect is determined by the lock effect determination means,
In a gaming state different from the special gaming state, the probability that the specific winning combination is determined as an internal winning combination by the internal winning combination determining means, and in the special gaming state, the specific locking effect is determined by the lock effect determining means. The probability determined to be executed is the same probability.

  In the gaming machine of the first invention, in a gaming state different from the special gaming state (for example, MB gaming state), a specific combination (for example, “F_black BAR”) that triggers an advantageous state (for example, during ART) The winning probability and the execution probability of a specific lock effect that triggers the advantageous state in the special gaming state are configured to have the same probability (for example, 8/65536). In other words, an advantageous operation trigger can be obtained with a certain probability regardless of which gaming state the gaming state is. Therefore, the interest of the game can be improved.

The gaming machine of the first invention is
The specific winning combination is an internal winning combination that is allowed to display a combination of specific symbols (for example, a combination of symbols of “C_black BAR”) when determined as an internal winning combination by the internal winning combination determining means. Yes,
The specific lock effect is an effect of invalidating a player's gaming operation for a predetermined period and temporarily stopping the combination of the specific symbols within the predetermined period.

  Further, in the gaming machine of the first invention, when a specific lock effect is executed in the special gaming state, a combination of symbols related to the specific combination (for example, a combination of symbols of “C_black BAR”) is temporary. Is configured to stop. In other words, if a combination of symbols relating to a specific combination is displayed regardless of which gaming state the gaming state is, the player can be made aware that the trigger for the advantageous state has been established. ing. Therefore, regardless of the determination of the internal winning combination and the reel stop control restrictions in the special game state, the player can easily feel that the operation trigger of the advantageous state has been established, and further improve the interest of the game Can be made.

[Game machines of the second to fourth inventions]
In a conventional gaming machine, during the operation of ART, for each unit game, the number of ART sets is set based on the internal winning combination (for example, the ART operation with 50 games as one set, or the continuation of ART is given) It is known that an addition lottery is executed, a winning lottery is performed, and the number of ART sets is added to allow the ART to be continued (for example, JP 2013-17520 A). See the official gazette).

  However, in such a gaming machine, whether or not the ART, which is an advantageous state advantageous to the player described above, continues is determined based on whether or not the addition lottery is won. There was a problem that the sex became monotonous.

  The second to fourth inventions have been made to solve the above-mentioned problems, and improve the interest of the game by making the gameability related to the continuation of the advantageous state advantageous to the player diverse. An object is to provide a gaming machine that can be used.

(A gaming machine of the second invention)
The gaming machine of the second invention is
A gaming machine (for example, pachislot 1) provided with advantageous state control means (for example, main CPU 101) for controlling to an advantageous state (for example, during ART) advantageous for a player when a predetermined condition is satisfied,
The advantageous states include a first advantageous state (eg, normal ART) and a second advantageous state (eg, continuous challenge);
The advantageous state control means includes:
Rights granting means for deciding whether or not to grant a specific right (for example, CP) that makes it possible to determine whether or not to extend the game period of the first advantageous state in the second advantageous state (For example, the main CPU 101),
When the first advantageous state ends,
If the specific right has not been granted, terminate the advantageous state;
When it is determined that when the specific right is granted, it is possible to play a game in the second advantageous state and the game period of the first advantageous state is extended in the second advantageous state In the extended game period, it is possible to play a game in the first advantageous state,
The right granting means can grant a plurality of the specific rights in the advantageous state,
In the case where a plurality of the specific rights are granted, even if it has already been decided to extend the game period of the first advantageous state in the second advantageous state, Decide whether to extend the game period of the first advantageous state until the right is consumed, and decide to extend in the second advantageous state when all the specific rights are consumed The gaming period of the first advantageous state is added together to extend the gaming period of the first advantageous state.

  In the gaming machine of the second invention, the advantageous state (for example, during ART) includes the first advantageous state (for example, normal ART) and the second advantageous state (for example, continuous challenge). In the second advantageous state, it is possible to grant a plurality of specific rights (for example, CP) for adding the number of games in the first advantageous state and performing lottery (deciding whether to extend the game period). Has been.

  In addition, when the specific right is granted when the first advantageous state ends, the state is shifted to the second advantageous state, and in the second advantageous state, the specific right is consumed and the first advantageous state is consumed. When the number of games is added, a lottery (deciding whether or not to extend the game period) is performed, and when the winning lottery is won (when it is determined to extend the game period), the first advantageous state is continued. It is configured to be able to.

  If a plurality of specific rights have been acquired, the specific rights will not be wasted and all will be added to the number of games in the first advantageous state (determination of whether to extend the game period) ). Therefore, in the second advantageous state, not only is it determined whether or not to continue the advantageous state, but also a possibility that a large number of games can be added at a time can be created. A variety of characteristics can be achieved, and the fun of the game can be improved.

(A gaming machine of the third invention)
The gaming machine of the third invention is
A gaming machine (for example, pachislot 1) provided with advantageous state control means (for example, main CPU 101) for controlling to an advantageous state (for example, during ART) advantageous for a player when a predetermined condition is satisfied,
The advantageous states include a first advantageous state (eg, normal ART) and a second advantageous state (eg, continuous challenge);
The advantageous state control means includes:
First right granting means (for example, the main CPU 101) for determining whether or not to grant a first right (for example, ART stock) that enables a game to be played in the first advantageous state for a predetermined game period; ,
Determining whether to grant a second right (e.g., CP) that allows the determination of whether to extend the gaming period of the first advantageous state in the second advantageous state; Right granting means (for example, main CPU 101),
When a game for the predetermined game period is performed in the first advantageous state,
If neither the first right nor the second right is granted, the advantageous state is terminated,
When the first right is granted, it is possible to play a game again in the first advantageous state for the predetermined game period,
When the second right is granted, it is determined that the game can be performed in the second advantageous state, and the game period of the first advantageous state is extended in the second advantageous state. In this case, it is possible to play a game in the first advantageous state for the extended game period,
When both of the first right and the second right are granted, control is performed so that priority is given to playing a game in the second advantageous state.

  In the gaming machine of the third invention, the advantageous state (for example, during ART) includes the first advantageous state (for example, normal ART) and the second advantageous state (for example, continuous challenge). A first right to continue the first advantageous state (for example, ART stock), and an extra lottery (determining whether to extend the game period) in the second advantageous state A second right to perform (for example, CP) can be granted.

  Then, when the first advantageous state ends, if both the first right and the second right are granted, control is performed so as to give priority to shifting to the second advantageous state. Has been. That is, the second right is digested in preference to the first right.

  In this case, in the second advantageous state, when the second right is consumed and the number of games in the first advantageous state is added and a lottery (determination of whether to extend the game period) is performed, and the additional lottery is won ( If it is decided to extend the game period), the first advantageous state can be continued without consuming the first right, and if the winning lottery is not won (the game period can be extended) The first advantageous state can be continued by consuming the first right even if it is not determined. Therefore, while ensuring the sense of security related to the continuation of the advantageous state, it is possible to make a variety of games and improve the interest of the game.

  In addition, when the first advantageous state ends, the first advantageous state is continued by the consumption of the second right or the consumption of the first right even if the state is shifted to the second advantageous state. Since the possibility can remain, the expectation regarding the continuation of the advantageous state can be maintained.

The gaming machine of the third invention is
The second rights granting means can grant a plurality of the second rights in the advantageous state,
In the second advantageous state, it is determined whether or not to extend the game period of the first advantageous state by the number of the second right granted.

The gaming machine of the third invention is
In the second advantageous state, even if it has already been decided to extend the gaming period of the first advantageous state, the first advantageous state will be used until all the second right is consumed. A determination is made as to whether or not to extend the game period, and when all the second rights are consumed, the game periods of the first advantageous state determined to be extended in the second advantageous state are added together. The game period of the first advantageous state is extended.

  In addition, in the gaming machine of the third invention, it is possible to acquire a plurality of second rights in an advantageous state, and when a plurality of second rights are acquired, All of the rights are not wasted, and all are used for the lottery (determining whether or not to extend the game period) for the number of games in the first advantageous state. Therefore, in the second advantageous state, it is possible not only to determine whether or not to continue the advantageous state, but also to create a possibility that a large number of games can be added at one time. Can improve the interest of the game.

(A gaming machine of the fourth invention)
The gaming machine of the fourth invention is
When a predetermined condition is established, an advantageous state control means (for example, the main CPU 101) that controls the advantageous state (for example, during ART) advantageous to the player;
When a specific condition is satisfied, the gaming machine (for example, pachislot 1) includes specific state control means (for example, the main CPU 101) for controlling to a specific state (for example, promotion chance) in which the advantageous gaming period is extended. ) And
The specific state is a state in which the game period of the advantageous state is extended based on the continued game in the specific state,
The specific state control means can determine in advance whether or not to continue a plurality of consecutive games in the specific state.

  The gaming machine of the fourth invention has a specific state (for example, promotion chance) in which the game period of the advantageous state (for example, during ART) is extended, and in this specific state, the advantageous state is The game period is configured to be extended. Moreover, it is comprised so that it can determine beforehand whether it continues about the game of the continuous multiple times in a specific state. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

The gaming machine of the fourth invention is
Effect execution means (for example, display device 11) for executing the effect;
Production control means (for example, sub CPU 201) for controlling the production execution means,
The production control means includes
In a predetermined game (for example, the first game) in the specific state, when it is determined to continue the specific state until the next game (for example, the second game) of the predetermined game, In the next game of the game, it is possible to cause the effect execution means to execute the first effect (for example, display of “222”),
In the predetermined game in the specific state, if it is determined to continue the specific state until the next game (for example, the third game) after the predetermined game, In the game, it is possible to cause the effect executing means to execute a second effect (for example, display of “223”) different from the first effect.

The gaming machine of the fourth invention is
The specific state control means includes
In the predetermined game in the specific state, the game period in the advantageous state is extended to a first game period (for example, 111 games),
In a game next to the predetermined game in the specific state, the game period in the advantageous state is extended to a second game period (for example, 222 games) that is greater than the first game period,
In the next game after the predetermined game in the specific state, it is possible to extend the game period in the advantageous state to a third game period (for example, 333 games) longer than the second game period. Yes,
The first effect is an effect of notifying the second game period,
The second effect is an effect of notifying a game period exceeding the second game period.

  In the gaming machine of the fourth invention, in the current game in the specific state, when it is determined to continue the game in the specific state until the next game, the game in the specific state is continued until the next game. It is configured so that the effect executed in the next game can be different from the case where the event is determined.

  For example, if it is not determined to continue the game in the specific state until the next game, the advantage that is extended based on the fact that the specific state has continued until the game in the next game When it is decided to continue the game in the specific state until the next game, while the game period of the state is informed, the specific state has continued until the game as the second effect in the next game The game period exceeding the advantageous game period extended based on the game period is notified.

  By comprising in this way, it can notify definitively that a specific state continues, ie, the game period of an advantageous state is further extended, and the interest of a game can be improved more. Moreover, while notifying specifically the game period of the advantageous state added, it is alert | reported that a specific state continues by the contradiction of the aspect, Therefore The interest of a game can be improved more.

[A gaming machine of the fifth invention]
Conventional gaming machines are known that have a plurality of specific internal states (for example, modes) and that can suggest the current specific internal state according to the production mode (for example, JP-A-2005-287880). No. publication).

  However, in such a gaming machine, it is only determined by the effect lottery whether or not to suggest the specific internal state as described above, and thus there is a problem that the suggestion of the specific internal state becomes monotonous. there were.

  The fifth invention has been made to solve the above-mentioned problems, and in a gaming machine having a plurality of specific internal states, it improves the interest of the game by making various indications of the specific internal states. An object of the present invention is to provide a gaming machine that can be used.

The gaming machine of the fifth invention is
Profit giving means (for example, main CPU 101) capable of performing variable display and giving profit based on the derived display result;
Specific internal state control means (for example, the main CPU 101) having a plurality of specific internal states (for example, normal mode) and controlling transition between the plurality of specific internal states;
Effect execution means (for example, display device 11) for executing the effect;
Production control means (for example, sub CPU 201) for controlling the production execution means,
The effect execution means can execute a predetermined effect (for example, a special effect) suggesting that the result of the transition control by the specific internal state control means is a predetermined result,
The production control unit reserves execution of the predetermined production when the result of the transition control by the specific internal state control unit is the predetermined result, and then a predetermined execution condition is satisfied. Further, it is characterized in that the predetermined effect is executed by the effect execution means.

The gaming machine of the fifth invention is
When a predetermined condition is satisfied, the apparatus further includes advantageous state control means (for example, the main CPU 101) for controlling to an advantageous state (for example, during ART) advantageous to the player,
The plurality of specific internal states include a plurality of lottery states each having different probabilities that the predetermined condition is satisfied,
The predetermined result is controlled by the specific internal state control means to shift from a lottery state having a relatively low probability that the predetermined condition is satisfied to a lottery state having a relatively high probability that the predetermined condition is satisfied. Including that
The predetermined execution condition is that a predetermined display result (for example, a combination of symbols of “S_TL Lip”) is derived.

The gaming machine of the fifth invention is
The plurality of specific internal states further includes a precursor state in which the predetermined condition is satisfied but a transition to the advantageous state is awaited,
The predetermined result further includes that the specific internal state control means has decided to control the transition from one of the plurality of lottery states to the precursor state.

  In the gaming machine according to the fifth aspect of the present invention, the game machine has a plurality of specific internal states (for example, a normal mode), and executes a predetermined effect (for example, a special effect) when the specific internal state has changed. After making a reservation, a predetermined effect is executed when a predetermined execution condition is satisfied.

  For example, when there are a plurality of lottery states having different transition probabilities to the advantageous state (for example, during ART) as the plurality of specific internal states, the lottery state becomes an advantageous lottery state, or the advantageous state If there is a precursor state where the transition to the state is awaited, execution of a predetermined effect is reserved when the precursor state is reached.

  Then, when a predetermined display result (for example, a combination of symbols of “S_TL Lip”) is derived (that is, when a predetermined internal winning combination (for example, “Normal Lip”) is established), a predetermined effect is executed. It is configured to be. In other words, every time a predetermined display result is derived, the player can expect whether or not a predetermined effect will be executed, and a unit game with a change in a specific internal state and a predetermined effect will be executed. The unit game to be played can be different. Therefore, when there are a plurality of specific internal states, various specific internal state suggestions can be provided.

[A gaming machine of the sixth invention]
In a conventional gaming machine, when a power failure occurs (that is, when a power interruption occurs), a power supply is maintained using a backup battery, and a control circuit that controls the production can execute a process according to the power failure state. There are known ones (for example, see JP 2010-172408 A).

  According to such a gaming machine, it is considered that the content of the performance at the time of a power failure can be restored at the time of power recovery (that is, at the time of power failure recovery).

  However, in such a gaming machine, if the content of the effect to be restored at the time of power recovery is enormous, the time required for the restoration also becomes long. As a result, there is a possibility that the contents of the performance cannot be restored on the control circuit side that controls the production, even though the control circuit that controls the progress of the game has returned to the state where the game is possible. There was a problem.

  Such a problem is particularly serious in a gaming machine having the above-described AT and ART functions. This is because if a player tries to play a game before the navigation function is properly exhibited, the player will suffer a significant disadvantage. Therefore, it is considered that there is room for further improvement in the method of returning the content of the performance at the time of power recovery.

  A sixth aspect of the invention is made to solve the above-described problem, and an object thereof is to provide a gaming machine that can appropriately restore the content of the effect at the time of power failure recovery.

The gaming machine of the sixth invention is
Information display means (for example, display device 11) for displaying information about the game;
In a gaming machine comprising display control means (for example, sub-control circuit 200) for controlling display contents of the information display means,
The information display means can display predetermined information corresponding to a predetermined numerical value (for example, a value of an ART game number counter),
The display control means includes
When the predetermined numerical value fluctuates based on the progress of the game, a specific numerical value change display (for example, for example, before displaying the predetermined information corresponding to the predetermined numerical value after the change on the information display means) It is possible to display specific information that is a count-up display or a count-down display) on the information display means for a predetermined time (for example, 500 ms),
When a restoration process (for example, a backup restoration process by the sub CPU 201) for returning to the state before the power interruption is performed after a power interruption occurs in the gaming machine, the specific information is displayed on the information display unit. Rather, the predetermined information corresponding to the present predetermined numerical value is displayed on the information display means.

The gaming machine of the sixth invention is
The gaming machine further includes specific gaming state control means (for example, the main CPU 101) that controls to a specific gaming state (for example, during ART) when a predetermined condition is established,
The specific game state control means can control to the specific game state for a predetermined game period (for example, between 50 games) when the predetermined condition is satisfied,
The predetermined numerical value corresponds to the remaining game period of the specific gaming state,
The display control means includes
In the specific game state, when the remaining game period of the specific game state changes, prior to displaying the predetermined information corresponding to the remaining game period of the specific game state after the change on the information display means. The specific information for variably displaying the remaining game period in the specific gaming state as the specific numerical value variation display can be displayed on the information display means,
When the return process is performed in the gaming machine, the information display unit displays the predetermined information corresponding to the remaining game period of the current specific gaming state without displaying the specific information on the information display unit. It is characterized by being displayed.

  In the gaming machine of the sixth aspect of the invention, normally, when a predetermined numerical value (for example, the value of the ART game number counter) fluctuates, the predetermined numerical value is displayed over a predetermined period before the changed predetermined numerical value is displayed. Although it is configured so that the presentation effect is enhanced by the variable display, after the interruption in the gaming machine, when returning to the state before the interruption, the fluctuation display is not performed and the fluctuation display is not performed. (I.e., the current) predetermined numerical value is displayed.

  For example, when a predetermined numerical value corresponds to the remaining game period in a specific gaming state (for example, during ART), and the remaining game period fluctuates, the remaining game period is usually set to a predetermined period ( For example, after the variable display is performed over 500 ms), the remaining game period after the change is displayed. However, when a power failure occurs in the gaming machine and then returns to the state before the power failure, the variable display is performed. Without change, the remaining (ie, current) remaining game period is displayed.

  In other words, at the time of power interruption recovery, control for returning to a gameable state is given priority over control for enhancing the effect. Therefore, it is possible to appropriately restore the content of the performance when the power interruption is restored.

The gaming machine of the sixth invention is
The gaming machine further includes game control means (for example, a main control circuit 90) for controlling the progress of the game,
The game control means includes command transmission means (for example, communication data transmission processing by the main CPU 101) for transmitting a command in one direction to the display control means,
The command transmission means transmits a specific command to the display control means when returning to the state before the power interruption after the power interruption occurs in the gaming machine,
The display control means causes the information display means to display initial information corresponding to an initial value (for example, 0) of the predetermined numerical value until the specific command is received when the return processing is performed. It is characterized by that.

  In the gaming machine according to the sixth aspect, the control circuit (display control means) controls the effect in conjunction with the return to the game-ready state on the control circuit (game control means) side that controls the progress of the game. It is configured to be able to return to a game-playable state on the side. At that time, the display of the predetermined numerical value is configured to be switched from the initial value to the current numerical value. Therefore, with a simple configuration, it is possible to notify that the gaming machine returns to a playable state, and it is possible to return the content of the production more appropriately when power is restored.

[A gaming machine of the seventh invention]
In a conventional gaming machine, there is known a gaming machine that obtains a checksum of data stored in a RAM at the time of power interruption, and performs a checksum determination process obtained at the time of power interruption when the power is restored (for example, JP 2009-011375). In the gaming machine disclosed in Japanese Patent Laid-Open No. 2009-011375, in the checksum determination process at the time of power recovery, if the checksum determined at the time of power recovery does not match the checksum determined at the time of power interruption, an error notification is performed.

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and there is a demand for capacity reduction of processing programs and tables other than the game management managed by the main control circuit.

  The seventh invention has been made to solve the above-mentioned problems, and an object of the seventh invention is to reduce the capacity of processing programs and tables other than the game management managed by the main control circuit and to perform main control. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM of a circuit and enhancing the playability by using the free space of the ROM corresponding to the increased capacity.

  In order to solve the above problems, according to a seventh aspect of the present invention, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Power supply means for supplying a power supply voltage (for example, the power supply substrate 53b and the switching regulator 94);
Starting means for outputting a starting signal to the arithmetic processing means when the power supply voltage exceeds a predetermined starting voltage value (for example, 10V) (for example, reset signal output processing of the power management circuit 93);
When the power supply voltage falls below a predetermined power failure voltage value (for example, 10.5 V), a power failure means for outputting a power failure signal to the arithmetic processing means (for example, output of a power failure detection signal of the power management circuit 93) Processing), and
The arithmetic processing means includes:
A flag register (eg, flag register F) that stores data corresponding to the result of the arithmetic processing;
When the power failure means outputs the power failure signal, the sum value is calculated by accumulating all the information stored in a predetermined storage area (for example, the game RAM area) in the second storage means. Sum value calculation means (for example, checksum generation processing);
A sum value that sequentially subtracts the information stored in the predetermined storage area from the sum value generated by the sum value calculation means at the time of the most recent power interruption when the activation means outputs the activation signal. Subtraction means (for example, S122 to S131 during the sum check process);
When the subtraction processing by the sum value subtracting unit is completed for all information stored in the predetermined storage area, the subtraction result set in the predetermined bit area (for example, zero flag) in the flag register is displayed. A gaming machine comprising sum value determination means (for example, S134 during sum check processing) for determining whether or not an abnormality has occurred based on corresponding data.

In addition, in the gaming machine of the seventh invention, the sum value calculating means executes a specific command (for example, a POP command) continuously when adding the information stored in the predetermined storage area. 2 bytes of information stored and acquired and added, and the information of the read start address of the information is updated by 2 bytes,
The sum value subtracting means executes the specific instruction when subtracting the information stored in the predetermined storage area from the sum value generated at the time of occurrence of power interruption, thereby continuously storing 2 While acquiring and subtracting information for bytes, the information of the read start address of the information may be updated for two bytes.

Furthermore, in the gaming machine of the seventh invention, the arithmetic processing means has a stack pointer capable of setting an address of the predetermined storage area of the second storage means,
The specific instruction executed when the sum value calculation means adds the information stored in the predetermined storage area may be a dedicated instruction (for example, a POP instruction) for operating the stack pointer. Good.

  According to the gaming machine of the seventh aspect of the invention, the capacity of processing programs and tables other than game play is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the ROM for the increased capacity It is possible to improve the playability by using the free space.

[Game machines of the eighth to eleventh inventions]
In a conventional gaming machine, there has been proposed a gaming machine equipped with a main control device that processes numerical data by using a stack pointer in an operation command (see, for example, JP-A-2005-237737).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The eighth to eleventh inventions have been made to solve the above-mentioned problems, and the object of the eighth to eleventh inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM of a main control circuit and enhancing the gameability by utilizing the free space of the ROM for the increased capacity.

  In order to solve the above problems, according to an eighth aspect of the invention, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
A dedicated register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
The arithmetic processing means executes a predetermined instruction (for example, a “BITQ” instruction, a “SETQ” instruction, an “LDQ” instruction, etc.) that can perform address designation in the second storage means by using the extension register. A gaming machine characterized by being capable.

  In the gaming machine according to the eighth aspect of the invention, a part of the address that can be specified by the extension register may be a higher-order address value constituting the address.

  In order to solve the above-described problems, the ninth invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
A dedicated register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
The arithmetic processing means includes:
In the process of checking the stop state of the display column,
A predetermined read instruction (for example, an “LDQ” instruction) capable of performing addressing in the second storage means by using the extension register is executed, and the predetermined stored in the second storage means Read the information indicating the status of the variable display in the display column,
Next, a predetermined OR operation instruction (for example, an “ORQ” instruction) that can perform addressing in the second storage means is executed using the extension register, and is stored in the second storage means Reading information indicating the state of the variable display of the other one display column, and performing an OR operation on the information and information indicating the state of the variable display of the predetermined display column,
Thereafter, the execution of the predetermined logical sum operation instruction is repeated, and the logical sum operation of the result of the logical sum operation and the information indicating the change display state of each remaining display column is repeated, and the logical sum for all the display columns is performed. A game machine characterized by determining whether or not all display columns are in a stopped state based on a result of an arithmetic sum operation obtained when the operation is completed.

  In addition, in the gaming machine of the ninth invention, a part of the address that can be specified by the extension register may be a higher-order address value constituting the address.

  In order to solve the above-mentioned problems, the tenth invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the internal winning combination determining operation by the internal winning combination determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
A dedicated register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
The internal winning combination determined by the internal winning combination determining means includes an internal winning combination for each setting whose winning probability changes in accordance with a setting value for adjusting an expected value for determining the internal winning combination related to the grant of a privilege. Is provided,
The arithmetic processing means includes:
In the process of determining the internal winning combination,
By setting a predetermined addition instruction (for example, “ADDQ” instruction) capable of performing address designation in the second storage means using the extension register, setting of the internal winning combination by setting to be a lottery target Add the current setting value to the top address of the area where the lottery value for each value is stored, and specify the address where the lottery value of the internal winning combination for each setting associated with the current setting value is stored, A gaming machine characterized by acquiring the lottery value.

  In the gaming machine according to the tenth aspect, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

  In order to solve the above problems, according to an eleventh invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When the variable display of the plurality of display columns is stopped by the stop control means, the symbol corresponding to the internal winning combination relating to the payout of the game medium on the determination line set across the plurality of display columns Bonus granting determination means (for example, winning search process) for determining whether or not the combination of is stopped and displayed,
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the determination operation by the privilege grant determination means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
The arithmetic processing means includes:
In the process of determining whether or not a combination of symbols corresponding to an internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line,
The game that can be given when a combination of symbols corresponding to an internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line by executing a predetermined read command (for example, “LDIN” command) It is characterized by simultaneously acquiring data on the number of paid-out media and determination data indicating the type of combination of symbols corresponding to the internal winning combination related to the payout of the game media, which is associated with the data on the number of paid-out To play.

In the gaming machine of the eleventh invention, the arithmetic processing means is
In the process of determining whether or not a combination of symbols corresponding to an internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line,
A predetermined determination instruction (for example, a “JSLAA” instruction) that can execute a determination instruction, a process jump destination address designation instruction, and a process jump operation instruction with a single instruction is executed, and an internal portion related to payout of the game medium It may be determined whether or not a combination of symbols corresponding to the winning combination is stopped and displayed.

  According to the gaming machines of the eighth to eleventh inventions, the capacity of processing programs and tables managed by the main control circuit is reduced, the free capacity of the ROM (first storage means) of the main control circuit is increased, and the increase It is possible to improve the playability by utilizing the free space of the ROM for the capacity.

[Amusement machines of the twelfth and thirteenth inventions]
In the conventional gaming machine, when an abnormality occurs in the data stored in the RAM of the main control unit, it is controlled to the RAM abnormality error state, the progress of the game is disabled, and the mode shifts to the setting change mode. There has been proposed a gaming machine in which when a set value is newly selected and set based on a setting change operation, the game progress disabled state is canceled and the game progress is enabled (for example, JP, A 2007-209810 publication).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The twelfth and thirteenth inventions have been made to solve the above problems, and the object of the twelfth and thirteenth inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM of a main control circuit and enhancing the gameability by utilizing the free space of the ROM for the increased capacity.

  In order to solve the above problems, according to a twelfth aspect, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Data transmission means for transmitting command data related to the gaming operation (for example, S904 (communication data transmission processing) during interrupt processing);
A setting change confirmation means (for example, a setting change confirmation process) capable of executing a setting value change process and a setting value confirmation process for adjusting an expected value for determining an internal winning combination related to the privilege grant;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the setting value changing operation or checking operation by the setting change confirmation means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A start command generation means for generating first command data at the start of the setting value change process or the setting value confirmation process (for example, S43 during the setting change confirmation process);
An end-time command generation means for generating second command data at the end of the setting value change process or the setting value confirmation process (for example, S57 during the setting change confirmation process);
The generation process of the first command data executed by the start time command generation means and the generation process of the second command data executed by the end time command generation means are shared. A featured gaming machine.

In the gaming machine of the twelfth aspect, the arithmetic processing means has a general-purpose register in which data is stored when the arithmetic processing means executes the arithmetic processing.
The arithmetic processing means includes:
When generating the first command data, a first value (for example, “005H”) is set in a predetermined register (for example, the L register) of the general-purpose register, and the generation process is executed.
When generating the second command data, a second value (for example, “004H”) may be set in a predetermined register of the general-purpose register, and the generation process may be executed.

  In order to solve the above-described problems, the thirteenth invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Data transmission means for transmitting command data related to the gaming operation (for example, S904 (communication data transmission processing) during interrupt processing);
Communication data generation means for creating the command data (for example, setting change command generation storage processing and communication data storage processing);
A setting change confirmation means (for example, a setting change confirmation process) capable of executing a setting value change process and a setting value confirmation process for adjusting an expected value for determining an internal winning combination related to the privilege grant;
Arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling command data generation operation by the communication data generation means and setting value change operation or confirmation operation by the setting change confirmation means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
At the start of the setting value change process or the setting value confirmation process, start command generation means for generating start command data (for example, S43 during the setting change confirmation process);
End-time command generation means (for example, S57 during the setting change confirmation process) that generates end-time command data at the end of the setting value change process or the setting value confirmation process;
The start command data generation process executed by the start command generation means and the end command data generation process executed by the end command generation means are shared,
The arithmetic processing means has a plurality of general-purpose registers in which a plurality of types of data are respectively stored when the arithmetic processing is executed by the arithmetic processing means.
The arithmetic processing means includes:
In the command data generation process,
Among a plurality of types of communication parameters constituting the command data, a communication parameter to be used is set in a corresponding general-purpose register among the plurality of general-purpose registers,
Storing the communication parameters used in the general-purpose register in a predetermined storage area (for example, a communication data temporary storage area) in the second storage unit;
If there is a communication parameter that is not used among the plurality of types of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter when the command data is generated is used as the communication parameter. Stored in the storage area of
A gaming machine characterized in that a sum value of the command data is generated based on data stored in the general-purpose register associated with a communication parameter.

  In the gaming machine of the thirteenth aspect, in the command data generation process, the value stored in the general-purpose register associated with the communication parameter is added to the value stored in the accumulator of the general-purpose register. Thus, the sum value of the command data may be generated, and the generated sum value may be stored in the predetermined storage area.

  According to the gaming machines of the twelfth and thirteenth inventions, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit. The playability can be improved by utilizing the free space.

[Amusement machines according to fourteenth and fifteenth inventions]
In a conventional gaming machine, there is known a gaming machine that transmits a command from a gaming control board (main control circuit) to an effect control board (sub control circuit) (see, for example, JP-A-2002-360766).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The fourteenth and fifteenth inventions have been made to solve the above problems, and the object of the fourteenth and fifteenth inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM of a main control circuit and enhancing the gameability by utilizing the free space of the ROM for the increased capacity.

  In order to solve the above problems, according to a fourteenth aspect, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Data transmission means for transmitting communication data relating to gaming operations (for example, S904 (communication data transmission processing) during interrupt processing);
Communication data generation and storage means (for example, communication data storage processing and communication) for creating the communication data and storing the generated communication data in a communication data storage area provided in a predetermined address range in the second storage means Data pointer update processing), and
The communication data generation storage means
When the communication data is sequentially stored in the communication data storage area from the storage area of the start address of the predetermined address range to the storage area of the last address, an update instruction, an upper limit determination instruction, and a determination branch instruction are combined. By executing a predetermined update instruction (for example, “ICPLD” instruction) that can be executed by one instruction, the current value of the communication data pointer, which is a parameter for addressing in the communication data storage area, and the last address And the communication data pointer is added and updated if the current communication data pointer is less than the upper limit, and the current communication data pointer is updated to the upper limit value. If it is above, the communication data pointer is below the communication data pointer corresponding to the head address. Gaming machine and changing the value.

  In the gaming machine of the fourteenth aspect, the communication data generation and storage means stores the communication data pointer in the communication data storage area when the communication data pointer is changed to a lower limit value of the communication data pointer corresponding to the head address. The transmitted communication data may be invalidated.

  In order to solve the above-mentioned problems, the fifteenth invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
In a counting process (for example, a medal payout number check process) of a predetermined data value related to the progress of a game operation,
When updating the value of the predetermined data, by executing a predetermined update instruction (for example, “DCPLD” instruction) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, The predetermined data value is compared with the lower limit value of the predetermined data value, and if the current predetermined data value is greater than the lower limit value of the predetermined data value, the predetermined data value The game machine is characterized in that if the current value of the predetermined data is less than or equal to the lower limit value of the predetermined data value, the predetermined data value is held at the lower limit value.

  In the gaming machine according to the fifteenth aspect, the predetermined data may be the number of payouts of the game medium.

  According to the gaming machines of the fourteenth and fifteenth inventions, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit. It is possible to improve the playability by utilizing the free space of the ROM for the capacity.

[16th Invention Machine]
In a conventional gaming machine, a gaming machine controlled by a timer subtraction process by software is known (see, for example, Japanese Patent Application Laid-Open No. 2004-041261).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  A sixteenth aspect of the present invention has been made to solve the above-described problems. An object of the sixteenth aspect of the present invention is to reduce the capacity of a processing program or a table managed by the main control circuit and reduce the capacity of the ROM of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space and enhancing the playability by using the free space of the ROM corresponding to the increased space.

  In order to solve the above-described problems, the sixteenth invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
In the count process (for example, timer update process) of the number of soft timers,
By executing a predetermined update instruction (for example, “DCPWLD” instruction) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, the current timer number of the soft timer and the lower limit of the timer number When the current timer number of the soft timer is larger than the lower limit value, the soft timer timer number is subtracted and updated, and if the current soft timer timer number is less than or equal to the lower limit value, A gaming machine, wherein the number of timers of the soft timer is held at the lower limit value.

  In a gaming machine according to a sixteenth aspect, the soft timer may be a 2-byte soft timer.

Further, in the gaming machine of the sixteenth aspect, the arithmetic processing means has fixed period processing means (for example, interrupt processing repeatedly executed at a period of 1.1172 msec) for performing processing at a constant period,
The counting process of the number of timers by the soft timer is executed by the periodic processing means
The elapsed time of the soft timer may be determined based on a cycle in which the periodic processing unit performs processing and the number of timers.

  Furthermore, in the gaming machine of the sixteenth aspect, the processing by the fixed period processing means is executed based on an interrupt signal generated by a timer function (for example, timer circuit 113) built in the arithmetic processing means. It may be.

  According to the gaming machine of the sixteenth aspect of the invention, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the increased capacity It is possible to provide a gaming machine capable of improving the game performance by using the free space of the ROM.

[Amusement machines of the seventeenth and eighteenth inventions]
In a conventional gaming machine, there is known a gaming machine that displays an internal lottery result with a 7-segment LED under the control of a main control circuit (see, for example, JP 2008-237337 A).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The seventeenth and eighteenth inventions have been made to solve the above-mentioned problems, and the object of the seventeenth and eighteenth inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM of a main control circuit and enhancing the gameability by utilizing the free space of the ROM for the increased capacity.

  In order to solve the above problems, in a seventeenth aspect of the invention, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
A plurality of 7-segment LEDs for notifying specific information about the game;
7-segment LED driving means for driving the plurality of 7-segment LEDs (for example, 7-segment LED drive processing);
LED drive control means for controlling the drive operation of the plurality of 7-segment LEDs by the 7-segment LED drive means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The LED drive control means includes
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read command (eg, “LDW” command) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A gaming machine characterized by that.

In the gaming machine according to a seventeenth aspect, the arithmetic processing means includes fixed-cycle processing means (for example, interrupt processing that is repeatedly executed at a cycle of 1.1172 msec) that performs processing at a constant cycle.
The periodic processing means counts the number of executions of processing by the periodic processing means,
When the counted value is an even number, the control process by the LED drive control means may be executed.

  In order to solve the above problems, according to an eighteenth aspect of the invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
An indication display (for example, an indication monitor) including a plurality of 7-segment LEDs for informing information related to a stop operation of the variable display of the plurality of display rows;
7-segment LED driving means for driving the plurality of 7-segment LEDs (for example, 7-segment LED drive processing);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the driving operation of the plurality of 7-segment LEDs by the 7-segment LED driving means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read command (eg, “LDW” command) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A gaming machine characterized by that.

In the gaming machine of the eighteenth invention, the arithmetic processing means is
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing unit executes the arithmetic processing, and that can specify a part of the address in the second storage unit by the stored data;
The arithmetic processing means executes a predetermined read instruction (for example, “LDQ” instruction) that can perform address designation in the second storage means by using the extension register, thereby causing the second storage means to And an address of a stop operation instruction information storage area (for example, a navigation data storage area) that stores information related to the stop operation of the variable display of the plurality of display columns, and a variable display of the plurality of display columns Information regarding the stop operation may be stored in the stop operation instruction information storage area.

  According to the gaming machines of the seventeenth and eighteenth inventions, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit. It is possible to improve the playability by utilizing the free space of the ROM for the capacity.

[19th invention gaming machine]
In a conventional gaming machine, a gaming machine in which a gaming control board (main control board) controls a reel unit is known (see, for example, Japanese Patent Laid-Open No. 2012-034914).

  By the way, in the rotation control of the reel (rotor), the lack of a sense of stability of the rotation operation of the reel may cause discomfort for the player (especially an expert), and the interest of the game may be cut off from the discomfort. There is. In this case, it is disadvantageous for the game store and may affect the sales of the game machine itself.

  A nineteenth aspect of the present invention has been made to solve the above-described problems, and an object of the nineteenth aspect of the present invention is to suppress a lack of stability in the rotational operation of the reel so as not to give a player unpleasant feeling. It is to provide a gaming machine that can be used.

  In order to solve the above problems, according to a nineteenth aspect of the invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
A setting switch (for example, a setting key type switch 54) for initializing a predetermined area of the second storage means,
The arithmetic processing means includes:
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
The input state of the input port and the output state of the output port at the time of power failure at the time of power recovery are set, and if the display row is changing at the time of power failure, it is stored in the second storage means The game return that clears the variation control management information (for example, reel control management information) of the display row at the time of occurrence of power interruption, and sets information instructing the start of variation of the display row to the variation control management information of the display row And a means (for example, a game return process).

In the gaming machine of the nineteenth invention, the arithmetic processing means is
When the setting switch is in the off state, the processing by the game return means is executed,
When the setting switch is in the ON state, a predetermined area of the second storage unit may be initialized without executing the process by the game return unit.

  According to the gaming machine of the nineteenth aspect, it is possible to suppress the lack of stability of the reel rotation operation (display row variation display operation) and to prevent the player from feeling uncomfortable.

[The gaming machine of the twentieth invention]
In a conventional gaming machine, gaming machines that can display setting values (1 to 6) by operating a setting change switch are known (for example, JP 2008-245704 A and JP 2013-042870 A). See the official gazette).

  By the way, conventionally, while a game is being played in a game state advantageous to the player, such as during a bonus game or an ART game, a gaming machine in which the set value cannot be confirmed is mainly used. In such a gaming machine, if a bonus game or an ART game is started immediately after an illegal act called “Goto”, the illegal act cannot be confirmed, which may cause a disadvantage to the game store. is there.

  A twentieth aspect of the invention is made to solve the above-described problem, and an object of the twentieth aspect of the invention is a set value even while a game is being played in a game state advantageous to the player. It is to provide a gaming machine capable of confirming such information and capable of suppressing illegal acts such as goto.

  In order to solve the above problems, in a twentieth invention, a gaming machine having the following configuration is provided.

A setting switch arranged at a predetermined position inside the gaming machine body;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Based on the internal winning combination determined by the internal winning combination determining means, advantageous gaming means (for example, bonus game described later) for executing a gaming state advantageous to the player;
A setting change confirmation means (for example, S233 during the medal acceptance / start check process) capable of changing or confirming a setting value related to the probability that an internal winning combination is determined according to the operation of the setting switch;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Game start determining means (for example, medal reception / start check processing) for determining whether or not the game can be started,
The setting change confirmation means can change a setting value related to a probability that an internal winning combination is determined according to an operation of the setting switch at power-on,
When it is determined by the game start determining means that the game can be started and the setting switch is operated, a setting value related to the probability that an internal winning combination is determined regardless of the gaming state is confirmed as the setting change. A gaming machine characterized in that it can be confirmed by processing by means.

  In the gaming machine of the twentieth invention, the setting change confirmation means initializes a predetermined storage area of the second storage means when the gaming machine is powered on with the setting switch being operated. The setting value may be changed, and the changed setting value may be stored in the second storage unit.

  According to the gaming machine of the twentieth aspect of the invention, information such as a set value is confirmed even when a game is being played in a gaming state advantageous to the player, such as during a bonus game or an ART game. And can deter fraudulent acts such as Goto.

[The gaming machine of the 21st and 22nd inventions]
In a conventional gaming machine, a gaming machine having a display device for displaying the number of inserted medals is known (see, for example, JP-A-1999-178983).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The twenty-first and twenty-second inventions have been made to solve the above problems, and the purpose of the twenty-first and twenty-second inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM of a main control circuit and enhancing the gameability by utilizing the free space of the ROM for the increased capacity.

  In order to solve the above-mentioned problems, the twenty-first invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Game medium detecting means (for example, medal sensor) for detecting the reception state of the game medium (for example, medal sensor input state);
Based on the reception state of the game medium detected in the previous process, whether or not the change state of the current reception state of the game medium detected by the game medium detection means is normal is determined by calculation processing. A gaming machine reception state determination means (for example, S255 to S258 during the medal insertion check process).

  In the gaming machine according to the twenty-first aspect, the game medium reception state determination means calculates a normal value of the reception state of the game medium that can be detected in the current process based on the reception state of the game medium detected in the previous process. It may be calculated by calculation, and the normal value may be compared with the current reception state of the game medium to determine whether or not the change mode of the reception state of the game medium is normal.

  In the gaming machine of the twenty-first aspect, the game medium reception state determination means determines whether or not the change state of the reception state of the game medium is normal based on 2 bits in 1-byte information. May be.

  In order to solve the above problems, according to a twenty-second invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Display means (for example, a first LED to a third LED) for notifying information indicating the number of inserted game media in a display mode corresponding to the number of inserted game media;
Arithmetic processing means (for example, main CPU 101, medal insertion processing) for performing arithmetic processing for controlling the notification operation by the display means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
Lighting control data for notifying information indicating the number of inserted game media in a display mode corresponding to the number of inserted game media is generated by a logical operation process based on the number of inserted game media. To play.

  In the gaming machine of the twenty-second invention, in the logical operation process, the lighting control data of the game medium may be generated from 3-bit data of information in one byte.

  According to the gaming machines of the twenty-first and twenty-second inventions, the capacity of the processing program and table managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the ROM capacity for the increased capacity is increased. The playability can be improved by utilizing the free space.

[Game machines of the 23rd and 24th inventions]
In a conventional gaming machine, a gaming machine in which a main board (main control board) and a sub board (sub control board) are connected by communication and a command is transmitted from the main board to the sub board is known (for example, a patent) No. 5725590).

  By the way, conventionally, communication between the main control board that performs control related to the game and the sub control board that performs control related to the effect is one-way communication from the main control board to the sub control board. There is a large gap between the start time of the main control board and that of the sub control board. Therefore, there is a possibility that the communication connection between the main control board and the sub-control board when the power is turned on becomes unstable.

  The twenty-third and twenty-fourth inventions have been made to solve the above-mentioned problems. An object of the twenty-third and twenty-fourth inventions is to provide a main control board (main control means) and a sub-control board (when power is turned on). It is to provide a gaming machine capable of stably operating communication between the sub-control means).

  In order to solve the above problems, according to a twenty-third aspect, a gaming machine having the following configuration is provided.

Comprising main control means (for example, main control circuit 90) for transmitting communication data relating to gaming operations;
The main control means includes
During the control process by the main control means, an interrupt process is executed at a predetermined cycle, and when there is no communication data related to the game operation at the time of executing the interrupt process, an interrupt process execution means for transmitting a no-operation command (for example, , Interrupt processing)
Power recovery processing execution means (for example, power-on processing) for executing a predetermined power recovery processing at the time of power recovery,
The power recovery process execution means waits until the interrupt process execution means can execute the interrupt process after starting the power recovery process (for example, S7 and S8 during the power-on process). Done
The game machine characterized in that the interrupt process execution means executes the interrupt process and transmits the no-operation command to the sub-control means at the end of the standby by the power recovery process execution means.

In the gaming machine of the twenty-third invention, the main control means is
A timer circuit (for example, timer circuit 113) that measures the predetermined period;
An interrupt circuit (for example, an interrupt controller 112) that generates an interrupt signal for executing the interrupt processing based on a timeout signal of the timer circuit,
The power recovery processing execution means is
After setting the initial setting for generating the timeout signal in the predetermined cycle in the timer circuit, performing a process of waiting until the interrupt process can be executed by the interrupt process execution means,
The end of the standby may be determined based on whether or not the timer circuit has generated the timeout signal.

  In order to solve the above-mentioned problems, in the twenty-fourth aspect of the invention, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
Communication data generation means for creating command data related to gaming operations (for example, setting change command generation storage processing and communication data storage processing);
During the control process by the arithmetic processing means, an interrupt process is executed at a predetermined cycle, and when there is no command data related to a game operation at the time of executing the interrupt process, an interrupt process execution means for transmitting a no-operation command (for example, , Interrupt processing)
Power recovery processing execution means (for example, power-on processing) for executing a predetermined power recovery processing at the time of power recovery;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The power recovery process execution means waits until the interrupt process execution means can execute the interrupt process after starting the power recovery process (for example, S7 and S8 during the power-on process). Done
The interrupt process execution means executes the interrupt process and transmits the no-operation command at the end of the standby by the power recovery process execution means,
The arithmetic processing means includes:
A plurality of general-purpose registers each storing a plurality of types of data when the arithmetic processing unit performs the arithmetic processing;
The command data includes a command type, a plurality of communication parameters, and a sum value.
The plurality of communication parameters are respectively assigned to the plurality of general purpose registers,
The communication data generating means
In accordance with the command type of the command data, after setting the communication parameter in the general-purpose register assigned to the communication parameter, the communication parameter set in the general-purpose register is stored in a predetermined storage in the second storage means Stored in an area (for example, a temporary communication data storage area)
Even if there is a communication parameter that is not used based on the command type of the command data among the plurality of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter is used as the communication parameter. Stored in the predetermined storage area as
A gaming machine that generates a sum value of the command data based on the command type and data stored in the general-purpose register assigned to a communication parameter.

The gaming machine according to the twenty-fourth aspect of the invention comprises power supply monitoring means (for example, a power supply monitoring port) for monitoring the state of the power supply voltage.
The arithmetic processing means includes:
If the state of the power supply voltage is not stable, wait until the state of the power supply voltage is stable,
After initializing the timer circuit, serial communication circuit and random number circuit of the arithmetic processing means on condition that the state of the power supply voltage is stable, the predetermined area of the second storage means is used to 2 Check whether the storage means is normal,
The no-operation command may be transmitted on condition that the second storage means is normal.

  According to the gaming machines of the twenty-third and twenty-fourth aspects, communication between the main control board and the sub-control board when the power is turned on can be stably operated.

[Game machines of the 25th and 26th inventions]
In a conventional gaming machine, the reel symbol variable display stop control is performed based on the internal winning combination and the player's stop operation, the winning determination is performed based on the combination of symbols, and the hopper (medal payout device) is determined based on the winning determination result. ) To control the medal payout (see Japanese Patent Application Laid-Open No. 2008-119498, for example).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The twenty-fifth and twenty-sixth inventions have been made to solve the above-mentioned problems, and an object of the twenty-fifth and twenty-sixth inventions is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM of a main control circuit and enhancing the gameability by utilizing the free space of the ROM for the increased capacity.

  In order to solve the above problems, in a twenty-fifth aspect of the invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the second storage means by the stored data;
By executing a predetermined read instruction (for example, “LDQ” instruction) that can perform address designation in the second storage means by using the extension register, the detection result of the stop operation by the stop operation detecting means is obtained. Stop operation detection result acquisition means (for example, S714 during reel stop control processing) to be acquired;
When a stop operation of a player for a predetermined display row is detected by the stop operation detecting means, by executing the predetermined read command, it is arranged in the second storage means and the predetermined display row Stop control data storage area setting means (for example, source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL) in FIG. 139)” for designating the address of the stop control data storage area for storing the variable display stop control data; A gaming machine characterized by comprising:

  In the gaming machine of the twenty-fifth aspect, a part of the address that can be specified by the extension register may be a higher-order address value that constitutes the address.

  In order to solve the above-mentioned problems, the twenty-sixth invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if the combinations are of a plurality of types corresponding to the plurality of types of internal winning combinations, they are set across the plurality of display columns. A priority stop symbol determination means (for example, a drawing priority order acquisition process) for determining a combination of symbols to be stopped and displayed preferentially on the determined determination line;
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means and the determination operation of the combination of symbols to be stopped and displayed by the priority stop symbol determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the second storage means by the stored data;
By executing a predetermined read instruction (for example, “LDQ” instruction) that can perform address designation in the second storage means by using the extension register, the detection result of the stop operation by the stop operation detecting means is obtained. Stop operation detection result acquisition means (for example, S714 during reel stop control processing) to be acquired;
When a stop operation of a player for a predetermined display row is detected by the stop operation detecting means, by executing the predetermined read command, it is arranged in the second storage means and the predetermined display row Stop control data storage area setting means (for example, source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL) in FIG. 139)” for designating the address of the stop control data storage area for storing the variable display stop control data;
In the process of preferentially determining the combination of symbols to be stopped and displayed on the determination line by the priority stop symbol determination means, a comparison determination command, a process jump destination address designation command, and a process jump operation command By executing a predetermined determination instruction (for example, “JCP” instruction) executable by the instruction, a combination of symbols corresponding to the internal winning combination to be determined is added to a specific display sequence (for example, currently determined) In addition, it is determined whether or not a predetermined symbol combination (for example, “ANY” combination) in which the stop symbol on the determination line in the right reel 3R) is arbitrary is included, and the internal winning combination to be determined When it is determined that the predetermined symbol combination is included in the corresponding symbol combination, a stop display of the symbol combination corresponding to the internal winning combination to be determined is displayed. Gaming machine, characterized in that it comprises any combination corresponding processing means for locking (e.g., S683 in attraction priority acquisition processing), the.

  In the gaming machine of the twenty-sixth aspect, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

  According to the gaming machines of the 25th and 26th aspects of the invention, the capacity of the processing program and table managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the ROM of the increased capacity is stored. The playability can be improved by utilizing the free space.

[Game machines of the 27th to 29th inventions]
In a conventional gaming machine, there is known a gaming machine that performs symbol stop control using a pull-in priority table during symbol stop control (see, for example, JP 2007-175450 A).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The twenty-seventh to twenty-ninth aspects of the present invention have been made to solve the above-described problems, and an object of the twenty-seventh to twenty-ninth aspects is to reduce the capacity of processing programs and tables managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM of a main control circuit and enhancing the gameability by utilizing the free space of the ROM for the increased capacity.

  In order to solve the above problems, according to a twenty-seventh aspect, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if the combinations are of a plurality of types corresponding to the plurality of types of internal winning combinations, they are set across the plurality of display columns. A priority stop symbol determination means (for example, a drawing priority order acquisition process) for determining a combination of symbols to be stopped and displayed preferentially on the determined determination line;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the determination operation of the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and that can specify a part of the address in the second storage means by the stored data; ,
In the process of determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means,
The arithmetic processing means includes:
By executing a predetermined read instruction (for example, “LDQ” instruction) capable of performing addressing in the second storage means using the extension register, the internal memory is arranged in the second storage means and the internal A winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) for specifying an address of a winning flag data storage area (for example, a hit request flag storage area) for storing the winning flag data corresponding to the winning combination;
By executing the predetermined read command, a winning flag data storage area for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line (for example, A winning flag storage area specifying means (for example, S686 during the drawing priority order acquisition process) for specifying an address of the winning action flag storage area);
A gaming machine comprising: AND operation means (for example, S686 during the drawing priority order acquisition process) that performs an AND operation between the winning flag data and the corresponding winning flag data.

In the gaming machine of the twenty-seventh aspect, in the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, the combination of symbols corresponding to the internal winning combination to be determined, In a case where a predetermined symbol combination (for example, “ANY” role) in which a stop symbol on the determination line in a specific display row (for example, the right reel 3R) currently being determined is included is included,
The arithmetic processing means includes: an address specifying process for the winning flag data storage area by the winning flag storage area specifying means, an address specifying process for the winning flag data storage area by the winning flag storage area specifying means, and the AND operation The AND operation processing by the means may not be executed.

  In order to solve the above-described problems, the twenty-eighth invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if the combinations are of a plurality of types corresponding to the plurality of types of internal winning combinations, they are set across the plurality of display columns. A priority stop symbol determination means (for example, a drawing priority order acquisition process) for determining a combination of symbols to be stopped and displayed preferentially on the determined determination line;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the determination operation of the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
In the process of determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means,
The arithmetic processing means includes:
By executing a predetermined read instruction (for example, “LDQ” instruction) capable of performing addressing in the second storage means using the extension register, the internal memory is arranged in the second storage means and the internal A winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) for specifying an address of a winning flag data storage area (for example, a hit request flag storage area) for storing the winning flag data corresponding to the winning combination;
By executing the predetermined read command, a winning flag data storage area for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line (for example, A winning flag storage area specifying means (for example, S686 during the drawing priority order acquisition process) for specifying an address of the winning action flag storage area);
AND operation means for performing an AND operation between the winning flag data and the winning flag data corresponding to the winning flag data (for example, S686 during the pull-in priority acquisition process);
Priority data table acquisition means (for example, pull-in priority) that acquires a data table that defines the priority of the combination of symbols to be stopped and displayed among the combinations of the plurality of types of symbols by executing the predetermined read command S687) during the acquisition process.

Further, in the gaming machine of the twenty-eighth aspect, in the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, in the combination of symbols corresponding to the internal winning combination to be determined, In a case where a predetermined symbol combination (for example, “ANY” role) in which a stop symbol on the determination line in a specific display row (for example, the right reel 3R) currently being determined is included is included,
The arithmetic processing means includes: an address specifying process for the winning flag data storage area by the winning flag storage area specifying means, an address specifying process for the winning flag data storage area by the winning flag storage area specifying means, and the AND operation The AND operation processing by the means may not be executed.

  In order to solve the above-described problems, the twenty-ninth invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Error detection means for determining whether or not an illegal hit error has occurred (for example, an illegal hit check process);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the determination operation by the error detecting means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and that can specify a part of the address in the second storage means by the stored data; ,
In the process of determining whether or not an illegal hit error has occurred by the error detection means,
The arithmetic processing means includes:
By executing a predetermined read instruction (for example, “LDQ” instruction) capable of performing address designation in the second storage means by using the extension register, the plurality of instructions are arranged in the second storage means and the plurality A winning flag that specifies an address of a winning flag data storage area (for example, a winning action flag storage area) that stores winning flag data corresponding to a combination of symbols stopped and displayed on the determination line set across the display line Storage area designating means (for example, S781 during illegal hit check processing);
AND operation means for performing an AND operation between the winning flag data stored in the winning flag data storage area and the corresponding winning flag data indicating the internal winning combination (for example, S784 during illegal hit check processing) When,
Error determination means (for example, S785 during the illegal hit check process) for determining whether or not an illegal hit error has occurred based on the calculation result by the logical product calculation means;
A gaming machine, wherein the structure of a winning flag data storage area (for example, a winning request flag storage area) in which the winning flag data is stored is the same as that of the winning flag data storage area.

  In the gaming machine of the twenty-ninth aspect, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

Furthermore, in a gaming machine according to a twenty-ninth aspect of the invention, the arithmetic processing means has error processing means for performing error processing when the error detection means determines that there is an illegal hit error.
The error processing means may notify the illegal hit error in a visually recognizable manner and stop the game until the illegal hit error is canceled.

  According to the gaming machines of the twenty-seventh to twenty-ninth inventions, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the ROM for the increased capacity is stored. The playability can be improved by utilizing the free space.

[The gaming machine of the 30th invention]
In conventional gaming machines, gaming machines that transmit command data from a game control board (main control board) to an effect control board (sub control board) are known (for example, JP2013-027655A and JP2014). -033751).

  By the way, in recent years, with diversification of game playability, there is a tendency that processing related to game play increases in effect control by the sub control circuit. For this reason, an illegal act called “Goto” that tampers communication data transmitted from the main control circuit to the sub-control circuit has occurred, causing damage to the game shop. On the other hand, conventionally, as proposed in, for example, the above-mentioned Japanese Patent Application Laid-Open No. 2014-033751 and the like, countermeasures for performing anti-going processing on transmission data in the main control circuit have also been implemented. However, there is a problem that the program capacity of the main control circuit is compressed by the addition of such anti-going processing.

  The thirtieth aspect of the invention is made to solve the above-mentioned problem, and the object of the thirtieth aspect is to prevent fraud and prevent fraud without performing fraud prevention processing on transmission data. It is an object of the present invention to provide a gaming machine that can eliminate the compression of the program capacity of a main control circuit due to processing.

  In order to solve the above problems, in the thirtieth invention, a gaming machine having the following configuration is provided.

Data transmission means (for example, main control circuit 90) for transmitting communication data relating to the gaming operation;
Communication data generation means for generating the communication data (for example, communication data storage processing);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling communication data generating operation by the communication data generating means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A plurality of general-purpose registers each storing a plurality of types of data when the arithmetic processing unit performs the arithmetic processing;
The arithmetic processing means includes:
In the communication data generation process by the communication data generation means,
Assigning a plurality of types of communication parameters constituting the communication data to the plurality of general purpose registers
Among a plurality of types of communication parameters constituting the communication data, a communication parameter is set in a corresponding general-purpose register among the plurality of general-purpose registers based on the type of the communication data,
Storing the communication parameters set in the general-purpose register in a predetermined storage area (communication data temporary storage area) in the second storage means;
Among the plurality of types of communication parameters, data stored in a general-purpose register associated with an unused communication parameter when generating communication data is stored as a communication parameter in the predetermined storage area,
A gaming machine that generates a sum value of the communication data based on data set in the plurality of general-purpose registers according to the plurality of types of communication parameters.

  In the gaming machine according to a thirtieth aspect of the invention, the communication data generating means sets the communication parameters set in the plurality of general purpose registers when there is no free space in the predetermined storage area in the second storage means. You may make it complete | finish the production | generation process of communication data, without storing in the predetermined storage area in the said 2nd memory | storage means.

  According to the gaming machine of the thirtieth invention, fraudulent acts can be suppressed without performing fraud prevention processing on transmission data (communication data), and pressure on the program capacity of the main control circuit due to fraud prevention processing is also eliminated. be able to.

[The gaming machine of the 31st invention]
In a conventional gaming machine, a gaming machine having a function of updating the number of credits according to the number of medals paid out by control of a main control circuit is known (see, for example, Japanese Patent Application Laid-Open No. 2009-079777). ).

  Conventionally, in games during ART or bonuses, medals are often paid out. At this time, the payout interval for each medal is often controlled uniformly (fixed). In this case, useless waiting time occurs in the medal payout period. Therefore, for example, in a long-time game such as ART, the game period becomes uselessly long, which may be a mental burden on the player.

  The thirty-first invention has been made to solve the above-mentioned problems, and an object of the thirty-first invention is to reduce a useless waiting time and a player's mental burden in a medal payout period. It is to provide a possible gaming machine.

  In order to solve the above-described problems, the thirty-first invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When the variable display of the plurality of display columns is stopped by the stop control means, the symbol corresponding to the internal winning combination relating to the payout of the game medium on the determination line set across the plurality of display columns Bonus granting determination means (for example, winning search process) for determining whether or not the combination of is stopped and displayed,
A game medium payout means for paying out the game medium when the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line by the bonus grant determination means (for example, , Winning check / medal payout processing),
Game medium storage means for storing the game medium (for example, a credit function);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the game medium payout operation by the game medium payout means,
The arithmetic processing means includes:
The game medium determined by the bonus granting determination means that the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line, and stored in the game medium storage means If the storage number of the game medium is less than the upper limit value, game medium addition means for adding 1 to the number of storage of the game medium (for example, S805 during the winning check / medal payout process);
After the game medium is added to the number of stored game media by the game medium adding means, the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed. A payout end determination means for determining whether or not the payout of the total payout number of game media has ended (for example, S807 during the winning check / medal payout process);
When the payout end determination means determines that the payout of the total payout amount of the game medium has not ended, a weight generation means (for example, a prize check A game machine having a medal payout process (S808).

In the gaming machine of the thirty-first invention, the arithmetic processing means has interrupt processing execution means for executing interrupt processing at a predetermined cycle,
The interrupt processing by the interrupt processing execution means may be executed a predetermined number of times with the weight where the operation related to the game by the weight generation means is invalid.

  According to the gaming machine of the thirty-first aspect, in the medal (game medium) payout period, it is possible to reduce useless waiting time and to reduce the mental burden on the player.

[Amusement machine of the thirty-second invention]
In a conventional gaming machine, a program and a table are arranged in predetermined areas in a ROM mounted on a main control board (see, for example, JP 2012-110635 A).

  By the way, as in the gaming machine described in JP 2012-110635 A, the programs and tables that can be arranged in the ROM of the main control board are limited by the rules of the gaming machine industry, and the ROM of the main control board The program and table expandability is extremely poor.

  A thirty-second invention has been made to solve the above-described problems, and an object of the thirty-second invention is to provide a gaming machine capable of enhancing the expandability of programs and tables in the ROM of the main control board. It is to be.

  In order to solve the above problems, in a thirty-second invention, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
In the first storage means, a game storage area (for example, a game ROM area) in which information necessary for executing a process related to the game performance of a game executed by a player is stored, and the game storage An unspecified storage area (for example, an unspecified ROM area) in which information necessary for execution of processing that is arranged in an area different from the area and is not related to the game performance of the game executed by the player is provided. A gaming machine characterized by

  In the gaming machine according to the thirty-second invention, the second storage means temporarily stores information necessary for execution of processing related to game playability performed by the player. And a game temporary storage area including a game stack area (for example, a game RAM area) and the game temporary storage area are arranged in different areas and are related to the game playability of the game executed by the player. There may be provided an unspecified temporary storage area (for example, an unspecified RAM area) including an unspecified work area and an unspecified stack area in which information necessary for executing the processing that is not temporarily stored is stored. .

Furthermore, in the gaming machine of the thirty-second invention, the arithmetic processing means has a stack pointer as a dedicated register,
The arithmetic processing means includes:
When executing the program stored in the non-standard storage area of the first storage unit, the address of the non-standard stack area of the second storage unit is set in the stack pointer,
When the program stored in the non-specified storage area of the first storage means is to be terminated, the game of the second storage means saved when the program stored in the non-standard storage area is executed An address of the stack area may be set in the stack pointer to return to the program stored in the game storage area of the first storage area.

  According to the gaming machine of the thirty-second invention, the expandability of the program and table in the ROM of the main control board can be improved.

  DESCRIPTION OF SYMBOLS 1 ... Pachislot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 6 ... Information indicator, 11 ... Display device, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72 ... Sub-control board, 90 ... Main control circuit, 91 ... Microprocessor, 101 ... Main CPU, 102 ... Main ROM, 103 ... Main RAM, 107 ... Arithmetic circuit, 114 ... First serial communication circuit, 115 ... Second serial Communication circuit 200 ... sub control circuit 201 ... sub CPU 201 301 ... first interface board 302 ... second interface board

Claims (1)

A gaming machine comprising an advantageous state control means for controlling an advantageous state advantageous to a player when a predetermined condition is established,
The advantageous states include a first advantageous state and a second advantageous state;
The advantageous state control means includes:
A right granting means for deciding whether or not to grant a specific right that allows a determination as to whether or not to extend the game period of the first advantageous state in the second advantageous state;
When the first advantageous state ends,
If the specific right has not been granted, terminate the advantageous state;
When it is determined that when the specific right is granted, it is possible to play a game in the second advantageous state and the game period of the first advantageous state is extended in the second advantageous state In the extended game period, it is possible to play a game in the first advantageous state,
The right granting means can grant a plurality of the specific rights in the advantageous state,
In the case where a plurality of the specific rights are granted, even if it has already been decided to extend the game period of the first advantageous state in the second advantageous state, Decide whether to extend the game period of the first advantageous state until the right is consumed, and decide to extend in the second advantageous state when all the specific rights are consumed A gaming machine characterized in that the gaming period in the first advantageous state is added up to extend the gaming period in the first advantageous state.

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