JP2018092327A - Information processor and information processing method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor and an embedded controller that make confirmation of a content of processing of BIOS possible without preparing a designated device.SOLUTION: An information processor according to the present invention comprises a CPU(Central Processing Unit), a chip set connected to the CPU, an embedded controller (EC) acquiring a processing result output successively by execution of a POST (Power On Self Test) by the CPU based on a BIOS(Basic Input/Output System) through a bus connected to the chip set, and an input device connected to the embedded controller, the embedded controller has a first storage means storing the latest result among the results output successively, a trigger detection means detecting a signal generated by a prescribed input operation to the input device and a second storage means storing the latest processing result with a nonvolatile manner based on detection of the signal.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an information processing apparatus, an information processing method, and a program.

  In recent years, information processing apparatuses such as personal computers (PCs) are provided with various functions such as a function for recording and reproducing music and a function for playing games. In addition, for the purpose of reducing the cost of the information processing apparatus, the shape of the mounted component itself has been changed, and the hardware configuration itself on the M / B (motherboard) has also changed in various ways.

  In the development and prototyping of an information processing apparatus having a variety of hardware on the M / B, when new hardware is installed on the M / B, a CPU (Central Processing Unit) and memory provided in the computer in advance In addition, an operation confirmation work based on BIOS (Basic Input / Output System) which is a program for controlling operations with input / output devices such as a keyboard and a mouse is indispensable. This operation check operation is realized by executing a POST (Power On Self Test) in which the BIOS activated when the information processing apparatus is powered on initializes the function by accessing the connected device.

  By executing POST, whether or not there is a problem in the combination of hardware and computer is output in a form that can be visually recognized by the user as information related to the processing content. The information output at this time is called BIOS POST CODE, and the developer can confirm what kind of problem is occurring by confirming the output of the BIOS POST CODE.

  Conventionally, as a method for confirming the BIOS POST CODE, as disclosed in Patent Document 1, a method of outputting the BIOS POST CODE to a 7-segment unit connected to a CPU and a chip set on an M / B is disclosed. Has been. In addition, a method has been proposed in which a dedicated debug card is connected in place of the 7-segment unit and BIOS POST CODE is output, and it is common to check the BIOS processing contents by one of the above two methods. Met.

  However, in order to confirm with a 7-segment unit or a dedicated debug card as in the prior art, it is necessary to secure a space for arranging the M / B on the 7-segment unit or the dedicated debug card. In recent years, as information processing devices such as personal computers are required to be downsized and diversified in function as described above, a space for arranging a 7-segment unit or a dedicated debug card is secured. It's getting harder to do.

JP 2001-331342 A

  The present invention has been made in view of such circumstances, and provides an information processing apparatus and an embedded controller that enable confirmation of the processing contents of a BIOS without providing a dedicated device. For the purpose.

  An information processing apparatus according to the present invention includes a CPU (Central Processing Unit), a chip set connected to the CPU, and the CPU executes POST (Power On Self Test) based on BIOS (Basic Input / Output System). The embedded controller includes an embedded controller (EC) that acquires processing results that are sequentially output via a bus connected to the chipset, and an input device that is connected to the embedded controller. Of the results, the first storage means for storing the latest processing result, the trigger detection means for detecting a signal generated by a predetermined input operation on the input device, and the latest processing result based on the detection of the signal. And second storage means for storing in a nonvolatile manner.

  In the method for realizing information processing according to the present invention, a CPU (Central Processing Unit) executes POST (Power On Self Test) based on BIOS (Basic Input / Output System), and sequentially outputs processing results. Of the processing results obtained and sequentially output, the step of storing the latest processing result, the step of detecting a signal emitted by an external input device, and the non-volatile processing result of the latest processing based on the detection of the signal And storing the data in a memory.

  A program for realizing information processing according to the present invention is a CPU (Central Processing Unit) that executes POST (Power On Self Test) based on BIOS (Basic Input / Output System), and displays processing results that are sequentially output. Of the processing results that are acquired and output sequentially, the most recent processing result is stored, the processing that detects the signal emitted by the external input device, and the detection of the most recent processing result based on the signal detection And storing the data in a computer.

  According to the present invention, it is possible to confirm the processing contents of the BIOS without providing a confirmation device.

It is a hardware block diagram of the information processing apparatus 1 concerning embodiment of this invention. It is a functional block diagram of information processor 1 concerning an embodiment of the present invention. It is an example of the BIOS processing content and BIOS POST CODE concerning embodiment of this invention. It is an example of BIOS POST CODE confirmation concerning embodiment of this invention. It is an example of the flowchart concerning embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail.

  First, the hardware configuration of the information processing apparatus 1 according to the present embodiment will be described with reference to FIG. Here, the information processing apparatus is a computer having a control function on an M / B (motherboard) such as an information terminal that can be connected to a network such as a personal computer, a tablet terminal, or a smartphone, an image forming apparatus such as a printer or a FAX General. Further, it may be a host computer or a server that requests processing to a plurality of computers through a network. Note that the configuration of the information processing apparatus 1 is not necessarily the same as that shown in FIG. 1, and it is sufficient if it has hardware capable of realizing the present embodiment. For example, the memory 1301 and the communication I / F 17 built in the embedded controller 13 are not essential components. Furthermore, an optical drive that reads and writes data stored on a CD or DVD may be additionally provided.

  The information processing apparatus 1 stores a program that is read by the CPU 10 when the power of the information processing apparatus 1 is turned on by executing a predetermined program to realize overall control of the information processing apparatus 1. It consists of mask ROM, EPROM, SSD, etc., which are read-only non-volatile memories, and SRAM, DRAM, etc., which are volatile memories for work in which the CPU 10 reads the program and temporarily writes data generated by arithmetic processing, etc. Main memory 11 connected to CPU 10, chipset 12 that controls the operation of the functions of the computer, embedded controller 13 that controls the sequence and functions unique to information processing device 1, input such as a keyboard composed of a mouse and input keys Device 14, projector or liquid crystal, and A display device 15 having a display using a panel such as a machine EL, and an HDD 16 capable of holding various data records when the information processing device 1 is powered off. It is connected to the chip set 12.

  The information processing apparatus 1 further includes a communication I / F 17. The information processing apparatus 1 is connected to the network 200 via the communication I / F 17. The communication I / F 17 accesses various types of information accessible via the network 200 based on the operation of the CPU 10. Specific examples of the communication I / F 17 include a USB port, a LAN port, and a wireless LAN port. Any device can be used as long as data can be transmitted / received to / from the device.

DMI as an example of a connection method between the CPU 10 and the chipset 12
(Direct Media Interface), but not limited to this. Further, the configuration of the chip set 12 is not limited to the two-chip configuration having the north bridge and the south bridge, and may be a one-chip configuration.

  The BIOS is stored in the nonvolatile memory 18, and the BIOS is read based on the operation of the CPU 10. An example of the processing contents of the BIOS is shown in FIG. As shown in FIG. 3, the BIOS is associated with a code (hereinafter referred to as BIOS POST CODE) in association with the execution processing contents. For example, if the BIOS POST CODE is “32”, the processing content is “CPU post-memory initialization is started”, and the processing is executed. If there is no problem, the processing of the next code “33” is executed. .

  The embedded controller 13 also performs control of sequences and functions unique to the information processing apparatus 1 and control of power supply to each device provided in the information processing apparatus 1. In the present embodiment, the CPU 10 and the chip set 12 also have a function of acquiring and storing the processing result output from the chip set 12 through the BIOS execution (POST) via the LPC Bus 20.

  FIG. 2 is a functional block diagram of the information processing apparatus 1 according to the embodiment of the present invention. As shown in FIG. 2, the information processing apparatus 1 according to the present invention includes a first storage unit 100, a trigger detection unit 101, and a second storage unit 102.

The first storage unit 100 of the information processing apparatus 1 acquires the processing result by the BIOS execution (POST) output from the chipset 12 by the embedded controller 13 and temporarily stores the acquired processing result. The embedded controller 13 monitors the execution of the BIOS by the CPU 10 and the chipset 12 based on a control device (not shown) provided therein, and the BIOS processing results are sequentially output from the chipset 12 and output. The processing result is acquired via the LPC Bus 20. Of the acquired processing results, the latest processing result is stored in a volatile memory. The volatile memory may be provided in the embedded controller 13 itself, or may be another memory as long as the embedded controller 13 can access it. Due to the amount of data, a predetermined time interval may be provided to store the latest processing result, and the latest processing result among the processing results obtained during the time interval may be overwritten at all times. preferable.

  The first storage unit 100 of the information processing apparatus 1 can be realized by processing the processing result obtained by executing the BIOS acquired by the embedded controller 13 so that the embedded controller 13 stores the result in a predetermined volatile memory.

  The trigger detection unit 101 of the information processing apparatus 1 detects a signal generated by a predetermined input operation on the input device 14 by the embedded controller 13. The input device 14 is a keyboard composed of, for example, a mouse and input keys, and may be a switch, a game controller, or the like as long as it can be connected to the embedded controller 13.

  The user performs a predetermined input operation on the input device 14. The predetermined input operation can be determined for each input device 14. For example, “right click once and left click twice” can be set for a mouse, and “1 # 4% 6 ¥ can be input simultaneously” can be set as an example.

  When the information processing apparatus 1 executes the BIOS by the CPU 10 and the chipset 12 (POST), when the developer as a user wants to check the current execution status of the BIOS, the input device 14 is as described above. Perform input operations. When a predetermined input operation is performed on the input device 14, the embedded controller 13 detects a signal output from the input device 14 as a trigger.

  The predetermined input operation detected as a trigger is defined by a program stored in the control device of the embedded controller 13 in advance or by a program stored in the main memory 11 of the information processing device 1. Also good.

  The trigger detection unit 101 of the information processing apparatus 1 can be realized when the embedded controller 13 receives a signal output by an input operation of the input device 14 via its input / output I / F. .

  The second storage unit 102 of the information processing apparatus 1 stores the latest processing result by the execution of the BIOS in a nonvolatile manner based on the detection of the signal received from the input device 14 by the embedded controller 13. Here, a case is considered in which the latest processing result obtained by executing the BIOS is stored in the memory 1301, which is a nonvolatile memory included in the embedded controller 13 itself.

  As described above, the embedded controller 13 acquires the execution processing of the BIOS output from the chipset 12 and stores the latest processing result in the predetermined volatile memory among the acquired processing results. When the trigger detection unit 101 detects a signal from the input device 14, the embedded controller 13 reads and reads the latest processing result of the BIOS stored in the volatile memory when the signal is detected as a trigger. The processing result is stored in the memory 1301 which is a nonvolatile memory. By storing the BIOS processing result in a nonvolatile manner in this way, it is possible to store the execution processing status of the BIOS at a timing when the user, that is, the developer wants to confirm.

  Note that the embedded controller 13 may not include a nonvolatile memory for storing the latest processing result of the BIOS as long as the embedded controller 13 includes a nonvolatile memory accessible to the embedded controller 13 outside.

  The second storage unit 102 of the information processing apparatus 1 stores the latest processing result by the execution of the BIOS in a predetermined nonvolatile memory based on the detection of a signal as a trigger received from the input device 14 by the embedded controller 13. This is possible.

  With the configuration as described above, the user, that is, the developer, can store the BIOS processing result at the timing at which the user wants to confirm the BIOS execution processing. Since the BIOS processing result stored in the nonvolatile manner is stored even if the information processing apparatus 1 is turned off, for example, it can be read and confirmed at a timing that the user wants to confirm.

  Consider a case where the user reads and confirms the latest processing result of the BIOS stored in a nonvolatile manner. For example, the display device 15 can be used to display the BIOS processing result. When the information processing apparatus 1 is a communication terminal such as a personal computer, an application as a tool for operating the embedded controller 13 is provided in the OS, and a display screen of the application is displayed on the display device 15 or the like. By executing the output display based on the above operation, the latest processing result of the stored BIOS is read out.

  FIG. 4 shows a BIOS processing result read by the display device 15. FIG. 4 is similar to FIG. 3 in which the BIOS POST CODE is associated with the execution process contents, and evaluated as “O” and “X” as “execution flags”. Here, it is assumed that there is a problem in the process with the BIOS POST CODE “33” and the latest process result of the BIOS whose execution flag is evaluated as “x” has been read. In this way, the user can confirm the processing content in which the problem has occurred. The BIOS POST CODE in which the problem has occurred is not limited to the determination by the execution flag as described above. For example, the BIOS POST CODE may be described by changing the color or shape of the character of the BIOS POST CODE, or a pop-up etc. It is good also as BIOS POST CODE "△△". As long as the user can confirm “in which process an error has occurred”, the notation may be changed.

  FIG. 5 is an example of a flowchart according to the embodiment of the present invention.

  First, a BIOS processing result sequentially output from the chipset 12 is acquired (step 1).

  Of the obtained BIOS processing results, the latest processing results are stored in a volatile memory (step 2). It is confirmed whether or not a trigger signal is detected from the input device 14 (step 3). When a trigger signal is detected from the input device 14, the latest processing result is stored in a nonvolatile memory (step 4). If no trigger signal is detected from the input device 14, the processing from step 2 is continued.

  As described above, in the present embodiment, based on the operation of the embedded controller 13 provided in advance, it is possible to store the processing result by the execution of the BIOS without providing a 7-segment unit or a dedicated debug card. Become. Since there is no need to use a 7-segment unit or a dedicated debug card, there is a great merit in terms of cost. And since the space provided with the said parts on M / B is not required, it becomes possible to lead to size reduction of an apparatus itself and effective utilization of the space of M / B.

In this embodiment, the chip set 12 and the embedded controller 13 are connected to the LPC Bus.
20, the BIOS processing result that the embedded controller 13 sequentially outputs from the chipset 12 even when an operation failure due to the influence of devices other than the embedded controller 13 occurs. Can be obtained without being affected by malfunctions in operation caused by other devices.

  As another embodiment of the present embodiment, the latest processing result of the BIOS stored in a nonvolatile manner by the embedded controller 13 is connected not only by the information processing apparatus 1 but also by the network 200, and the embedded controller 13 If it is connected so that it can be accessed, it can be configured to read out and display from another device. It is not displayed on the 7-segment unit of its own device or a dedicated debugging card as in the past, but is also useful in that it can be confirmed from other devices other than its own device because the BIOS processing result is stored as data. It can be said that there is.

  As long as the present invention can be realized, the content of the device used, the number of devices, and the like are not limited to the present embodiment.

100 First storage means 101 Trigger detection means 102 Second storage means

Claims (7)

CPU (Central Processing Unit),
A chipset connected to the CPU;
The CPU executes POST (Power On Self Test) based on BIOS (Basic Input / Output System), and obtains processing results output sequentially through a bus connected to the chipset (EC )When,
An input device connected to the embedded controller;
With
The embedded controller is
A first storage means for storing the latest processing result among the processing results sequentially output;
Trigger detection means for detecting a signal emitted by a predetermined input operation on the input device;
Based on detection of the signal, second storage means for storing the latest processing result in a nonvolatile manner;
Having
An information processing apparatus characterized by that. The first storage means stores the latest processing result in a volatile first memory included in the EC itself.
The information processing apparatus according to claim 1. The second storage means stores the most recent processing result in a nonvolatile second memory included in the EC itself based on the detection of the signal.
The information processing apparatus according to claim 1 or 2. Processing result output means for reading out and outputting the latest processing result stored in the nonvolatile manner based on a predetermined access;
Display means for displaying the latest processing result read out together with the BIOS POST CODE;
Further comprising
The information processing apparatus according to claim 1, wherein the information processing apparatus is an information processing apparatus. The input device is a mouse or a keyboard.
The information processing apparatus according to claim 1, wherein the information processing apparatus is an information processing apparatus. An information processing method for an information processing apparatus having an embedded controller (EC),
The embedded controller is
A serial output result of a BIOS (Basic Input / Output System) that is POST (Power On Self Test) by a CPU (Central Processing Unit) is acquired via the bus. Storing the latest processing result;
Detecting a signal emitted by an external input device;
Based on the detection of the signal, storing the latest processing result in a nonvolatile manner;
Having
An information processing method characterized by the above. A program executed by an embedded controller (EC) provided in the information processing apparatus,
A serial output result of a BIOS (Basic Input / Output System) that is POST (Power On Self Test) by a CPU (Central Processing Unit) is acquired via the bus. , Storing the latest processing result,
Processing to detect a signal emitted by an external input device;
Based on the detection of the signal, processing to store the latest processing result in a nonvolatile manner,
To run on a computer,
A program characterized by that.

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