JP2018085503A - Transistor, semiconductor device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of holding data for a long time period.SOLUTION: The semiconductor device comprises: a first transistor; an insulator that covers the first transistor; and a second transistor on the insulator. The first transistor has: a first gate electrode; a second gate electrode overlapped with the first gate electrode; and a semiconductor provided between the first gate electrode and the second gate electrode. The first gate electrode is electrically connected with one of a source and a drain of the second transistor.SELECTED DRAWING: Figure 3

Description

The present invention relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). One embodiment of the present invention relates to a semiconductor device, a light-emitting device, a display device, an electronic device, a lighting device, and manufacturing methods thereof. In particular, one embodiment of the present invention relates to a light-emitting device using an organic electroluminescence (hereinafter also referred to as EL) phenomenon and a manufacturing method thereof. For example, the present invention relates to an electronic device in which a semiconductor integrated circuit including a power device, a memory, a thyristor, a converter, an image sensor, and the like mounted on an LSI, a CPU, and a power supply circuit are mounted as components.

Note that one embodiment of the present invention is not limited to the above technical field.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. An electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

In recent years, semiconductor devices have been developed, and LSIs, CPUs, and memories are mainly used. The CPU is a collection of semiconductor elements each having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes serving as connection terminals.

A semiconductor circuit (IC chip) such as an LSI, a CPU, or a memory is mounted on a circuit board, for example, a printed wiring board, and used as one of various electronic device components.

In addition, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

A transistor using an oxide semiconductor is known to have extremely small leakage current in a non-conduction state. For example, a low power consumption CPU using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).

In addition, for the purpose of improving the carrier mobility of a transistor, a technique of stacking oxide semiconductor layers having different electron affinities (or conduction band bottom levels) is disclosed (see Patent Document 2 and Patent Document 3).

In recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for integrated circuits in which transistors and the like are integrated at high density. There is also a need for improved productivity of semiconductor devices including integrated circuits.

JP 2012-257187 A JP 2011-124360 A JP 2011-138934 A

An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long period of time. An object of one embodiment of the present invention is to provide a semiconductor device with high information writing speed. An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

A first transistor and a second transistor having different electrical characteristics from the first transistor are provided over an insulator covering the first transistor. In that case, for example, a first transistor having a first threshold voltage and a second transistor having a second threshold voltage are provided. Semiconductor materials having different electron affinities are used for the semiconductor layer in which the channel of the first transistor is formed and the semiconductor layer in which the channel of the second transistor is formed. A first transistor whose carrier mobility and on-state current are higher than those of the second transistor and a second transistor whose drain current when the gate voltage is 0 V are smaller than the first transistor are provided.

In addition, the first transistor, the second transistor having different electrical characteristics from the first transistor, and the capacitor are provided over the insulator covering the first transistor. At this time, the second transistor and the capacitor are provided in the same layer.

By providing transistors having different electrical characteristics in one semiconductor device, the degree of freedom in circuit design can be increased. On the other hand, when a transistor having different electrical characteristics and a capacitor are formed in one semiconductor device, the number of manufacturing steps of the semiconductor device may be significantly increased. A large increase in the number of manufacturing steps tends to induce a decrease in yield and may significantly reduce the productivity of semiconductor devices. According to one embodiment of the present invention, a part of a manufacturing process of a transistor and a manufacturing process of a capacitor are commonly used, so that the number of manufacturing processes of the semiconductor device is not significantly increased. A transistor having a characteristic and a capacitor can be provided.

One embodiment of the present invention includes a first transistor, an insulator that covers the first transistor, and a second transistor over the insulator, the first transistor including a first gate electrode, And a semiconductor provided between the first gate electrode and the second gate electrode, the first gate electrode being connected to the source and drain of the second transistor. On the other hand, the semiconductor device is electrically connected to the third gate electrode of the second transistor.

In the above semiconductor device, the semiconductor is a first semiconductor, and the second transistor includes a second semiconductor, and a first electrode and a second electrode that are electrically connected to the second semiconductor. The first gate electrode and one of the source and the drain of the second transistor are preferably electrically connected to each other through one of the first electrode and the second electrode.

In the above semiconductor device, the insulator is a first insulator and has a capacitor on the first insulator. The capacitor includes a third electrode, a fourth electrode, and a third electrode. A second insulator provided between the fourth electrodes, the third electrode electrically connected to one of a source and a drain of the first transistor, and the third electrode The first electrode and the second electrode are made of the same material, the fourth electrode is made of the same material as the third gate electrode, and the second insulator is made of the same material as the gate insulating film of the second transistor Preferably it consists of.

In the above semiconductor device, the carrier mobility of the first transistor is preferably higher than the carrier mobility of the second transistor.

In the semiconductor device, the drain current of the second transistor when the gate voltage applied to the second transistor is 0V is the first transistor when the gate voltage applied to the first transistor is 0V. It is preferable that the drain current is smaller.

In a semiconductor device including a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

Alternatively, a novel semiconductor device can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

4A and 4B are a cross-sectional view and a circuit diagram of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a cross-sectional view and a circuit diagram of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a cross-sectional view and a circuit diagram of a semiconductor device according to one embodiment of the present invention. 6A and 6B illustrate a cross-sectional structure of a transistor according to one embodiment of the present invention. 6A and 6B illustrate a cross-sectional structure of a transistor according to one embodiment of the present invention. 3A and 3B illustrate a cross-sectional structure of a capacitor according to one embodiment of the present invention. 6A and 6B illustrate a cross-sectional structure of a transistor according to one embodiment of the present invention. 6A and 6B illustrate a cross-sectional structure of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a range of the atomic ratio of an oxide according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4D illustrate a method for manufacturing a transistor according to one embodiment of the present invention. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention. 10A and 10B are a flowchart and a perspective schematic diagram illustrating an example of a manufacturing process of an electronic component. FIG. 14 illustrates an electronic device according to one embodiment of the present invention.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

In the drawings, the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

In this specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

In addition, in this specification, terms indicating arrangement such as “above” and “below” are used for convenience to describe the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

In this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel formation region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and between the source and drain via the channel formation region. It is possible to pass a current through. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.

In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

Note that in this specification and the like, a silicon oxynitride film has a composition that contains more oxygen than nitrogen, and preferably contains 55 atomic% to 65 atomic% of oxygen and 1 atom of nitrogen. % To 20 atomic%, silicon is contained in a concentration range of 25 atomic% to 35 atomic%, and hydrogen is contained in a concentration range of 0.1 atomic% to 10 atomic%. The silicon nitride oxide film has a composition containing more nitrogen than oxygen. Preferably, nitrogen is 55 atomic% to 65 atomic% and oxygen is 1 atomic% to 20 atomic%. , Which includes silicon in a concentration range of 25 atomic% to 35 atomic% and hydrogen in a concentration range of 0.1 atomic% to 10 atomic%.

In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

The transistors described in this specification and the like are enhancement-type (normally-off-type) field effect transistors unless otherwise specified. The transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.

Further, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

For example, in this specification and the like, when X and Y are explicitly described as being connected, X and Y are electrically connected, and X and Y are functional. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And the case where X and Y are directly connected (that is, the case where another element or another circuit is not connected between X and Y). It shall be disclosed in the document. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that

Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined.

Alternatively, as another expression method, for example, “a source (or a first terminal or the like of a transistor) is electrically connected to X through at least a first connection path, and the first connection path is The second connection path does not have a second connection path, and the second connection path includes a transistor source (or first terminal or the like) and a transistor drain (or second terminal or the like) through the transistor. The first connection path is a path through Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y through at least the third connection path. The third connection path is connected and does not have the second connection path, and the third connection path is a path through Z2. " Or, “the source (or the first terminal or the like) of the transistor is electrically connected to X via Z1 by at least a first connection path, and the first connection path is a second connection path. The second connection path has a connection path through the transistor, and the drain (or the second terminal, etc.) of the transistor is at least connected to Z2 by the third connection path. , Y, and the third connection path does not have the second connection path. Or “the source of the transistor (or the first terminal or the like) is electrically connected to X through Z1 by at least a first electrical path, and the first electrical path is a second electrical path Does not have an electrical path, and the second electrical path is an electrical path from the source (or first terminal or the like) of the transistor to the drain (or second terminal or the like) of the transistor; The drain (or the second terminal or the like) of the transistor is electrically connected to Y through Z2 by at least a third electrical path, and the third electrical path is a fourth electrical path. The fourth electrical path is an electrical path from the drain (or second terminal or the like) of the transistor to the source (or first terminal or the like) of the transistor. can do. Using the same expression method as those examples, by defining the connection path in the circuit configuration, the source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are distinguished. The technical scope can be determined.

In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

In addition, even when the components shown in the circuit diagram are electrically connected to each other, even when one component has the functions of a plurality of components. There is also. For example, in the case where part of the wiring also functions as an electrode, one conductive film has both the functions of both the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

Note that in this specification, a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. There is.

(Embodiment 1)
By providing the semiconductor device with transistors having different electrical characteristics, the degree of freedom in designing the semiconductor device can be increased. Further, by providing transistors having different electrical characteristics in different layers, the degree of integration of the semiconductor device can be increased. Specifically, transistors having different compositions of semiconductor materials and different semiconductor film thicknesses are provided, a transistor with higher carrier mobility and on-current, and a drain current when the gate voltage is 0 V are more in the semiconductor device. Make small transistors. As a transistor that requires a high operating frequency, such as a switching transistor, a transistor with higher carrier mobility and higher on-state current is used. As a transistor for holding charge in a capacitor or an electrode such as a holding transistor, a transistor having a smaller drain current when the gate voltage is 0V is used. As described later in this embodiment, a semiconductor device formed by combining such transistors can have various functions. In this embodiment, an example of an embodiment in which transistors having different electrical characteristics are provided in different layers will be described.

<Configuration Example of Semiconductor Device 1000>
FIG. 1A is a cross-sectional view illustrating the semiconductor device 1000, and FIG. 1B is a circuit diagram illustrating the semiconductor device 1000. The semiconductor device 1000 includes a transistor 100 and a transistor 200. The transistor 100 and the transistor 200 have different structures. The transistor 200 is provided over an insulator 110 provided so as to cover the transistor 100.

In FIG. 1A, a transistor 100 is provided over an insulator substrate, a semiconductor substrate, or a substrate having an insulating surface, and is formed using a conductor 101, an insulator 103, a semiconductor 104, a conductor 105, a conductor 106, and an insulator. 108 and a conductor 109. The conductor 101 is formed so as to be embedded in the insulator 102. In addition, the conductor 101 functions as a first gate electrode of the transistor 100. At least part of the semiconductor 104 is provided so as to overlap with at least part of the conductor 101. The insulator 103 provided between the conductor 101 and the semiconductor 104 can function as a first gate insulating film. The conductor 105 functions as one of a source electrode and a drain electrode and is electrically connected to the semiconductor 104. In addition, the conductor 106 functions as the other of the source electrode and the drain electrode and is electrically connected to the semiconductor 104. On the other hand, in the case where regions serving as a source region and a drain region are provided in the semiconductor 104, the conductor 105 and the conductor 106 are not necessarily provided. The conductor 109 functions as a second gate electrode. The insulator 108 is provided between the semiconductor 104 and the conductor 109 and functions as a second gate insulating film. The insulator 108 only needs to be provided at least in a portion where the conductor 109 and the semiconductor 104 overlap with each other. The insulator 108 may be provided so as to cover the entire semiconductor 104, or may be provided so as to cover the semiconductor 104 and the insulator 103. Also good.

The transistor 100 is covered with an insulator 110. A conductor 112 and a conductor 113 are provided so as to be embedded in the insulator 110. The conductor 112 is electrically connected to the semiconductor 104 through the conductor 105, and the conductor 113 is electrically connected to the semiconductor 104 through the conductor 106. A conductor 114 and a conductor 115 are provided over the insulator 110. The conductor 114 is electrically connected to the conductor 112, and the conductor 115 is electrically connected to the conductor 113.

A conductor 117 is provided so as to be embedded in the insulator 103 and the insulator 110 and is electrically connected to the conductor 116. The conductor 116 may be provided in the same layer as the conductor 101 and may be electrically connected to the conductor 101. Alternatively, the conductor 101 and the conductor 116 may be integrated.

A transistor 200 is provided over the insulator 110. The transistor 200 includes a semiconductor 201 over the insulator 110, a conductor 202, a conductor 203, an insulator 204, and a conductor 205. The semiconductor 201 has different characteristics from the semiconductor 104. Specifically, the semiconductor material, the content ratio of elements contained in the semiconductor, the thickness of the semiconductor, and the like are different. In addition, characteristics may be changed by changing the width or length of a channel formation region formed in a semiconductor. The conductor 202 functions as one of a source electrode and a drain electrode of the transistor 200 and is electrically connected to the conductor 117. The conductor 203 functions as the other of the source electrode and the drain electrode. The insulator 204 is provided so as to cover the semiconductor 201, the conductor 202, and the conductor 203. The insulator 204 may be provided so as to cover the conductor 114 and the conductor 115. The conductor 205 is provided over the insulator 204 so that at least part of the conductor 205 overlaps with at least part of the semiconductor 201. The conductor 205 functions as a gate electrode of the transistor 200.

The transistor 200 is covered with an insulator 206. A conductor 207, a conductor 208, and a conductor 209 are provided so as to be embedded in the insulator 206. The conductor 207 is electrically connected to the conductor 205, the conductor 208 is electrically connected to the conductor 202, and the conductor 209 is electrically connected to the conductor 203. A conductor 210 and a conductor 211 are provided over the insulator 206. The conductor 210 is electrically connected to the conductors 207 and 208, and the conductor 211 is electrically connected to the conductor 209. Further, an insulator 212 may be provided so as to cover the conductor 210 and the conductor 211.

That is, in this embodiment, the first gate of the transistor 100, the gate of the transistor 200, and one of the source and the drain of the transistor 200 are the conductor 116, the conductor 117, the conductor 202, the conductor 208, Electrical connection is made through the conductor 210, the conductor 207, and the like. In addition, the conductor 109, the conductor 114, the conductor 115, and the conductor 211 are electrically connected to the terminal 1001, the terminal 1002, the terminal 1003, and the terminal 1004, respectively.

By connecting the transistor 100 and the transistor 200 as illustrated in FIGS. 1A and 1B, the potential of the terminal 1004 can be applied to the conductor 101 and held. By applying a desired potential to the conductor 101 functioning as the first gate electrode, the threshold value of the transistor 100 is controlled, and the semiconductor device 1000 can have favorable characteristics. In particular, by using a transistor with higher carrier mobility or higher on-state current as the transistor 100, the semiconductor device 1000 can operate at high speed. Further, by using a transistor having a lower drain current when the gate voltage is 0 V as the transistor 200, the charge of the conductor 101 can be held for a long time with lower power consumption.

However, the connection relation between the transistor 100 and the transistor 200 is not limited to this embodiment mode. The connection relationship can be changed as appropriate according to the required circuit configuration.

<Configuration Example of Semiconductor Device 1000a>
2A is a cross-sectional view illustrating the semiconductor device 1000a, FIG. 2B is a circuit diagram illustrating the semiconductor device 1000a, and FIG. 2C is a circuit diagram illustrating an application example using the semiconductor device 1000a. is there. The semiconductor device 1000a includes the transistor 100, the transistor 200, and the capacitor 300. The transistor 100 and the transistor 200 have different structures. The transistor 200 and the capacitor 300 are provided over the insulator 110 provided so as to cover the transistor 100 and in the same layer.

In FIG. 2A, the transistor 100 and the transistor 200 which are described in the semiconductor device 1000 can be used as the transistor 100 and the transistor 200, and thus redundant description is omitted. The capacitor 300 includes a conductor 301, an insulator 204, and a conductor 303. The conductor 301 functions as a first electrode (lower electrode), and the conductor 303 functions as a second electrode (upper electrode). The insulator 204 functions as a dielectric.

The conductor 301 is made of the same material as the conductor 202 and the conductor 203 of the transistor 200 and is formed at the same time. The insulator 204 is formed of the same layer as the gate insulating film of the transistor 200. The conductor 303 is made of the same material as the conductor 205 of the transistor 200 and is formed at the same time. Further, a conductor 304 and a conductor 305 which are electrically connected to the conductor 303 may be provided. The conductor 304 is provided so as to be embedded in the insulator 206 provided so as to cover the transistor 200 and the capacitor 300. In addition, the conductor 305 is provided over the insulator 206.

The conductor 301 is electrically connected to one of a source and a drain of the transistor 100 through a conductor 112 provided so as to be embedded in the insulator 110.

In FIG. 2A, the first gate of the transistor 100, the gate of the transistor 200, and one of the source and the drain of the transistor 200 are the conductor 116, the conductor 117, the conductor 202, the conductor 208, the conductor It is electrically connected through the body 210, the conductor 207, and the like. The conductor 109 functioning as the second gate electrode of the transistor 100 is electrically connected to the terminal 1001, and one of the source and the drain of the transistor 100 is electrically connected to the first electrode of the capacitor 300. The other of the source and the drain of the transistor 100 is electrically connected to the terminal 1003, the other of the source and the drain of the transistor 200 is electrically connected to the terminal 1004, and the second electrode of the capacitor 300 is connected to the terminal 1005. And electrically connected.

By connecting the transistor 100, the transistor 200, and the capacitor 300 as illustrated in FIG. 2A, the semiconductor device 1000a can form a memory element (memory cell).

FIG. 2B is a circuit diagram illustrating FIG. 2A, in which the memory cell 1010 includes the transistor 100 and the capacitor 300, and the transistor 200 is connected to the first gate of the transistor 100. ing. A terminal 1001 illustrated in FIG. 2A is connected to the word line (WL) illustrated in FIG. 2B, and a terminal 1003 is connected to the bit line (BL). In addition, a ground potential or an arbitrary potential is applied to the terminal 1005.

When the transistor 100 is turned on by a WL signal, the potential of BL can be applied to the first electrode of the capacitor 300. After that, the transistor 100 is turned off by a WL signal, whereby charge can be held in the capacitor 300. Thereby, information can be written.

When reading information, the transistor 100 is turned on by a WL signal, and the charge amount held in the capacitor 300 is read by a reading circuit connected to BL.

By using a transistor with higher carrier mobility or higher on-state current as the transistor 100, writing of information to the memory cell 1010 and reading of information from the memory cell 1010 in the semiconductor device 1000a can be performed at higher speed. Further, when the transistor 200 is connected to the conductor 101 functioning as the first gate of the transistor 100, the threshold value of the transistor 100 is controlled, and thus the memory cell 1010 can hold information for a long time. That is, when the transistor 200 is turned on and the potential of the terminal 1004 is applied to the conductor 101, a negative charge can be given to the conductor 101, and the threshold value of the transistor 100 can be shifted to the plus side. By shifting the threshold value of the transistor 100 to the plus side, the drain current when the gate voltage of the transistor 100 is 0 V becomes lower, and thus the memory cell 1010 can hold information for a long time. In particular, by using a transistor with a lower drain current when the gate voltage is 0 V as the transistor 200, the charge given to the conductor 101 can be held for a long time with lower power consumption.

FIG. 2C is a circuit diagram illustrating an example of a memory cell array in which a plurality of memory cells 1010 are arranged in a matrix. Such a memory cell array can be used as a memory device or an integrated circuit including the memory device.

Note that FIG. 2C illustrates an example in which one transistor 200 is connected to all the memory cells in the memory cell array; however, this embodiment is not limited thereto. A transistor 200 may be provided for each row of the memory cell array as illustrated in FIG. Although not illustrated, the transistor 200 may be provided for each column of the memory cell array, or the memory cell array may be divided into a plurality of blocks and the transistor 200 may be provided for each block.

<Configuration Example of Semiconductor Device 1000b>
3A is a cross-sectional view illustrating the semiconductor device 1000b, FIG. 3B is a circuit diagram illustrating the semiconductor device 1000b, and FIG. 3C is a circuit diagram illustrating an application example using the semiconductor device 1000b. is there. The semiconductor device 1000b includes a transistor 100, a transistor 200, a capacitor 300, and a transistor 400. The transistor 100 and the transistor 200 have different structures. The transistor 100 is provided over the insulator 404 and the insulator 411 provided so as to cover the transistor 400, and the transistor 200 and the capacitor 300 are over the insulator 110 provided so as to cover the transistor 100. It is provided in the same layer.

In FIG. 3A, the transistor 100, the transistor 200, and the capacitor 300 described in the semiconductor device 1000 or the semiconductor device 1000a can be used as the transistor 100, the transistor 200, and the capacitor 300; To do. The transistor 400 includes a semiconductor 401, an insulator 402, and a conductor 403. The semiconductor 401 is formed over the semiconductor substrate 415 and is provided between a region 401a that functions as one of a source region and a drain region, a region 401b that functions as the other of a source region and a drain region, a region 401a, and a region 401b, and functions as a channel. An area 401c is provided. In the case where a plurality of semiconductors 401 are provided on the semiconductor substrate 415, an insulator 416 is provided between the semiconductors 401.

An insulator 402 is provided over the region 401c. The insulator 402 only needs to be provided over at least the region 401c, and may be provided so as to cover the entire semiconductor 401 or may be provided so as to cover the semiconductor substrate 415.

An insulator 404 is provided over the semiconductor substrate 415 so as to cover the transistor 400. A conductor 405, a conductor 406, and a conductor 407 are provided so as to be embedded in the insulator 404. The conductor 405 is electrically connected to the region 401a, the conductor 406 is electrically connected to the region 401b, and the conductor 407 is electrically connected to the conductor 403. A conductor 408, a conductor 409, and a conductor 410 are provided over the insulator 404. The conductor 408 is electrically connected to the conductor 405, the conductor 409 is electrically connected to the conductor 406, and the conductor 410 is electrically connected to the conductor 407.

An insulator 411 is provided over the insulator 404 so as to cover the conductor 408, the conductor 409, and the conductor 410. A conductor 412 is provided so as to be embedded in the insulator 411. The insulator 102, the transistor 100, the transistor 200, the capacitor 300, and the like are provided over the insulator 411. The insulator 102 is provided so that a conductor 413 is embedded therein. The conductor 413 is electrically connected to the conductor 412. A conductor 414 is provided so as to be embedded in the insulator 103 and the insulator 110. The conductor 414 is electrically connected to the conductor 413 and the conductor 301 functioning as the first electrode of the capacitor 300.

The conductor 408 is electrically connected to the terminal 1006, and the conductor 409 is electrically connected to the terminal 1007.

By connecting the transistor 100, the transistor 200, the capacitor 300, and the transistor 400 as illustrated in FIG. 3A, the semiconductor device 1000b can form a memory element (memory cell).

FIG. 3B is a circuit diagram illustrating FIG. 3A in which the memory cell 1020 includes the transistor 100, the capacitor 300, and the transistor 400, and the transistor 200 is connected to the first gate of the transistor 100. Shows the configuration. A terminal 1001 illustrated in FIG. 3A is connected to a write word line (WWL) illustrated in FIG. 3B, a terminal 1003 is connected to a bit line (BL), and a terminal 1005 is a read word line (RWL). The terminal 1006 is connected to the source line (SL), and the terminal 1007 is connected to the bit line (BL). Here, a portion where the gate of the transistor 400, one of the source electrode and the drain electrode of the transistor 100, and the first electrode of the capacitor 300 are electrically connected may be referred to as a node (FG).

Information writing by such a memory cell 1020 will be described. By setting the potential of the write word line WWL to a potential at which the transistor 100 is turned on and the transistor 100 is turned on, the potential of the bit line BL is supplied to the gate of the transistor 400 and the first electrode of the capacitor 300. . That is, predetermined charge is given to the gate of the transistor 400. Here, one of charges corresponding to two different potentials (hereinafter, a charge giving a low potential is called a charge Q _L and a charge giving a high potential is called a charge Q _H ) is selectively given to the gate of the transistor 400. Shall. Here, by associating one of Q _L and Q _H with data “1” and the other with data “0”, 1-bit information can be written in the memory cell. Note that by selecting the charge applied to the gate of the transistor 400 from among charges corresponding to three or more different potentials, multi-value (multiple bits) information is written per memory cell, and the memory of the semiconductor device 1000b is stored. The capacity may be improved.

After that, the potential of the write word line WWL is decreased to turn off the transistor 100, whereby the charge given to the gate of the transistor 400 and the first electrode of the capacitor 300 is held.

As described above, the transistor 400 is on, and the source or drain of the transistor 400 is set to a fixed potential of the source line SL. Therefore, the decrease in potential applied to the gate of the transistor 400 and the first electrode of the capacitor 300 can be suppressed without being affected by the decrease in potential of the write word line WWL when holding charge. is there.

Since the off-state current of the transistor 100 is extremely small, the charge of the gate of the transistor 400 is held for a long time.

Next, reading of information will be described. When an appropriate potential (read potential) is applied to the read word line RWL in a state where a predetermined potential (constant potential) is applied to the source line SL, the transistor 400 has a current corresponding to the amount of charge held in the gate of the transistor 400. The resistance of the source or drain is a different value. In general, when the transistor 400 is a p-channel transistor, the apparent threshold value V _thH of the transistor 400 when Q _H is _{supplied to} the gate of the transistor 400 is when Q _L is _{supplied to} the gate of the transistor 400 This is because the transistor 400 becomes lower than the apparent threshold value V _thL . Here, the apparent threshold value is a potential of the read word line RWL necessary for turning on the transistor 400. Therefore, by _setting the potential of the read word line RWL to the potential V0 between _VthH and _VthL , the charge given to the gate of the transistor 400 at the time of writing information can be determined. For example, in the case where Q _H is _supplied to the gate of the transistor 400 in writing, the transistor 400 is turned off when the potential of the read word line RWL becomes V0 (<V _thL ). On the other hand, when Q _L is applied to the gate of the transistor 400 in writing, the potential of the read word line RWL is V0 (> V _thH ), and the transistor 400 is turned on. In this manner, the held information can be read by detecting the resistance state of the transistor 400.

By using a transistor with higher carrier mobility or higher on-state current as the transistor 100, information can be written into and read from the memory cell 1020 in the semiconductor device 1000b at higher speed. Further, when the transistor 200 is connected to the conductor 101 functioning as the first gate of the transistor 100, the threshold value of the transistor 100 is controlled, and thus the memory cell 1020 can hold information for a long time. For example, by shifting the threshold value of the transistor 100 to the plus side, the drain current when the gate voltage of the transistor 100 is 0 V becomes lower, and the memory cell 1020 can hold information for a long time. In particular, by using a transistor with a lower drain current when the gate voltage is 0 V as the transistor 200, the charge given to the conductor 101 can be held for a long time with lower power consumption.

FIG. 3C is a circuit diagram illustrating an example of a memory cell array in which a plurality of memory cells 1020 are arranged in a matrix. Such a memory cell array can be used as a memory device or an integrated circuit including the memory device.

Note that FIG. 3C illustrates an example in which one transistor 200 is connected to all the memory cells in the memory cell array; however, this embodiment is not limited thereto. As shown in FIG. 3D, the transistor 200 may be provided for each row of the memory cell array. Although not illustrated, the transistor 200 may be provided for each column of the memory cell array, or the memory cell array may be divided into a plurality of blocks and the transistor 200 may be provided for each block.

<Structural Example of Transistor 100a>
FIG. 4 illustrates a structural example of a transistor applicable to the transistor 100. The transistor 100a includes a conductor 120, an insulator 123 over the conductor 120, an insulator 124 over the insulator 123, an insulator 125 over the insulator 124, an oxide 126 over the insulator 125, and an oxide. An oxide 127 on the object 126, a conductor 128a and a conductor 128b on the oxide 127, a barrier 129a on the conductor 128a, a barrier 129b on the conductor 128b, an oxide 127, a barrier 129a, and a barrier The oxide 130 over 129b, the insulator 131 over the oxide 130, the conductor 132 over the insulator 131, and the barrier 133 over the insulator 131 covering the conductor 132 are included.

The conductor 120 functions as a first gate electrode. The conductor 120 has a structure in which a plurality of conductors are stacked. In this embodiment, the conductor 120 includes a conductor 120a, a conductor 120b, and a conductor 120c. The conductor 120 is provided so as to be embedded in the insulator 121 and the insulator 122.

Here, the conductor 120a is preferably formed using a conductive material having a function of suppressing permeation of impurities such as water or hydrogen (impurity is difficult to permeate). For example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, and a single layer or a stacked layer may be used. Thus, impurities such as hydrogen and water from the lower layer than the insulator 121 can be prevented from diffusing into the upper layer through the conductor 120. Note that the conductor 120a includes an impurity such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO ₂ ), a copper atom, or oxygen (for example, an oxygen atom) , Oxygen molecules, etc.) are preferably difficult to permeate. The same applies to the case where a conductive material that does not easily transmit impurities is described below. When the conductor 120a has a function of suppressing the permeation of oxygen, the conductor 120b and the conductor 120c can be prevented from being oxidized to lower the conductivity.

The conductor 120b is preferably formed using a conductive material such as titanium or titanium nitride. The conductor 120c is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.

The insulator 121 can function as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 100a from below. The insulator 121 is preferably formed using an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen (impermeability of impurities), for example, aluminum oxide or the like. Thereby, impurities such as hydrogen and water can be prevented from diffusing into the upper layer than the insulator 121. Note that the insulator 121 is difficult to transmit at least one of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (N ₂ O, NO, NO _{2, and the} like) and a copper atom. Is preferred. The same applies to the case where an insulating material which does not easily transmit impurities is described below.

The insulator 121 is preferably formed using an insulating material which does not easily transmit oxygen (for example, oxygen atoms or oxygen molecules). Thus, downward diffusion of oxygen contained in the insulator 125 and the like can be suppressed.

The insulator 124 is preferably formed using an insulating material that does not easily transmit impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. Thus, impurities such as hydrogen and water from a lower layer than the insulator 124 can be prevented from diffusing from the insulator 124 to an upper layer. Further, downward diffusion of oxygen contained in the insulator 125 or the like can be suppressed.

In addition, the concentration of impurities such as water, hydrogen, or nitrogen oxide in the insulator 125 is preferably reduced. For example, the amount of hydrogen desorbed from the insulator 125 is determined by the temperature desorption gas analysis (TDS (Thermal Desorption Spectroscopy)) in the range of 50 ° C. to 500 ° C. It may be 2 × 10 ¹⁵ molecules / cm ² or less, preferably 1 × 10 ¹⁵ molecules / cm ² or less, more preferably 5 × 10 ¹⁴ molecules / cm ² or less in terms of the area of the body 125. The insulator 125 is preferably formed using an insulator from which oxygen is released by heating.

The insulator 123, the insulator 124, and the insulator 125 can function as a first gate insulating film, and the insulator 131 can function as a second gate insulating film. Note that although the transistor 100a illustrates a structure in which the insulator 123, the insulator 124, and the insulator 125 are stacked, the present invention is not limited thereto. For example, any two layers of the insulator 123, the insulator 124, and the insulator 125 may be stacked, or any one of the layers may be used.

As the oxide 126, the oxide 127, and the oxide 130, a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. As the metal oxide, it is preferable to use one having an energy gap of 2 eV or more, preferably 2.5 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.

Since a transistor including an oxide semiconductor has extremely low leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.

The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one kind or plural kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

Here, a case where the oxide semiconductor is an In-M-Zn oxide containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

Here, in the metal oxide used for the oxide 126, the atomic ratio of the element M in the constituent element is preferably larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 127. . In the metal oxide used for the oxide 126, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 127.

When a metal oxide that can be used for the oxide 126 is used as the oxide 130, the energy at the lower end of the conduction band of the oxide 130 is lower than that at the lower end of the conduction band of the oxide 127. It is preferable to be high. In other words, the electron affinity of the oxide 130 is preferably smaller than the electron affinity in a region where the energy at the lower end of the conduction band of the oxide 127 is low.

Here, in the oxide 126, the oxide 127, and the oxide 130, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to achieve this, the defect state density of the mixed layer formed at the interface between the oxide 126 and the oxide 127 and the interface between the oxide 127 and the oxide 130 is preferably lowered.

Specifically, the oxide 126 and the oxide 127 and the oxide 127 and the oxide 130 have a common element other than oxygen (main component), so that a mixed layer with a low density of defect states is formed. be able to. For example, in the case where the oxide 127 is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 126 and the oxide 130.

At this time, the main path of carriers is a narrow gap portion formed in the oxide 127. Since the defect level density at the interface between the oxide 126 and the oxide 127 and the interface between the oxide 127 and the oxide 130 can be reduced, the influence on carrier conduction due to interface scattering is small, and a high on-state current is obtained. can get.

Alternatively, a metal oxide that can be used for the oxide 127 can be used as the oxide 130.

For example, in the case where the oxide 126, the oxide 127, and the oxide 130 are all In—Ga—Zn oxide, the composition of In, Ga, and Zn contained in the oxide 126 is In: Ga: Zn = 1: 3: 4 or In: Ga: Zn = 1: 3: 2. Further, the composition of In, Ga, and Zn contained in the oxide 127 can be In: Ga: Zn = 4: 2: 3 or In: Ga: Zn = 1: 1: 1. The composition of In, Ga, and Zn contained in the oxide 130 is In: Ga: Zn = 1: 3: 2, In: Ga: Zn = 4: 2: 3, and In: Ga: Zn = 1: 1. 1 or In: Ga: Zn = 1: 3: 4.

The thickness of the oxide 126 can be 3 nm to 50 nm, preferably 3 nm to 20 nm, more preferably 3 nm to 10 nm. The thickness of the oxide 127 can be greater than or equal to 10 nm and less than or equal to 50 nm, preferably greater than or equal to 10 nm and less than or equal to 25 nm. The thickness of the oxide 130 can be 3 nm to 20 nm, preferably 3 nm to 10 nm.

The conductor 128a and the conductor 128b function as a source electrode or a drain electrode. As the conductor 128a and the conductor 128b, a conductive material mainly containing tungsten, titanium, tantalum, or the like is preferably used, and a conductive material such as tungsten, titanium nitride, or tantalum nitride is preferably used.

The barrier 129a and the barrier 129b are provided so as to cover the conductor 128a and the conductor 128b, respectively. The barrier 129a and the barrier 129b are preferably formed using an atomic layer deposition (ALD) method. Thus, the barrier 129a and the barrier 129b can be formed with a thickness of 1 nm to 20 nm, preferably 1 nm to 10 nm. Many precursors used in the ALD method contain impurities such as carbon. Therefore, the barrier 129a and the barrier 129b may contain impurities such as carbon. For example, even when the barrier 129a and the barrier 129b and the insulator 121 are formed using aluminum oxide, the barrier 129a and the barrier 129b may contain more impurities such as carbon than the insulator 121. Note that the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

The barrier 129a and the barrier 129b are preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, for example, aluminum oxide or hafnium oxide. Thereby, oxidation of the conductor 128a and the conductor 128b can be suppressed.

The insulator 131 is preferably disposed in contact with the upper surface of the oxide 130. The insulator 131 is preferably formed using an insulator from which oxygen is released by heating. By providing such an insulator 131 in contact with the upper surface of the oxide 130, oxygen can be effectively supplied to the oxide 127 through the oxide 130. Similarly to the insulator 125, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 131 be reduced. The thickness of the insulator 131 is 1 nm to 20 nm, preferably 1 nm to 5 nm.

The insulator 131 preferably contains oxygen. For example, in temperature-programmed desorption gas spectroscopy analysis (TDS analysis), the amount of desorbed oxygen molecules per area of the insulator 131 is in the range of a surface temperature of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. 1 × 10 ¹⁴ molecules / cm ² or more, preferably 2 × 10 ¹⁴ molecules / cm ² or more, more preferably 4 × 10 ¹⁴ molecules / cm ² or more.

The conductor 132 functions as a second gate electrode. The conductor 132 has a structure in which a plurality of conductors are stacked. In this embodiment, the conductor 132 includes a conductor 132a, a conductor 132b, and a conductor 132c. A conductive oxide is preferably used as the conductor 132a. For example, a metal oxide which can be used as the oxide 126, the oxide 127, or the oxide 130 can be used. In particular, among In—Ga—Zn-based oxides, the metal atomic ratio is high from [In]: [Ga]: [Zn] = 4: 2: 3 to 4.1, and the vicinity thereof. It is preferable to use those. By providing such a conductor 132a, permeation of oxygen to the conductor 132b can be suppressed and an increase in the electrical resistance value of the conductor 132b due to oxidation can be prevented.

Further, by forming such a conductive oxide by a sputtering method, oxygen can be added to the insulator 131 and oxygen can be supplied to the oxide 127. Accordingly, oxygen vacancies in the oxide 127 can be reduced.

As the conductor 132b, a conductor that can improve the conductivity of the conductor 132a by adding an impurity such as nitrogen to the conductor 132a may be used. For example, the conductor 132b is preferably formed using titanium nitride or the like. For the conductor 132c, a metal such as tungsten can be used, for example. A metal nitride such as titanium nitride can be used as the conductor 132b, and a metal such as tungsten can be stacked as the conductor 132c.

Here, the conductor 132 having the function of the second gate electrode is provided so as to cover the top surface and the side surface in the channel width direction of the oxide 127 with the insulator 131 and the oxide 130 interposed therebetween. Therefore, the upper surface of the oxide 127 and the side surface in the channel width direction can be electrically surrounded by the electric field of the conductor 132 functioning as the second gate electrode. A structure of a transistor that electrically surrounds a channel formation region by an electric field of the conductor 132 is referred to as a surrounded channel (s-channel) structure. Therefore, since a channel can be formed on the top surface of the oxide 127 and the side surface in the channel width direction, a large current can flow between the source and the drain, and a current during conduction (on-current) can be increased. In addition, since the upper surface of the oxide 127 and the side surface in the channel width direction are surrounded by the electric field of the conductor 132, leakage current (off-state current) at the time of non-conduction can be reduced.

The barrier 133 is provided so as to cover the conductor 132. The barrier 133 is preferably formed using an atomic layer deposition (ALD) method. Thus, the barrier 133 can be formed with a thickness of 1 nm to 20 nm, preferably 1 nm to 10 nm. Many precursors used in the ALD method contain impurities such as carbon. For this reason, the barrier 133 may contain impurities such as carbon. For example, even when the barrier 133 and the insulator 121 are formed using aluminum oxide, the barrier 133 may include more impurities such as carbon than the insulator 121. Note that the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

The barrier 133 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, for example, aluminum oxide or hafnium oxide. Thereby, oxygen in the insulator 131 can be prevented from diffusing outside. Further, oxidation of the conductor 132 can be suppressed.

An insulator 134 is preferably provided so as to cover the transistor 100a. The insulator 134 preferably has a reduced concentration of impurities such as water or hydrogen in the film, like the insulator 125 and the like.

Further, an insulator 135 is preferably provided over the insulator 134. The insulator 135 can function as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor or the like from an upper layer. As in the case of the insulator 121, the insulator 135 is preferably formed using an insulating material that does not easily transmit impurities such as water and hydrogen and oxygen, such as aluminum oxide.

Alternatively, an oxide insulator formed using an ALD method, which is similar to the barrier 129a, the barrier 129b, or the barrier 133, may be provided over or below the insulator 135.

<Structural Example of Transistor 200a>
FIG. 5A illustrates a structural example of the transistor 200a applicable to the transistor 200. The transistor 200a is provided over the insulator 221 over the insulator 135 that covers the transistor 100a. The transistor 200a covers the oxide 222 over the insulator 221, the conductors 223 and 224 provided so as to be electrically connected to the oxide 222, and the oxide 222, the conductor 223, and the conductor 224. Thus, the insulator 225, the insulator 226, and the conductor 227 over the insulator 226 are provided. The transistor 200a is covered with the insulator 228, the insulator 229, and the insulator 230.

As the oxide 222, a metal oxide that functions as an oxide semiconductor is preferably used, and a metal oxide that can be used as the oxide 126, the oxide 127, and the oxide 130 can be used. For example, the oxide 222 is formed from the same material as any one of the oxide 126, the oxide 127, and the oxide 130. In this case, the thickness of the oxide 222 may be adjusted as appropriate in accordance with characteristics required for the transistor 200a. The transistor 200 is required to have a lower drain current when the gate voltage is 0V. In the case where the oxide 127 in the transistor 100a is an oxide containing In, Ga, and Zn and the oxide 222 is an oxide containing In, Ga, and Zn, the ratio of In contained in the oxide 222 is included in the oxide 127. It is preferable that it is lower than the ratio of In. By using such an oxide for the transistor 100a and the transistor 200a, the transistor 100a is a transistor with higher carrier mobility or on-current, and the transistor 200a is a transistor with lower drain current when the gate voltage is 0V. be able to. Note that an oxide similar to that of the transistor 200a is preferably used for the transistor 200b described later. Further, the oxide 222 may be thicker than the oxide 130 in the transistor 100a.

For example, in the case where the oxide 222 is an In—Ga—Zn oxide, the composition of In, Ga, and Zn contained in the oxide 222 is In: Ga: Zn = 1: 3: 2, In: Ga: Zn = 4. : 2: 3, In: Ga: Zn = 1: 1: 1, or In: Ga: Zn = 1: 3: 4.

The thickness of the oxide 222 can be greater than or equal to 3 nm and less than or equal to 40 nm, preferably greater than or equal to 3 nm and less than or equal to 15 nm. Further, the thickness of the oxide 222 can be larger than the thickness of the oxide 130 of the transistor 100a. For example, when the thickness of the oxide 130 is 3 nm, the thickness of the oxide 222 may be 4 nm to 15 nm, for example, 5 nm. When the thickness of the oxide 130 is 5 nm, the thickness of the oxide 222 may be 6 nm to 15 nm, for example, 10 nm. The thickness of the oxide 222 may be determined in accordance with the electrical characteristics of the transistor 200a and the transistor 200b described later, that is, the electrical characteristics of the transistor 200 or the composition of the oxide 222. In order to reduce the drain current when the gate voltage applied to the transistor 200 is 0 V, the thickness of the oxide 222 may be reduced, and may be greater than or equal to 3 nm and less than 10 nm, preferably greater than or equal to 3 nm and less than or equal to 5 nm. On the other hand, depending on the material of the oxide 222, the drain current when the gate voltage applied to the transistor 200 is 0 V can be reduced even when the thickness of the oxide 222 is large. In this case, the thickness of the oxide 222 may be greater than or equal to 10 nm and less than or equal to 40 nm, preferably greater than or equal to 10 nm and less than or equal to 15 nm.

One of the conductor 223 and the conductor 224 functions as a source electrode, and the other of the conductor 223 and the conductor 224 functions as a drain electrode. For the conductors 223 and 224, a conductive material containing tungsten, titanium, tantalum, aluminum, or the like as a main component is preferably used, and a conductive material such as tungsten, titanium nitride, or tantalum nitride is preferably used.

The insulator 225 and the insulator 226 function as gate insulating films, and at least one of them is preferably provided with an insulator formed by an ALD method. As the insulator formed by the ALD method, for example, aluminum oxide or hafnium oxide is preferably used. For example, aluminum oxide formed by an ALD method may be used as the insulator 225, and silicon oxynitride, silicon oxide, or the like formed by a CVD method may be used as the insulator 226.

The conductor 227 functions as a gate electrode. For the conductor 227, a conductive material mainly containing tungsten, titanium, tantalum, aluminum, or the like is preferably used, and a conductive material such as tungsten, titanium nitride, or tantalum nitride is preferably used as a single layer or a stacked layer. .

The insulator 228 is preferably formed using the same material as the barrier 129a and the barrier 129b. As the insulator 228, aluminum oxide or hafnium oxide formed by an ALD method is preferably used.

For the insulator 229, an insulating material having a function equivalent to that of the insulator 121 or the insulator 135 is preferably used, and aluminum oxide or the like is preferably used. By stacking the insulator 228 and the insulator 229, impurities such as hydrogen and water can be prevented from entering the transistor 200 or the transistor 100, and oxygen and the like can be prevented from diffusing upward from the insulator 229. it can.

<Structural Example of Transistor 200b>
FIG. 5B illustrates an example of a different structure of a transistor that can be used as the transistor 200. The transistor 200b is different from the transistor 200a in the stacking order of the oxide 222, the conductor 223, and the conductor 224. The transistor 200b can be manufactured by forming the conductor 223 and the conductor 224 and then providing the oxide 222 so as to cover at least part of the conductor 223 and the conductor 224. For other components having the same reference numerals as those of the transistor 200a, the description of the transistor 200a may be referred to and detailed description thereof is omitted.

<Structural Example of Capacitance Element 300a>
FIG. 6A illustrates a structure example of a capacitor 300 a that can be used as the capacitor 300. Note that the capacitor 300 can be manufactured in the same layer as the transistor 200 by using some common components. For the common reference numerals, the description of the transistor 200a and the like may be referred to, and detailed description thereof is omitted. The capacitor 300a includes a conductor 310 over the insulator 221, an insulator 225 and an insulator 226 provided so as to cover the conductor 310, and a conductor 311 over the insulator 226. The capacitor 300a is covered with the insulator 228, the insulator 229, and the insulator 230.

The conductor 310 can be formed using the same material as the conductor 223, the conductor 224, and the like in the same step. The conductor 311 can be formed using the same material as the conductor 227 and the like in the same step.

The insulator 225 and the insulator 226 which are used as gate insulating films in the transistor 200a and the like function as dielectrics in the capacitor 300a. Here, the conductor 311 is provided so as to cover the side surface of the conductor 310 with the insulator 225 and the insulator 226 interposed therebetween. This is preferable because the capacitance value of the capacitor 300a increases by the area of the side surface of the conductor 310.

<Structural Example of Capacitance Element 300b>
FIG. 6B illustrates a different structure example of a capacitor that can be used for the capacitor 300. In the capacitor 300 b, the conductor 311 is provided so as to face only the upper surface of the conductor 310 without covering the side surface of the conductor 310. In the capacitor 300b, the capacitance value is determined according to the area of the lower surface of the conductor 311. For other components having the same reference numerals as those of the capacitor 300a, the description of the capacitor 300a may be referred to, and detailed description thereof is omitted.

<Structural Example of Transistor 400a>
FIG. 7A illustrates an example of a structure of a transistor that can be used as the transistor 400. The transistor 400a includes a conductor 422, an insulator 423, a semiconductor region 424 including a part of the substrate 421, a low resistance region 425a which functions as a source region or a drain region, and a low resistance region 425b. .

The transistor 400a may be either a p-channel type or an n-channel type.

A region where a channel of the semiconductor region 424 is formed, a region in the vicinity thereof, a low resistance region 425a which serves as a source region or a drain region, a low resistance region 425b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 400a may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

The low-resistance region 425a and the low-resistance region 425b provide an n-type conductivity element such as arsenic or phosphorus, or p-type conductivity such as boron, in addition to the semiconductor material used for the semiconductor region 424. Containing elements.

The conductor 422 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

Note that the threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.

An insulator 426, an insulator 427, and an insulator 428 are sequentially stacked to cover the transistor 400a.

Note that the transistor 400a illustrated in FIG. 7A is an example, and the present invention is not limited to this structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method. An insulator 429 may be provided on side surfaces of the conductor 422 and the insulator 423. With the insulator 429, the width of the low resistance region 425a and the low resistance region 425b which serve as a region where the channel of the semiconductor region 424 is formed, a region in the vicinity thereof, a source region or a drain region can be controlled. In the case where the plurality of transistors 400a are provided over the substrate 421, the insulator 430 is provided between the transistors 400a.

<Structural Example of Transistor 400b>
FIG. 7B illustrates an example of a different structure of a transistor that can be used as the transistor 400. In the transistor 400b, a semiconductor region 431 (a part of the substrate 421) where a channel is formed has a convex shape. Further, the conductor 433 is provided so as to cover the side surface and the upper surface of the semiconductor region 431 with an insulator 432 interposed therebetween. Note that the conductor 433 may be formed using a material that adjusts a work function. The insulator 432 and the conductor 433 are provided so as to be embedded in the insulator 434 provided over the semiconductor region 431, the low resistance region 425a, and the low resistance region 425b. Such a transistor 400b is also referred to as a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

<Structural Example of Semiconductor Device 1100a>
FIG. 8 is a schematic cross-sectional view of a semiconductor device 1100a according to one embodiment of the present invention. The semiconductor device 1100a uses the transistor 100a, the transistor 200a, the capacitor 300a, and the transistor 400a instead of the transistor 100, the transistor 200, the capacitor 300, and the transistor 400 of the semiconductor device 1000b described above. For each component, the above description may be referred to, and detailed description thereof is omitted.

A conductor 440 is connected to each of a source, a drain, and a gate of the transistor 400a. The conductor 440 is provided so as to be embedded in the insulator 426 and the insulator 427. Each conductor 440 has a stacked structure of a conductor 440a and a conductor 440b. The conductor 440a is preferably a single layer or a stacked layer formed using a conductive material such as titanium, titanium nitride, tantalum, or tantalum nitride. The conductor 440b is preferably formed using a conductive material such as tungsten.

An insulator 441 is provided over the insulator 428, and a conductor 442 is provided so as to be embedded in the insulator 428 and the insulator 441. The conductor 442 is electrically connected to the source, the drain, or the gate of the transistor 400a through the conductor 440. The conductor 442 has a stacked structure of a conductor 442a and a conductor 442b. For the conductor 442a, a single layer or a stack of conductive materials such as titanium, titanium nitride, tantalum, and tantalum nitride is preferably used. The conductor 442b is preferably formed using a conductive material such as copper, tungsten, or aluminum.

A wiring layer 448 is provided over the insulator 441 and the conductor 442. The wiring layer 448 is formed by stacking a plurality of layers including an insulator 443, an insulator 444, an insulator 445, and a conductor 446. In the present embodiment, the wiring layer 448 has four layers, but is not limited thereto. The wiring layer 448 may have three or less layers, or may have five or more layers.

The insulator 443 is preferably an insulator having a function of preventing diffusion of impurities such as hydrogen and water and metal components such as copper, and silicon nitride or silicon nitride oxide can be used. The insulator 444 and the insulator 445 are preferably formed using a low dielectric constant material in order to prevent parasitic capacitance between wirings or between conductors. As the insulator 444 and the insulator 445, silicon oxide, silicon oxynitride, silicon oxide containing carbon or hydrogen, or the like can be used.

The conductor 446 is provided to be embedded in the insulator 443, the insulator 444, and the insulator 445. The conductor 446 has a stacked structure of a conductor 446a and a conductor 446b. The conductor 446a is preferably a single layer or a stacked layer formed using a conductive material such as titanium, titanium nitride, tantalum, or tantalum nitride. The conductor 446b is preferably formed using a conductive material such as copper, tungsten, or aluminum.

An insulator 449 and an insulator 450 are provided over the wiring layer 448. A conductor 451 is provided so as to be embedded in the insulator 449, the insulator 450, the insulator 121, and the insulator 122.

The insulator 449 is preferably an insulator having a function of preventing diffusion of impurities such as hydrogen and water and a metal component such as copper, and silicon nitride or silicon nitride oxide can be used. The insulator 450 is preferably formed of a material having a low dielectric constant in order to prevent parasitic capacitance between wirings or between conductors. As the insulator 450, silicon oxide, silicon oxynitride, silicon oxide containing carbon or hydrogen, or the like can be used.

The conductor 451 has a stacked structure of a conductor 451a, a conductor 451b, and a conductor 451c, and includes a conductor 120a that functions as a first gate electrode of the transistor 100a, a conductor 120b, and a conductor 120c. 120 can be produced simultaneously.

Further, the transistor 100a is provided over the insulator 450. A transistor 200a and a capacitor 300a are provided over the transistor 100a. The transistor 200a and the capacitor 300a are formed over the insulator 221, that is, formed in the same layer.

A conductor 453 is provided so as to be embedded in the insulator 123, the insulator 124, the insulator 125, the insulator 134, the insulator 135, the insulator 221, and the like. The conductor 453 has a structure similar to that of the conductor 446 and the conductor 451.

One of a source and a drain of the transistor 200a is electrically connected to a conductor 452 formed to be embedded in the insulator 121 and the insulator 122 through the conductor 453. The conductor 452 is electrically connected to the conductor 120 functioning as the first gate of the transistor 100a. Alternatively, the conductor 452 is obtained by extending the conductor 120. In other words, the first gate of the transistor 100a is electrically connected to one of the source and the drain of the transistor 200a through the conductor 452 and the conductor 453.

In addition, one of the source and the drain of the transistor 100a is electrically connected to the first electrode of the capacitor 300a through the conductor 453. Further, the first electrode of the capacitor 300a is electrically connected to the gate of the transistor 400a through the conductor 453, the conductor 451, the wiring layer 448, the conductor 442, and the conductor 440. That is, one of the source and the drain of the transistor 100a, the first electrode of the capacitor 300a, and the gate of the transistor 400a are electrically connected to each other.

A conductor 456 is provided so as to be embedded in the insulator 225, the insulator 226, the insulator 228, the insulator 229, and the insulator 230. The conductor 456 is electrically connected to the source, drain, and gate of the transistor 200a, the second electrode of the capacitor 300a, the conductor 454 provided over the insulator 221, and the like.

A conductor 457 and a conductor 458 are provided over the insulator 230 and the conductor 456. The conductor 457 is electrically connected to the conductor 456 electrically connected to the gate of the transistor 200a and the conductor 456 electrically connected to one of the source and the drain. In other words, the gate of the transistor 200a and one of the source and the drain are electrically connected through the conductor 456 and the conductor 457, so-called diode connection. One of the gate, the source, and the drain of the diode-connected transistor 200a is electrically connected to the first gate of the transistor 100a.

An insulator 459 is provided over the insulator 230, the conductor 457, and the conductor 458. A conductor 460 is provided so as to be embedded in the insulator 459. The conductor 460 has a structure similar to that of the conductor 446 and the conductor 451. In addition, the conductor 460 is electrically connected to the conductor 458.

A conductor 461 is provided over the conductor 460. An insulator 462 is provided over the insulator 459 so as to cover part of the conductor 461. For the conductor 461, a conductive material containing titanium or aluminum as a main component can be used as a single layer or a stacked layer. For example, a stacked structure including three layers of titanium, aluminum, and titanium can be used. Further, titanium nitride may be used instead of titanium.

<About each component>
Below, each component used for the semiconductor device shown above is demonstrated.

<Board>
As the substrate for forming the semiconductor device, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

<Insulator>
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.

By surrounding the transistor with an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, electrical characteristics of the transistor can be stabilized. For example, as the insulator 121, the insulator 125, and the insulator 135, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used.

Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.

For example, the insulator 121, the insulator 125, and the insulator 135 include aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. Metal oxide, silicon nitride oxide, silicon nitride, or the like may be used. Note that the insulator 121, the insulator 125, and the insulator 135 preferably include aluminum oxide, hafnium oxide, or the like.

For the insulator 228 and the insulator 229, an insulator similar to the insulator 121, the insulator 125, and the insulator 135 can be used.

Examples of the insulator 122, the insulator 123, the insulator 125, and the insulator 131 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. For example, the insulator 122, the insulator 123, the insulator 125, and the insulator 131 preferably include silicon oxide, silicon oxynitride, or silicon nitride.

The insulator 123, the insulator 124, the insulator 125, and / or the insulator 131 preferably includes an insulator having a high relative dielectric constant. For example, the insulator 123, the insulator 124, the insulator 125, and / or the insulator 131 include gallium oxide, hafnium oxide, zirconium oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium, silicon, and silicon It is preferable to include an oxide containing hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium. Alternatively, the insulator 123, the insulator 124, the insulator 125, and / or the insulator 131 preferably has a stacked structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having high thermal stability and high relative dielectric constant can be obtained by combining with an insulator having high relative dielectric constant. For example, when the insulator 125 and the insulator 131 have a structure in which aluminum oxide, gallium oxide, or hafnium is in contact with the oxide 126, the oxide 127, or the oxide 130, silicon contained in silicon oxide or silicon oxynitride Can be prevented from being mixed into the oxide 126, the oxide 127, and the oxide 130. For example, in the insulator 125 and the insulator 131, silicon oxide or silicon oxynitride has a structure in contact with the oxide 126 and the oxide 127, or the oxide 130, whereby aluminum oxide, gallium oxide, or hafnium oxide; A trap center may be formed at the interface with silicon oxide or silicon oxynitride. In some cases, the trap center can change the threshold voltage of the transistor in the positive direction by capturing electrons.

For the insulator 225 and the insulator 226, an insulator similar to the insulator 122, the insulator 123, the insulator 125, and the insulator 131 can be used.

The insulator 122 and the insulator 134 preferably include an insulator with a low relative dielectric constant. For example, the insulator 122 and the insulator 134 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, It is preferable to have silicon oxide or resin having holes. Alternatively, the insulator 122 and the insulator 134 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or empty It is preferable to have a laminated structure of silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

The insulator 221, the insulator 230, the insulator 427, the insulator 441, the insulator 444, the insulator 445, the insulator 450, the insulator 459, and the insulator 462 also include the insulator 122 and the insulator 134. Similar insulators can be used.

As the barrier 129a, the barrier 129b, and the barrier 133, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used. The barrier 129a, the barrier 129b, and the barrier 133 can prevent excess oxygen in the insulator 134 from diffusing into the conductor 128a, the conductor 128b, the conductor 132b, and the conductor 132c.

Examples of the barrier 129a, the barrier 129b, and the barrier 133 include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitride Silicon oxide, silicon nitride, or the like may be used. Note that the barrier 129a, the barrier 129b, and the barrier 133 may include silicon nitride.

<Conductor>
The conductor 120a, conductor 120b, conductor 120c, conductor 132a, conductor 132b, conductor 132c, conductor 128a, and conductor 128b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel A material containing one or more metal elements selected from titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

In addition, a conductive material containing a metal element and oxygen contained in a metal oxide applicable to the oxide 126, the oxide 127, and the oxide 130 is used as the conductor, particularly the conductor 120a and the conductor 120b. Also good. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide 126, the oxide 127, and the oxide 130 can be captured in some cases. Alternatively, hydrogen mixed from an external insulator or the like may be captured.

A plurality of conductive layers formed using the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

Note that in the case where an oxide is used for a channel formation region of the transistor, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined as the gate electrode is preferably used. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.

In addition, the conductor 223, the conductor 224, the conductor 227, the conductor 310, the conductor 311, the conductor 440a, the conductor 440b, the conductor 442a, the conductor 442b, the conductor 446a, the conductor 446b, the conductor 451a, In the conductor 451b, the conductor 451c, the conductor 453a, the conductor 453b, the conductor 454, the conductor 456, the conductor 457, the conductor 458, the conductor 460, and the conductor 461, the conductor 120a, the conductor 120b, A conductor similar to the conductor 120c, the conductor 132a, the conductor 132b, the conductor 132c, the conductor 128a, and the conductor 128b can be used.

<Metal oxide applicable to oxide>
The oxide 126, the oxide 127, the oxide 130, and the oxide 222 according to the present invention are described below. As the oxide 126, the oxide 127, the oxide 130, and the oxide 222, a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.

The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one kind or plural kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

Here, a case where the oxide semiconductor is InMZnO containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

Here, a case where the metal oxide includes indium, the element M, and zinc is considered. Note that the terms of the atomic ratio of indium, element M, and zinc of the metal oxide are [In], [M], and [Zn].

A metal oxide that can be used for the oxide 126, the oxide 127, the oxide 130, and the oxide 222 is described below with reference to FIGS. 9A, 9B, and 9C. A preferable range of the atomic ratio of indium, element M, and zinc will be described. Note that the atomic ratio of oxygen is not described in FIGS. 9A, 9B, and 9C. The terms of the atomic ratio of indium, element M, and zinc of the metal oxide are [In], [M], and [Zn].

9A, 9B, and 9C, the broken line indicates the atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. Line that satisfies (−1 ≦ α ≦ 1), [In]: [M]: [Zn] = (1 + α) :( 1-α): line that has an atomic ratio of 2 [In]: [M] : [Zn] = (1 + α): (1-α): a line having an atomic ratio of 3; [In]: [M]: [Zn] = (1 + α): (1-α): number of atoms of 4 A line to be a ratio and a line to have an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1−α): 5.

The one-dot chain line is a line having an atomic ratio of [In]: [M]: [Zn] = 5: 1: β (β ≧ 0), and [In]: [M]: [Zn] = 2: A line with an atomic ratio of 1: β, [In]: [M]: [Zn] = 1: 1: a line with an atomic ratio of β, [In]: [M]: [Zn] = 1 2: Line with an atomic ratio of β, [In]: [M]: [Zn] = 1: 3: Line with an atomic ratio of β, and [In]: [M]: [Zn] = 1 : 4: represents a line having an atomic ratio of β.

Further, the atomic ratio of [In]: [M]: [Zn] = 0: 2: 1 shown in FIGS. 9 (A), 9 (B), and 9 (C), and the neighborhood values thereof. Metal oxides tend to have a spinel crystal structure.

In addition, a plurality of phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is a value close to [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel crystal structure and a layered crystal structure tend to coexist. Further, when the atomic ratio is a value close to [In]: [M]: [Zn] = 1: 0: 0, two phases of a bixbite type crystal structure and a layered crystal structure tend to coexist. When a plurality of phases coexist in a metal oxide, a crystal grain boundary may be formed between different crystal structures.

A region A illustrated in FIG. 9A illustrates an example of a preferable range of the atomic ratio of indium, element M, and zinc included in the metal oxide.

The metal oxide can increase the carrier mobility (electron mobility) of the metal oxide by increasing the indium content. Therefore, a metal oxide having a high indium content has higher carrier mobility than a metal oxide having a low indium content.

On the other hand, when the content of indium and zinc in the metal oxide is lowered, the carrier mobility is lowered. Therefore, when the atomic ratio is [In]: [M]: [Zn] = 0: 1: 0 and its vicinity (for example, the region C shown in FIG. 9C), the insulating property becomes high. .

For example, the metal oxide used for the oxide 127 preferably has a high carrier mobility and an atomic ratio represented by the region A in FIG. The metal oxide used for the oxide 127 may be, for example, In: Ga: Zn = 4: 2: 3 to 4.1 and its vicinity. On the other hand, the metal oxide used for the oxide 126 and the oxide 222 preferably has an atomic ratio represented by a region C in FIG. The metal oxide used for the oxide 126 and the oxide 222 may be, for example, about In: Ga: Zn = 1: 3: 4 or about In: Ga: Zn = 1: 3: 2. As the metal oxide used for the oxide 130, a metal oxide equivalent to the oxide 127 may be used, or a metal oxide equivalent to the oxide 222 may be used.

In particular, in the region B illustrated in FIG. 9B, an excellent metal oxide with high carrier mobility and high reliability can be obtained among the regions A.

Note that the region B includes [In]: [M]: [Zn] = 4: 2: 3 to 4.1 and the vicinity thereof. The neighborhood value includes, for example, [In]: [M]: [Zn] = 5: 3: 4. The region B includes [In]: [M]: [Zn] = 5: 1: 6 and its neighboring values, and [In]: [M]: [Zn] = 5: 1: 7, and Includes neighborhood values.

In the case where an In-M-Zn oxide is used as the metal oxide, a target including a polycrystalline In-M-Zn oxide is preferably used as the sputtering target. Note that the atomic ratio of the metal oxide film to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target. For example, when the composition of the sputtering target used for the metal oxide is In: Ga: Zn = 4: 2: 4.1 [atomic ratio], the composition of the metal oxide formed is In: Ga: Zn = It may be in the vicinity of 4: 2: 3 [atomic ratio]. In addition, when the composition of the sputtering target used for the metal oxide is In: Ga: Zn = 5: 1: 7 [atomic ratio], the composition of the metal oxide formed is In: Ga: Zn = 5: It may be in the vicinity of 1: 6 [atomic ratio].

Note that the properties of metal oxides are not uniquely determined by the atomic ratio. Even if the atomic ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. For example, when a metal oxide film is formed using a sputtering apparatus, a film having an atomic ratio that deviates from the atomic ratio of the target is formed. Further, depending on the substrate temperature during film formation, [Zn] of the film may be smaller than [Zn] of the target. Therefore, the illustrated region is a region that exhibits an atomic ratio in which the metal oxide tends to have specific characteristics, and the boundaries of the regions A to C are not strict.

<Composition of metal oxide>
A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

Note that in this specification and the like, they may be described as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

The CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and the whole material has a function as a semiconductor. Note that in the case where a CAC-OS or a CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is an electron serving as carriers. It is a function that does not flow. By performing the conductive function and the insulating function in a complementary manner, a switching function (function to turn on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

<Structure of metal oxide>
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. This is probably because of this.

The CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of an oxide semiconductor may be deteriorated due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

Oxide semiconductors have various structures and different properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

<Transistor with oxide>
Next, the case where the above oxide is used for a transistor will be described.

Note that when the above oxide is used for a transistor, carrier scattering and the like at crystal grain boundaries can be reduced; therefore, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

In addition, an oxide with low carrier density is preferably used for a channel formation region of the transistor. For example, the oxide has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / cm 3. ^It may be ³ or more.

Note that a high-purity intrinsic or substantially high-purity intrinsic oxide has few carrier generation sources, and thus can have a low carrier density. In addition, an oxide that is highly purified intrinsic or substantially highly purified intrinsic has a low defect level density and thus may have a low trap level density.

In addition, the charge trapped in the trap level of the oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide having a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the channel formation region. In order to reduce the impurity concentration in the oxide, it is preferable to reduce the impurity concentration in the film adjacent to the channel formation region. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

<Impurity>
Here, the influence of each impurity in the oxide will be described.

In the oxide, when silicon or carbon which is one of Group 14 elements is included, a defect level is formed in the oxide. Therefore, in a transistor using an oxide, the concentration of silicon or carbon in a channel formation region and the concentration of silicon or carbon in the vicinity of the interface with the channel formation region (secondary ion mass spectrometry (SIMS)) The concentration obtained by (1) is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed and carriers may be generated. Therefore, a transistor including an oxide containing an alkali metal or an alkaline earth metal in a channel formation region is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the channel formation region. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is included in the oxide, electrons as carriers are generated, the carrier density is increased, and the oxide is likely to be n-type. As a result, a transistor in which an oxide containing nitrogen in the channel formation region is used as a semiconductor is likely to be normally on. Therefore, in the oxide, it is preferable that the nitrogen in the channel formation region is reduced as much as possible. For example, the nitrogen concentration in the oxide is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × in SIMS. 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, hydrogen contained in the oxide reacts with oxygen bonded to a metal atom to become water, so that oxygen vacancies may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide containing hydrogen in a channel formation region is likely to be normally on. For this reason, it is preferable that hydrogen is reduced as much as possible in the channel formation region. Specifically, in the oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm ^3. Less than, more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using an oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electric characteristics can be imparted.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
<Method for Manufacturing Semiconductor Device>
Hereinafter, a method for manufacturing a semiconductor device including the transistor 100a illustrated in FIG. 4, the transistor 200a illustrated in FIG. 5A, and the capacitor 300a illustrated in FIG. 6A according to the present invention will be described with reference to FIGS. I will explain.

The conductor 120 and the conductor 451 are formed on the semiconductor substrate by a single damascene method or a dual damascene method. Note that although not illustrated, the transistor 400a illustrated in FIG. 7A or the transistor 400b illustrated in FIG. 7B is formed over the semiconductor substrate, and the transistor 400a or the transistor 400b is formed over the transistor 400a illustrated in FIG. A wiring layer 448 shown is formed. An insulator 449, an insulator 450, an insulator 121, and an insulator 122 are formed over the wiring layer 448, and the conductor 120 and the conductor 451 are formed to be embedded in the insulator (FIG. A)).

Over the insulator 122, the conductor 120, and the conductor 451, the insulator 123, the insulator 124, the insulator 125, the oxide 126A, the oxide 127A, the conductor 128A, and the barrier 129A are formed. In this embodiment, the thickness of the oxide 126A is 5 nm, and the thickness of the oxide 127A is 15 nm.

Next, the oxide 126A and the oxide 127A are processed into island shapes, so that the oxide 126 and the oxide 127 are formed (FIG. 10B). A resist mask, a hard mask made of a conductor, or an insulator can be used for processing the oxide 126A and the oxide 127A. Alternatively, part of the conductor 128A and the barrier 129A can be used as a hard mask. Although not shown, in this embodiment, the oxide 126A and the oxide 127A were processed using a hard mask made of tantalum nitride and part of the conductor 128A. Thereby, the insulator 125, the conductor 128B, and the barrier 129B are also formed.

Next, the conductor 128B and the barrier 129B are processed to form the conductor 128a, the conductor 128b, the barrier 129a, and the barrier 129b (FIG. 10C). After that, the oxide 130A, the insulator 131A, the conductor 132aA, the conductor 132bA, and the conductor are formed so as to cover the insulator 125, the oxide 126, the oxide 127, the conductor 128a, the conductor 128b, the barrier 129a, and the barrier 129b. A body 132cA is formed. In this embodiment, the thickness of the oxide 130A is 5 nm.

Next, the conductor 132aA, the conductor 132bA, and the conductor 132cA are processed to form the conductor 132a, the conductor 132b, and the conductor 132c (FIG. 11A). Thereafter, the barrier 133A is formed.

Next, the barrier 133A is processed to form the barrier 133 (FIG. 11B). At this time, the insulator 131A and the oxide 130A can be processed to form the insulator 131 and the oxide 130. In this embodiment, the barrier 133A is processed so that the end of the barrier 133 overlaps the barrier 129a and the barrier 129b, but the present invention is not limited to this. The barrier 133A may be processed such that the end of the barrier 133 is located outside the barrier 129a and the barrier 129b, that is, outside the oxide 126 and the oxide 127, or the barrier 133A may not be processed. Further, when the barrier 133A is processed, the insulator 131A and the oxide 130A are not necessarily processed. Through the above steps, the transistor 100a can be formed.

An insulator 134, an insulator 135, and an insulator 221 are formed so as to cover the transistor 100a (FIG. 12A).

Openings are provided in the insulator 123, the insulator 124, the insulator 125, the insulator 134, the insulator 135, the insulator 221, and the like (FIG. 12B). In FIG. 12B, at least the conductor 451, the conductor 452, and the opening reaching the conductor 128a and the conductor 128b functioning as the source electrode and the drain electrode of the transistor 100a are illustrated. Not exclusively. An opening reaching the gate of the transistor 100a or an opening reaching the conductor formed at the same time as the conductor 451 or the conductor 452 may be provided.

Next, a conductor 453aA and a conductor 453bA are formed so as to fill the opening (FIG. 13A). The conductors 453aA and 453bA are formed by a CVD method, an ALD method, a sputtering method, or the like. At this time, the conductor 453aA and the conductor 453bA are also formed over the insulator 221.

Next, the conductor 453aA and the conductor 453bA are processed to form the conductor 453a and the conductor 453b (FIG. 13B). Processing of the conductor 453aA and the conductor 453bA may be performed by removing unnecessary portions of the conductor 453aA and the conductor 453bA provided over the insulator 221 and the like, and chemical mechanical polishing (CMP). It is carried out by polishing using such as. Thereafter, an oxide 222A is formed. In this embodiment, the thickness of the oxide 222A is 5 nm. However, the thickness of the oxide 222A is not limited to this. As described above, the film thickness can be changed in accordance with the characteristics of the transistor 200 and the composition of the oxide 222A. For example, the oxide 130A can be made thicker or thinner.

Next, the oxide 222A is processed to form the oxide 222 (FIG. 14A). For the processing of the oxide 222A, wet etching or dry etching can be used. The etching method may be determined in consideration of the etching rate of the insulator 221 and the conductor 453 as well as the etching rate of the oxide 222A under the etching conditions of the oxide 222A. In the case where the oxide 222A is processed by wet etching, phosphoric acid, hydrofluoric acid, or oxalic acid can be used as an etchant. The etchant concentration and processing time may be determined in accordance with the thickness of the oxide 222A and the etching rate of the oxide 222A for each etchant. On the other hand, dry etching is suitable for fine processing, and dry etching is preferably used to form a fine pattern of, for example, 1 μm or less. Thereafter, a conductor 454A is formed.

Next, the conductor 454A is processed to form the conductor 223, the conductor 224, the conductor 310, and the conductor 454 (FIG. 14B). The conductors 223 and 224 are formed so as to be in contact with the oxide 222, and one of them functions as a source electrode of the transistor 200a and the other functions as a drain electrode. In addition, the conductor 310 functions as a first electrode of the capacitor 300a. After that, the insulator 225, the insulator 226, and the conductor 227A are formed so as to cover the insulator 221, the oxide 222, the conductor 223, the conductor 224, the conductor 310, and the conductor 454.

Next, the conductor 227A is processed to form the conductor 227 and the conductor 311 (FIG. 15A). The conductor 227 functions as a gate of the transistor 200a, and the conductor 311 functions as a second electrode of the capacitor 300a. As described above, the transistor 200a and the capacitor 300a can be formed over the insulator 221. An insulator 228, an insulator 229, and an insulator 230 are formed so as to cover the transistor 200a and the capacitor 300a.

The insulator 225, the insulator 226, the insulator 228, the insulator 229, the insulator 230, and the like are processed, and at least the conductor 223, the conductor 224, the conductor 454, the conductor 227, and the opening reaching the conductor 311 Part is formed (FIG. 15B).

Next, a conductor 456 is formed at least in the opening, and a conductor 457A is formed so as to cover the insulator 230 and the conductor 456 (FIG. 16A). After that, the conductor 457A is processed to form a conductor 457 that electrically connects the gate of the transistor 200a to one of the source and the drain and a conductor 458 that is electrically connected to the conductor 456 (FIG. 16). (B)).

In this embodiment, an example in which the transistor 200a is formed as the transistor 200 in FIG. 3A is described; however, the present invention is not limited to this. A transistor 200b illustrated in FIG. 5B may be formed instead of the transistor 200a. In the case of forming the transistor 200b, the conductor 454A is formed before the oxide 222A is formed, and the conductor 454A is processed to form the conductor 223, the conductor 224, the conductor 310, and the conductor 454. Then, the oxide 222A may be formed by forming and processing the oxide 222A.

Further, instead of the capacitor 300a, the capacitor 300b illustrated in FIG. 6B may be formed.

As described above, the transistor 100a, the transistor 200a over the insulator 221 that covers the transistor 100a, and the capacitor 300a can be formed.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

<Semiconductor wafer, chip>
FIG. 17A shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality of circuit regions 712 are provided on the substrate 711. The circuit region 712 can be provided with a semiconductor device according to one embodiment of the present invention.

Each of the plurality of circuit regions 712 is surrounded by the isolation region 713. A separation line (also referred to as “dicing line”) 714 is set at a position overlapping with the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711. FIG. 17B shows an enlarged view of the chip 715.

Further, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, ESD that may occur in the dicing process can be reduced, and a reduction in yield due to the dicing process can be prevented. In general, the dicing step is performed while supplying pure water having a specific resistance lowered by dissolving carbon dioxide gas or the like for the purpose of cooling the substrate, removing shavings, and preventing charging. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, the amount of pure water used can be reduced. Thus, the production cost of the semiconductor device can be reduced. In addition, productivity of the semiconductor device can be increased.

<Electronic parts>
An example of an electronic component using the chip 715 will be described with reference to FIGS. Note that the electronic component is also referred to as a semiconductor package or an IC package. Electronic parts have a plurality of standards, names, and the like depending on the terminal take-out direction, the terminal shape, and the like.

Electronic components are completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post-process).

The post-process will be described with reference to the flowchart shown in FIG. After the semiconductor device or the like according to one embodiment of the present invention is formed over the substrate 711 in the previous step, a “back surface grinding step” of grinding the back surface (the surface where the semiconductor device or the like is not formed) of the substrate 711 is performed (step S721). . By reducing the thickness of the substrate 711 by grinding, the electronic component can be downsized.

Next, a “dicing process” for separating the substrate 711 into a plurality of chips 715 is performed (step S722). Then, a “die bonding step” is performed in which the separated chip 715 is bonded onto each lead frame (step S723). For the bonding of the chip 715 and the lead frame in the die bonding step, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. Note that the chip 715 may be bonded on the interposer substrate instead of the lead frame.

Next, a “wire bonding process” is performed in which the lead of the lead frame and the electrode on the chip 715 are electrically connected with a thin metal wire (step S724). A silver wire, a gold wire, etc. can be used for a metal fine wire. For wire bonding, for example, ball bonding or wedge bonding can be used.

The chip 715 that has been wire bonded is subjected to a “sealing process (molding process)” that is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, the wire connecting the chip 715 and the lead can be protected from mechanical external force, and deterioration of characteristics due to moisture, dust, etc. (reliability Reduction) can be reduced.

Next, a “lead plating process” for plating the leads of the lead frame is performed (step S726). The plating process prevents rusting of the lead, and soldering when mounted on a printed circuit board later can be performed more reliably. Next, a “molding process” for cutting and molding the lead is performed (step S727).

Next, a “marking process” is performed in which a printing process (marking) is performed on the surface of the package (step S728). An electronic component is completed through an “inspection process” (step S729) for checking whether the external shape is good or not, and whether there is a malfunction.

FIG. 18B is a schematic perspective view of the completed electronic component. FIG. 18B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 750 illustrated in FIG. 18B includes a lead 755 and a chip 715. The electronic component 750 may have a plurality of chips 715.

An electronic component 750 illustrated in FIG. 18B is mounted on a printed circuit board 752, for example. A plurality of such electronic components 750 are combined and each is electrically connected on the printed circuit board 752 to complete a substrate (mounting substrate 754) on which the electronic components are mounted. The completed mounting board 754 is used for an electronic device or the like.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. FIG. 19 illustrates a specific example of an electronic device including the semiconductor device according to one embodiment of the present invention.

FIG. 19A is an external view illustrating an example of an automobile. The automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. The automobile 2980 includes an antenna, a battery, and the like.

An information terminal 2910 illustrated in FIG. 19B includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. In addition, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

A laptop personal computer 2920 illustrated in FIG. 19C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. The laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.

A video camera 2940 illustrated in FIG. 19D includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like. The operation switch 2944 and the lens 2945 are provided on the housing 2941, and the display portion 2944 is provided on the housing 2942. In addition, the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941. The housing 2941 and the housing 2942 are connected to each other by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.

FIG. 19E illustrates an example of a bangle information terminal. The information terminal 2950 includes a housing 2951, a display portion 2952, and the like. In addition, the information terminal 2950 includes an antenna, a battery, and the like inside the housing 2951. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.

FIG. 19F illustrates an example of a wristwatch type information terminal. The information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. The information terminal 2960 includes an antenna, a battery, and the like inside the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.

The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon 2967 displayed on the display unit 2962. The operation switch 2965 can have various functions such as time setting, power on / off operation, wireless communication on / off operation, manner mode execution and release, and power saving mode execution and release. . For example, the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.

In addition, the information terminal 2960 can execute short-range wireless communication that is a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. Further, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.

For example, a memory device including the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the above electronic devices for a long period. With the use of the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

100 transistor 100a transistor 101 conductor 102 insulator 103 insulator 104 semiconductor 105 conductor 106 conductor 108 insulator 109 conductor 110 insulator 112 conductor 113 conductor 114 conductor 115 conductor 116 conductor 117 conductor 120 conductor 120 Body 120a conductor 120b conductor 120c conductor 121 insulator 122 insulator 123 insulator 124 insulator 125 insulator 126 oxide 126A oxide 127 oxide 127A oxide 128a conductor 128A conductor 128b conductor 128B conductor 129a Barrier 129A barrier 129b barrier 129B barrier 130 oxide 130A oxide 131 insulator 131A insulator 132 conductor 132a conductor 132aA conductor 132b conductor 132bA conductor 132c conductor 32cA conductor 133 barrier 133A barrier 134 insulator 135 insulator 200 transistor 200a transistor 200b transistor 201 semiconductor 202 conductor 203 conductor 204 insulator 205 conductor 206 insulator 207 conductor 208 conductor 209 conductor 210 conductor 211 conductor Body 212 insulator 221 insulator 222 oxide 223 conductor 224 conductor 225 insulator 226 insulator 227 conductor 227A conductor 228 insulator 229 insulator 230 insulator 300 capacitor 300a capacitor 300b capacitor 301 conductor 303 Conductor 304 Conductor 305 Conductor 310 Conductor 311 Conductor 400 Transistor 400a Transistor 400b Transistor 401 Semiconductor 401a Region 401b Region 401c Region 402 Body 403 conductor 404 insulator 405 conductor 406 conductor 407 conductor 408 conductor 409 conductor 410 conductor 411 insulator 412 conductor 413 conductor 414 conductor 415 semiconductor substrate 416 insulator 421 substrate 422 conductor 423 insulation Body 424 semiconductor region 425a low resistance region 425b low resistance region 426 insulator 427 insulator 428 insulator 430 insulator 431 semiconductor region 432 insulator 433 conductor 434 insulator 440 conductor 440a conductor 440b conductor 441 insulator Body 442 conductor 442a conductor 442b conductor 443 insulator 444 insulator 445 insulator 446 conductor 446a conductor 446b conductor 448 wiring layer 449 insulator 450 insulator 451 conductor 451a conductor 451b conductor 451c conductor 4 2 Conductor 453 Conductor 453a Conductor 453aA Conductor 453b Conductor 453bA Conductor 454 Conductor 454A Conductor 456 Conductor 457 Conductor 457A Conductor 458 Conductor 459 Insulator 460 Conductor 461 Conductor 462 Insulator 711 Substrate 712 Circuit region 713 Separation region 714 Separation line 715 Chip 750 Electronic component 752 Printed circuit board 754 Mounting substrate 755 Lead 1000 Semiconductor device 1000a Semiconductor device 1000b Semiconductor device 1001 Terminal 1002 Terminal 1003 Terminal 1004 Terminal 1005 Terminal 1006 Terminal 1007 Terminal 1010 Memory cell 1020 Memory Cell 1100a Semiconductor device 2910 Information terminal 2911 Housing 2912 Display unit 2913 Camera 2914 Speaker unit 2915 Operation switch 2916 External connection unit 2 917 Microphone 2920 Notebook type personal computer 2921 Case 2922 Display unit 2923 Keyboard 2924 Pointing device 2940 Video camera 2941 Case 2492 Case 2944 Display unit 2944 Operation switch 2945 Lens 2946 Connection unit 2950 Information terminal 2951 Case 2951 Display unit 2960 Information terminal 2961 Housing 2962 Display unit 2963 Band 2964 Buckle 2965 Operation switch 2966 Input / output terminal 2967 Icon 2980 Car 2981 Car body 2982 Wheel 2983 Dashboard 2984 Light

Claims (5)

A first transistor;
An insulator covering the first transistor;
A second transistor on the insulator;
The first transistor includes:
A first gate electrode;
A second gate electrode overlapping the first gate electrode;
A semiconductor provided between the first gate electrode and the second gate electrode;
The semiconductor device is characterized in that the first gate electrode is electrically connected to one of a source and a drain of the second transistor and a third gate electrode included in the second transistor. In claim 1,
The semiconductor is a first semiconductor;
The second transistor is
A second semiconductor;
A first electrode and a second electrode electrically connected to the second semiconductor;
The semiconductor device is characterized in that the first gate electrode and one of a source and a drain of the second transistor are electrically connected to each other through one of the first electrode and the second electrode. In claim 2,
The insulator is a first insulator;
Having a capacitance on the first insulator;
The capacitor has a third electrode;
A fourth electrode;
A second insulator provided between the third electrode and the fourth electrode;
The third electrode is electrically connected to one of a source and a drain of the first transistor;
The third electrode is made of the same material as the first electrode and the second electrode,
The fourth electrode is made of the same material as the third gate electrode,
The semiconductor device is characterized in that the second insulator is made of the same material as a gate insulating film included in the second transistor. In claims 1 to 3,
The semiconductor device is characterized in that the carrier mobility of the first transistor is higher than the carrier mobility of the second transistor. In Claims 1 to 4,
The drain current of the second transistor when the gate voltage applied to the second transistor is 0V is the drain current of the first transistor when the gate voltage applied to the first transistor is 0V. A semiconductor device characterized by being smaller.

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