JP2018085003A - Data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve mutual notification of an interruption of DMA transfer with low latency.SOLUTION: A data processing device includes: a first system having a first control part, a first DMA control part, and a first external bus conversion part for converting an external bus and an internal bus; and a second system having a second control part, a second DMA control part, and a second external bus conversion part for converting the external bus and the internal bus. The first system and the second system are mutually connected by the external bus accessible to an address space on the internal bus, and the first system has a first address determination part for comparing the last address of data transferred by the second DMA control part notified from the second system via the external bus with an internal bus address outputted by the first external bus control part, and notifying the first control part of an interruption in accordance with the result.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a data processing apparatus.

  In recent years, as represented by big data processing, the need for integrated circuit systems for processing large amounts of data has increased. In order to process a large amount of data at high speed, it is essential that a plurality of integrated circuits each having a memory operate in cooperation. For this purpose, it is required to transmit / receive data separately possessed by a plurality of integrated circuits operating in cooperation with each other at high speed and with low latency. In an integrated circuit, a memory transfer control device called a DMA controller is generally used for data transfer. Japanese Patent Application Laid-Open No. 2004-228561 describes a method of performing DMA transfer using a DMA controller and notifying the CPU of the completion of the transfer as an interrupt.

  On the other hand, with the spread of technology in recent years, a bus that can access the address space of a general-purpose and connected device represented by PCI or PCI Express (hereinafter referred to as PCIe) for data transfer between a plurality of integrated circuits. It is being used.

JP 2004-287654 A

  As shown in Patent Document 1, an interrupt signal is generally used to notify the CPU of completion of DMA transfer. The CPU that has received the interrupt signal determines that all of the data from the DMA transfer is available, and performs processing on the data. However, in PCI, an interrupt signal can only be transmitted from a PCI device to the PCI host in a single direction. Similarly, in PCIe, an interrupt signal can be transmitted only in a single direction from End Point (hereinafter referred to as EP) to Root Complex (hereinafter referred to as RC).

  Therefore, there is a problem that the completion of DMA transfer by the RC or the host cannot be notified to the CPU of the integrated circuit connected as the EP or device.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide DMA transfer interrupts to each other and with low latency in a configuration in which a plurality of integrated circuits are connected by a bus that can access the device address space represented by PCI and PCIe. It is to provide a device that can be notified by.

  In order to achieve the above object, a data processing apparatus of the present invention includes a first control unit, a first DMA control unit, and a first external bus conversion unit that converts an external bus and an internal bus. And a second system having a second control unit, a second DMA control unit, and a second external bus conversion unit for converting an external bus and an internal bus, and the first system The system and the second system are connected to each other by an external bus accessible to the address space on the internal bus, and the first system is notified from the second system via the external bus. Compares the final address of the data transferred by the second DMA control unit with the internal bus address output by the first external bus control unit, and notifies the first control unit of an interrupt according to the result. A first address determination unit.

  According to the present invention, in a configuration in which a plurality of integrated circuits are connected by a bus that can access a device address space represented by PCI or PCIe, DMA transfer interrupts are notified to each other with low latency. It becomes possible to do.

It is a block diagram which shows the data processor in 1st Embodiment. It is a flowchart which shows a DMA transfer process. It is a figure which shows the content of DMA transfer setting. It is a flowchart which shows a last address detection process. It is a figure which shows the content of DMA transfer setting. It is a flowchart which shows a DMA transfer process. It is a block diagram which shows the data processor in 3rd Embodiment. It is a flowchart which shows a DMA transfer process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Example 1]
FIG. 1 is a block diagram showing a data processing apparatus according to the first embodiment of the present invention. In FIG. 1, reference numeral 1000 denotes a data processing device, and 1100 and 1200 denote integrated circuits. In FIG. 1, the control units 1101 and 1201 include programmable processors such as a CPU and an MPU, and a nonvolatile memory that stores a control program executed by the programmable processor, and controls the overall processing of the integrated circuits 1100 and 1200. The DMA control units 1102 and 1202 control so-called direct memory access.

  In the first embodiment of the present invention, DMA controllers 1102 and 1202 are used to transfer data between the integrated circuits 1100 and 1200. The DMA control units 1102 and 1202 are set by the control units 1101 and 1202 existing in the integrated circuits 1100 and 1200, and a start instruction is given. The memory control units 1103 and 1203 control the memory 1104 and 1204 to issue commands and refresh, and control access to the memories 1104 and 1204 of the operation units existing in the integrated circuits 1100 and 1200, respectively. .

  The PCIe control units 1110 and 1210 include serial / parallel conversion units 1111 and 1211, command analysis setting units 1112 and 1212, address conversion units 1113 and 1213, and setting notification register units 1114 and 1214, respectively.

  The serial / parallel converters 1111 and 1211 extract a clock signal from serial data transmitted on the PCIe bus 1300, convert the clock signal into parallel data, further perform 8b10b conversion and descrambling processing, and the result is a command analysis setting unit 1112. , 1212. In addition, the parallel data supplied from the command analysis setting units 1112 and 1212 is converted into serial data and transmitted onto the PCIe bus 1301.

  The command analysis setting units 1112 and 1212 analyze the packets supplied from the serial / parallel conversion units 1111 and 1211 and transfer the packet data to each unit according to the command. PCIe defines four types of commands: message transactions, configuration transactions, memory transactions, and I / O transactions. Among them, the memory transaction and the I / O transaction are converted into commands for the internal buses 1107 and 1207 by the command analysis setting units 1112 and 1212 and supplied to the address conversion units 1113 and 1213.

  The message transaction and the configuration transaction are transferred to the setting notification register units 1114 and 1214. The address conversion units 1113 and 1213 use the external bus based on the address of the internal bus command transmitted from the command analysis unit based on the BAR (Base Address Register) setting based on the PCIe standard and the offset address setting of each BAR space. Convert from address to internal bus address.

  Also, the address of the internal bus command supplied from the control units 1101 and 1201 to the PCIe control units 1110 and 1210 is converted into an external bus address based on the BAR setting. The setting notification register units 1114 and 1214 hold various settings related to the operation units of the PCIe control units 1110 and 1210. Further, notifications from the respective operation units of the PCIe control units 1110 and 1210 are held, and the contents thereof are referred to by the control units 1101 and 1201 and the like.

  The PCIe needs to select either Root Complex (hereinafter referred to as RC) or EndPoint (hereinafter referred to as EP) when performing a link-up operation. However, in the first embodiment of the present invention, the PCIe control units 1110 and 1210 are not limited to RC / EP. The PCIe control unit 1110 may be linked up as RC, and the PCIe control unit 1210 may be linked up as EP, or vice versa.

  The internal buses 1107 and 1207 are interconnects such as AXI and OCP. Each operation unit is set with an address. For example, access to an arbitrary address designated by the control units 1101 and 1201 is distributed to each operation unit. It also performs operations related to general bus control such as so-called arbitration.

  The access analysis units 1105 and 1205 analyze a command transmitted to the internal buses 1107 and 1207 by the PCIe control units 1110 and 1210 or received from the internal buses 1107 and 1207, and access to a preset monitoring target address is performed. Analyzes whether it occurred. If access has occurred as a result of the analysis, the interrupt generation units 1106 and 1206 are notified to generate interrupts for the control units 1101 and 1201.

  FIG. 2 is a flowchart showing a DMA transfer process in the first embodiment of the present invention. FIG. 2 shows a flow when the integrated circuit 1100 writes data to the integrated circuit 1200 by using DMA transfer. First, in step S <b> 201, the control unit 1101 performs settings related to DMA transfer to the DMA control unit 1102.

  FIG. 3 is a table showing the contents of the DMA transfer settings in the first embodiment of the present invention. In the first embodiment of the present invention, as shown in FIG. 3, the control unit 1101 sets four parameters: a PCIe bus address, an internal bus address, a transfer data size, and a transfer direction.

  Next, in FIG. 2, the control unit 1101 sends an instruction to start DMA transfer to the DMA control unit 1102 (S202). In general, step S202 is realized by the control unit 1101 writing a start instruction in the DMA start register of the DMA control unit 1102. Thereafter, the control unit 1101 waits until receiving a transfer completion notification from the DMA control unit 1102 (S203).

  In S203, the control unit 1101 is configured to receive a transfer completion notification as an interrupt, so that the control unit 1101 can perform processing other than the DMA transfer processing illustrated in FIG. Upon receiving the transfer completion notification from the DMA control unit 1102, the control unit 1101 ends the DMA transfer process.

  When receiving a start instruction from the control unit 1101, the DMA control unit 1102 first performs final address calculation processing (S211). In S211, the final external bus address is calculated from the following equation using the DMA transfer settings set in Step S101.

Final external bus address = external bus address + transfer data size-1
Next, the DMA control unit 1102 notifies the access analysis unit 1205 of the final external bus address via the PCIe bus 1300 (S212). Thereafter, the DMA control unit 1102 accesses the memory 1104 via the memory control unit 1103, acquires transfer data corresponding to the transfer data size from the internal bus address (S213), and passes through the PCIe control unit 1110 and the PCIe bus 1300. Then, data is transmitted to the integrated circuit 1200 (S214).

  Upon receiving the final external bus address transferred in step S212, the access analysis unit 1205 performs address conversion processing on the final external bus address, and calculates the final internal bus address (S221). This process is the same as the address conversion process performed by the address conversion unit 1213. By this conversion processing, the final external bus address notified via the PCIe bus 1300 is converted into the final internal bus address. Next, the access analysis unit 1205 sets the address converted in step S221 as a monitoring target address (S222).

  Next, the access analysis unit 1205 monitors the access from the PCIe control unit 1210 to the monitoring target address set in step S222 (S223). The specific processing content of S223 will be described later. Finally, in S234, the access analysis unit 1205 controls the interrupt generation unit 1206 to generate an interrupt, and generates an interrupt for the control unit 1202. The interrupt signal generated in S224 is notified to the control unit 1201, and the control unit 1201 performs DMA transfer end processing (S231), and this flow ends.

  FIG. 4 is a flowchart showing the final address detection process in the first embodiment of the present invention. First, the access analysis unit 1205 waits until an access from the PCIe control unit 1210 is received (S401). After detecting an access from the PCIe control unit 1210, the access analysis unit 1205 calculates the address range of the access received in S401 (S402). Specifically, the lower limit value and upper limit value of the address range in S402 are calculated from the following equations.

Lower address limit (when writing) = AWADDR
Address upper limit value (when writing) = AWADDR + AWLEN-1
Address lower limit (when reading) = ARADDR
Address upper limit value (when reading) = ARADDR + ARLEN-1

  Next, the access analysis unit 1205 determines whether or not the monitoring target address set in step S222 is included in the address range calculated in step S402 (S403). If the monitoring target address is not included in the address range, the process returns to step S401 and waits until the next access occurs. When the monitoring target is included in the address range, the access analysis unit 1205 waits until the final data is received (S404), and ends the flow after the reception is confirmed. The final data reception is determined by the following equation.

Final data reception determination (during writing) = WVALID && WREADY && WLAST
Final data reception determination (when reading) = RVALID && RREADY && RLAST

  As described above, according to the data processing apparatus of the first embodiment of the present invention, it is possible to generate an interrupt to the integrated circuits connected in the opposite direction without the intervention of the control unit when the DMA transfer is completed. It becomes. As a result, in a configuration in which a plurality of integrated circuits are connected to the PCIe bus, it is possible to notify the opposite device that data transfer has been completed at high speed, thereby enabling higher-speed data processing.

  In the first embodiment, an example of performing data transfer from the integrated circuit 1100 to the integrated circuit 1200 has been described. However, a similar procedure is used for data transfer from the integrated circuit 1200 to the integrated circuit 1100 to perform DMA transfer. The transfer completion can be notified. Therefore, the first embodiment does not depend on the setting of RC or EP of the PCIe control unit.

  In the first embodiment, the configuration in which the access analysis unit 1205 performs the address conversion process in step S221 has been described. However, by setting the address conversion unit 1213 so that the memory map of the PCIe bus and the memory map of the local bus are the same, the address conversion processing S221 is omitted, and the external bus address is set as the monitoring target address as it is. This is also included as a derivation of the first embodiment of the present invention.

  In the first embodiment, the example in which the final address calculation process and the final address notification process are performed by the DMA control unit 1102 has been described. However, the final address calculation process and the final address notification process may be performed by the control unit 1101. Included as a derivation of the first embodiment of the invention. In that case, the final address conversion process performed in step S221 may also be performed by the control unit 1101.

[Example 2]
In the first embodiment of the present invention, an example is shown in which the DMA control unit 1102 is controlled by a single DMA transfer. However, in the second embodiment, the DMA control unit 1102 continuously performs a plurality of DMA transfers. An example controlled by a so-called chain transfer operation will be described. In addition, the part which performs the same process as 1st Embodiment is shown with the same symbol, and description is abbreviate | omitted.

  FIG. 5 is a table showing the contents of the DMA transfer settings in the second embodiment of the present invention. In addition to the DMA setting contents (PCIe bus address, internal bus address, transfer data size, transfer direction) for the DMA control unit shown in FIG. 3, a pointer to the next DMA setting for the DMA control unit, Sets whether the setting contents exist. The DMA control unit analyzes the contents of this DMA setting, and if the next DMA setting exists, acquires the next DMA setting through the memory control unit.

  FIG. 6 is a flowchart showing a DMA transfer process in the second embodiment of the present invention. First, the control unit 1101 writes the DMA transfer setting shown in FIG. 5 in the memory 1104 (S601). Further, the control unit 1101 sets an address on the memory 1104 in which the first DMA transfer setting is stored among the DMA transfer settings written in step S601 to the DMA control unit 1102 (S602). Thereafter, a DMA transfer start instruction is issued to the DMA controller (S202).

  When receiving the DMA transfer start instruction from the control unit 1101, the DMA control unit 1102 acquires the DMA transfer setting from the memory 1104 from the address set in step S602 (S611). Next, the acquired DMA transfer setting is analyzed, and it is confirmed whether or not the acquired DMA transfer setting is the final DMA transfer setting (S612). If the acquired DMA transfer setting is not the final DMA transfer setting, the final address calculated from this DMA transfer setting is different from that generated at the completion of DMA, so the final address calculation process (S211) and the final address notification process Without proceeding to step S213.

  If the DMA transfer setting acquired in step S612 is the final DMA transfer setting, the final address must be set before sending / receiving the DMA data, so the access analysis unit 1205 calculates the final address. Notification is made (S211, S212). After transferring the DMA data (S213, S214), the DMA control unit 1102 confirms again whether or not the current DMA transfer setting is the final DMA transfer setting (S613). If it is not the final DMA transfer setting, the process returns to S611 to acquire the next DMA transfer setting. If it is the final DMA transfer setting, the DMA control unit 1102 ends the operation.

  As described above, according to the data processing device of the second exemplary embodiment of the present invention, even when the DMA transfer that operates as the chain transfer is used, an appropriate interrupt is given to the control unit connected to the opposite side. Can be generated. As a result, in a configuration in which a plurality of integrated circuits are connected to the PCIe bus, it is possible to notify the opposite device that data transfer has been completed at high speed, thereby enabling higher-speed data processing.

  In the second embodiment, an example of performing data transfer from the integrated circuit 1100 to the integrated circuit 1200 has been described. However, by taking the same procedure at the time of data transfer from the integrated circuit 1200 to the integrated circuit 1100, The completion of DMA transfer can be notified. Therefore, the second embodiment does not depend on the setting of RC or EP of the PCIe control unit.

  In the second embodiment, the configuration in which the access analysis unit 1205 performs the address conversion process in step S221 has been described. However, by setting the address conversion unit 1213 so that the memory map of the PCIe bus and the memory map of the local bus are the same, the address conversion processing S221 is omitted, and the external bus address is set as the monitoring target address as it is. This is also included as a derivation of the second embodiment of the present invention.

  In the second embodiment, the example in which the final address calculation process and the final address notification process are performed by the DMA control unit 1102 has been described. However, the final address calculation process and the final address notification process may be performed by the control unit 1101. Included as a derivation of the second embodiment of the invention. In that case, the final address conversion process performed in step S221 may also be performed by the control unit 1101.

[Example 3]
Next, as a third embodiment of the present invention, an example in a configuration using a PCI bus for an external bus will be described. In addition, the part which performs the same process as 1st Embodiment and 2nd Embodiment is shown with the same symbol, and description is abbreviate | omitted.

  FIG. 7 is a block diagram showing a data processing apparatus according to the third embodiment of the present invention. In the third embodiment, the integrated circuit 1100 and the integrated circuit 1200 are connected by a PCI bus 7300.

  The PCI control units 7110 and 7220 include command analysis setting units 7112 and 7212, address conversion units 7113 and 7213, and setting notification register units 7114 and 7214. The command analysis units 7112 and 7212 analyze the bus signal transmitted via the PCI bus 7300 and transfer the bus data to each unit according to the command. In PCI, three types of commands are defined: a configuration transaction, a memory transaction, and an I / O transaction.

  Among them, the memory transaction and the I / O transaction are converted into commands for the internal buses 7107 and 7207 by the command analysis setting units 7112 and 7212 and supplied to the address conversion units 7113 and 7213. The configuration transaction is transferred to setting notification register units 7114 and 7214.

  The address conversion units 7113 and 7213 use the BUS (Base Address Register) setting based on the PCI standard and the offset address setting of each BAR space to set the address of the internal bus command transmitted from the command analysis unit. Convert from address to internal bus address. Also, the address of the internal bus command supplied from the control units 1101 and 1201 to the PCI control units 7110 and 7210 is converted into an external bus address based on the BAR setting.

  The setting notification register units 7114 and 7214 hold various settings related to the operation units of the PCI control units 7110 and 7210. Further, notifications from the respective operation units of the PCI control units 7110 and 7210 are held, and the contents are referred to by the control units 1101 and 1201 and the like.

  FIG. 8 is a flowchart showing a DMA transfer process in the third embodiment of the present invention.

  When receiving a start instruction from the control unit 1101, the DMA control unit 1102 first performs final address calculation processing (S211). Next, the DMA control unit 1102 notifies the access analysis unit 1205 of the final external bus address via the PCI bus 7300 (S812). Thereafter, the DMA control unit 1102 accesses the memory 1104 via the memory control unit 1103, acquires transfer data corresponding to the transfer data size from the internal bus address (S213), and passes through the PCI control unit 7110 and the PCI bus 7300. Then, data is transmitted to the integrated circuit 1200 (S814).

  The PCI control unit is not changed in connection with the PCIe control unit and the internal bus. Therefore, it is possible to notify the DMA transfer interrupt using the PCI control unit in the same flow as that when using the PCIe control unit shown in FIG. 2 in most procedures.

  As described above, according to the data processing apparatus of the third embodiment of the present invention, it is possible to generate an interrupt to the integrated circuits connected in the opposite direction without the intervention of the control unit when the DMA transfer is completed. It becomes. As a result, in a configuration in which a plurality of integrated circuits are connected to the PCI bus, it is possible to notify the connected device that data transfer has been completed at high speed, thereby enabling faster data processing. .

  In the third embodiment, the example of performing data transfer from the integrated circuit 1100 to the integrated circuit 1200 has been described. However, by taking the same procedure for data transfer from the integrated circuit 1200 to the integrated circuit 1100, The completion of DMA transfer can be notified. Therefore, the third embodiment does not depend on the setting of the PCI device or host.

  In the third embodiment, the configuration in which the access analysis unit 1205 performs the address conversion process in step S221 has been described. However, by setting the address conversion unit 1213 so that the memory map of the PCI bus and the memory map of the local bus are the same, the address conversion processing S221 is omitted, and the external bus address is set as the monitoring target address as it is. This is also included as a derivation of the third embodiment of the present invention.

  In the third embodiment, an example in which the final address calculation process and the final address notification process are performed by the DMA control unit 1102 has been described. However, the final address calculation process and the final address notification process may be performed by the control unit 1101. Included as a derivation of the third embodiment of the invention. In that case, the final address conversion process performed in step S221 may also be performed by the control unit 1101.

1000 Data processing device 1100, 1200 Integrated circuit 1101, 1201 Control unit 1102, 1202 DMA control unit

Claims (8)

A first system having a first control unit, a first DMA control unit, and a first external bus conversion unit for converting an external bus and an internal bus;
A second system having a second control unit, a second DMA control unit, and a second external bus conversion unit for converting the external bus and the internal bus,
The first system and the second system are interconnected by an external bus accessible to an address space on the internal bus;
The first system includes a final address of data transferred by the second DMA controller notified from the second system via the external bus, and an internal output from the first external bus controller. A data processing apparatus comprising: a first address determination unit that compares a bus address and notifies an interrupt to the first control unit according to the result.   The first address determination unit monitors a write address to the internal bus output from the first external bus control unit, and notifies an interrupt when an access to the final address occurs. Item 4. The data processing device according to Item 1. The internal bus supports burst transfer,
The first address determination unit monitors the write address and burst length to the internal bus output from the first external bus control unit, and determines that access to the final address exists in burst transfer. The data processing apparatus according to claim 1.   2. The last address is notified to the first address determination unit by the second DMA control unit before starting the data transfer by the second DMA control unit. Data processing device.   2. The data according to claim 1, wherein the final address is notified to the first address determination unit by the second control unit before starting data transfer by the second DMA control unit. 3. Processing equipment. The second DMA control unit performs chain transfer using a descriptor,
The data processing apparatus according to claim 1, wherein the second DMA control unit generates the final address from last descriptor information.   The data processing apparatus according to claim 1, wherein the external bus is a bus that conforms to a PCI Express standard.   The data processing apparatus according to claim 1, wherein the external bus is a bus conforming to a PCI standard.