JP2007072685A - Data transfer device and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently transfer data without increasing a circuit scale when exchanging data between a host CPU connected to a host bus and a peripheral device connected to a slave bus. <P>SOLUTION: This data transfer device 200 includes: a bus bridge circuit 210 connected to the host bus and the slave bus; and a data transfer control circuit 220 controlling data transmission/reception between the host bus and the slave bus. The data transfer control circuit 220 includes: an address storage part 222; a buffer 230 storing the data received from the host bus or the slave bus; and circuits 226, 224, 240 or the like receiving the data from the slave bus through the bus bridge circuit when performing the transfer to a host from the peripheral device, storing the received data into the buffer, comparing whether a request address received from the host bus matches an address stored in the address storage part, and performing control such that the data stored in the buffer are outputted to the host bus through the bus bridge circuit when they match each other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer apparatus and an information processing apparatus.

  When data is exchanged between a host CPU connected to the host bus and a peripheral device connected to the slave bus, there is a means for the bus bridge to become a master to access the host bus in order to perform data transfer smoothly. .

As such means, for example, there is a case where a DMA controller is incorporated in a bus bridge, or a device connected to a slave bus becomes a bus master and accesses the host bus.
JP-A-1-205366

  However, if a DMA controller is provided in the bus bridge or if the master function of the host bus is included, the bus bridge has a relatively large number of gates, resulting in an increase in circuit scale.

  The present invention has been made in view of the above-described problems, and its object is to exchange data between a host CPU connected to a host bus and a peripheral device connected to a slave bus. An object of the present invention is to provide a data transfer apparatus and an information processing apparatus that can efficiently perform data transfer without causing an increase in circuit scale.

(1) The present invention
A data transfer device connected to a host bus to which a host and a DMA controller are connected and a slave bus to which a peripheral device is connected, and transfers data between the host bus and the slave bus,
A bus bridge circuit connected to the host bus and the slave bus, for transmitting and receiving data between the host bus and the slave bus;
A data transfer control circuit for controlling data transmission / reception between the host bus and the slave bus,
The data transfer control circuit includes:
In the case of transfer from the peripheral device to the host, the address of the transfer source is stored; in the case of transfer from the host bus to the slave bus, an address storage unit in which the address of the transfer destination is stored;
A buffer for storing data received from a host bus or a slave bus via the bus bridge circuit;
When transferring data from the peripheral device to the host, it receives data from the slave bus via the bus bridge circuit, stores the received data in the buffer,
The request address received from the host bus is compared with the address stored in the address storage unit. If they match, the data stored in the buffer is passed through the bus bridge circuit. And a circuit for controlling to output to the host bus.

  According to the present invention, the bus bridge is provided with an address register, a data number register, an address comparison circuit, a buffer and an interrupt generation function in accordance with the bus capability, but the number of gates is smaller than that of the DMA controller / bus master function. Expect equivalent data transfer capability. In addition, by using the DMA controller in conjunction with the channel priority setting, it is possible to match the transfer capability of devices with various performances, so that the host bus performance is not impaired.

  According to the present invention, it is possible to transfer data efficiently between the host bus and the slave bus without significantly increasing the function of the bus bridge.

  Therefore, when data is exchanged between a host CPU connected to a host bus and a peripheral device connected to a slave bus, a data transfer device capable of efficiently transferring data without increasing the circuit scale is provided. be able to.

(2) The data transfer apparatus of the present invention
The data transfer control circuit is
When transferring from the host to the peripheral device, data from the host bus is received via the bus bridge circuit and stored in the buffer, and the data stored in the buffer is transferred to the slave bus via the bus bridge circuit. A circuit for controlling to output is included.

(3) The data transfer device of the present invention
The data transfer control circuit is
Including a transfer data number storage for specifying the number of transfer data;
When transferring data from the peripheral device to the host, data from the slave bus is received via the bus bridge circuit until the transfer data number stored in the transfer data number storage unit is reached, and the received data is stored in the buffer. And
The request address received from the host bus is compared with the address stored in the address storage unit, and if it matches, the transfer data number stored in the transfer data number storage unit is It includes a circuit that controls to output data stored in the buffer until it reaches the host bus via the bus bridge circuit.

(4) The data transfer device of the present invention
The data transfer control circuit is
When transferring data from the host to the peripheral device, data from the host bus is received via the bus bridge circuit until the number of transfer data stored in the transfer data number storage unit is reached, and stored in the buffer. The circuit includes a circuit that outputs data stored in the buffer to the slave bus via the bus bridge circuit until the number of transfer data stored in the number storage unit is reached.

(5) The data transfer device of the present invention
The data transfer control circuit is
In the case of transfer from the peripheral device to the host, the transfer source address stored in the address storage unit is updated in response to reading from the host bus, and the updated address and the request address received from the host bus match. It is characterized in that it includes a circuit for controlling to output the data stored in the buffer to the host bus when the match is indicated.

  According to the present invention, the transfer source address stored in the address storage unit is updated in response to reading from the host bus, and a comparison is made as to whether the updated address matches the request address received from the host bus. If the match is indicated, the data stored in the buffer is output to the host bus. Therefore, the data transfer should be performed without confusion between the request from the DMA and the access to the other slave bus. Can do.

(6) The present invention
A data transfer device according to any of the above;
A host bus connected to the data transfer device;
A slave bus connected to the data transfer device;
A CPU connected to the host bus;
A DMA controller connected to the host bus;
An information processing device including a peripheral device connected to a slave bus,
The CPU
When receiving data from the peripheral device, set the transfer source address, the transfer destination address, the number of data transfers to the DMA controller, set the transfer enable,
Set the transfer source address in the address storage part of the data transfer device, set the transfer data number in the transfer data number storage part,
When the transfer enable setting is made, the DMA controller starts the DMA, and transfers the data stored in the buffer of the data transfer device through the host bus based on the set transfer source address, transfer destination address, and data transfer number. It is characterized by DMA transfer.

(7) The information processing apparatus of the present invention
The CPU is
When transmitting data from the host to the peripheral device, set the transfer enable to the DMA controller by setting the transfer source address, the transfer destination address, the number of data transfers,
Set the transfer destination address in the address storage part of the data transfer device, set the transfer data number in the transfer data number storage part,
When the DMA controller is set to enable transfer, it activates DMA,
DMA transfer data to the buffer of the data transfer device via the host bus based on the set transfer source address, transfer destination address, data transfer number,
When transmission of data to the data transfer apparatus is completed, the host bus is released.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram for explaining a data transfer apparatus according to the present embodiment. Note that the information processing apparatus 200 of the present embodiment does not have to include all the components (respective parts) in FIG. 1 and may have a configuration in which some of them are omitted.

  The data transfer apparatus 200 of this embodiment is a data transfer apparatus that is connected to a host bus to which a host and a DMA controller are connected and a slave bus to which peripheral devices are connected, and transfers data between the host bus and the slave bus. A bus bridge circuit 210 and a data transfer control circuit 220.

  The bus bridge circuit 210 is connected to the host bus and the slave bus, and transmits and receives data between the host bus and the slave bus, and includes a host bus interface 212, a host bus-slave bus conversion unit 214, and a slave bus interface 216. .

  The host bus-slave bus conversion unit 214 converts access from the host into slave access.

  The automatic transfer control unit 220 includes a start address storage register 222, a data buffer 230, a data buffer control unit 232, a transfer data number storage register 224, an address comparator 226, a transfer control unit 240, a slave bus data transfer counter 242, and host bus data. It includes a transfer counter 244 and functions as a data transfer control circuit that controls data transmission / reception between the host bus and the slave bus.

  The start address storage register 222 stores a start address when performing automatic transfer from the slave. In the case of transfer from the peripheral device to the host, the transfer source address is stored, and from the host bus to the slave bus. In the case of this transfer, it functions as an address storage unit for storing the transfer destination address.

  The data buffer 230 stores data at the time of automatic transfer, and functions as a buffer for storing data received from the host bus or slave bus via the bus bridge circuit 210.

  The data buffer control unit 232 controls the buffer in synchronization with the operations of the host bus and slave bus.

  The transfer data number storage register 224 is set with a data transfer number using a buffer, and functions as a transfer data number storage unit for specifying the transfer data number.

  The address comparator 226 compares the start address storage register with the address received from the host bus, and generates an access generation signal from the host bus.

  The transfer control unit 240 monitors data transfer from the bus access signal from the peripheral and the host bus access, and generates a control signal for buffer control.

  The slave bus data transfer counter 242 counts the number of slave bus automatic transfers.

  The host bus data transfer counter 244 counts the number of host bus automatic transfers.

  When the transfer from the peripheral device to the host is performed (when a transfer request from the slave bus to the host bus is received), the automatic transfer control unit 220 performs the bus until the transfer data number stored in the transfer data number storage unit is reached. Receives data from the slave bus via the bridge circuit, stores the received data in a buffer, and compares whether the request address received from the host bus matches the address stored in the address storage unit If the data indicates a match, the data is controlled so that the data stored in the buffer is output to the host bus via the bus bridge circuit until the transfer data number stored in the transfer data number storage unit is reached. Functions as a transfer control circuit.

  When transferring data from the host to the peripheral device, the automatic transfer control unit 220 receives data from the host bus via the bus bridge circuit until the transfer data number stored in the transfer data number storage unit is reached. As the data transfer control circuit for controlling the data stored in the buffer to be output to the slave bus via the bus bridge circuit until the number of transfer data stored in the transfer data number storage unit is reached. It may be configured to function.

  Further, in the case of transfer from the peripheral device to the host, the automatic transfer control unit 220 updates the transfer source address stored in the address storage unit in response to reading from the host bus, and from the updated address and the host bus. The received request address is compared with the received request address, and if it matches, it functions as a data transfer control circuit that controls to output the data stored in the buffer to the host bus. You may comprise.

  1 is a host bus address signal, 2 is a host bus data signal, 3 is a slave bus address signal, 4 is a slave bus data signal, 5 is a bus bridge internal data bus, and 7 is a transfer start 8 is a peripheral device transfer enable signal, 9 is an address comparison result, 10 is a transfer number output, 11 is a host bus data transfer counter control signal, and 12 is a host bus data transfer count value. 13 is a slave bus data transfer counter control signal, 14 is a slave bus data transfer counter value output, 15 is a comparison enable signal, 16 is a peripheral device data transfer request, and 17 is a buffer write. Pointer value, 18 is a buffer read pointer value, and 19 is a buffer write timing signal. It is.

  An address increment mode signal 20 designates an address increment mode and a fixed mode by a register in the bridge unit.

  A bus access signal 21 indicates that a host / slave bus access is occurring.

  A bus access request signal 22 outputs a bus transfer request from the peripheral. As a result, the bus bridge automatically starts accessing the peripheral.

  23 is a host bus command signal, 24 is a slave bus command signal, 25 is a slave bus access timing signal, and 26 is a host bus access timing signal.

  FIG. 2 is a diagram for explaining the information processing apparatus according to the present embodiment. Note that the information processing apparatus 100 of the present embodiment does not have to include all of the components (each unit) in FIG. 2 and may have a configuration in which some of them are omitted.

  The information processing apparatus 200 according to the present embodiment is connected to the data transfer apparatus 200, the host bus 110 connected to the data transfer apparatus 200, the slave bus 2 connected to the data transfer apparatus 200, and the host bus 110. CPU 120, DMA controller 130 connected to host bus 110, memory 140 connected to host bus 110, interrupt controller 160 connected to host bus 110, system control unit 150 connected to host bus 110, Peripheral devices 180-1 (peripheral devices using the function of the data transfer device) and 180-2 (normal peripheral devices not using the function of the data transfer device) connected to the slave bus 170 are included.

  3 is a transfer start signal, 4 is a data transfer request, 5 is an input / output signal of the peripheral device 1, 6 is an input / output signal of the peripheral device 2, and 7 is an interrupt generation report signal from the interrupt controller. 8 is an interrupt signal indicating the end of transfer.

  The data transfer device 200 is connected to a host bus 110 to which a host (CPU) 120 and a DMA controller 130 are connected, and to a slave bus 170 to which peripheral devices 180-1 and 180-2 are connected. A data transfer device that transfers data between the terminals, and has the configuration and functions described with reference to FIG.

  Here, when receiving data from the peripheral devices 180-1 and 180-2, the CPU 120 sets a transfer source address, a transfer destination address, and the number of data transfers to the DMA controller, and sets transfer enable. The transfer source address may be set in the address storage unit of the data transfer apparatus 200, and the transfer data number may be set in the transfer data number storage unit.

  When the transfer enable setting is made, the DMA controller 130 activates the DMA, and transfers the data stored in the buffer of the data transfer device 200 based on the set transfer source address, transfer destination address, and data transfer number to the host bus. DMA transfer may be performed via the network 110.

  Further, when transmitting data to the peripheral devices 180-1 and 180-2, the CPU 120 sets the transfer enable to the DMA controller 130 by setting the transfer source address, the transfer destination address, and the number of data transfers. The transfer destination address may be set in the address storage unit of the data transfer apparatus 200, and the transfer data number may be set in the transfer data number storage unit.

  When the transfer enable setting is made, the DMA controller 130 activates the DMA, and the data is transferred to the buffer of the data transfer apparatus 200 via the host bus 110 based on the set transfer source address, transfer destination address, and data transfer number. When the DMA transfer is performed and the transmission of data to the data transfer apparatus 200 is completed, the host bus may be released.

  In this embodiment, the information processing apparatus 100 has two buses (host bus 110 / slave bus 170), and is connected to the data transfer apparatus 200, which is a bus bridge connecting the two buses 1 and 2, and the bus 1 on the master side. The DMA controller 130 can be linked to perform efficient data transfer between the two buses.

  Regarding the transfer from the slave (peripheral device) to the master (host), the CPU (host) 120 transfers the transfer source to the start address storage register (address storage unit) inside the data transfer device 200 in preparation for a data transfer request on the slave side. The number of data to be transferred is stored in the transfer data number storage register (transfer data number storage unit), and the DMA controller 130 stores the same address (transfer source address), the number of data to be transferred, the data transfer destination address, and the host. A bus priority may be set.

  The transfer request from the peripheral device on the slave bus 170 having the above settings becomes an input to the data transfer device 200, and the data transfer device 200 activates the DMA controller 130, and the data transfer device 200 receives the data from the DMA controller 130. Regardless of the request, the data from the peripheral device 180-1 is read and stored in the buffer in the data transfer device 200.

  The activated DMA controller 130 accesses the data transfer apparatus 200, and the data transfer apparatus 200 determines that it matches the set start address. If they match, the data transfer apparatus 200 and the DMA controller 130 work together. Thus, it is determined that the data transfer process has started, and the data in the buffer is transmitted to the DMA controller 130. Data transfer device 200 reads data from the peripheral device until transfer of the set number of transfer data is completed.

  When the transfer of all data is completed, the CPU 120 determines from the two end signals of the end interrupt from the data transfer device 200 and the end interrupt from the DMA controller 130 that the target data transfer has ended.

  For transmission from the CPU 120 to the peripheral device 180-1, a transfer source address, a transfer destination device address, the number of transfer data, and a bus priority are set in the DMA controller 130, and a transfer destination address is set in the data transfer device 200. When the CPU 120 activates the DMA controller 130, the DMA transfer starts. When the data transfer device 200 detects that the address matches the set address, the data is temporarily stored in the buffer and the operation of the host bus 110 is terminated. The transfer device 200 transmits the buffer data to the transfer destination. The data transfer device 200 interrupts the CPU 120 when all the data has been transferred. The CPU may determine that the data transfer is complete from two end interrupts from the DMA controller and the data transfer apparatus 200.

  3 and 4 are flowcharts of the operation (data receiving operation from the peripheral device) at the time of transfer from the slave to the master.

  Here, it is assumed that the received data of the peripheral device 1 is stored in a predetermined area of the memory (140 in FIG. 2) by the DMA controller (130 in FIG. 2). Assume that the peripheral device (180-1 in FIG. 2) receives data packetized at regular intervals. The reception of packetized data is assumed to occur at certain intervals.

  The DMA controller has an on-demand channel, and in this example, this channel is used.

  First, the CPU (120 in FIG. 2) performs settings for the next reception operation in preparation for data reception from the peripheral device 1 (180-1 in FIG. 2) (step S1).

  (1) A transfer source address (received data register of peripheral device 1), a transfer destination address (data area of memory) and the number of data transfers are set in the DMA controller.

  (2) The transfer source address is set in the start address storage register of the data transfer device, and the data transfer number is set in the transfer data number storage register. Since writing has occurred in the start address storage register, both transfer counters (242 and 244 in FIG. 1) are reset to zero.

  (3) The CPU sets transfer enable to the DMA controller.

  Next, when the peripheral device 1 receives the data, it turns on the data transfer request signal (step S2).

  Next, the transfer control unit (240 in FIG. 1) outputs a bus access request signal (22 in FIG. 1) to the host bus-slave bus conversion unit (214 in FIG. 1). The bus access request signal (22 in FIG. 1) turns on when the peripheral device data transfer request signal (16 in FIG. 1) is on under the condition of host bus data transfer counter value <transfer data number storage counter value (16 in FIG. 1). Step S2).

  Next, the host bus-slave bus conversion unit executes a read cycle of the slave bus using the start address storage register as an address (step S4).

  Next, when the slave bus access is executed, the slave bus access signal (25 in FIG. 1) is turned on at the data read timing, and the timing is determined by the data buffer control unit (232 in FIG. 1) and the transfer control unit (in FIG. 1). 240) (step S5).

  Next, data is written to the buffer and the buffer write pointer is incremented. The transfer control unit increments the slave bus data transfer counter, turns on the transfer start signal (7 in FIG. 1), and makes a transfer request to the DMA controller. The transfer start signal (7 in FIG. 1) is turned on when host bus data transfer counter value <transfer data number storage counter value is satisfied (step S6).

  Next, the DMA controller activates the DMA and accesses the data transfer device (step S7).

  Next, the address from the host bus is compared with the value of the start address storage register by the comparator, and the comparison result is notified to the host bus-slave bus conversion unit and the transfer control unit. If they match, the address comparison result signal (9 in FIG. 1) is turned on (step S8).

  When the address comparison result signal is on, the host bus-slave bus conversion unit does not access the slave bus, and the host bus access signal (26 in FIG. 1) is turned on to read the data read from the buffer to the host bus. (Step S9).

  The buffer control unit increments the read pointer by the access signal (26 in FIG. 1). The transfer control unit increments the host bus data transfer counter (step S10).

  The DMA controller receives data and stores it in memory. By repeating the above operation, all packetized data can be transferred to the memory (step S11).

  When the host bus data counter is equal to the transfer data number storage register value, the comparison enable signal (15 in FIG. 1) is turned off, and thereafter, the address comparison is not performed and the transfer ends (step S12).

  The address of the reception data register of the peripheral device 1 is considered to be fixed or not. In order to specify this, a setting register is provided in the host bus-slave bus conversion unit (214 in FIG. 1), and a signal indicating this setting state is used as an address increment mode signal.

  When the address increment mode signal (20 in FIG. 1) is ON, the host bus access timing is recognized by the host bus access timing signal (26 in FIG. 1), and the value of the start address storage register is incremented by one word. And

  When there is a reception memory or the like in the peripheral device 1, a case where the increment mode is turned on and used is conceivable. Otherwise, it is normally a received data register, in which case the address is fixed.

  FIGS. 5 and 6 are flowcharts of the operation at the time of transfer from the master to the slave (data transmission operation from the peripheral device).

  Here, the process of transferring the transmission data for the peripheral device 1 (180-1 in FIG. 2) from the predetermined area of the memory (140 in FIG. 2) to the peripheral device 1 by the DMA controller (130 in FIG. 2). Is assumed.

  It is assumed that the peripheral device transmits data at regular intervals. In this example, the packetization of data is performed in advance by the CPU (120 in FIG. 2).

  The DMA controller (130 in FIG. 2) has an on-demand channel, which is used in this example.

  First, after generating a packet of transmission data, the CPU (120 in FIG. 2) performs the following settings for a transmission operation.

  (1) A transfer destination address (transmission data register of peripheral device 1), a transfer source address (data area of memory), and the number of data transfers are set in the DMA controller.

  (2) A transfer destination address is set in the start address storage register of the data transfer device, and a data transfer number is set in the transfer data number storage register. Since writing has occurred in the start address storage register, both transfer counters (242 and 244 in FIG. 1) are reset to zero.

  (3) The CPU sets transfer enable to the DMA controller (step S21).

  Next, in the case of the mode of the transmission operation to the peripheral device, the peripheral device transfer permission signal (8 in FIG. 1) is always on in the transmittable state, and the transfer start signal (7 in FIG. 1) is also on. In this case, when enable is set for the DMA controller, the DMA controller immediately starts data transfer. The DMA controller transfers the data read from the memory to the data transfer device (step S22).

  Next, since the address comparison result (9 in FIG. 1), which is the output of the address comparator, is on, the host bus-slave bus conversion unit stores the data in the buffer and terminates the host bus access. Until the buffer is full, the operation of the host bus is performed with the transfer start signal turned on regardless of the operation of the slave bus (step S23).

  The data buffer control unit (232 in FIG. 1) controls the buffer by the host bus access timing signal (26 in FIG. 1). The write pointer is incremented (step S24).

  The host bus-slave bus conversion unit performs a write operation on the slave bus. A write slave address register (not shown) exists in the bus conversion unit, and the same value is written simultaneously with the writing of the start address storage register (222 in FIG. 1). The existence of this register is not visible to the CPU.

  The value of the slave address register is output to the slave address signal (3 in FIG. 1) as an address at the time of writing. In the case of the increment mode, every access is incremented by one word (step S25).

  The peripheral device receives the data and turns off the peripheral device transfer permission signal (8 in FIG. 1) when the data cannot be received due to the transmission operation (step S26). As long as the peripheral device transfer permission signal is ON and there is untransferred data in the buffer, the bus converter continues to transfer the buffer data to the peripheral device.

  Next, the slave bus data transfer counter is incremented every time the slave bus is transferred. The host bus data transfer counter is incremented every time a transfer from the host bus occurs. When the slave bus data transfer counter is equal to the transfer data count storage register value, the transfer is completed, the comparison enable signal (15 in FIG. 1) is turned off, the subsequent address comparison is not performed, and the host bus transfer operation ends. To do. In the slave bus operation, the transfer is performed until the transfer of the data stored in the buffer is completed, and the transfer is terminated when the slave bus data transfer counter = the transfer data number storage register value is satisfied (step S27).

  Note that a register for distinguishing the reception operation and the transmission operation to the peripheral device may exist in the bus conversion unit, and may be set by the CPU before the transfer. For example, the following three operation modes can be set.

NOUSE; do not use buffer
TX: Transmission to peripheral device
RX: Reception from peripheral devices Also, having multiple automatic transfer processing units (data transfer control circuits) and having a corresponding DMA channel enables multiple transfers to peripheral devices in parallel. Become.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

The block diagram of the data transfer apparatus of this Embodiment. The block diagram of the information processing apparatus of this Embodiment. The flowchart of the operation | movement at the time of transfer from a slave to a master. The flowchart of the operation | movement at the time of transfer from a slave to a master. The flowchart of the operation | movement at the time of transfer from a master to a slave. The flowchart of the operation | movement at the time of transfer from a master to a slave.

Explanation of symbols

100 Information processing device, 110 Host bus, 120 CPU, 130 DMA controller, 140 Memory, 150 System control unit, 160 Interrupt controller, 170 Slave bus, 180-1 peripheral device, 200 Data transfer device, 210 Bus bridge circuit, 212 Host Bus interface, 214 Host bus-slave bus conversion unit, 216 Slave bus interface, 220 Automatic transfer processing unit (transfer control processing unit), 222 Start address register, 224 Transfer data number storage register, 226 Address comparator, 230 buffer, 232 Data buffer control unit, 240 transfer control unit, 242 slave bus data transfer counter, 244 host bus data transfer counter

Claims (7)

A data transfer device connected to a host bus to which a host and a DMA controller are connected and a slave bus to which a peripheral device is connected, and transfers data between the host bus and the slave bus,
A bus bridge circuit connected to the host bus and the slave bus, for transmitting and receiving data between the host bus and the slave bus;
A data transfer control circuit for controlling data transmission / reception between the host bus and the slave bus,
The data transfer control circuit includes:
In the case of transfer from the peripheral device to the host, the address of the transfer source is stored; in the case of transfer from the host bus to the slave bus, an address storage unit in which the address of the transfer destination is stored;
A buffer for storing data received from a host bus or a slave bus via the bus bridge circuit;
When transferring data from the peripheral device to the host, it receives data from the slave bus via the bus bridge circuit, stores the received data in the buffer,
The request address received from the host bus is compared with the address stored in the address storage unit. If they match, the data stored in the buffer is passed through the bus bridge circuit. And a circuit for controlling the output to the host bus. In claim 1,
The data transfer control circuit includes:
When transferring from the host to the peripheral device, data from the host bus is received via the bus bridge circuit and stored in the buffer, and the data stored in the buffer is transferred to the slave bus via the bus bridge circuit. A data transfer device comprising a circuit for controlling output. In any one of Claims 1-2.
The data transfer control circuit includes:
Including a transfer data number storage for specifying the number of transfer data;
When transferring data from the peripheral device to the host, data from the slave bus is received via the bus bridge circuit until the number of transfer data stored in the transfer data number storage unit is reached, and the received data is stored in the buffer. And
The request address received from the host bus is compared with whether the address stored in the address storage unit matches, and if it matches, the transfer data number stored in the transfer data number storage unit is determined. A data transfer device comprising: a circuit that controls to output data stored in a buffer until it reaches the host bus via a bus bridge circuit. In claim 3,
The data transfer control circuit includes:
When transferring data from the host to the peripheral device, data from the host bus is received via the bus bridge circuit until the number of transfer data stored in the transfer data number storage unit is reached, and stored in the buffer. A data transfer apparatus comprising: a circuit that controls to output data stored in a buffer to a slave bus via a bus bridge circuit until the number of transfer data stored in the number storage unit is reached. In any one of Claims 1 thru | or 4,
The data transfer control circuit includes:
In the case of transfer from the peripheral device to the host, the transfer source address stored in the address storage unit is updated in response to reading from the host bus, and the updated address and the request address received from the host bus match. A data transfer device comprising: a circuit that controls to output data stored in a buffer to a host bus when a match is indicated by comparison. A data transfer device according to any one of claims 1 to 5,
A host bus connected to the data transfer device;
A slave bus connected to the data transfer device;
A CPU connected to the host bus;
A DMA controller connected to the host bus;
An information processing device including a peripheral device connected to a slave bus,
The CPU
When receiving data from the peripheral device, set the transfer source address, the transfer destination address, the number of data transfers to the DMA controller, set the transfer enable,
Set the transfer source address in the address storage part of the data transfer device, set the transfer data number in the transfer data number storage part,
When the transfer enable setting is made, the DMA controller starts the DMA, and transfers the data stored in the buffer of the data transfer device through the host bus based on the set transfer source address, transfer destination address, and data transfer number. An information processing apparatus that performs DMA transfer. In claim 6,
The CPU
When sending data from the host to the peripheral device, set the transfer enable to the DMA controller by setting the transfer source address, the transfer destination address, the number of data transfers,
Set the transfer destination address in the address storage part of the data transfer device, set the transfer data number in the transfer data number storage part,
The DMA controller starts DMA when transfer enable is set, and
DMA transfer data to the buffer of the data transfer device via the host bus based on the set transfer source address, transfer destination address, data transfer number,
An information processing apparatus that opens a host bus when transmission of data to a data transfer apparatus is completed.

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