JP2018074111A - Method for manufacturing light-emitting diode chip - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000005520 cutting process Methods 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 11
- 239000010980 sapphire Substances 0.000 claims description 11
- 230000010354 integration Effects 0.000 claims description 9
- 239000005304 optical glass Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000005488 sandblasting Methods 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 description 9
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 238000002679 ablation Methods 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000002173 cutting fluid Substances 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005323 electroforming Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
Abstract
Description
本発明は、発光ダイオードチップの製造方法に関する。 The present invention relates to a method for manufacturing a light-emitting diode chip.
サファイア基板、ＧａＮ基板、ＳｉＣ基板等の結晶成長用基板の表面にｎ型半導体層、発光層、ｐ型半導体層が複数積層された積層体層が形成され、この積層体層に交差する複数の分割予定ラインによって区画された領域に複数のＬＥＤ（Ｌｉｇｈｔ Ｅｍｉｔｔｉｎｇ Ｄｉｏｄｅ）等の発光デバイスが形成されたウエーハは、分割予定ラインに沿って切断されて個々の発光デバイスチップに分割され、分割された発光デバイスチップは携帯電話、パソコン、照明機器等の各種電気機器に広く利用されている。 A stacked body layer in which a plurality of n-type semiconductor layers, light-emitting layers, and p-type semiconductor layers are stacked is formed on the surface of a crystal growth substrate such as a sapphire substrate, a GaN substrate, or a SiC substrate. A wafer in which a plurality of light emitting devices such as LEDs (Light Emitting Diodes) are formed in a region partitioned by the planned division line is cut along the planned division line and divided into individual light emitting device chips, and the divided light emission Device chips are widely used in various electric devices such as mobile phones, personal computers, and lighting devices.
発光デバイスチップの発光層から出射される光は等方性を有しているため、結晶成長用基板の内部にも照射されて基板の裏面及び側面からも光が出射する。然し、基板の内部に照射された光のうち空気層との界面での入射角が臨界角以上の光は界面で全反射されて基板内部に閉じ込められ、基板から外部に出射されることがないから発光デバイスチップの輝度の低下を招くという問題がある。 Since the light emitted from the light emitting layer of the light emitting device chip is isotropic, the light is emitted also to the inside of the crystal growth substrate, and the light is also emitted from the back and side surfaces of the substrate. However, of the light irradiated to the inside of the substrate, light whose incident angle at the interface with the air layer is greater than the critical angle is totally reflected at the interface and confined inside the substrate, and is not emitted outside from the substrate. Therefore, there is a problem that the luminance of the light emitting device chip is lowered.
この問題を解決するために、発光層から出射された光が基板の内部に閉じ込められるのを抑制するために、基板の裏面に透明部材を貼着して輝度の向上を図るようにした発光ダイオード（ＬＥＤ）が特開２０１４−１７５３５４号公報に記載されている。 In order to solve this problem, a light emitting diode in which a transparent member is attached to the back surface of the substrate to improve the luminance in order to prevent light emitted from the light emitting layer from being confined inside the substrate. (LED) is described in Japanese Patent Application Laid-Open No. 2014-175354.
然し、特許文献１に開示された発光ダイオードでは、基板の裏面に透明部材を貼着することにより輝度が僅かに向上したものの十分な輝度が得られないという問題がある。 However, the light emitting diode disclosed in Patent Document 1 has a problem that sufficient luminance cannot be obtained although the luminance is slightly improved by sticking a transparent member to the back surface of the substrate.
本発明はこのような点に鑑みてなされたものであり、その目的とするところは、十分な輝度が得られる発光ダイオードチップの製造方法を提供することである。 The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a light-emitting diode chip capable of obtaining sufficient luminance.
本発明によると、発光ダイオードチップの製造方法であって、結晶成長用の透明基板上に発光層を含む複数の半導体層が形成された積層体層を有し、該積層体層の表面に互いに交差する複数の分割予定ラインによって区画された各領域にそれぞれＬＥＤ回路が形成されたウエーハを準備するウエーハ準備工程と、該ウエーハの裏面に内部に複数の気泡が形成された透明基板の表面を貼着して一体化ウエーハを形成する一体化工程と、該一体化工程を実施した後、該一体化ウエーハの該透明基板の裏面に該ウエーハの各ＬＥＤ回路に対応して複数の窪みを形成する透明基板加工工程と、該透明基板加工工程を実施した後、該ウエーハを該分割予定ラインに沿って該透明基板と共に切断して該一体化ウエーハを個々の発光ダイオードチップに分割する分割工程と、を備えたことを特徴とする発光ダイオードチップの製造方法が提供される。 According to the present invention, there is provided a method for manufacturing a light-emitting diode chip, comprising: a stacked body layer in which a plurality of semiconductor layers including a light-emitting layer are formed on a transparent substrate for crystal growth; A wafer preparation step of preparing a wafer in which LED circuits are formed in each region partitioned by a plurality of intersecting scheduled lines, and a surface of a transparent substrate in which a plurality of bubbles are formed on the back surface of the wafer are pasted. An integration step for forming an integrated wafer and performing the integration step, and then forming a plurality of depressions corresponding to each LED circuit of the wafer on the back surface of the transparent substrate of the integrated wafer. After performing the transparent substrate processing step and the transparent substrate processing step, the wafer is cut along with the transparent substrate along the division line to divide the integrated wafer into individual light emitting diode chips. That the light-emitting diode chip production method of the division process, comprising the is provided.
好ましくは、透明基板加工工程において形成される窪みの断面形状は、三角形状、四角形状、又は円形状の何れかである。好ましくは、透明基板加工工程において形成される窪みは、エッチング、サンドブラスト、レーザーの何れかで形成される。 Preferably, the cross-sectional shape of the recess formed in the transparent substrate processing step is any one of a triangular shape, a quadrangular shape, and a circular shape. Preferably, the recess formed in the transparent substrate processing step is formed by any one of etching, sand blasting, and laser.
好ましくは、該透明基板は、透明セラミックス、光学ガラス、サファイア、透明樹脂の何れかで形成され、該一体化工程において該透明基板は透明接着剤でウエーハに接着される。 Preferably, the transparent substrate is formed of any one of transparent ceramics, optical glass, sapphire, and transparent resin, and in the integration step, the transparent substrate is bonded to the wafer with a transparent adhesive.
本発明の発光ダイオードチップは、ＬＥＤの裏面に貼着された内部に複数の気泡を有する透明部材の裏面に窪みが形成されているので、透明部材の表面積が増大することに加え、ＬＥＤの発光層から照射され透明部材に進入した光の一部が外部に出射する際、窪み部分で複雑に屈折して出射する。従って、透明部材から出射する際に透明部材と空気層との界面での入射角が臨界角以上の光の割合が減少し、透明部材から出射される光の量が増大して発光ダイオードチップの輝度が向上する。 Since the light emitting diode chip of the present invention has depressions formed on the back surface of the transparent member having a plurality of bubbles inside the LED chip attached to the back surface of the LED, in addition to increasing the surface area of the transparent member, the light emission of the LED When a part of the light irradiated from the layer and entering the transparent member is emitted to the outside, it is refracted and emitted in a complicated manner at the recessed portion. Accordingly, when the light is emitted from the transparent member, the ratio of light whose incident angle at the interface between the transparent member and the air layer is greater than the critical angle is decreased, and the amount of light emitted from the transparent member is increased, so that the light emitting diode chip Brightness is improved.
以下、本発明の実施形態を図面を参照して詳細に説明する。図１を参照すると、光デバイスウエーハ（以下、単にウエーハと略称することがある）１１の表面側斜視図が示されている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, there is shown a front side perspective view of an optical device wafer 11 (hereinafter sometimes simply referred to as a wafer) 11.
光デバイスウエーハ１１は、サファイア基板１３上に窒化ガリウム（ＧａＮ）等のエピタキシャル層（積層体層）１５が積層されて構成されている。光デバイスウエーハ１１は、エピタキシャル層１５が積層された表面１１ａと、サファイア基板１３が露出した裏面１１ｂとを有している。 The optical device wafer 11 is configured by laminating an epitaxial layer (laminated body layer) 15 such as gallium nitride (GaN) on a sapphire substrate 13. The optical device wafer 11 has a front surface 11a on which an epitaxial layer 15 is stacked and a back surface 11b on which the sapphire substrate 13 is exposed.
ここで、本実施形態の光デバイスウエーハ１１では、結晶成長用基板としてサファイア基板１３を採用しているが、サファイア基板１３に替えＧａＮ基板又はＳｉＣ基板等を採用するようにしてもよい。 Here, in the optical device wafer 11 of the present embodiment, the sapphire substrate 13 is employed as the crystal growth substrate. However, a GaN substrate or a SiC substrate may be employed instead of the sapphire substrate 13.
積層体層（エピタキシャル層）１５は、電子が多数キャリアとなるｎ型半導体層（例えば、ｎ型ＧａＮ層）、発光層となる半導体層（例えば、ＩｎＧａＮ層）、正孔が多数キャリアとなるｐ型半導体層（例えば、ｐ型ＧａＮ層）を順にエピタキシャル成長させることにより形成される。 The stacked body layer (epitaxial layer) 15 includes an n-type semiconductor layer (for example, an n-type GaN layer) in which electrons are majority carriers, a semiconductor layer (for example, an InGaN layer) that is a light emitting layer, and a p in which holes are majority carriers. It is formed by epitaxially growing a type semiconductor layer (for example, a p-type GaN layer) in this order.
サファイア基板１３は例えば１００μｍの厚みを有しており、積層体層１５は例えば５μｍの厚みを有している。積層体層１５に複数のＬＥＤ回路１９が格子状に形成された複数の分割予定ライン１７によって区画されて形成されている。ウエーハ１１は、ＬＥＤ回路１９が形成された表面１１ａと、サファイア基板１３が露出した裏面１１ｂとを有している。 The sapphire substrate 13 has a thickness of 100 μm, for example, and the laminate layer 15 has a thickness of 5 μm, for example. A plurality of LED circuits 19 are defined on the laminate layer 15 by a plurality of division lines 17 formed in a lattice pattern. The wafer 11 has a front surface 11a on which the LED circuit 19 is formed and a back surface 11b on which the sapphire substrate 13 is exposed.
本発明実施形態の発光ダイオードチップの製造方法によると、まず図１に示すような光デバイスウエーハ１１を準備するウエーハ準備工程を実施する。次いで、図２（Ａ）に示すように、ウエーハ１１の裏面１１ｂに内部に複数の気泡２９を有する透明基板２１の表面２１を貼着して、ウエーハ１１と透明基板２５とを一体化して図２（Ｂ）に示す一体化ウエーハ２５を形成する一体化工程を実施する。 According to the light emitting diode chip manufacturing method of the embodiment of the present invention, first, a wafer preparation step for preparing an optical device wafer 11 as shown in FIG. 1 is performed. Next, as shown in FIG. 2A, the front surface 21 of the transparent substrate 21 having a plurality of bubbles 29 is attached to the back surface 11b of the wafer 11 so that the wafer 11 and the transparent substrate 25 are integrated. An integration step for forming the integrated wafer 25 shown in FIG.
一体化工程を実施した後、一体化ウエーハ２５の透明基板２１の裏面２１ｂにＬＥＤ回路１９に対応して複数の窪みを形成する透明基板加工工程を実施する。この透明基板加工工程では、図３（Ａ）に示すように、ウエーハ１１のＬＥＤ回路１９に対応した複数の穴４を有するマスク２を使用する。 After performing the integration step, a transparent substrate processing step is performed in which a plurality of depressions are formed on the back surface 21b of the transparent substrate 21 of the integrated wafer 25 corresponding to the LED circuit 19. In this transparent substrate processing step, as shown in FIG. 3A, a mask 2 having a plurality of holes 4 corresponding to the LED circuits 19 of the wafer 11 is used.
図３（Ｂ）に示すように、マスク２の穴４をウエーハ１１の各ＬＥＤ回路１９に対応させてマスク２を一体化ウエーハ２５の透明基板２１の裏面２１ｂに貼着する。そして、ウェットエッチング又はプラズマエッチングにより透明基板２１の裏面２１ｂに、図３(Ｃ)に示すように、マスク２の穴４の形状に対応した三角形状の窪み５を形成する。 As shown in FIG. 3B, the mask 2 is attached to the back surface 21 b of the transparent substrate 21 of the integrated wafer 25 with the holes 4 of the mask 2 corresponding to the LED circuits 19 of the wafer 11. Then, a triangular recess 5 corresponding to the shape of the hole 4 of the mask 2 is formed on the back surface 21b of the transparent substrate 21 by wet etching or plasma etching, as shown in FIG.
マスク２の穴４の形状を四角形状、又は円形状に変形することにより、透明基板２１の裏面２１ｂに図３（Ｄ）に示すような四角形状の窪み５Ａを形成するか、図３（Ｅ）に示すような透明基板２１の裏面２１ｂに円形状の窪み５Ｂを形成するようにしてもよい。 By changing the shape of the hole 4 of the mask 2 into a quadrangular shape or a circular shape, a rectangular recess 5A as shown in FIG. 3D is formed on the back surface 21b of the transparent substrate 21, or FIG. The circular recess 5B may be formed on the back surface 21b of the transparent substrate 21 as shown in FIG.
内部に複数の気泡２９を有する透明基板２１の裏面２１ｂにＬＥＤ回路１９に対応した複数の窪みを形成するのに、レーザー加工装置を利用するようにしてもよい。レーザー加工装置による実施形態では、図４（Ａ）に示すように、透明基板２１に対して吸収性を有する波長(例えば、２６６ｎｍ)のレーザービームを集光器（レーザーヘッド）２４から透明基板２１の裏面２１ｂに間欠的に照射しながら、一体化ウエーハ２５を保持した図示しないチャックテーブルを矢印Ｘ１方向に加工送りすることにより、透明基板２１の裏面２１ｂに窪み９をアブレーションにより形成する。 A laser processing apparatus may be used to form a plurality of depressions corresponding to the LED circuit 19 on the back surface 21b of the transparent substrate 21 having a plurality of bubbles 29 therein. In the embodiment using the laser processing apparatus, as shown in FIG. 4A, a laser beam having a wavelength (for example, 266 nm) having an absorptivity with respect to the transparent substrate 21 is transmitted from the condenser (laser head) 24 to the transparent substrate 21. A recess 9 is formed on the back surface 21b of the transparent substrate 21 by ablation by processing and feeding a chuck table (not shown) holding the integrated wafer 25 in the direction of the arrow X1 while intermittently irradiating the back surface 21b of the transparent substrate 21b.
一体化ウエーハ２５を矢印Ｘ１方向に直交する方向にウエーハ１１の分割予定ライン１７のピッチずつ割り出し送りしながら、透明基板２１の裏面２１ｂをアブレーション加工して、図４（Ｂ）に示すような窪み９を次々と形成する。 The back surface 21b of the transparent substrate 21 is ablated while indexing and feeding the integrated wafer 25 in the direction orthogonal to the direction of the arrow X1 by the pitch of the division lines 17 of the wafer 11, and a depression as shown in FIG. 9 are formed one after another.
透明基板２１は、透明樹脂、光学ガラス、サファイア、透明セラミックスの何れかから形成される。本実施形態では、光学ガラスに比べて耐久性のあるポリカーボネイト、アクリル等の透明樹脂から透明基板２１を形成した。 The transparent substrate 21 is formed from any one of transparent resin, optical glass, sapphire, and transparent ceramics. In the present embodiment, the transparent substrate 21 is formed from a transparent resin such as polycarbonate or acrylic that is more durable than optical glass.
一体化ウエーハ２５を構成する透明基板２１の裏面２１ｂに複数の窪み９を形成する透明基板加工工程を実施した後、図５に示すように、一体化ウエーハ２５の透明基板２１を外周部が環状フレームＦに貼着されたダイシングテープＴに貼着してフレームユニットを形成し、一体化ウエーハ２５をダイシングテープＴを介して環状フレームＦで支持する支持工程を実施する。 After carrying out the transparent substrate processing step of forming a plurality of depressions 9 on the back surface 21b of the transparent substrate 21 constituting the integrated wafer 25, the outer peripheral portion of the transparent substrate 21 of the integrated wafer 25 is annular as shown in FIG. A frame unit is formed by adhering to the dicing tape T adhered to the frame F, and a supporting process for supporting the integrated wafer 25 with the annular frame F through the dicing tape T is performed.
支持工程を実施した後、フレームユニットを切削装置に投入し、切削装置で一体化ウエーハ２５を切削して個々の発光ダイオードチップに分割する分割ステップを実施する。この分割ステップについて、図６を参照して説明する。 After carrying out the supporting process, the frame unit is put into a cutting device, and the dividing step of cutting the integrated wafer 25 with the cutting device and dividing it into individual light emitting diode chips is carried out. This division step will be described with reference to FIG.
図６に示すように、切削装置の切削ユニット１０は、スピンドルハウジング１２と、スピンドルハウジング１２中に回転可能に挿入された図示しないスピンドルと、スピンドルの先端に装着された切削ブレード１４とを含んでいる。 As shown in FIG. 6, the cutting unit 10 of the cutting apparatus includes a spindle housing 12, a spindle (not shown) rotatably inserted into the spindle housing 12, and a cutting blade 14 attached to the tip of the spindle. Yes.
切削ブレード１４の切り刃は、例えば、ダイヤモンド砥粒をニッケルメッキで固定した電鋳砥石で形成されており、その先端形状は三角形状、四角形状、又は半円形状をしている。 The cutting blade of the cutting blade 14 is formed of, for example, an electroforming grindstone in which diamond abrasive grains are fixed by nickel plating, and the tip shape thereof is triangular, quadrangular, or semicircular.
切削ブレード１４の概略上半分はブレードカバー（ホイールカバー）１６で覆われており、ブレードカバー１６には切削ブレード１４の奥側及び手前側に水平に伸長する一対の（１本のみ図示）クーラーノズル１８が配設されている。 The upper half of the cutting blade 14 is covered with a blade cover (wheel cover) 16, and the blade cover 16 is a pair of cooler nozzles (only one is shown) extending horizontally toward the back side and the near side of the cutting blade 14. 18 is arranged.
分割ステップでは、一体化ウエーハ２５をフレームユニットのダイシングテープＴを介して切削装置のチャックテーブル２０で吸引保持し、環状フレームＦは図示しないクランプでクランプして固定する。 In the dividing step, the integrated wafer 25 is sucked and held by the chuck table 20 of the cutting device via the dicing tape T of the frame unit, and the annular frame F is clamped and fixed by a clamp (not shown).
そして、切削ブレード１４を矢印Ｒ方向に高速回転させながら切削ブレード１４の先端がダイシングテープＴに届くまでウエーハ１１の分割予定ライン１７に切り込み、クーラーノズル１８から切削ブレード１４及びウエーハ１１の加工点に向かって切削液を供給しつつ、一体化ウエーハ２５を矢印Ｘ１方向に加工送りすることにより、ウエーハ１１の分割予定ライン１７に沿ってウエーハ１１及び透明基板２１を切断する切断溝２７を形成する。 Then, while rotating the cutting blade 14 in the direction of arrow R at high speed, the cutting blade 14 is cut into the division line 17 of the wafer 11 until the tip of the cutting blade 14 reaches the dicing tape T. From the cooler nozzle 18 to the processing point of the cutting blade 14 and the wafer 11. The cutting groove 27 for cutting the wafer 11 and the transparent substrate 21 is formed along the division line 17 of the wafer 11 by processing and feeding the integrated wafer 25 in the direction of the arrow X1 while supplying the cutting fluid.
切削ユニット１０をＹ軸方向に割り出し送りしながら、第１の方向に伸長する分割予定ライン１７に沿って同様な切断溝２７を次々と形成する。次いで、チャックテーブル２０を９０°回転してから、第１の方向に直交する第２の方向に伸長する全ての分割予定ライン１７に沿って同様な切断溝２７を形成して、図７に示す状態にすることで、一体化ウエーハ２５を図８に示すような発光ダイオードチップ３１に分割する。 While indexing and feeding the cutting unit 10 in the Y-axis direction, similar cutting grooves 27 are formed one after another along the planned dividing line 17 extending in the first direction. Next, after the chuck table 20 is rotated by 90 °, similar cutting grooves 27 are formed along all the planned dividing lines 17 extending in the second direction orthogonal to the first direction, as shown in FIG. In this state, the integrated wafer 25 is divided into light emitting diode chips 31 as shown in FIG.
上述した実施形態では、一体化ウエーハ２５を個々の発光ダイオードチップ３１に分割するのに切削装置を使用しているが、ウエーハ１１及び透明基板２１に対して透過性を有する波長のレーザービームを分割予定ライン１３に沿ってウエーハ１１に照射して、ウエーハ１１及び透明基板２１の内部に厚み方向に複数層の改質層を形成し、次いで、一体化ウエーハ２５に外力を付与して、改質層を分割起点に一体化ウエーハ２５を個々の発光ダイオードチップ３１に分割するようにしてもよい。 In the embodiment described above, the cutting device is used to divide the integrated wafer 25 into the individual light emitting diode chips 31. However, the laser beam having a wavelength that is transmissive to the wafer 11 and the transparent substrate 21 is divided. Irradiate the wafer 11 along the planned line 13 to form a plurality of modified layers in the thickness direction inside the wafer 11 and the transparent substrate 21, and then apply an external force to the integrated wafer 25 to modify the wafer. The integrated wafer 25 may be divided into individual light emitting diode chips 31 using the layers as division starting points.
図８に示された発光ダイオードチップ３１は、表面にＬＥＤ回路１９を有するＬＥＤ１３Ａの裏面に内部に複数の気泡２９が形成された透明部材２１Ａが貼着されている。更に、透明部材２１Ａの裏面に窪み５，５Ａ，５Ｂ又は９が形成されている。 The light emitting diode chip 31 shown in FIG. 8 has a transparent member 21A in which a plurality of bubbles 29 are formed on the back surface of an LED 13A having an LED circuit 19 on the front surface. Further, the recess 5, 5A, 5B or 9 is formed on the back surface of the transparent member 21A.
従って、図８に示す発光ダイオードチップ３１では、透明部材２１Ａの裏面２１ｂに窪み５，５Ａ，５Ｂ又は９が形成されているため、透明部材２１Ａの表面積が増大する。更に、発光ダイオードチップ３１のＬＥＤ回路１９から出射され透明部材２１Ａ中に進入した光の一部は、透明部材２１Ａから出射する際、窪み５，５Ａ，５Ｂ又は９部分で複雑に屈折されて出射する。 Therefore, in the light emitting diode chip 31 shown in FIG. 8, since the recess 5, 5A, 5B or 9 is formed on the back surface 21b of the transparent member 21A, the surface area of the transparent member 21A increases. Further, part of the light emitted from the LED circuit 19 of the light emitting diode chip 31 and entering the transparent member 21A is refracted in a complicated manner at the recess 5, 5A, 5B, or 9 when emitted from the transparent member 21A. To do.
従って、透明部材２１Ａから外部に屈折して出射する際、透明部材２１Ａと空気層との界面での入射角が臨界角以上となる光の割合が減少し、透明部材２１Ａから出射される光の量が増大し、発光ダイオードチップ３１の輝度が向上する。 Accordingly, when the light is refracted and emitted from the transparent member 21A, the ratio of the light whose incident angle at the interface between the transparent member 21A and the air layer is greater than the critical angle is reduced, and the light emitted from the transparent member 21A is reduced. The amount increases, and the luminance of the light emitting diode chip 31 is improved.
５，５Ａ，５Ｂ，９ 窪み
１０ 切削ユニット
１１ 光デバイスウエーハ（ウエーハ）
１３ サファイア基板
１４ 切削ブレード
１５ 積層体層
１７ 分割予定ライン
１９ ＬＥＤ回路
２１ 透明基板
２１Ａ 透明部材
２５ 一体化ウエーハ
２７ 切断溝
２９ 気泡
３１ 発光ダイオードチップ
5, 5A, 5B, 9 Dimple 10 Cutting unit 11 Optical device wafer (wafer)
DESCRIPTION OF SYMBOLS 13 Sapphire substrate 14 Cutting blade 15 Laminate body layer 17 Scheduled division line 19 LED circuit 21 Transparent substrate 21A Transparent member 25 Integrated wafer 27 Cutting groove 29 Air bubble 31 Light emitting diode chip
Claims (4)
結晶成長用の透明基板上に発光層を含む複数の半導体層が形成された積層体層を有し、該積層体層の表面に互いに交差する複数の分割予定ラインによって区画された各領域にそれぞれＬＥＤ回路が形成されたウエーハを準備するウエーハ準備工程と、
該ウエーハの裏面に内部に複数の気泡が形成された透明基板の表面を貼着して一体化ウエーハを形成する一体化工程と、
該一体化工程を実施した後、該一体化ウエーハの該透明基板の裏面に該ウエーハの各ＬＥＤ回路に対応して複数の窪みを形成する透明基板加工工程と、
該透明基板加工工程を実施した後、該ウエーハを該分割予定ラインに沿って該透明基板と共に切断して該一体化ウエーハを個々の発光ダイオードチップに分割する分割工程と、
を備えたことを特徴とする発光ダイオードチップの製造方法。 A method of manufacturing a light emitting diode chip,
Each of the regions has a laminate layer in which a plurality of semiconductor layers including a light emitting layer are formed on a transparent substrate for crystal growth, and is divided into a plurality of division lines intersecting each other on the surface of the laminate layer. A wafer preparation step of preparing a wafer on which an LED circuit is formed;
An integration step of forming an integrated wafer by sticking the surface of a transparent substrate having a plurality of bubbles formed therein on the back surface of the wafer;
After performing the integration step, a transparent substrate processing step of forming a plurality of depressions corresponding to each LED circuit of the wafer on the back surface of the transparent substrate of the integrated wafer;
After performing the transparent substrate processing step, the dividing step of cutting the wafer together with the transparent substrate along the division line to divide the integrated wafer into individual light emitting diode chips;
A method for producing a light-emitting diode chip, comprising:
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| CN201711000328.3A CN108023005A (en) | 2016-11-04 | 2017-10-24 | The manufacture method of light-emitting diode chip for backlight unit |
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