JP2018067625A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing deterioration in heat radiation property of a cell region even in a case where positional deviation occurs when a conductive member is arranged.SOLUTION: In a semiconductor device, a cell region 20A, and a peripheral region 20B surrounding the cell region are formed on a semiconductor substrate 24. In the cell region, an electrode layer 21 is arranged on an upper surface of the semiconductor substrate. A junction electrode 22 is arranged on an upper surface of the electrode layer. The cell region comprises: a first semiconductor layer 212 of a first conductivity type formed within a range exposed to the upper surface of the semiconductor substrate; a second semiconductor layer 214 of a second conductivity type formed at a lower surface side of the first semiconductor layer; a third semiconductor layer 232 of the first conductivity type formed at a lower surface side of the second semiconductor layer; and a trench gate 244 that penetrates through the first and second semiconductor layers and reaches the third semiconductor layer. An impurity concentration of the second conductivity type of the second semiconductor layer at an outer peripheral part is higher than that at a central part of the cell region.SELECTED DRAWING: Figure 4

Description

  The technology disclosed in this specification relates to a semiconductor device.

Patent Document 1 discloses a semiconductor device having a cell region that functions as a switching element and a peripheral region that is formed around the cell region and retains the element breakdown voltage. A surface electrode is formed on the upper surface of the cell region.
As shown in Patent Document 2, the upper surface of the surface electrode of the semiconductor element is electrically connected to an external conductive member (heat sink block) by solder. Heat generated in the semiconductor element by switching is radiated from the heat dissipation plate via the conductive member.

JP 2004-349556 A JP2008-210829

  In order to stably arrange the conductive member on the surface electrode, the surface area of the surface electrode and the area of the solder joint surface of the conductive member are substantially equal. For this reason, when a displacement occurs in the arrangement of the conductive members, a region where no conductive member is present above the cell region is generated on the outer peripheral side of the cell region of the semiconductor substrate. As a result, the heat dissipation on the outer peripheral side of the cell region deteriorates and heat is generated, which may affect the element characteristics.

  Therefore, the present specification provides a semiconductor device that suppresses heat generation in a cell region even when a displacement occurs when a conductive member is disposed.

  In the semiconductor device disclosed in this specification, a cell region and a peripheral region surrounding the cell region are formed over the same semiconductor substrate. In the cell region, an electrode layer is disposed on the upper surface of the semiconductor substrate. A joining electrode is disposed on the upper surface of the electrode layer. A conductive member is connected to the upper surface of the bonding electrode via a bonding member. The cell region is formed in a first conductive type first semiconductor layer formed in a range exposed on the upper surface of the semiconductor substrate, and is formed on the lower surface side of the first semiconductor layer and is in contact with the first semiconductor layer. Type second semiconductor layer, a first conductive type third semiconductor layer formed on the lower surface side of the second semiconductor layer and separated from the first semiconductor layer by the second semiconductor layer, and an upper surface of the semiconductor substrate A trench that penetrates through the first semiconductor layer and the second semiconductor layer and reaches the third semiconductor layer, a gate insulating film that covers an inner surface of the trench, and a gate. And a gate electrode that is insulated from the semiconductor substrate by an insulating film. The impurity concentration of the second conductivity type of the second semiconductor layer is higher in the outer peripheral portion than in the central portion of the cell region.

  In the semiconductor device, in the cell region, the concentration of the second conductivity type impurity of the second semiconductor layer is higher in the outer peripheral portion than in the central portion of the cell region. That is, the gate threshold voltage of the cell region is higher in the outer peripheral portion than in the central portion of the cell region. Therefore, the outer peripheral portion is easier to turn off and harder to turn on than the central portion of the cell region. The energization time is shorter in the outer peripheral portion than in the central portion of the cell region, and heat generation in the outer peripheral portion of the cell region is suppressed. Thereby, even if it is a case where position shift arises in arrangement of a conductive member, it can control that a cell field generates heat.

1 is a cross-sectional view of a semiconductor device 10 according to an embodiment. FIG. 2 is an enlarged view of element II in FIG. 1. It is a top view of semiconductor element 20 with which semiconductor device 10 concerning an embodiment is provided. FIG. 4 is an enlarged view of element IV in FIG. 3.

  As shown in FIG. 1, the semiconductor device 10 according to the embodiment includes a semiconductor element 20, a heat sink block 80, a front surface side heat radiating plate 81, a back surface side heat radiating plate 82, and a sealing resin 83. The semiconductor element 20 has a semiconductor substrate, a surface electrode, and a back electrode. In FIG. 1, illustration of the front surface electrode and the back surface electrode is omitted. The heat sink block 80 is fixed to the surface electrode of the semiconductor element 20 via the solder layer 91. The front-side heat radiating plate 81 is fixed to the surface of the heat sink block 80 via the solder layer 92. The backside heat sink 82 is fixed to the backside electrode of the semiconductor element 20 via the solder layer 93. The sealing resin 83 covers the lower surface of the front surface side heat radiating plate 81, the upper surface of the heat sink block 80, the semiconductor element 20, and the rear surface side heat radiating plate 82.

  As the semiconductor element 20, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), or a diode can be used. The semiconductor element 20 generates heat during operation. As shown in FIG. 2, the semiconductor element 20 includes a semiconductor substrate 24, a surface electrode 23, a protective film 26, a back electrode 28, an insulating film 62, and an electrode 64.

  The semiconductor substrate 24 has a plate shape and is made of, for example, silicon (Si), silicon carbide (SiC), or the like.

  The surface electrode 23, the insulating film 62, and the electrode 64 are provided on the semiconductor substrate 24. The surface electrode 23 has a first metal film 21 and a second metal film 22.

  FIG. 3 is a top view of the semiconductor element 20. As shown in FIG. 3, the first metal film 21 is provided on the upper surface of the semiconductor substrate 24. The first metal film 21 covers the upper surface of the semiconductor substrate 24. The first metal film 21 has conductivity and is made of, for example, an aluminum alloy (AlSi).

  The protective film 26 is made of resin and has an insulating property. The protective film 26 is made of polyimide, for example. As shown in FIGS. 2 and 3, the protective film 26 covers the outer peripheral portion of the upper surface of the insulating film 62, the upper surface of the electrode 64, and the upper surface of the first metal film 21. The protective film 26 has an opening 52 above the first metal film 21. A central portion of the surface of the first metal film 21 is disposed in the opening 52. Accordingly, the central portion of the upper surface of the first metal film 21 is not covered with the protective film 26 and is exposed from the protective film 26.

  The second metal film 22 has conductivity and is made of, for example, nickel (Ni). As shown in FIG. 2, the second metal film 22 covers a range extending from the center of the upper surface of the first metal film 21 to the upper surface of the protective film 26. The central portion of the second metal film 22 covers the central portion of the upper surface of the first metal film 21. The outer peripheral portion of the second metal film 22 rides on the upper part of the protective film 26. The upper surface of the second metal film 22 is covered with the solder layer 91.

  As shown in FIG. 3, the semiconductor substrate 24 has a cell region 20A and a peripheral region 20B. The inside of the line L shown in FIG. 3 is the cell region 20A, and the outside of the line L is the peripheral region 20B. The line L substantially coincides with the end portion of the first metal film 21. The cell region 20A is formed inside the peripheral region 20B. A semiconductor element is formed in the cell region 20A. In the present embodiment, a vertical IGBT (Insulated Gate Bipolar Transistor) is formed in the cell region 20A. The peripheral region 20B is formed outside the cell region 20A. The peripheral region 20B is formed around the cell region 20A. The peripheral area 20B surrounds the cell area 20A. A breakdown voltage structure is formed in the peripheral region 20B by RESURF or FLR.

  FIG. 4 is an enlarged view of element IV of FIG. The inside of the line L shown in FIG. 4 is the cell region 20A, and the outside of the line L is the peripheral region 20B. As shown in FIG. 4, a first metal film 21 is formed on the upper surface of the semiconductor substrate 24 in the cell region 20A. The line L substantially coincides with the end portion of the first metal film 21. An insulating film 62 is formed on the upper surface of the semiconductor substrate 24 in the peripheral region 20B. An electrode 64 is formed on the end of the upper surface of the semiconductor substrate 24. The protective film 26 covers the outer peripheral portion of the upper surface of the insulating film 62, the upper surface of the electrode 64, and the upper surface of the first metal film 21. The protective film 26 has an opening 52 above the first metal film 21. A central portion of the upper surface of the first metal film 21 is disposed in the opening 52. Therefore, the central portion of the upper surface of the first metal film 21 is not covered with the protective film 26. The second metal film 22 covers a range extending from the center of the upper surface of the first metal film 21 to the upper surface of the protective film 26. The central portion of the second metal film covers the central portion of the upper surface of the first metal film 21. The outer peripheral portion of the second metal film 22 rides on the upper part of the protective film 26. The upper surface of the second metal film 22 is covered with the solder layer 91. The second metal film 22 is bonded to the heat sink block 80 via the solder layer 91. The surface area of the first metal film and the area of the solder joint surface of the heat sink block 80 are substantially equal. A back electrode 28 is formed on the lower surface of the semiconductor substrate 24.

  As shown in FIG. 4, a plurality of gate trenches 240 are formed on the upper surface of the semiconductor substrate 24 in the cell region 20A. The inner surface of each trench 240 is covered with a gate insulating film 242. A gate electrode 244 is disposed inside each trench. The gate electrode 244 is insulated from the semiconductor substrate 24 by the gate insulating film 242. An interlayer insulating film 247 is formed on the upper surface of the gate electrode 244. A first metal film 21 is formed on the upper surface of the semiconductor substrate 24 in the cell region 20A. The first metal film 21 is insulated from the gate electrode 244 by the interlayer insulating film 247.

  Inside the semiconductor substrate 24, an emitter layer 212, a body contact layer 215, a body layer 214, a drift layer 232, a buffer layer 234, and a collector layer 236 are formed in the cell region 20A.

  As shown in FIG. 4, the emitter layer 212 is an n-type region having n-type impurities. The emitter layer 212 is formed in a range exposed on the upper surface of the semiconductor substrate 24. The emitter layer 212 is connected to the first metal film 21. The emitter layer 212 is in contact with the gate insulating film 242.

  The body contact layer 215 is a p-type region having a high concentration of p-type impurities. The body contact layer 215 is formed in a range exposed on the upper surface of the semiconductor substrate 24. The body contact layer 215 is connected to the first metal film 21. The body contact layer 215 is in contact with the emitter layer 212.

  Body layer 214 is a p-type region having a p-type impurity concentration lower than that of body contact layer 215. The body layer 214 is formed below the emitter layer 21 and the body contact layer 215, and is in contact with the gate insulating film 242 below the emitter layer 212.

  The body layer 214 includes a first body layer 214a located in the central portion 20a of the cell region 20A and a second body layer 214b located in the outer peripheral portion 20b of the cell region 20A. The concentration of the p-type impurity in the second body layer 214b is higher than the concentration of the p-type impurity in the first body layer 214a.

  The drift layer 232 is an n-type region having a low concentration of n-type impurities. The drift layer 232 is formed below the body layer 214. The drift layer 232 is in contact with the gate insulating film 242 located at the lower end of the trench 240.

  The buffer layer 234 is an n-type region having a high concentration of n-type impurities. The buffer layer 234 is formed below the drift layer 232.

  The collector layer 236 is a p-type region having a high concentration of p-type impurities. The collector layer 236 is formed below the buffer layer 234. The collector layer 236 is formed on the entire surface exposed in the lower surface of the semiconductor substrate 24. The collector layer 236 is connected to the back electrode 28.

  In the semiconductor substrate 24, a peripheral region 20B is formed in a region outside the dotted line L. An insulating film 62 is formed on the upper surface of the semiconductor substrate 24 in the cell region 20B. An electrode 64 is formed on the end of the upper surface of the semiconductor substrate 24. The protective film 26 covers the upper surface of the insulating film 62 and the upper surface of the electrode 64. A RESURF layer 252, a deep p-type layer 256, an end n-type layer 258, a drift layer 232, a buffer layer 234, and a collector layer 236 are formed in the peripheral region 20B. The drift layer 232, the buffer layer 234, and the collector layer 236 are common in the cell region 20A and the peripheral region 20B.

  The RESURF layer 252 is a p-type region having a low concentration p-type impurity. The RESURF layer 252 is formed in a range exposed on the upper surface of the semiconductor substrate 24. The RESURF layer 252 is formed in an annular shape so as to surround the cell region 20A.

  The deep p-type layer 256 is a p-type region having a high concentration of p-type impurities. The deep p-type layer 256 is formed in a range exposed on the upper surface of the semiconductor substrate 24. The deep p-type layer 256 is formed in an annular shape so as to surround the cell region 20A. The deep p-type layer 256 is formed at the boundary between the cell region 20A and the peripheral region 20B, and is in contact with the RESURF layer 252. A part of the upper surface of the contact region 256 is not covered with the insulating film 28 and is connected to the first electrode film 21.

  The end n-type layer 258 is an n-type region having a high concentration of n-type impurities. The end n-type layer 258 is formed in a range exposed on the end surface of the semiconductor substrate 24 and exposed on the upper surface of the semiconductor substrate 24. The end n-type layer 258 is connected to the electrode 60 formed on the upper surface thereof. The end n-type layer 258 is formed in an annular shape so as to surround the cell region 20A.

  The drift layer 232 is an n-type region having a low concentration of n-type impurities. The drift layer 232 is formed below the RESURF layer 252, the deep p-type layer 256, and the end n-type layer 258. The drift layer 232 is formed in a region exposed to the upper surface of the semiconductor substrate 24 in a region between the RESURF layer 252 and the end n-type layer 258.

  The buffer layer 234 is an n-type region having a high concentration of n-type impurities. The buffer layer 234 is formed below the drift layer 232.

  The collector layer 236 is a p-type region having a high concentration of p-type impurities. The collector layer 236 is formed below the buffer layer 234. The collector layer 236 is formed on the entire surface exposed in the lower surface of the semiconductor substrate 24. The collector layer 236 is connected to the back electrode 28. The collector layer 236 is common in the cell region 20A and the peripheral region 20B.

  Next, the IGBT operation of the semiconductor element 20 will be described. When a voltage that makes the back electrode 28 positive is applied between the first metal film 21 and the back electrode 28 and an ON potential (potential greater than the potential necessary for forming a channel) is applied to the gate electrode 244, the IGBT Turns on. That is, a channel is formed in the body layer 214 in a range in contact with the gate insulating film 242 by application of an on-potential to the gate electrode 244. Then, electrons flow from the first metal film 21 to the back electrode 28 through the emitter layer 212, the channel, the drift layer 232, the buffer layer 234, and the collector layer 236. In addition, holes flow from the back electrode 28 to the first metal film 21 through the collector layer 236, the drift layer 234, the body layer 214, and the body contact layer 215. That is, a current flows from the back electrode 28 to the first metal film 21. At this time, the cell region 20 </ b> A of the semiconductor substrate 24 generates heat due to the energization operation of the semiconductor element 20. Heat generated in the cell region 20 </ b> A of the semiconductor substrate 24 is radiated from the surface side heat radiating plate 81 through the solder layer 91, the heat sink block 80, and the solder layer 92.

  When the potential applied to the gate electrode 244 is switched from the on potential to the off potential, the IGBT is turned off. When the IGBT is turned off, a high voltage Vce is applied between the back electrode 28 and the first metal film 21. At this time, the end n-type layer 258 has substantially the same potential as the back electrode 28. Further, the deep p-type layer 256 has substantially the same potential as the first metal film 21. Therefore, a voltage V1 substantially equal to the voltage Vce is applied between the end n-type layer 258 and the deep p-type layer 256. Then, the depletion layer spreads from the deep p-type layer 256 toward the end n-type layer 258. The RESURF layer 252 promotes the elongation of this depletion layer. For this reason, the depletion layer extends over substantially the entire RESURF layer 252 and the drift layer 232. The insulating property between the end n-type layer 258 and the deep p-type layer 256 is ensured by the depletion layer thus spread.

  In the semiconductor device 10, the first metal film 21 is formed on the upper surface of the cell region 20 </ b> A of the semiconductor substrate 24. A heat sink block 80 is connected to the upper surface of the first metal film 21 via a solder layer 91. In order to stably arrange the heat sink block 80, the surface area of the first metal film 21 and the area of the solder joint surface of the heat sink block 80 are substantially equal. Therefore, if a displacement occurs when the heat sink block 80 is disposed, a region where the heat sink block 80 does not exist on the outer peripheral side of the cell region 20A of the semiconductor substrate 24 is generated.

  In the semiconductor device 10 described above, the body layer 214 includes the first body layer 214a located in the central portion 20a of the cell region 20A and the second body layer 214b located in the outer peripheral portion 20b of the cell region 20A. The concentration of the p-type impurity in the second body layer 214b is higher than the concentration of the p-type impurity in the first body layer 214a. That is, the gate threshold voltage of the outer peripheral portion 20b of the cell region 20A is higher than the gate threshold voltage of the central portion 20a of the cell region 20A. Therefore, the outer peripheral portion 20b of the cell region 20A is easier to turn off and harder to turn on than the central portion 20a of the cell region 20A. Accordingly, the energization time is shorter in the outer peripheral portion 20b of the cell region 20A than in the central portion 20a of the cell region 20A, and heat generation in the outer peripheral portion 20b of the cell region 20A is reduced. Therefore, even if a positional shift occurs when the heat sink block 80 is disposed, the heat generation at the outer peripheral portion 20b of the cell region 20A is small, so that the element characteristics are hardly affected.

  In the above embodiment, the cell region 20A is divided into two regions, the central portion 20a and the outer peripheral portion 20b, and the concentration of the body layer 214 is switched. However, the cell region 20A may be switched with a gradient. In this case, a gentle gradient that continuously changes or a gradient that changes stepwise may be used.

  A correspondence relationship between the constituent elements of the embodiment described above and the constituent elements of the claims will be described. The emitter layer 212 of the embodiment is an example of the first semiconductor layer of claim 1. The body layer 214 of the embodiment is an example of the second semiconductor layer of claim 1. The drift layer 232 of the embodiment is an example of a third semiconductor layer according to claim 1. The first metal film 21 of the embodiment is an example of an electrode layer according to claim 1. The second metal film 22 of the embodiment is an example of the bonding electrode according to claim 1. The heat sink block 80 of the embodiment is an example of the conductive member of claim 1. The solder layer 91 according to the embodiment is an example of the joining member according to claim 1.

  The embodiments have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical usefulness by achieving one of them.

10: Semiconductor device 20: Semiconductor element 21: First metal film (electrode layer)
22: Second metal film (bonding electrode)
23: Front electrode 24: Semiconductor substrate 26: Protective film 28: Back electrode 52: Opening 62: Insulating film 64: Electrode 80: Heat sink block (conductive member)
81: Front side heat sink 82: Back side heat sink 83: Sealing resin 91: Solder layer (joining member)
92: Solder layer 93: Solder layer 20A: Cell region 20B: Peripheral region 212: Emitter layer (first semiconductor layer)
214: Body layer (second semiconductor layer)
215: Body contact layer 232: Drift layer (third semiconductor layer)
234: buffer layer 236: collector layer 240: trench 242: gate insulating film 244: gate electrode 252: RESURF layer 256: deep p-type layer 258: end n-type layer

Claims (1)

A semiconductor substrate having a cell region and a peripheral region surrounding the cell region;
An electrode layer disposed on an upper surface of the semiconductor substrate in the cell region;
A bonding electrode disposed on the upper surface of the electrode layer;
A conductive member connected to the upper surface of the bonding electrode via a bonding member;
A semiconductor device comprising:
The cell region is a first semiconductor layer of a first conductivity type formed in a range exposed on the upper surface of the semiconductor substrate;
A second semiconductor layer of a second conductivity type formed on a lower surface side of the first semiconductor layer and in contact with the first semiconductor layer;
A third semiconductor layer of a first conductivity type formed on a lower surface side of the second semiconductor layer and separated from the first semiconductor layer by the second semiconductor layer;
A trench formed on an upper surface of the semiconductor substrate, penetrating the first semiconductor layer and the second semiconductor layer and reaching the third semiconductor layer;
A gate insulating film covering the inner surface of the trench;
A gate electrode disposed inside the trench and insulated from the semiconductor substrate by the gate insulating film;
With
The second semiconductor layer has a second conductivity type impurity concentration higher in the outer peripheral portion than in the central portion of the cell region.

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