JP2018060587A - Semiconductor device and display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is new and has good reliability.SOLUTION: A semiconductor device includes a first transistor and a second transistor, and a first capacitor element and a second capacitor element. One of a source or a drain of the first transistor, one electrode of the first capacitive element, and a gate of the second transistor are electrically connected, and one of a source or a drain of the second transistor, one electrode of the second capacitive element, and the gate of the first transistor are electrically connected.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device and a display system.

  Note that one embodiment of the present invention is not limited to the above technical field. Technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, and the like Examples of the driving method or the manufacturing method thereof can be given.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, or the like is one embodiment of a semiconductor device. An imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

  In recent years, electronic components such as a central processing unit (CPU), a storage device, and a sensor are used in various electronic devices such as personal computers, smartphones, and digital cameras.

  Patent Document 1 describes a memory device including a transistor using an oxide semiconductor and a transistor using single crystal silicon. Further, it is described that a transistor including an oxide semiconductor has extremely small off-state current.

JP 2012-256400 A

  An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

  Note that one embodiment of the present invention does not necessarily have to solve all of the problems described above, and may be one that can solve at least one problem. Further, the description of the above problem does not disturb the existence of other problems. Issues other than these will be apparent from the description of the specification, claims, drawings, etc., and other issues will be extracted from the description of the specification, claims, drawings, etc. Is possible.

  One embodiment of the present invention includes a first transistor, a second transistor, a first capacitor, and a second capacitor, one of a source and a drain of the first transistor, and the first capacitor And the gate of the second transistor are electrically connected to each other, and one of the source and the drain of the second transistor, the one electrode of the second capacitor, and the gate of the first transistor Is a semiconductor device that is electrically connected.

  In the semiconductor device of one embodiment of the present invention, one of the source and the drain of the first transistor, the one electrode of the first capacitor, and the gate of the second transistor are connected to the first node. One of the source and the drain of the second transistor, the one electrode of the second capacitor, and the gate of the first transistor are electrically connected at the second node. The first potential may be held at the first node, and the second potential may be held at the second node.

  The semiconductor device according to one embodiment of the present invention does not hold the second potential when holding the first potential, and holds the first potential when holding the second potential. You don't have to.

  In the semiconductor device according to one embodiment of the present invention, when the first potential is held, the potential is applied to one of the source and the drain of the first transistor and the gate of the second transistor. At the time of holding, a potential may be applied to one of the source and the drain of the second transistor and the gate of the first transistor.

  In the semiconductor device according to one embodiment of the present invention, potentials having opposite polarities are applied to the gate insulator of the first transistor when the first potential is held and when the second potential is held. In addition, potentials having opposite polarities may be applied to the gate insulator of the second transistor when the first potential is held and when the second potential is held.

  In the semiconductor device of one embodiment of the present invention, the first transistor and the second transistor may use a metal oxide.

  In addition, a semiconductor device according to one embodiment of the present invention includes a first driver circuit, a second driver circuit, and first to fourth wirings, and the other of the source and the drain of the first transistor. And the first wiring is electrically connected, the other of the source and the drain of the second transistor is electrically connected, the second wiring is electrically connected, the other electrode of the first capacitor, 3 is electrically connected, the other electrode of the second capacitor and the fourth wiring are electrically connected, and the first driving circuit includes the first wiring and the second wiring. The second driver circuit may have a function of controlling the potentials of the third wiring and the fourth wiring.

  A display system according to one embodiment of the present invention includes a frame memory using the semiconductor device, a control circuit having an image processing unit, and a driver circuit, and a display unit. The frame memory stores image data. The image processing unit has a function of performing image processing on the image data input from the frame memory and generating a video signal, and the drive circuit is configured to output the video signal input from the image processing unit. Is output to the display unit.

  In the display system according to one embodiment of the present invention, the display portion includes a first display unit and a second display unit, and the first display unit includes a reflective liquid crystal element. The second display unit may have a light emitting element.

  According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Further, one embodiment of the present invention does not necessarily have all of these effects. Effects other than these will be apparent from the description of the specification, claims and drawings, and other effects will be extracted from the description of the specification, claims and drawings. Is possible.

4A and 4B illustrate a structure example of a semiconductor device according to one embodiment of the present invention and a structure example of a memory cell according to one embodiment of the present invention. FIG. 10 illustrates a structure example of a memory cell according to one embodiment of the present invention. 3 is a timing chart illustrating an example of a data write operation and a data read operation of a memory cell according to one embodiment of the present invention. FIG. 10 illustrates a structure example of a memory cell according to one embodiment of the present invention. FIG. 10 illustrates a configuration example of a memory device according to one embodiment of the present invention. FIG. 14 illustrates a configuration example of a computer according to one embodiment of the present invention. FIG. 10 illustrates a configuration example of a display system according to one embodiment of the present invention. 6A and 6B illustrate a structure example of a display device according to one embodiment of the present invention. 6A and 6B illustrate a structural example of a pixel of a display device according to one embodiment of the present invention. 6A and 6B illustrate a structural example of a pixel of a display device according to one embodiment of the present invention. FIG. 6 illustrates a structure example of a display device according to one embodiment of the present invention. FIG. 6 illustrates a structure example of a display device according to one embodiment of the present invention. 10A and 10B illustrate a structure example of a transistor according to one embodiment of the present invention. FIG. 6 illustrates an energy band structure of a transistor according to one embodiment of the present invention. The top view of a semiconductor wafer. The flowchart figure and perspective view which show the manufacturing process of an electronic component. FIG. 14 illustrates a structure example of an electronic device according to one embodiment of the present invention. FIG. 14 illustrates a structure example of an electronic device according to one embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description in the following embodiments, and those skilled in the art can easily understand that the forms and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

  One embodiment of the present invention includes, in its category, any device such as a semiconductor device, a memory device, a display device, an imaging device, and an RF (Radio Frequency) tag. In addition, the display device includes a liquid crystal display device, a light-emitting device including a light-emitting element typified by an organic light-emitting element in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission). Display) and the like are included in the category.

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, in the case where a metal oxide is used for a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short. In the case of describing as an OS FET, it can be said to be a transistor including a metal oxide or an oxide semiconductor.

  In this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

  Moreover, in this specification etc., it may describe as CAAC (c-axis aligned crystal) and CAC (cloud-aligned composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

  In this specification and the like, a CAC-OS or a CAC-metal oxide has a conductive function in part of a material and an insulating function in part of the material, and the whole material is a semiconductor. It has the function of. Note that in the case where a CAC-OS or a CAC-metal oxide is used for a channel formation region of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is This is a function of preventing electrons (or holes) from flowing. By performing the conductive function and the insulating function in a complementary manner, a switching function (a function for turning on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, the functions of both can be maximized by separating the functions.

  In this specification and the like, a CAC-OS or a CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

  In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

  Moreover, CAC-OS or CAC-metal oxide is comprised by the component which has a different band gap. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be called a matrix composite material or a metal matrix composite material.

  In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are directly connected and X and Y are electrically connected. And the case where X and Y are functionally connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and things other than the connection relation shown in the figure or text are also described in the figure or text. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

  As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

  As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a current flow path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

  As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

  In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And when X and Y are directly connected (that is, when X and Y are connected without interposing another element or another circuit), It is disclosed in this specification and the like. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that

  Moreover, the component to which the same code | symbol is attached | subjected between different drawings represents the same unless there is particular description.

  In addition, even in the case where independent components are illustrated as being electrically connected to each other in the drawing, one component may have the functions of a plurality of components. is there. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

(Embodiment 1)
In this embodiment, a semiconductor device and a memory device according to one embodiment of the present invention will be described.

<Configuration example of semiconductor device>
FIG. 1A illustrates a configuration example of the memory cell array 10 included in the semiconductor device according to one embodiment of the present invention. The memory cell array 10 has a plurality of memory cells MC. The memory cell MC is a circuit having a function of storing data. FIG. 1A shows a configuration example in which the memory cell array 10 includes m columns and n rows of memory cells MC. Hereinafter, a memory cell MC in x columns and y rows (x is an integer of 1 to m and y is an integer of 1 to n) is expressed as MC [x, y]. The plurality of memory cells MC can be used as the memory cell array 10 of the semiconductor device.

  The memory cell MC is connected to a plurality of wirings WL (wiring WLa, wiring WLb) and a plurality of wirings BL (wiring BLa, wiring BLb). The wiring WL has a function of supplying a potential for writing, reading, or holding data to the memory cells MC in a predetermined row. The wiring BL has a function of supplying a potential for writing, reading, or holding data to the memory cells MC in a predetermined column. In addition, the wiring BL has a function of transmitting a potential corresponding to data to be written to the memory cell MC (hereinafter also referred to as a write potential). Note that the wiring WLa, the wiring WLb, the wiring BLa, and the wiring BLb connected to MC [x, y] are respectively connected to the wiring WLa [y], the wiring WLb [y], the wiring BLa [x], and the wiring BLb [x]. write.

  FIG. 1A illustrates a configuration example in which the wiring WL is shared by the memory cells MC in the same row and the wiring BL is shared by the memory cells MC in the same column. However, these wirings may be provided individually for each memory cell MC.

  The memory cell MC can be composed of a transistor or a capacitor element. Here, a transistor having a metal oxide in a channel formation region (hereinafter also referred to as an OS transistor) is preferably used for the memory cell MC. Since a metal oxide has a larger band gap and a lower minority carrier density than a semiconductor such as silicon, the off-state current of a transistor in which a metal oxide is used for a channel formation region is extremely small. Therefore, in the case where an OS transistor is used for the memory cell MC, the potential held in the memory cell MC is maintained over a long period of time as compared with a case where a transistor including silicon in a channel formation region (hereinafter also referred to as Si transistor) or the like is used. Can be held. This eliminates the need for an operation (refresh operation) in which writing is performed again at a predetermined cycle, or the frequency of the refresh operation can be extremely reduced. In addition, data can be held for a long time even in a period in which signal supply to the memory cell MC is stopped. Therefore, power consumption in the memory cell array 10 can be reduced.

  FIG. 1B illustrates part of the structure of the memory cell MC according to one embodiment of the present invention. In one embodiment of the present invention, the memory cell MC includes a circuit MCa and a circuit MCb. Each of the circuit MCa and the circuit MCb has a function of storing data. The circuit MCa includes a transistor Tra and a capacitive element Ca. The circuit MCb includes a transistor Trb and a capacitor Cb.

  One of the source and the drain of the transistor Tra is connected to one electrode of the capacitor Ca, and the other of the source and the drain is connected to the wiring L1a. The other electrode of the capacitive element Ca is connected to the wiring L2a. Note that the wiring L1a and the wiring L2a are wirings to which predetermined signals are supplied. Here, a node connected to one of the source and drain of the transistor Tra and one electrode of the capacitor Ca is denoted as a node FNa. The node FNa has a function as a potential holding portion of the memory cell MC. Note that the circuit MCb also has a circuit configuration similar to that of the circuit MCa.

  The transistors Tra and Trb function as data write switches. Further, the wiring L1a and the wiring L1b have a function of transmitting a writing potential. When the transistor Tra is turned on, the potential of the wiring L1a is supplied to the node FNa through the transistor Tra. As a result, data is written to the circuit MCa. After that, when the transistor Tra is turned off, the node FNa is in a floating state, and data is held. In the circuit MCb, data is written and held by the same operation.

  Here, an OS transistor is preferably used as the transistor Tra and the transistor Trb which function as a data write switch. As described above, since the off-state current of the OS transistor is extremely small, the potentials of the node FNa and the node FNb can be held for a very long period in a period in which the transistor Tra and the transistor Trb are off. Therefore, power consumption in the memory cell MC can be reduced.

Note that the off-state current of the OS transistor normalized by the channel width is 10 × 10 ⁻²¹ A / μm (10 zept A / μm) or less when the source or drain voltage is 10 V and room temperature (about 25 ° C.). Is possible. The off-state current of the OS transistor used for the transistor Tra and the transistor Trb is preferably 1 × 10 ⁻¹⁸ A or less, or 1 × 10 ⁻²¹ A or less, or 1 × 10 ⁻²⁴ A or less at room temperature (about 25 ° C.). . Alternatively, the leak current is preferably 1 × 10 ⁻¹⁵ A or less, or 1 × 10 ⁻¹⁸ A or less, or 1 × 10 ⁻²¹ A or less at 85 ° C.

The metal oxide contained in the channel formation region of the OS transistor preferably contains at least one of indium (In) and zinc (Zn). As such a metal oxide, an In oxide, a Zn oxide, an In—Zn oxide, an In—M—Zn oxide (the element M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Or Hf) is typical. These metal oxides reduce impurities such as hydrogen, which are electron donors (donors), and reduce oxygen vacancies, thereby making the metal oxide an i-type semiconductor (intrinsic semiconductor), or an i-type semiconductor. It can be as close as possible. Such a metal oxide can be referred to as a highly purified metal oxide. For example, the carrier density of the metal oxide is less than 8 × 10 ¹⁵ cm ⁻³ , preferably less than 1 × 10 ¹¹ cm ⁻³ , more preferably less than 1 × 10 ¹⁰ cm ⁻³ , and 1 × 10 ⁻ It can be ⁹ cm ⁻³ or more.

  In addition, the metal oxide has a large band gap, electrons are not easily excited, and the effective mass of holes is large. For this reason, an OS avalanche breakdown may be less likely to occur in an OS transistor than in a Si transistor. By suppressing hot carrier deterioration caused by electron avalanche breakdown, the OS transistor has a high drain breakdown voltage, and can be driven with a high drain voltage. Therefore, by using OS transistors as the transistors Tra and Trb, the range of potentials held at the nodes FNa and FNb can be expanded.

  Note that transistors other than the OS transistor may be used as the transistor Tra and the transistor Trb. For example, in a substrate including a single crystal semiconductor other than a metal oxide, a transistor in which a channel is formed in part of the substrate may be used. Examples of such a substrate include a single crystal silicon substrate and a single crystal germanium substrate. Alternatively, a transistor in which a channel is formed in a film containing a semiconductor material other than a metal oxide may be used as the transistor Tra and the transistor Trb. Examples of such a film include an amorphous silicon film, a microcrystalline silicon film, a polycrystalline silicon film, a single crystal silicon film, an amorphous germanium film, a microcrystalline germanium film, a polycrystalline germanium film, or a single crystal germanium. Examples include membranes.

  As a capacitor element included in the memory cell MC, a parasitic capacitor formed by a transistor or a wiring included in the memory cell MC may be used. In addition, as a capacitor element included in the memory cell MC, a capacitor formed between the gate of the transistor included in the memory cell MC and the source or the drain may be used. Two or more capacitor elements connected to the node FNa or / and the node FNb may be provided.

  Here, in one embodiment of the present invention, the gate of the transistor Tra is connected to the node FNb, and the gate of the transistor Trb is connected to the node FNa. Therefore, the conduction states of the transistors Tra and Trb can be controlled by the potentials of the nodes FNb and FNa, respectively.

  In one embodiment of the present invention, the node FNa is connected to the wiring L2a through the capacitor Ca. Therefore, by changing the potential of the wiring L2a, the potential of the node FNa can be controlled using the capacitive coupling of the capacitor Ca. Similarly, by changing the potential of the wiring L2b, the potential of the node FNb can be controlled by using the capacitive coupling of the capacitor Cb.

  Here, for example, when the memory cell MC has only the circuit MCa, when the data of the memory cell MC is held, only a constant potential is held at the node FNa. This is because the memory cell MC can hold either a constant positive (or negative) potential (hereinafter also referred to as data “1”) or 0 V (hereinafter also referred to as data “0”) at the node FNa 2. In the case of a value memory cell, a positive (or negative) potential is applied to only one of the source and drain of the transistor Tra when data “1” is held, and any electrode ( A positive (or negative) potential is not applied to the source, drain, and gate. That is, in the case where the memory cell MC has only the circuit MCa, only one type of stress called a positive (or negative) potential continues to be applied to one of the source and drain of the transistor Tra when data “1” is held. It will be. For this reason, in the case where the memory cell MC has only the circuit MCa, the deterioration of the transistor Tra may be induced / accelerated due to the applied stress caused by the retention of the data “1”. When the electrical characteristics (threshold voltage, off-state current, etc.) of the transistor Tra change due to the deterioration, there are cases where data read / write and retention in the circuit MCa (memory cell MC) are hindered.

  However, in one embodiment of the present invention, two circuits (the circuit MCa and the circuit MCb) are electrically connected as illustrated in FIG. 1B, and this is configured as one memory cell MC. As a result, the deterioration of the transistor Tra described above can be suppressed. Details will be described below.

  As shown in FIG. 1B, the gate of the transistor Tra and the node FNb are connected, and one of the source or drain of the transistor Tra and the node FNa are connected. Also. The gate of the transistor Trb and the node FNa are connected, and one of the source or drain of the transistor Trb and the node FNb are connected. Here, the data “1” is a combination in which a constant positive potential is held at the node FNa and 0 V is held at the node FNb, 0 V is held at the node FNa, and a constant positive potential is held at the node FNb. The defined combination is redefined as data “0”. For example, when the memory cell MC is a binary memory cell capable of holding either the data “1” or the data “0”, when holding the data “1”, one of the source and drain of the transistor Tra and the transistor Trb are stored. A positive potential is applied to the gate of the transistor Tr. When data “0” is held, a positive potential is applied to one of the source or drain of the transistor Trb and the gate of the transistor Tra. Considering this as the reference (0 V) of one of the source and drain of each transistor, it is equivalent to applying a negative potential to the gate insulator (node FNa side) of the transistor Tra when data “1” is retained. When data “0” is held, the state is equivalent to the case where a negative potential is applied to the gate insulator (node FNb side) of the transistor Trb.

  That is, in the memory cell MC shown in FIG. 1B, when data “1” is held, a negative gate bias stress (hereinafter also referred to as “-GBS”) is applied to the transistor Tra. Further, since the node FNa in which the positive potential is held is connected to the gate of the transistor Trb, a positive gate bias stress (hereinafter also referred to as + GBS) is applied to the transistor Trb. Similarly, when data “0” is held, + GBS is applied to the transistor Tra and −GBS is applied to the transistor Trb (see Table 1).

  Thus, according to one embodiment of the present invention, when the data “1” and the data “0” are held in the memory cell MC, stresses (+ GBS and −GBS) having opposite polarities are applied to the transistor Tra and the transistor Trb, respectively. Applied. As a result, when data is held in the memory cell MC, only the stress having either polarity of + GBS or −GBS is not applied to the transistor Tra and the transistor Trb. For example, even if the transistor Tra (transistor Trb) deteriorates due to -GBS (+ GBS) when data "1" is held, the transistor Tra (transistor Trb) deteriorates due to + GBS (-GBS) when data "0" is held. By doing so, each deterioration can be offset.

  As described above, by applying the configuration in FIG. 1B to the memory cell MC, deterioration of the transistor Tra and the transistor Trb and variation in characteristics are reduced, and the reliability of the memory cell array 10 in FIG. Can be improved. Hereinafter, specific configuration examples and operation examples of the memory cell MC having the above configuration will be described in detail.

<Configuration example of memory cell>
FIG. 2 illustrates a specific configuration example of the memory cell MC according to one embodiment of the present invention. FIG. 2 shows the memory cell MC [1,1], the memory cell MC [2,1], the memory cell MC [1,2], and the memory cell MC [2,2] as representative examples. Other memory cells MC can have the same configuration.

  The memory cell MC [1,1], the memory cell MC [2,1], the memory cell MC [1,2], and the memory cell MC [2,2] each include a circuit MCa and a circuit MCb. The circuit MCa includes a transistor Tra and a capacitor Ca. The circuit MCb includes a transistor Trb and a capacitor Cb.

  The gate of the transistor Tra is connected to the node FNb, one of the source and the drain is connected to the gate of the transistor Trb and one electrode of the capacitor Ca at the node FNa, and the other of the source or the drain is connected to the wiring BLa. . The other electrode of the capacitive element Ca is connected to the wiring WLa. The gate of the transistor Trb is connected to the node FNa, one of the source and the drain is connected to the gate of the transistor Tra and one electrode of the capacitor Cb at the node FNb, and the other of the source and the drain is connected to the wiring BLb. . The other electrode of the capacitor Cb is connected to the wiring WLb.

  In FIG. 2, the memory cell MC (here, the memory cell MC [1,1] and the memory cell MC [2,1] or MC [1,2] and MC [2, 2]), and the wiring BLa and the wiring BLb are in the same column of the memory cells MC (here, the memory cell MC [1,1] and the memory cell MC [1,2], or the memory cell MC The configuration example is shared by [2,1] and the memory cell MC [2,2]). However, these wirings may be provided individually for each memory cell MC.

  The wiring WLa has a function of supplying a potential for writing, reading, or holding data to the memory cell MC to the node FNa of the memory cell MC in a predetermined row. Since the wiring WLa is connected to the node FNa through the capacitive element Ca, the potential of the node FNa can be controlled by using the capacitive coupling of the capacitive element Ca by controlling the potential of the wiring WLa. . Further, since the node FNa is connected to the gate of the transistor Trb, the conduction state of the transistor Trb can be controlled by controlling the potential of the wiring WLa. Similarly, by controlling the potential of the wiring WLb, the potential of the node FNb can be controlled, and the conduction state of the transistor Tra can be controlled.

  The wiring BLa has a function of supplying a potential for writing, reading, or holding data to the memory cell MC to the node FNa of the memory cell MC in a predetermined column. Since the wiring BLa is connected to the other of the source and the drain of the transistor Tra, the potential from the wiring BLa is changed to the node FNa through the transistor Tra by turning on the transistor Tra by controlling the potential of the wiring WLb. Can be supplied to. Similarly, the potential from the wiring BLb can be supplied to the node FNb through the transistor Trb.

  As described above, by appropriately combining the potential supply from the wiring WL (the wiring WLa and the wiring WLb) and the potential supply from the wiring BL (the wiring BLa and the wiring BLb), data can be written to the memory cell MC. The potential for performing can be supplied to the node FNa and the node FNb.

  As described above, the memory cell MC according to one embodiment of the present invention has the above-described circuit structure, so that a positive (or negative) potential is supplied (written) to each of the node FNa and the node FNb and held. Can do. For example, when the memory cell MC is a binary memory cell that can hold either the data “1” or the data “0”, the wiring WLa uses the capacitive coupling of the capacitor Ca when writing the data “1”. Thus, the potential of the node FNa is controlled to be positive (or negative), and the wiring WLb has a function of controlling the potential of the node FNb to 0 V by using capacitive coupling of the capacitor Cb. On the other hand, when data “0” is written, the wiring WLa has a function of controlling the potential of the node FNa to 0 V using the capacitive coupling of the capacitive element Ca, and the wiring WLb uses the capacitive coupling of the capacitive element Cb. , Has a function of controlling the potential of the node FNb to be positive (or negative). As a result, stresses (+ GBS, −GBS) having opposite polarities are applied to the transistor Tra and the transistor Trb when the data “1” is held and when the data “0” is held in the memory cell MC. The deterioration of the transistor Tra and the transistor Trb can be suppressed. Hereinafter, a specific operation example of the memory cell MC when a positive (or negative) potential is supplied to and held in the node FN will be described.

<Operation example of memory cell>
FIG. 3 is a timing chart illustrating an example of an operation of writing data to the memory cell MC according to one embodiment of the present invention and an operation of reading written (stored) data.

  Hereinafter, a case where 1-bit (binary) data is stored in each of the memory cells MC in FIG. 2 will be described. Here, as a specific example, the state where the potential of the node FNa is positive and the potential of the node FNb is 0 V corresponds to the state where data “1” is stored in the memory cell MC, the potential of the node FNa is 0 V, and the node FNb A case where the state where the potential is positive corresponds to the state where data “0” is stored in the memory cell MC will be described.

  Note that the potentials of the node FNa and the node FNb are not limited to the above. In other words, the node FNa and the node FNb can hold not only binary values of positive and zero but also potentials of three or more values. In this case, the amount of information that can be stored in the memory cell MC can be increased. Further, the correspondence between the potentials of the nodes FNa and FNb and the data is not limited to the above, and can be arbitrarily defined.

[Data write operation]
First, an example of a data writing operation to the memory cell MC [1,1] illustrated in FIG. 2 will be described with reference to a timing chart illustrated in FIG. In FIG. 3, a period T1 is a period in which data “1” is written, and a period T3 is a period in which data “0” is written.

  Note that a potential of 0 V is held at the node FNa and the node FNb immediately before the period T1.

  First, in the period T1, a positive potential (+ V) is applied to the wiring WLb [1]. Then, the transistor Tra is turned on, and the positive potential (+ V) applied to the wiring BLa [1] is gradually supplied to the node FNa through the transistor Tra. At this time, by setting the potentials of the wirings WLa [1] and BLb [1] to 0V, the potential of the node FNb is decreased to 0V. Accordingly, a potential of + V is supplied to the node FNa and a potential of 0 V is supplied to the node FNb, so that data “1” is written in the memory cell MC [1, 1]. Note that in the timing chart in FIG. 3, the potential applied to the wiring WLb [1] and the potential applied to the wiring BLa [1] are both + V; however, the potentials may be different from each other. When the writing of data “1” to the memory cell MC is completed, the potentials of the wiring WLb [1] and the wiring BLa [1] are returned to 0V as shown in a period T2.

  Next, in the period T3, a positive potential (+ V) is applied to the wiring WLa [1]. Then, the transistor Trb is turned on, and the positive potential (+ V) applied to the wiring BLb [1] is supplied to the node FNb through the transistor Trb. When the potential of + V is supplied to the node FNb, the transistor Tra is also turned on. At this time, since the potential of the wiring BLa [1] is 0V, the positive potential (+ V) supplied to the node FNa by writing the data “1” described above is decreased to 0V. In FIG. 3, the potential fluctuations of the node FNa and the node FNb at the time of writing data “0” (period T3) are sharply shown compared to the above-described data “1” writing (period T1). In FIG. 3, since the positive potential (+ V) is already supplied to the node FNa before the data “0” is written, the timing at which the transistor Trb becomes conductive after the potential is supplied from the wiring WLa. This is to speed up. Accordingly, the potential supply speed to the node FNb through the transistor Trb is increased, and accordingly, the timing at which the transistor Tra is turned on and the timing at which the potential (0 V) is supplied to the node FNa are also advanced. As in the above example, the node FNa is supplied with 0V potential and the node FNb is supplied with + V potential, so that data “0” is written in the memory cell MC [1,1]. Note that in the timing chart shown in FIG. 3, the potential applied to the wiring WLa [1] and the potential applied to the wiring BLb [1] are both + V; however, different potentials may be used. When writing of data “0” to the memory cell MC [1,1] is completed, the potentials of the wiring WLa [1] and the wiring BLb [1] are returned to 0V as shown in a period T4.

  As described above, by controlling the potentials of the wiring WL [1] (wiring WLa [1], wiring WLb [1]) and the wiring BL [1] (wiring BLa [1], wiring BLb [1]), Data “1” or data “0” can be written to the memory cell MC [1, 1] by controlling the potentials of the node FNa and the node FNb.

  Note that the data rewrite operation is collectively performed on the memory cells MC in the same row having the same wiring WL (wiring WLa, wiring WLb). FIG. 3 illustrates an example in which the wiring WLa [1] and the wiring WLb [1] are selected and data is written to the memory cell MC [1,1]. At this time, similarly, writing to the memory cells MC [2, 1] in the same row sharing the wiring WLa [1] and the wiring WLb [1] is also preferable. The memory cells MC in the same row sharing the data “1” or the data “0” sharing the wiring WLa [1] and the wiring WLb [1] when the positive potential is written are written for each memory cell MC. Also good. Alternatively, at the time of writing, the wiring WLa [1] and the wiring WLb [1] are simultaneously raised to a positive potential (+ V), and the wiring WLa [1] and the wiring WLb [1] are connected to the memory cells MC in the same row. On the other hand, a voltage corresponding to data “1” or data “0” may be applied to each wiring BL, and data “1” or data “0” may be written simultaneously.

  In addition, when data is written in a memory cell MC in a selected row, a potential is supplied to the memory cells MC in other non-selected rows so that the transistors Tra and Trb can be kept off. It is preferable. For example, when data is written by selecting the memory cell MC [1,1] in FIG. 2, the wiring WLa [2] and the wiring WLb [connected to the memory cells MC [1,2] and MC [2,2]. 2] is preferably applied with a certain negative potential (-V) (see FIG. 3). Thereby, it is possible to prevent unintended data fluctuations in the non-selected memory cells MC. Note that the voltage applied to the non-selected wiring WLa [2] and the wiring WLb [2] is −V, but the voltage applied to the non-selected wiring WLa [2] and the wiring WLb [2] is not selected in the memory. The transistors Tra and transistor Trb of the cell MC [1,2] and the memory cell MC [2,2] are turned off by capacitive coupling via the capacitors Ca and Cb regardless of the data holding state of the nodes FNa and FNb. Any potential can be used, and a negative potential having an absolute value different from the positive potential (+ V) used in writing may be used. If the transistor Tra and the transistor Trb of the non-selected memory cell MC [1,2] or the memory cell MC [2,2] are in the OFF state, the non-selected memory cell MC [1 in the column in which the wiring BLa and the wiring BLb are shared. , 2] or the potential of the node FNa and the node FNb of the memory cell MC [2,2] and the potential of writing entering the wiring BLa and the wiring BLb, so that erroneous rewriting can be prevented.

[Data read operation]
Next, an example of a data read operation from the memory cell MC [1,1] illustrated in FIG. 2 will be described with reference to a timing chart illustrated in FIG. In FIG. 3, a period T5 to a period T7 are periods in which data “0” stored in the memory cell MC is read. That is, immediately before the period T5, a potential of 0 is held at the node FNa and a positive potential (+ V) is held at the node FNb.

  First, in the period T5, a negative potential (−V) is applied to the wiring WL (the wiring WLa and the wiring WLb) connected to each memory cell MC. This is to prevent erroneous writing from the precharge potential applied to the wiring BL (wiring BLa, wiring BLb) to the selected memory cell MC and the non-selected memory MC when performing precharging described later. . Here, the negative potential is not limited to −V, and may be any potential that allows the transistor Tra and the transistor Trb in the memory cell MC to be turned off regardless of the data holding states of the nodes FNa and FNb. That's fine. Note that a potential is written to the node FNa and the node FNb in a data “1” state or a data “0” state by a writing operation, but in reality, it can be said that a charge corresponding to the potential is given. In addition, the node FNa and the node FNb can be arbitrarily set to potentials by capacitive coupling via the capacitance Ca and the capacitance Cb from the potential of the wiring WL (wiring WLa, wiring WLb) or the like while holding charges according to the potential at the time of the writing operation. Can be changed. Therefore, the transistor Tra and the transistor Trb can be turned off by applying a negative potential (−V) to the wiring WL (the wiring WLa and the wiring WLb).

Next, in a period T6, a positive precharge potential (+ V _P ) is applied to the wiring BLa [1] and the wiring BLb [1] connected to the selected memory cell MC [1,1]. The precharge potential is a reference potential for identifying whether data “1” or data “0” is stored in the selected memory cell MC [1, 1]. For example, the potential (both + V _P ) applied to the wiring BLa [1] and the wiring BLb [1] connected to the selected memory cell MC [1,1] by potential supply to each wiring described later is larger than this. It can be changed to a potential or a small potential. This potential fluctuation by (in the wiring BLa [1] to the wiring BLb [1], which varies in greater potential than + V _P, Which is varied to smaller potential than + V _P.) Monitoring, selection It is possible to identify whether data “1” or data “0” is stored in the memory cell MC [1, 1]. As shown in FIG. 3, it is assumed that + V _P is a potential smaller than + V.

Next, in a period T7, a positive potential (+ V) is applied to the wiring WLa [1] and the wiring WLb [1] connected to the selected memory cell MC [1,1]. Then, due to the capacitive coupling of the capacitive element Ca and the capacitive coupling of the capacitive element Cb in the selected memory cell MC [1, 1], the potential applied to the gates of the transistor Tra and the transistor Trb of the selected memory cell MC [1, 1] increases. Both of the transistors become conductive. Accordingly, the node FNa in the selected memory cell MC [1,1] and the wiring BLa [1] connected to the selected memory cell MC [1,1] and the node in the selected memory cell MC [1,1] Between FNb and the wiring BLb [1] connected to the selected memory cell MC [1,1], the capacitance Ca and the capacitance Cb and the wiring capacitance of the wiring BLa [1] and the wiring BLb [1] are stored. Redistribution of generated charges is performed. In the timing chart shown in FIG. 3, data “0” is stored in the selected memory cell MC [1,1] at a time T4 before the read operation (period T5 to period T7) is performed. In other words, the node FNa of the selected memory cell MC [1,1] is supplied with 0V potential and the node FNb is supplied with + V potential. Therefore, the potential of the wiring BLa [1] is decreased from + V _P to a lower potential (+ V _L ), and the potential of the wiring BLb [1] is increased from + V _P to a higher potential (+ V _H ). To rise. By monitoring this potential fluctuation, it is possible to identify that the data “0” is stored in the selected memory cell MC [1, 1]. Although not shown in the timing chart of FIG. 3, when the potential of the wiring BLa [1] increases to + V _H and the potential of the wiring BLb [1] decreases to + _VL , the selected memory cell MC It is identified that the data “1” is stored in [1, 1].

  Note that in the period T4 before the reading period T5, the data “0” is stored in the selected memory cell MC [1,1], and in the case of the data “0”, the node FNb is positive. Since the potential (+ V) is held, the transistor Tra is in a conductive state, and the node FNa and the wiring BLa [1] are in a conductive state. For this reason, the node FNa is in a state that does not necessarily hold the 0 V potential in the storage state of the data “0”. However, in the period T4 immediately before a negative potential (−V) is applied to the wiring WLb [1] in order to turn off the transistor Tra in the period T5, the potential of the node FNa is applied by applying 0V to the wiring BLa [1]. Can be fixed at 0V. In the case of data “1” other than the example of FIG. 3, the potential of the node FNb can be similarly fixed to 0 V immediately before reading.

Further, when a positive potential (+ V) is applied to the wiring WLa [1] and the wiring WLb [1] in the period T7, the wiring BLa [1] and the wiring BLb [connected to the selected memory cell MC [1,1]. reference potential + _{V P} precharging of 1], capacitance Ca and the capacitance Cb of the capacitance and wiring BLa, wiring BLb, the capacitive coupling of the parasitic capacitance of the wiring WLa and wiring WLb, there may be a slightly higher potential fluctuates. In this case, data "1" and data "0" to the variable potential amount to the reference potential + V _P identifies the potential may be a reference to the addition.

Alternatively, in the period T7, a positive precharge potential (+ V _P ) supplied from the wiring BLa [1] and the wiring BLb [1] instead of the positive potential (+ V) to the wiring WLa [1] and the wiring WLb [1]. 0V may be applied if the transistor Tra and the transistor Trb can be turned on by a potential (+ V _L ) slightly smaller than). In a period T7 in FIG. 3, the state where data “0” is stored in the selected memory cell MC [1, 1] is to be read. In this case, the node FNa of the selected memory cell MC [1,1] is supplied with 0V potential and the node FNb is supplied with + V potential, and the wiring WLa [1] and the wiring WLb [1] are set to 0V. However, the transistor Tra of the selected memory cell MC [1,1] is in a conductive state. The other transistor Trb of the selected memory cell MC [1,1] is supplied with a positive precharge potential (+ V _P ) to the wiring BLa [1], whereby the node FNa is connected via the transistor Tra in a conductive state. Is supplied with a potential (+ V _L ) by charge redistribution. In the case where the transistor Trb can be turned on by this potential (+ V _L ), the wiring WLa [1] and the wiring WLb [1] may be 0V. Once the transistor Trb is conductive, via the transistor Trb, a node FNb wiring BLb [1] occurs redistribution of charges between the wiring BLb [1] greater potential than the potential + _{V P} of the (+ V _H ). By monitoring this potential fluctuation, it is possible to identify that the data “0” is stored in the selected memory cell MC [1, 1]. Data “1” can also be identified in a similar manner.

  By the above-described data read operation, the storage state (0V at the node FNa and + V at the node FNb) before the read in the selected memory cell MC [1,1] is lost (destructive read). Therefore, for example, a sense amplifier or the like is provided outside the memory cell MC, and the selected memory cell MC [1, 1] as shown in the period T8 is connected to the wiring BLa [1] corresponding to the storage state data “0” before reading. A refresh operation for applying 0V and + V to the wiring BLb [1] is performed. As a result, 0 V is written to the node FNa corresponding to the storage state data “0” of the selected memory cell MC lost by the destructive reading described above, and + V is written to the node FNb by the refresh operation, and then each wiring WL (wiring WLa, wiring WLb), each wiring BL (wiring BLa, wiring BLb) can be returned to 0 V, and the memory state before destructive reading can be restored (period T9).

  Note that, as with the above-described data write operation, the data read operation is collectively performed on the memory cells MC in the same row having the same wiring WL (wiring WLa, wiring WLb). When data is read from a memory cell MC in a certain row, it is preferable to supply a potential at which the transistors Tra and Trb can be kept off to the memory cells MC in other rows. For example, when data is read by selecting the memory cell MC [1,1] in FIG. 2, the wiring WLa [2] and the wiring WLb [connected to the memory cells MC [1,2] and MC [2,2]. 2] is preferably applied with a negative potential (-V) (see FIG. 3). Accordingly, it is possible to prevent an unintended potential from being output to the wiring BLa and the wiring BLb from the non-selected memory cell MC.

[Data retention operation]
The memory cell MC can hold the potential of the node FN regardless of whether the potential of the node FN is positive (or negative) or zero.

  When data “1” is stored in the memory cell MC [1, 1], a positive potential (+ V) is supplied to the node FNa, and a potential of 0 V is supplied to the node FNb. Therefore, the transistor Tra is turned off, and the potential (+ V) of the node FNa can be held. Although the transistor Trb is turned on by the potential (+ V) of the node FNa, the wiring WL [1] (the wiring WLa [1], the wiring WLb [1]) and the wiring BL which are connected to the memory cell MC [1,1]. If a potential of 0V is applied to [1] (wiring BLa [1], wiring BLb [1]), the potential difference between the wiring BLb [1] (potential 0V) and the node FNb (potential 0V) is 0V. Therefore, the potential 0 V supplied to the node FNb is maintained. Therefore, data “1” can be held in the memory cell MC [1,1] (see the period T2 in FIG. 3).

  When data “0” is stored in the memory cell MC [1, 1], the node FNa is supplied with 0V potential and the node FNb is supplied with positive potential (+ V). Therefore, the transistor Trb is turned off, and the potential (+ V) of the node FNb can be held. Although the transistor Tra is turned on by the potential (+ V) of the node FNb, the wiring WL [1] (the wiring WLa [1], the wiring WLb [1]) and the wiring BL [1] (wiring) connected to the memory cell MC If a potential of 0V is applied to BLa [1] and wiring BLb [1]), the potential difference between the wiring BLa [1] (potential 0V) and the node FNa (potential 0V) becomes 0V. The potential 0 V supplied to FNa is maintained. Therefore, data “0” can be held in the memory cell MC [1,1] (see the period T4 in FIG. 3).

  For example, when data “0” is stored in the memory cell MC [1,1], the negative potentials (wires WLa, WLb) in all the wirings WL (wiring WLa, wiring WLb) as in the period T5 in FIG. Even when −V) is applied to turn off the transistor Tra and the transistor Trb, data can be retained. By turning off the transistor Tra and the transistor Trb, for example, the node FNa and the node FNb in the data “0” are held at the node FNa and the node FNb with a charge corresponding to a positive potential (+ V). Can do.

  Hereinafter, the stress applied to the transistor Tra and the transistor Trb when the data “1” and the data “0” of the memory cell MC [1, 1] are held will be described. When data “1” is held in the memory cell MC [1, 1], a positive potential (+ V) is applied to one of the source and drain of the transistor Tra (on the node FNa side), and the other of the source and drain (the wiring BLa [1] ] And the gate are applied with a potential of 0V. A positive potential (+ V) is applied to the gate of the transistor Trb, and a potential of 0 V is applied to the source and drain. On the other hand, when data “0” is held in the memory cell MC [1, 1], a positive potential (+ V) is applied to the gate of the transistor Tra, and a potential of 0 V is applied to the source and drain. Then, a positive potential (+ V) is applied to one of the source and the drain (the node FNb side) of the transistor Trb, and a potential of 0 V is applied to the other of the source and the drain (the side connected to the wiring BLb [1]) and the gate. Applied. This is because, when the potential of one of the sources or drains (node FNa side and node FNb side) of each transistor is considered as a reference (0 V), when holding data “1” in the memory cell MC, the gate insulator ( A negative gate bias stress (-GBS) is applied to the node FNa side, and a positive gate bias stress (+ GBS) is applied to the gate insulator of the transistor Trb. Similarly, when data “0” is held in the memory cell MC, a negative gate bias stress (−GBS) is applied to the gate insulator (node FNb side) of the transistor Trb, and a positive gate bias is applied to the gate insulator of the transistor Tra. The state is equivalent to the application of stress (+ GBS) (see Table 1).

  Thus, according to one embodiment of the present invention, when the data “1” and the data “0” are held in the memory cell MC, stresses (+ GBS and −GBS) having opposite polarities are applied to the transistor Tra and the transistor Trb, respectively. Applied. As a result, when data is held in the memory cell MC, only the stress having either polarity of + GBS or −GBS is not applied to the transistor Tra and the transistor Trb. Therefore, deterioration of the transistor Tra and the transistor Trb due to the data holding operation of the memory cell MC can be suppressed.

  In addition, when data “1” is retained (data “0” is retained), a positive potential (+ V) is applied to the gate of the transistor Trb (transistor Tra). It may be injected into the gate insulator of the transistor Trb (transistor Tra) and cause deterioration in which the threshold voltage of the transistor Trb (transistor Tra) changes. However, in one embodiment of the present invention, when the data stored in the memory cell MC is switched from the data “1” (data “0”) to the data “0” (data “1”), the transistor Trb (transistor Tra) Since a negative potential (−V) is applied to the gate, ions or particles having a negative charge are released from the gate insulator of the transistor Trb (transistor Tra) to repair the above-described deterioration. Can do.

  Assuming that the probabilities that the data “1” and the data “0” are stored in the memory cells MC are almost equal, from Table 1, positive and negative stresses (+ GBS and −GBS) are equally applied to the transistors Tra and Trb. Will be applied. Therefore, deterioration of the transistor Tra and the transistor Trb can be more effectively suppressed. Note that when the holding period of specific data stored in the memory cell MC is expected to be long, an operation of intentionally changing the memory cell MC storing data is performed and applied to the transistor Tra and the transistor Trb. Voltage stress may be controlled. As described above, according to one embodiment of the present invention, a semiconductor device having favorable reliability can be provided.

  Note that in order to realize data retention in the memory cell MC for a long time, the off-state current of the transistor Tra and the transistor Trb constituting the memory cell MC (Vd of the Vg-Id characteristic may be referred to as Id at Vg = 0V). ) Should be as small as possible. In the transistor Tra and the transistor Trb according to one embodiment of the present invention, when a metal oxide is used for a channel formation region, the off-state current of the transistor can be significantly reduced as compared with the case where Si or the like is used. Therefore, the semiconductor device according to one embodiment of the present invention can hold data for an extremely long time. In addition, since the data can be retained for a long time, the refresh operation of the memory cell MC becomes unnecessary or the frequency of the refresh operation can be extremely reduced. Therefore, in one embodiment of the present invention, a semiconductor device with extremely low power consumption can be provided.

  As described above, in the memory cell array 10 according to one embodiment of the present invention, both good reliability and low power consumption can be realized.

<Modification of memory cell>
The circuit configuration of the memory cell MC according to one embodiment of the present invention is not limited to that illustrated in FIG. FIG. 4 illustrates another configuration example of the memory cell MC according to one embodiment of the present invention.

  The memory cell MC illustrated in FIG. 4A is different from FIG. 2 in that the transistor Tra and the transistor Trb have a pair of gates. Note that in the case where a transistor includes a pair of gates, one gate may be referred to as a first gate, a top gate, or simply a gate, and the other gate may be referred to as a second gate or a bottom gate. Hereinafter, of the pair of gates included in the transistor included in the memory cell MC illustrated in FIG. 4A, the gate included in the transistor in FIG. 2 is simply referred to as a gate, and the gate not included is referred to as a bottom gate. Call.

  In the memory cell MC shown in FIG. 4A, the bottom gate of the transistor Tra is connected to the gate of the transistor, and the bottom gate of the transistor Trb is connected to the gate of the transistor. In this case, since the gate potential and the bottom gate potential of each transistor are equal, in the transistor illustrated in FIG. 4A, the same potential is applied to the channel formation region from both the gate and the bottom gate. Accordingly, the electric field controllability by the gate and the bottom gate in the channel formation region is improved in the transistor illustrated in FIG. 4A than in the transistor illustrated in FIG. Thereby, the transistor shown in FIG. 4A can more easily control the electric field control of the gate and the bottom gate than the electric field between the source and the drain, and the switching characteristics of the transistor can be improved as compared with the transistor shown in FIG. .

  For example, when the memory cell MC illustrated in FIG. 4A performs data “1” writing (data “0” writing), a positive potential (+ V) is applied to both the gate and the bottom gate of the transistor Tra (transistor Trb). Applied. As described above, the electric field controllability by the gate and the bottom gate in the channel formation region of the transistor Tra (transistor Trb) is higher than that of the memory cell MC shown in FIG. Tra (transistor Trb) can be turned on. That is, the potential (+ V) can be supplied to the node FNa (node FNb) more reliably than the memory cell MC shown in FIG.

  For example, when the memory cell MC shown in FIG. 4A holds data “1” (data “0”), a potential of 0 V is applied to both the gate and the bottom gate of the transistor Tra (transistor Trb). Is done. As described above, the electric field controllability by the gate and the bottom gate in the channel formation region of the transistor Tra (transistor Trb) is higher than that of the memory cell MC shown in FIG. Tra (transistor Trb) can be turned off. That is, the potential (+ V) supplied to the node FNa (node FNb) can be prevented more reliably than the memory cell MC shown in FIG. 2 from leaking through the transistor Tra (transistor Trb). Accordingly, the memory cell MC illustrated in FIG. 4A can achieve data retention for a longer period than the memory cell MC illustrated in FIG.

  In the memory cell MC shown in FIG. 4B, each bottom gate of the transistor Tra and the transistor Trb is connected to the wiring BGL. The wiring BGL is a wiring having a function of supplying a predetermined potential to the bottom gate. By controlling the potential of the wiring BGL, the threshold voltage of the transistor Tra and the transistor Trb can be individually controlled by the bottom gate separately from the control by the gate. That is, the threshold voltage for the gates of the transistors Tra and Trb can be changed and controlled by the potential of the bottom gate.

  Note that the wiring BGL connected to the transistor Tra and the wiring BGL connected to the transistor Trb can be individually provided. Further, the wiring BGL may be shared by all the memory cells MC included in the memory cell array 10 or may be shared by some of the memory cells MC. In addition, the potential supplied to the wiring BGL may be a fixed potential (single potential) or a varying potential (plural potentials). In the case where a potential that fluctuates is supplied to the wiring BGL, for example, the thresholds of the transistor Tra and the transistor Trb are changed by changing the potential of the wiring BGL between a period in which the transistor Tra and the transistor Trb are turned on and a period in which the transistor Trab is turned off. The voltage may be changed.

  As described above, in one embodiment of the present invention, a semiconductor device including a memory cell MC including two transistors (a transistor Tra and a transistor Trb) and two capacitors (a capacitor Ca and a capacitor Cb). Can be provided. For example, when the memory cell MC is a binary memory cell that can hold either data “1” or data “0”, each wiring connected to the memory cell MC has a predetermined potential at an appropriate timing. Thus, deterioration of the transistor Tra and the transistor Trb due to the memory cell holding operation can be suppressed. Thus, according to one embodiment of the present invention, a semiconductor device having favorable reliability can be provided.

  Further, in one embodiment of the present invention, by using a transistor (OS transistor) including a metal oxide for the memory cell MC, the off-state current of the transistor can be significantly reduced as compared with the case where Si or the like is used. . Thus, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

  This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 2)
In this embodiment, a structure example of a memory device using the memory cell array 10 described in the above embodiment will be described.

  FIG. 5 shows a configuration example of the storage device 100. The storage device 100 includes a cell array 110 and a drive circuit unit 120.

  The cell array 110 includes a plurality of memory cells MC and has a function of storing data. As the cell array 110, the memory cell array 10 described in the above embodiment can be used.

  The drive circuit unit 120 includes a drive circuit 130, a drive circuit 140, a control circuit 160, and an output circuit 170. The driver circuit 130 has a function of controlling the potential of the wiring WL (the wiring WLa and the wiring WLb). The driver circuit 140 has a function of controlling the potential of the wiring BL (the wiring BLa and the wiring BLb).

  The drive circuit 130 includes a decoder 131, a row driver 132, and a sense amplifier 133.

  The decoder 131 has a function of decoding an address signal ADDR input from the outside and supplying a control signal to the row driver 132 or the sense amplifier 133.

  The row driver 132 has a function of selecting the wiring WLa and the wiring WLb connected to the memory cells MC in a predetermined row and a function of supplying a potential for writing or reading data to or from the wiring WLa or the wiring WLb. The selection of the wiring WLa and the wiring WLb is performed based on a control signal input from the decoder 131. Further, when data is written, a potential supplied to the wiring WLa and the wiring WLb is generated using data WDATA input from the outside. Data WDATA corresponds to data to be written in the cell array 110.

  The sense amplifier 133 has a function of amplifying the potential generated by the row driver 132 and supplying the amplified potential to the wiring WLa and the wiring WLb. Note that if it is not necessary to amplify the potential generated by the row driver 132, the sense amplifier 133 can be omitted.

  The drive circuit 140 includes a decoder 141, a column driver 142, a sense amplifier 143, and a precharge circuit 144.

  The decoder 141 has a function of decoding an address signal ADDR input from the outside and supplying a control signal to the column driver 142 or the sense amplifier 143.

  The column driver 142 has a function of selecting the wirings BLa and BLb connected to the memory cells MC in a predetermined column and a function of supplying a potential for writing or reading data to or from the wirings BLa and BLb. The selection of the wiring BLa and the wiring BLb is performed based on a control signal input from the decoder 141. Further, when data is written, a potential supplied to the wiring BLa and the wiring BLb is generated using data WDATA input from the outside.

  The sense amplifier 143 has a function of amplifying the potential generated by the column driver 142 and supplying the amplified potential to the wiring BLa and the wiring BLb. The sense amplifier 143 has a function of amplifying a potential corresponding to data stored in the cell array 110 and outputting the amplified potential to the output circuit 170. Note that the sense amplifier 143 can be omitted when it is not necessary to amplify the potential generated by the column driver 142 and the potential output from the cell array 110.

  The precharge circuit 144 has a function of precharging the wiring BLa and the wiring BLb to a predetermined potential and a function of bringing the wiring BLa and the wiring BLb into a floating state.

  The control circuit 160 is a logic circuit having a function of controlling the overall operation of the drive circuit unit 120, and has a function of generating a signal for controlling the operation of the drive circuit 130 and the drive circuit 140. Specifically, the control circuit 160 has a function of generating a control signal by performing a logical operation using a signal input from the outside and supplying the control signal to the drive circuit 130 and the drive circuit 140. Examples of the signal input to the control circuit 160 include a chip enable signal, a write enable signal, and a read enable signal.

  The output circuit 170 has a function of controlling output of data read from the cell array 110 to the outside. When a data read operation is performed, a read potential is supplied from the cell array 110 to the driver circuit 140. The read potential is amplified by the sense amplifier 143 and then output to the outside as data RDATA via the output circuit 170.

  This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 3)
In this embodiment, application examples of the semiconductor device or the memory device described in the above embodiment will be described.

<Computer>
The memory cell array 10 or the storage device 100 can be used for a storage device of a computer. FIG. 6 shows a configuration example of the computer 300. The computer 300 includes an input device 310, an output device 320, a central processing unit 330, and a main storage device 340.

  The central processing unit 330 includes a control circuit 331, an arithmetic circuit 332, a storage device 333, and a storage device 334.

  The input device 310 has a function of receiving data from the outside of the computer 300. The output device 320 has a function of outputting data to the outside of the computer 300.

  The control circuit 331 has a function of outputting a control signal to the input device 310, the output device 320, the main storage device 340, the arithmetic circuit 332, the storage device 333, and the storage device 334. The arithmetic circuit 332 has a function of performing arithmetic operations using input data. The storage device 333 can hold data used for calculation in the arithmetic circuit 332 and has a function as a register. The storage device 334 can store a part of the data in the main storage device 340 and has a function as a cache memory.

  In FIG. 6, the storage device 334 is provided inside the central processing unit 330, but may be provided outside the central processing unit 330, or inside and outside the central processing unit 330. It may be provided in both. A plurality of storage devices 334 may be provided both inside and outside the central processing unit 330. When the storage device 334 is provided both inside and outside the central processing unit 330, the storage device 334 provided inside can be used as a primary cache, and the storage device 334 provided outside can be used as a secondary cache. Can be used as a cache.

  The storage device 333 and the storage device 334 can operate at a higher speed than the main storage device 340. Further, the main storage device 340 may have a capacity larger than the storage device 334, and the storage device 334 may have a larger capacity than the storage device 333.

  By providing the storage device 334 having a function as a cache memory, the processing speed of the central processing unit 330 can be improved.

  The memory cell array 10 or the storage device 100 in the above embodiment is preferably used for the storage device 334 or the main storage device 340. Thereby, a highly reliable computer can be realized.

<Display system>
The memory cell array 10 or the storage device 100 can be used for a device other than a computer, for example, a storage device incorporated in a circuit used for driving a display device. FIG. 7 illustrates a configuration example of a display system 400 including a display unit 410 and a control circuit 420 having a function of driving the display unit 410.

  The control circuit 420 includes an interface 421, a frame memory 422, a decoder 423, a sensor controller 424, a controller 425, a clock generation circuit 426, an image processing unit 430, a storage device 441, a timing controller 442, a register 443, a drive circuit 450, and a touch sensor controller. 461.

  The control circuit 420 has a function of generating a signal for displaying a predetermined video (hereinafter also referred to as a video signal) and outputting the signal to the display unit 410. The display unit 410 has a function of displaying an image on the display unit 411 using the video signal input from the control circuit 420. In addition, the display unit 410 may include a touch sensor unit 412 having a function of obtaining information such as presence / absence of touch and a touch position. When the display unit 410 does not include the touch sensor unit 412, the touch sensor controller 461 can be omitted.

  As the display unit 411, a display unit that performs display using a liquid crystal element, a display unit that performs display using a light-emitting element, or the like can be used. Note that the number of display units 411 provided in the display unit 410 may be one or two or more. As an example, FIG. 7 illustrates a configuration in which the display unit 410 includes a display unit 411a that performs display using a reflective liquid crystal element and a display unit 411b that performs display using a light-emitting element.

  For the display unit 411, a reflective display element other than the reflective liquid crystal element can be used. For example, for the display unit 411, a shutter-type MEMS (Micro Electro Mechanical System) element, a light interference-type MEMS element, a display element using a microcapsule method, an electrophoresis method, an electrowetting method, or the like may be used. it can.

  As the light-emitting element, for example, a self-luminous light-emitting element such as an OLED (Organic Light Emitting Diode), an LED (Light Emitting Diode), a QLED (Quantum-Dot Light Emitting Diode), or a semiconductor laser can be used.

  The drive circuit 450 includes a source driver 451. The source driver 451 is a circuit having a function of supplying a video signal to the display unit 411. In FIG. 7, since the display portion 410 includes a display unit 411a and a display unit 411b, the driver circuit 450 includes a source driver 451a and a source driver 451b. The source driver 451a has a function of supplying a video signal to the display unit 411a, and the source driver 451b has a function of supplying a video signal to the display unit 411b. Note that the source driver 451 may be provided in the display unit 410.

  Communication between the control circuit 420 and the host 470 is performed via the interface 421. Data corresponding to an image displayed on the display unit 410 (hereinafter also referred to as image data), various control signals, and the like are sent from the host 470 to the control circuit 420. Further, information such as the presence / absence of a touch and a touch position acquired by the touch sensor controller 461 is sent from the control circuit 420 to the host 470. Note that each circuit included in the control circuit 420 is appropriately discarded depending on the standard of the host 470, the specification of the display unit 410, and the like.

  The frame memory 422 is a storage circuit having a function of storing image data input to the control circuit 420. When compressed image data is sent from the host 470 to the control circuit 420, the frame memory 422 can store the compressed image data. The decoder 423 is a circuit for decompressing the compressed image data. When it is not necessary to decompress the image data, the decoder 423 does not perform processing. Note that the decoder 423 can also be disposed between the frame memory 422 and the interface 421.

  The image processing unit 430 has a function of performing various kinds of image processing on the image data input from the frame memory 422 or the decoder 423 and generating a video signal. For example, the image processing unit 430 includes a gamma correction circuit 431, a dimming circuit 432, and a toning circuit 433.

  In the case where the source driver 451b includes a circuit (current detection circuit) having a function of detecting a current flowing through a light-emitting element included in the display unit 411b, the image processing unit 430 may be provided with an EL correction circuit 434. The EL correction circuit 434 has a function of adjusting the luminance of the light-emitting element based on a signal transmitted from the current detection circuit.

  The video signal generated by the image processing unit 430 is output to the drive circuit 450 via the storage device 441. The storage device 441 has a function of temporarily storing image data. Each of the source driver 451a and the source driver 451b has a function of performing various kinds of processing on the video signal input from the storage device 441 and outputting the processed signal to the display unit 411a and the display unit 411b.

  The timing controller 442 has a function of generating a timing signal used in a gate driver included in the driving circuit 450, the touch sensor controller 461, and the display unit 411.

  The touch sensor controller 461 has a function of controlling the operation of the touch sensor unit 412. A signal including touch information detected by the touch sensor unit 412 is processed by the touch sensor controller 461 and then transmitted to the host 470 via the interface 421. The host 470 generates image data reflecting the touch information and transmits it to the control circuit 420. Note that the control circuit 420 may have a function of reflecting touch information in image data. The touch sensor controller 461 may be provided in the touch sensor unit 412.

  The clock generation circuit 426 has a function of generating a clock signal used in the control circuit 420. The controller 425 has a function of processing various control signals sent from the host 470 via the interface 421 and controlling various circuits in the control circuit 420. Further, the controller 425 has a function of controlling power supply to various circuits in the control circuit 420. For example, the controller 425 can temporarily cut off the power supply to the stopped circuit.

  The register 443 has a function of storing data used for the operation of the control circuit 420. Examples of data stored in the register 443 include parameters used for the image processing unit 430 to perform correction processing, parameters used by the timing controller 442 to generate waveforms of various timing signals, and the like. The register 443 can be configured by a scan chain register including a plurality of registers.

  The control circuit 420 can include a sensor controller 424 connected to the optical sensor 480. The optical sensor 480 has a function of detecting external light 481 and generating a detection signal. The sensor controller 424 has a function of generating a control signal based on the detection signal. The control signal generated by the sensor controller 424 is output to the controller 425, for example.

  When the display unit 411a and the display unit 411b display the same video, the image processing unit 430 has a function of separately generating the video signal of the display unit 411a and the video signal of the display unit 411b. In this case, the reflection intensity of the reflective liquid crystal element included in the display unit 411a and the emission intensity of the light emitting element included in the display unit 411b according to the brightness of the external light 481 measured using the optical sensor 480 and the sensor controller 424. And can be adjusted. Here, the adjustment is referred to as dimming or dimming processing. A circuit that executes the processing is called a dimming circuit.

  For example, when an image is displayed on the display unit 410 outside on a sunny day, the image is displayed on the display unit 410 at night or in a dark place by displaying only with a reflective liquid crystal element without illuminating the light emitting element. In the case of displaying, the light emitting element can be illuminated to perform display.

  The image processing unit 430 also displays a video signal for display only with the display unit 411a, a video signal for display only with the display unit 411b, and the display unit 411a and the display unit 411b according to the brightness of external light. Any one of the video signals for display can be selected and generated. As a result, it is possible to perform a good display both in an environment where the external light is bright and in an environment where the external light is dark. Furthermore, in an environment where the outside light is bright, the power consumption can be reduced by preventing the light emitting element from emitting light or reducing the luminance of the light emitting element.

  Further, the color tone can be corrected by combining the display of the reflective liquid crystal element with the display of the light emitting element. For such color tone correction, a function for measuring the color tone of the external light 481 may be added to the optical sensor 480 and the sensor controller 424. For example, in the case where an image is displayed on the display unit 410 in a reddish environment at dusk, since the B (blue) component is insufficient only by display using a reflective liquid crystal element, the color tone is corrected by causing the light emitting element to emit light. be able to. Here, the correction is referred to as toning or toning processing. A circuit that executes the processing is called a toning circuit.

  The image processing unit 430 may include other processing circuits such as an RGB-RGBW conversion circuit depending on the specifications of the display unit 410. The RGB-RGBW conversion circuit is a circuit having a function of converting RGB (red, green, blue) image data into RGBW (red, green, blue, white) image signals. That is, when the display unit 410 has RGBW four color pixels, the power consumption can be reduced by displaying the W (white) component in the image data using the W (white) pixel. The RGB-RGBW conversion circuit is not limited to this, and may be, for example, an RGB-RGBY (red, green, blue, yellow) conversion circuit.

  In addition, different images can be displayed on the display unit 411a and the display unit 411b. A reflective liquid crystal element has a lower operation speed than a light emitting element, and may take time to display an image. Therefore, for example, the problem can be solved by displaying a background still image on a reflective liquid crystal element and displaying a moving image on the light emitting element. At this time, the frequency of rewriting the video displayed on the reflective liquid crystal element can be reduced, and the operation of the source driver 451a and the gate driver included in the display unit 411a can be stopped in a period in which the video is not rewritten. . Thereby, it is possible to achieve both smooth moving image display and low power consumption. In this case, the frame memory 422 is provided with an area for storing the video signal supplied to the reflective liquid crystal element and an area for storing the video signal supplied to the light emitting element.

  As the frame memory 422 or the storage device 441 in FIG. 7, the memory cell array 10 or the storage device 100 described in the above embodiment can be used. Thereby, a highly reliable control circuit or display system can be realized.

  This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 4)
In this embodiment, a structure example of a display device that can be used for the display system described in Embodiment 3 will be described. The display device described below can be used for the display unit 410 in FIG. Here, a display device capable of performing display using a reflective liquid crystal element and a light-emitting element will be described in particular.

  FIG. 8A is a block diagram illustrating an example of a structure of the display device 500. The display device 500 includes a plurality of pixel units 502 arranged in a matrix in the pixel portion 501. The display device 500 includes a driver circuit 503a, a driver circuit 503b, a driver circuit 504a, and a driver circuit 504b. The display device 500 is connected to a plurality of pixel units 502 arranged in the direction R and a plurality of wirings GLa connected to the drive circuit 503a, and to a plurality of pixel units 502 and a drive circuit 503b arranged in the direction R. And a plurality of wirings GLb. The display device 500 is connected to the plurality of pixel units 502 arranged in the direction C and the plurality of wirings SLa connected to the drive circuit 504a, and to the plurality of pixel units 502 arranged in the direction C and the drive circuit 504b. A plurality of wirings SLb.

  The drive circuit 504a and the drive circuit 504b correspond to the source driver 451a and the source driver 451b in FIG. 7, respectively. That is, the display device 500 corresponds to a configuration in which the source driver 451a and the source driver 451b in FIG. However, the driver circuit 504a and the driver circuit 504b may be provided in the control circuit 420 in FIG.

  The pixel unit 502 includes a reflective liquid crystal element and a light emitting element. In the pixel unit 502, the liquid crystal element and the light emitting element have portions that overlap each other.

  FIG. 8B1 illustrates a configuration example of the conductive layer 530b included in the pixel unit 502. The conductive layer 530 b functions as a reflective electrode of the liquid crystal element in the pixel unit 502. An opening 540 is provided in the conductive layer 530b.

  In FIG. 8B1, the light-emitting element 520 located in a region overlapping with the conductive layer 530b is indicated by a broken line. The light-emitting element 520 is provided so as to overlap with the opening 540 included in the conductive layer 530b. Accordingly, light emitted from the light emitting element 520 is emitted to the display surface side through the opening 540.

  In FIG. 8B1, the pixel units 502 adjacent in the direction R are pixels corresponding to different colors. At this time, as shown in FIG. 8B1, it is preferable that the openings 540 are provided at different positions in the conductive layer 530b so that the two pixels adjacent in the direction R are not arranged in a line. Accordingly, the two light emitting elements 520 can be separated from each other, and a phenomenon (also referred to as crosstalk) in which light emitted from the light emitting elements 520 enters a colored layer included in the adjacent pixel unit 502 can be suppressed. . Further, since the two adjacent light emitting elements 520 can be arranged apart from each other, a display device with high definition can be realized even when the EL layer of the light emitting element 520 is separately formed using a shadow mask or the like.

  Alternatively, an arrangement as shown in FIG.

  If the ratio of the total area of the openings 540 to the total area of the non-openings is too large, the display using the liquid crystal element will be dark. If the ratio of the total area of the openings 540 to the total area of the non-openings is too small, the display using the light emitting element 520 becomes dark.

  In addition, when the area of the opening 540 provided in the conductive layer 530b functioning as the reflective electrode is too small, the efficiency of light that can be extracted from the light emitted from the light-emitting element 520 decreases.

  The shape of the opening 540 can be, for example, a polygon, a rectangle, an ellipse, a circle, a cross, or the like. Moreover, it is good also as an elongated streak shape, a slit shape, and a checkered shape. Further, the opening 540 may be arranged close to adjacent pixels. Preferably, the opening 540 is arranged close to another pixel that displays the same color. Thereby, crosstalk can be suppressed.

<Example of circuit configuration>
FIG. 9 is a circuit diagram illustrating a configuration example of the pixel unit 502. FIG. 9 shows two adjacent pixel units 502. Each pixel unit 502 includes a pixel 505a and a pixel 505b.

  The pixel 505a includes a switch SW1, a capacitor C10, and a liquid crystal element 510, and the pixel 505b includes a switch SW2, a transistor M, a capacitor C20, and a light-emitting element 520. The pixel 505a is connected to the wiring SLa, the wiring GLa, and the wiring CSCOM, and the pixel 505b is connected to the wiring GLb, the wiring SLb, and the wiring ANO. Note that FIG. 9 illustrates a wiring VCOM1 connected to the liquid crystal element 510 and a wiring VCOM2 connected to the light-emitting element 520. FIG. 9 shows an example in which transistors are used for the switch SW1 and the switch SW2.

  The gate of the switch SW1 is connected to the wiring GLa, one of the source and the drain is connected to the wiring SLa, and the other of the source and the drain is connected to one electrode of the capacitor C10 and one electrode of the liquid crystal element 510. . The other electrode of the capacitive element C10 is connected to the wiring CSCOM. The other electrode of the liquid crystal element 510 is connected to the wiring VCOM1.

  The gate of the switch SW2 is connected to the wiring GLb, one of the source and the drain is connected to the wiring SLb, and the other of the source and the drain is connected to one electrode of the capacitor C20 and the gate of the transistor M. The other electrode of the capacitor C20 is connected to one of the source and the drain of the transistor M and the wiring ANO. The other of the source and the drain of the transistor M is connected to one electrode of the light emitting element 520. The other electrode of the light emitting element 520 is connected to the wiring VCOM2.

  FIG. 9 shows an example in which the transistor M has a pair of gates and these are connected. As a result, the current that can be passed by the transistor M can be increased.

  A predetermined potential can be supplied to each of the wiring VCOM1 and the wiring CSCOM. In addition, the wiring VCOM2 and the wiring ANO can each be supplied with a potential for causing a potential difference that enables the light emitting element 520 to emit light.

  For example, in the case of performing reflection mode display, the pixel unit 502 illustrated in FIG. 9 drives the pixel 505a with a signal supplied to the wiring GLa and the wiring SLa, and uses the optical modulation by the liquid crystal element 510 to display an image. Can be displayed. In the case where display is performed in the transmissive mode, the pixel 505b is driven by signals supplied to the wiring GLb and the wiring SLb, whereby the light-emitting element 520 can emit light and an image can be displayed. In the case of driving in both modes, the pixel 505a and the pixel 505b can be driven by signals supplied to the wiring GLa, the wiring GLb, the wiring SLa, and the wiring SLb.

  Note that although FIG. 9 illustrates an example in which one pixel unit 502 includes one liquid crystal element 510 and one light emitting element 520, the present invention is not limited thereto. For example, as illustrated in FIG. 10A, the pixel 505b may include a plurality of sub-pixels 506b (sub-pixel 506br, sub-pixel 506bg, sub-pixel 506bb, and sub-pixel 506bw). The sub-pixel 506br, the sub-pixel 506bg, the sub-pixel 506bb, and the sub-pixel 506bw each include a light-emitting element 520r, a light-emitting element 520g, a light-emitting element 520b, and a light-emitting element 520w. A pixel unit 502 illustrated in FIG. 10A is a pixel capable of full-color display with one pixel unit, unlike FIG.

  In FIG. 10A, a wiring GLba, a wiring GLbb, a wiring SLba, a wiring SLbb, and a wiring ANO are connected to the pixel 505b.

  In the example illustrated in FIG. 10A, for example, as the four light-emitting elements 520, light-emitting elements exhibiting red (R), green (G), blue (B), and white (W) can be used. As the liquid crystal element 510, a reflective liquid crystal element exhibiting white can be used. Thereby, when displaying in reflection mode, white display with high reflectance can be performed. In addition, when display is performed in the transmissive mode, display with high color rendering properties can be performed with low power.

  FIG. 10B shows a configuration example of the pixel unit 502. The pixel unit 502 includes a light-emitting element 520w that overlaps with an opening of the conductive layer 530, and a light-emitting element 520r, a light-emitting element 520g, and a light-emitting element 520b that are disposed around the conductive layer 530. The light emitting element 520r, the light emitting element 520g, and the light emitting element 520b preferably have substantially the same light emitting area.

<Configuration example of display device>
FIG. 11 is a schematic perspective view of a display device 500 of one embodiment of the present invention. The display device 500 has a structure in which a substrate 551 and a substrate 561 are attached to each other. In FIG. 11, the substrate 561 is indicated by a broken line.

  The display device 500 includes a display region 562, a circuit 564, a wiring 565, and the like. The substrate 551 is provided with, for example, a circuit 564, a wiring 565, a conductive layer 530b functioning as a pixel electrode, and the like. FIG. 11 shows an example in which an IC 573 and an FPC 572 are mounted on a substrate 551. Therefore, the structure illustrated in FIG. 11 can also be referred to as a display module including the display device 500, the FPC 572, and the IC 573.

  As the circuit 564, a circuit functioning as the driver circuit 504 can be used, for example.

  The wiring 565 has a function of supplying a signal and power to the display region 562 and the circuit 564. The signal and power are input to the wiring 565 from the outside or the IC 573 through the FPC 572.

  FIG. 11 illustrates an example in which the IC 573 is provided on the substrate 551 by a COG (Chip On Glass) method or the like. As the IC 573, for example, an IC having a function as the driver circuit 503, the driver circuit 504, or the like can be used. Note that when the display device 500 includes a circuit that functions as the driver circuit 503 and the driver circuit 504, or a signal for driving the display device 500 via the FPC 572 by providing a circuit that functions as the driver circuit 503 or the driver circuit 504 outside. For example, the IC 573 may not be provided. The IC 573 may be mounted on the FPC 572 by a COF (Chip On Film) method or the like.

  FIG. 11 shows an enlarged view of a part of the display area 562. In the display region 562, conductive layers 530b included in the plurality of display elements are arranged in a matrix. The conductive layer 530b has a function of reflecting visible light, and functions as a reflective electrode of a liquid crystal element 510 described later.

  In addition, as illustrated in FIG. 11, the conductive layer 530b has an opening. Further, the light-emitting element 520 is provided on the substrate 551 side with respect to the conductive layer 530b. Light from the light-emitting element 520 is emitted to the substrate 561 side through the opening of the conductive layer 530b.

  FIG. 12 illustrates an example of a cross section of the display device illustrated in FIG. 11 when a part of the region including the FPC 572, a part of the region including the circuit 564, and a part of the region including the display region 562 are cut. Show.

  The display device 500 includes an insulating layer 720 between the substrate 551 and the substrate 561. Further, a light-emitting element 520, a transistor 701, a transistor 705, a transistor 706, a coloring layer 634, and the like are provided between the substrate 551 and the insulating layer 720. In addition, the liquid crystal element 510, the coloring layer 631, and the like are provided between the insulating layer 720 and the substrate 561. The substrate 561 and the insulating layer 720 are bonded to each other through an adhesive layer 641, and the substrate 551 and the insulating layer 720 are bonded to each other through an adhesive layer 642.

  The transistor 706 is connected to the liquid crystal element 510, and the transistor 705 is connected to the light emitting element 520. Since both the transistor 705 and the transistor 706 are formed over the surface of the insulating layer 720 on the substrate 551 side, they can be manufactured using the same process.

  The substrate 561 is provided with a coloring layer 631, a light shielding layer 632, an insulating layer 621, a conductive layer 613 functioning as a common electrode of the liquid crystal element 510, an alignment film 633b, an insulating layer 617, and the like. The insulating layer 617 functions as a spacer for maintaining the cell gap of the liquid crystal element 510.

  Insulating layers such as an insulating layer 711, an insulating layer 712, an insulating layer 713, an insulating layer 714, an insulating layer 715, and an insulating layer 716 are provided on the substrate 551 side of the insulating layer 720. Part of the insulating layer 711 functions as a gate insulator of each transistor. The insulating layer 712, the insulating layer 713, and the insulating layer 714 are provided so as to cover each transistor. An insulating layer 716 is provided to cover the insulating layer 714. The insulating layer 714 and the insulating layer 716 function as a planarization layer. Note that although the case where the insulating layer covering the transistor and the like has three layers of the insulating layer 712, the insulating layer 713, and the insulating layer 714 is shown here, the number of layers is not limited to this, and four or more layers may be used. There may be a layer or two layers. The insulating layer 714 functioning as a planarization layer is not necessarily provided if not necessary.

  In addition, the transistor 701, the transistor 705, and the transistor 706 each include a conductive layer 721 that partially functions as a gate, a conductive layer 722 that partially functions as a source or a drain, and a semiconductor layer 731. Here, the same hatching pattern is given to a plurality of layers obtained by processing the same film.

  The liquid crystal element 510 is a reflective liquid crystal element. The liquid crystal element 510 has a structure in which a conductive layer 530a, a liquid crystal 612, and a conductive layer 613 are stacked. A conductive layer 530b that reflects visible light is provided in contact with the conductive layer 530a on the substrate 551 side. The conductive layer 530 b has an opening 540. The conductive layer 530a and the conductive layer 613 include a material that transmits visible light. An alignment film 633a is provided between the liquid crystal 612 and the conductive layer 530a, and an alignment film 633b is provided between the liquid crystal 612 and the conductive layer 613. In addition, a polarizing plate 630 is provided on the outer surface of the substrate 561.

  In the liquid crystal element 510, the conductive layer 530b has a function of reflecting visible light, and the conductive layer 613 has a function of transmitting visible light. Light incident from the substrate 561 side is polarized by the polarizing plate 630, passes through the conductive layer 613 and the liquid crystal 612, and is reflected by the conductive layer 530b. Then, the light passes through the liquid crystal 612 and the conductive layer 613 again and reaches the polarizing plate 630. At this time, alignment of liquid crystal can be controlled by a voltage applied between the conductive layer 530b and the conductive layer 613, and optical modulation of light can be controlled. That is, the intensity of light emitted through the polarizing plate 630 can be controlled. In addition, light that is not in a specific wavelength region is absorbed by the colored layer 631, so that the extracted light is, for example, red light.

  The light emitting element 520 is a bottom emission type light emitting element. The light-emitting element 520 has a structure in which a conductive layer 691, an EL layer 692, and a conductive layer 693b are stacked in this order from the insulating layer 720 side. A conductive layer 693a is provided to cover the conductive layer 693b. The conductive layer 693b includes a material that reflects visible light, and the conductive layer 691 and the conductive layer 693a include a material that transmits visible light. Light emitted from the light-emitting element 520 is emitted to the substrate 561 side through the colored layer 634, the insulating layer 720, the opening 540, the conductive layer 613, and the like.

  Here, as shown in FIG. 12, the opening 540 is preferably provided with a conductive layer 530a that transmits visible light. Thereby, in the region overlapping with the opening 540, the liquid crystal 612 is aligned in the same manner as in the other regions, so that it is possible to suppress the occurrence of unintended light leakage due to the alignment failure of the liquid crystal at the boundary between these regions. .

  Here, a linear polarizing plate may be used as the polarizing plate 630 disposed on the outer surface of the substrate 561, but a circular polarizing plate may also be used. As a circularly-polarizing plate, what laminated | stacked the linearly-polarizing plate and the quarter wavelength phase difference plate, for example can be used. Thereby, external light reflection can be suppressed. In addition, a desired contrast may be realized by adjusting a cell gap, an alignment, a driving voltage, and the like of the liquid crystal element used for the liquid crystal element 510 according to the type of the polarizing plate.

  An insulating layer 717 is provided over the insulating layer 716 that covers the end portion of the conductive layer 691. The insulating layer 717 has a function as a spacer for suppressing the insulating layer 720 and the substrate 551 from approaching more than necessary. Further, in the case where the EL layer 692 or the conductive layer 693a is formed using a shielding mask (metal mask), the EL layer 692 or the conductive layer 693a has a function as a mask gapper for suppressing contact of the shielding mask with a formation surface. Also good. Note that the insulating layer 717 is not necessarily provided if not necessary.

  One of a source and a drain of the transistor 705 is connected to the conductive layer 691 of the light-emitting element 520 through the conductive layer 724.

  One of a source and a drain of the transistor 706 is connected to the conductive layer 530 b through a connection portion 707. The conductive layer 530b and the conductive layer 530a are provided in contact with each other and are connected to each other. Here, the connection portion 707 is a portion that connects conductive layers provided on both surfaces of the insulating layer 720 through an opening provided in the insulating layer 720.

  A connection portion 704 is provided in a region of the substrate 551 that does not overlap with the substrate 561. The connection portion 704 is connected to the FPC 572 through the connection layer 742. The connection unit 704 has a configuration similar to that of the connection unit 707. A conductive layer obtained by processing the same conductive film as the conductive layer 530a is exposed on the upper surface of the connection portion 704. Thereby, the connection portion 704 and the FPC 572 can be connected via the connection layer 742.

  A connection portion 752 is provided in a part of the region where the adhesive layer 641 is provided. In the connection portion 752, a conductive layer obtained by processing the same conductive film as the conductive layer 530 a and a part of the conductive layer 613 are connected by a connection body 743. Therefore, a signal or a potential input from the FPC 572 connected to the substrate 551 side can be supplied to the conductive layer 613 formed on the substrate 561 side through the connection portion 752.

  As the connection body 743, for example, conductive particles can be used. As the conductive particles, those obtained by coating the surface of particles such as an organic resin or silica with a metal material can be used. It is preferable to use nickel or gold as the metal material because the contact resistance can be reduced. In addition, it is preferable to use particles in which two or more kinds of metal materials are coated in layers, such as further coating nickel with gold. Further, as the connection body 743, a material that is elastically deformed or plastically deformed is preferably used. At this time, the connection body 743 which is an electroconductive particle may become a shape crushed up and down as shown in FIG. By doing so, the contact area between the connection body 743 and the conductive layer electrically connected to the connection body 743 can be increased, the contact resistance can be reduced, and the occurrence of problems such as poor connection can be suppressed.

  The connection body 743 is preferably disposed so as to be covered with the adhesive layer 641. For example, the connection body 743 may be sprayed after applying a paste or the like to be the adhesive layer 641.

  FIG. 12 illustrates an example in which a transistor 701 is provided as the circuit 564.

  In FIG. 12, as an example of the transistor 701 and the transistor 705, a structure in which a semiconductor layer 731 in which a channel is formed is sandwiched between a pair of gates is applied. One gate is formed using a conductive layer 721, and the other gate is formed using a conductive layer 723 that overlaps with the semiconductor layer 731 with an insulating layer 712 interposed therebetween. With such a structure, the threshold voltage of the transistor can be reliably controlled. At this time, the transistor may be driven by connecting two gates and supplying the same signal thereto. Such a transistor can increase the on-state current compared to other transistors, and can increase field-effect mobility. As a result, a circuit that can be driven at high speed can be manufactured. Furthermore, the area occupied by the circuit portion can be reduced. By applying a transistor with a large on-state current, signal delay in each wiring can be reduced and display unevenness can be suppressed even if the number of wirings increases when the display device is increased in size or definition. can do.

  Note that the transistor included in the circuit 564 and the transistor included in the display region 562 may have the same structure. Further, the plurality of transistors included in the circuit 564 may have the same structure or may be combined with transistors having different structures. In addition, the plurality of transistors included in the display region 562 may have the same structure or may be combined with transistors having different structures.

  At least one of the insulating layer 712 and the insulating layer 713 covering each transistor is preferably formed using a material in which impurities such as water and hydrogen hardly diffuse. That is, the insulating layer 712 or the insulating layer 713 can function as a barrier film. With such a structure, impurities can be effectively prevented from diffusing from the outside with respect to the transistor, and a highly reliable display device can be realized.

  On the substrate 561 side, an insulating layer 621 is provided so as to cover the coloring layer 631 and the light-blocking layer 632. The insulating layer 621 may function as a planarization layer. Since the surface of the conductive layer 613 can be substantially flattened by the insulating layer 621, the alignment state of the liquid crystal 612 can be made uniform.

  An example of a method for manufacturing the display device 500 will be described. For example, a conductive layer 530a, a conductive layer 530b, and an insulating layer 720 are formed in this order over a supporting substrate having a separation layer, and then a transistor 705, a transistor 706, a light-emitting element 520, and the like are formed, and then an adhesive layer 642 is used. The substrate 551 and the support substrate are bonded together. After that, the supporting substrate and the peeling layer are removed by peeling at the interfaces of the peeling layer and the insulating layer 720 and the peeling layer and the conductive layer 530a. Separately, a substrate 561 on which a colored layer 631, a light shielding layer 632, a conductive layer 613, and the like are formed in advance is prepared. Then, the display device 500 can be manufactured by dropping the liquid crystal 612 over the substrate 551 or the substrate 561 and bonding the substrate 551 and the substrate 561 with the adhesive layer 641.

  As the separation layer, a material that causes separation at the interface between the insulating layer 720 and the conductive layer 530a can be selected as appropriate. In particular, a layer including a refractory metal material such as tungsten and a layer including an oxide of the metal material are stacked as the separation layer, and the insulating layer 720 over the separation layer is formed using silicon nitride, silicon oxynitride, or oxynitride. It is preferable to use a layer in which a plurality of silicon layers are stacked. When a refractory metal material is used for the separation layer, the formation temperature of a layer formed later can be increased, the concentration of impurities is reduced, and a highly reliable display device can be realized.

  As the conductive layer 530a, a metal oxide, a metal nitride, or the like is preferably used. In the case of using a metal oxide, a material in which at least one of the concentration of hydrogen, boron, phosphorus, nitrogen, and other impurities and the amount of oxygen vacancies is higher than that of a semiconductor layer used for a transistor is formed using a conductive layer 530a. Can be used.

  Below, each component shown above is demonstrated.

[substrate]
As the substrate included in the display device, a material having a flat surface can be used. For the substrate from which light from the display element is extracted, a material that transmits the light is used. For example, materials such as glass, quartz, ceramic, sapphire, and organic resin can be used.

  By using a thin substrate, the display device can be reduced in weight and thickness. Furthermore, a flexible display device can be realized by using a flexible substrate.

  Further, since the substrate on the side from which light emission is not extracted does not have to be translucent, a metal substrate or the like can be used in addition to the above-described substrates. A metal substrate is preferable because it has high thermal conductivity and can easily conduct heat to the entire substrate, which can suppress a local temperature increase of the display device. In order to obtain flexibility and bendability, the thickness of the metal substrate is preferably 10 μm to 200 μm, and more preferably 20 μm to 50 μm.

  Although there is no limitation in particular as a material which comprises a metal substrate, For example, metals, such as aluminum, copper, and nickel, aluminum alloys, or alloys, such as stainless steel, etc. can be used conveniently.

  Alternatively, a substrate that has been subjected to an insulating process by oxidizing the surface of the metal substrate or forming an insulating film on the surface may be used. For example, the insulating film may be formed by using a coating method such as a spin coating method or a dip method, an electrodeposition method, a vapor deposition method, or a sputtering method, or it is left in an oxygen atmosphere or heated, or an anodic oxidation method. For example, an oxide film may be formed on the surface of the substrate.

Examples of the material having flexibility and transparency to visible light include, for example, glass having a thickness having flexibility, polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), and polyacrylonitrile resin. , Polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyvinyl chloride resin, polytetrafluoroethylene (PTFE) resin Etc. In particular, a material having a low thermal expansion coefficient is preferably used. For example, a polyamideimide resin, a polyimide resin, PET, or the like having a thermal expansion coefficient of 30 × 10 ⁻⁶ / K or less can be suitably used. Further, a substrate in which glass fiber is impregnated with an organic resin, or a substrate in which an inorganic filler is mixed with an organic resin to reduce the thermal expansion coefficient can be used. Since a substrate using such a material is light, a display device using the substrate can be light.

  When a fibrous body is included in the material, a high-strength fiber of an organic compound or an inorganic compound is used as the fibrous body. The high-strength fiber specifically refers to a fiber having a high tensile elastic modulus or Young's modulus, and representative examples include polyvinyl alcohol fiber, polyester fiber, polyamide fiber, polyethylene fiber, aramid fiber, Examples include polyparaphenylene benzobisoxazole fibers, glass fibers, and carbon fibers. Examples of the glass fiber include glass fibers using E glass, S glass, D glass, Q glass, and the like. These may be used in the state of a woven fabric or a non-woven fabric, and a structure in which the fibrous body is impregnated with a resin and the resin is cured may be used as a flexible substrate. When a structure made of a fibrous body and a resin is used as the flexible substrate, it is preferable because reliability against breakage due to bending or local pressing is improved.

  Alternatively, glass, metal, or the like thin enough to have flexibility can be used for the substrate. Alternatively, a composite material in which glass and a resin material are bonded together with an adhesive layer may be used.

  On a flexible substrate, a hard coat layer (eg, silicon nitride, aluminum oxide, etc.) that protects the surface of the display device from scratches, or a layer of a material that can disperse the pressure (eg, aramid resin). Etc. may be laminated. In order to suppress a decrease in the lifetime of the display element due to moisture or the like, an insulating film with low water permeability may be stacked over a flexible substrate. For example, an inorganic insulating material such as silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, or aluminum nitride can be used.

  The substrate can be used by stacking a plurality of layers. In particular, when the glass layer is used, the barrier property against water and oxygen can be improved, and a highly reliable display device can be obtained.

[Transistor]
The transistor includes a conductive layer that functions as a gate electrode, an insulating layer that functions as a gate insulator, a semiconductor layer, a conductive layer that functions as a source electrode, and a conductive layer that functions as a drain electrode. The above shows the case where a bottom-gate transistor is applied.

  Note that there is no particular limitation on the structure of the transistor included in the display device of one embodiment of the present invention. For example, a planar transistor, a staggered transistor, or an inverted staggered transistor may be used. Further, a top-gate or bottom-gate transistor structure may be employed. Alternatively, gate electrodes may be provided above and below a semiconductor layer in which a channel is formed.

[Semiconductor layer]
There is no particular limitation on the crystallinity of the material used for the semiconductor layer of the transistor, and the semiconductor is amorphous or crystalline (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor having part of a crystalline region) Any of these may be used. It is preferable to use a crystalline semiconductor because deterioration of transistor characteristics can be suppressed.

  For the semiconductor layer of the transistor, a material such as a Group 14 element (silicon, germanium, or the like) or a metal oxide can be used, for example. Typically, a semiconductor containing silicon, a semiconductor containing gallium arsenide, a metal oxide containing indium, or the like can be used.

  In particular, it is preferable to use a metal oxide having a larger band gap than silicon. It is preferable to use a semiconductor material having a larger band gap and lower carrier density than silicon because current in the off-state of the transistor can be reduced.

  A transistor using a metal oxide having a band gap larger than that of silicon can hold charge accumulated in a capacitor connected in series with the transistor for a long time because of the low off-state current. By applying such a transistor to a pixel, the driving circuit can be stopped while maintaining the gradation of an image displayed in each display region. As a result, a display device with extremely reduced power consumption can be realized.

  The semiconductor layer is expressed by an In-M-Zn-based oxide containing at least indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It is preferable to include a film to be formed. In addition, in order to reduce variation in electric characteristics of a transistor including the semiconductor layer, a stabilizer is preferably included together with the transistor.

  Examples of the stabilizer include gallium, tin, hafnium, aluminum, zirconium, and the like, including the metals described in M above. Other stabilizers include lanthanoids such as lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

  As a metal oxide forming the semiconductor layer, for example, an In—Ga—Zn-based oxide, an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, an In—Hf—Zn-based oxide, an In— La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm -Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al- Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn acid Things, can be used In-Hf-Al-Zn-based oxide.

  Note that here, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

  In addition, the semiconductor layer and the conductive layer may have the same metal element among the above oxides. Manufacturing costs can be reduced by using a semiconductor layer and a conductive layer containing the same metal element. For example, the manufacturing cost can be reduced by using a metal oxide target having the same metal composition when the semiconductor layer and the conductive layer are formed. Further, an etching gas or an etching solution for processing the semiconductor layer and the conductive layer can be used in common. However, the semiconductor layer and the conductive layer may have different compositions even if they have the same metal element. For example, a metal element in a film may be detached during a manufacturing process of a transistor and a capacitor to have a different metal composition.

  The metal oxide constituting the semiconductor layer preferably has a band gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a large band gap.

  In the case where the metal oxide forming the semiconductor layer is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is In ≧ M, Zn ≧ It is preferable to satisfy M. As the atomic ratio of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, 4 : 2: 4.1 is preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio included in the sputtering target as an error.

It is preferable to use a metal oxide having a low carrier density for the semiconductor layer. For example, the semiconductor layer has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, more preferably 1 × 10 ¹³ / cm ³ or less, more preferably 1 × 10 ¹¹ / cm 3. ³ or less, more preferably less than 1 × ^{10 10} / cm ^3, it is possible to use a 1 × ¹⁰ -9 / cm ³ metal oxide or more carrier density. Such a semiconductor layer has a low impurity concentration and a low density of defect states, and thus provides stable electrical characteristics of the transistor.

  Note that the semiconductor layer is not limited thereto, and a semiconductor layer with an appropriate composition may be used depending on required electrical characteristics of the transistor (field-effect mobility, threshold voltage, and the like). In order to obtain necessary transistor electrical characteristics, it is preferable that the semiconductor layer have appropriate carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like. .

If the metal oxide constituting the semiconductor layer contains silicon or carbon, which is one of the Group 14 elements, oxygen vacancies increase in the semiconductor layer, which may become n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less. preferable.

Further, when alkali metal and alkaline earth metal are combined with a metal oxide, carriers may be generated, and an off-state current of a transistor using the metal oxide for a semiconductor layer may increase. Therefore, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry in the semiconductor layer is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. Is preferred.

In addition, when nitrogen is contained in the metal oxide constituting the semiconductor layer, electrons as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor using a metal oxide containing nitrogen as a semiconductor layer is likely to be normally on. Therefore, the nitrogen concentration obtained by secondary ion mass spectrometry in the semiconductor layer is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

  The semiconductor layer may have a non-single crystal structure, for example. The non-single crystal structure includes, for example, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect states.

  A metal oxide having an amorphous structure has, for example, disordered atomic arrangement and no crystal component. Alternatively, the oxide film having an amorphous structure has, for example, a completely amorphous structure and does not have a crystal part.

  Note that the semiconductor layer may be a mixed film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, and a single crystal structure region. For example, the mixed film may have a single-layer structure or a stacked structure including any two or more of the above-described regions.

  Alternatively, silicon is preferably used for a semiconductor layer where a channel of the transistor is formed. Although amorphous silicon may be used as silicon, it is particularly preferable to use crystalline silicon. For example, microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like is preferably used. In particular, polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon. By applying such a polycrystalline semiconductor to a pixel, the aperture ratio of the pixel can be improved. In addition, even in the case of an extremely high-definition display portion, the driver circuit can be formed over the same substrate as the pixels, and the number of components included in the electronic device can be reduced.

  The bottom-gate transistor described in this embodiment is preferable in that the number of manufacturing steps can be reduced. In addition, since amorphous silicon is used for the semiconductor layer, it can be formed at a temperature lower than that of polycrystalline silicon. Therefore, it is possible to use a material having low heat resistance for a wiring, an electrode, a substrate, or the like below the semiconductor layer. The range of selection can be expanded. For example, a glass substrate having an extremely large area can be used. On the other hand, a top-gate transistor is preferable in that an impurity region can be easily formed in a self-aligned manner and variation in electrical characteristics can be reduced. In particular, a top gate transistor is suitable when polycrystalline silicon, single crystal silicon, or the like is used for the semiconductor layer.

[Conductive layer]
In addition to the gate, source, and drain of the transistor, materials that can be used for conductive layers such as various wirings and electrodes constituting the display device include aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, A metal such as tantalum or tungsten, or an alloy containing this as a main component can be used. A film containing any of these materials can be used as a single layer or a stacked structure. For example, a single layer structure of an aluminum film containing silicon, a two layer structure in which an aluminum film is stacked on a titanium film, a two layer structure in which an aluminum film is stacked on a tungsten film, and a copper film on a copper-magnesium-aluminum alloy film Two-layer structure to stack, two-layer structure to stack copper film on titanium film, two-layer structure to stack copper film on tungsten film, titanium film or titanium nitride film, and aluminum film or copper film on top of it A three-layer structure for forming a titanium film or a titanium nitride film thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film stacked thereon, and a molybdenum film or There is a three-layer structure for forming a molybdenum nitride film. Note that an oxide such as indium oxide, tin oxide, or zinc oxide may be used. Further, it is preferable to use copper containing manganese because the controllability of the shape by etching is increased.

  As the light-transmitting conductive material, conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, or zinc oxide to which gallium is added, or graphene can be used. Alternatively, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or an alloy material containing the metal material can be used. Alternatively, a nitride (eg, titanium nitride) of the metal material may be used. Note that in the case where a metal material or an alloy material (or a nitride thereof) is used, it may be thin enough to have a light-transmitting property. In addition, a stacked film of the above materials can be used as a conductive layer. For example, it is preferable to use a laminated film of an alloy of silver and magnesium and indium tin oxide because the conductivity can be increased. These can also be used for conductive layers such as various wirings and electrodes constituting the display device and conductive layers (conductive layers functioning as pixel electrodes and common electrodes) included in the display element.

[Insulation layer]
Insulating materials that can be used for each insulating layer include, for example, resins such as acrylic and epoxy, resins having a siloxane bond such as silicone, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide An inorganic insulating material such as can also be used.

  The light-emitting element is preferably provided between a pair of insulating films with low water permeability. Thereby, impurities such as water can be prevented from entering the light emitting element, and a decrease in reliability of the apparatus can be suppressed.

  Examples of the low water-permeable insulating film include a film containing nitrogen and silicon such as a silicon nitride film and a silicon nitride oxide film, and a film containing nitrogen and aluminum such as an aluminum nitride film. Alternatively, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like may be used.

For example, the water vapor transmission rate of an insulating film with low water permeability is 1 × 10 ⁻⁵ [g / (m ² · day)] or less, preferably 1 × 10 ⁻⁶ [g / (m ² · day)] or less, More preferably, it is 1 × 10 ⁻⁷ [g / (m ² · day)] or less, and further preferably 1 × 10 ⁻⁸ [g / (m ² · day)] or less.

[Liquid crystal element]
As the liquid crystal element, for example, a liquid crystal element to which a vertical alignment (VA: Vertical Alignment) mode is applied can be used. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

  As the liquid crystal element, liquid crystal elements to which various modes are applied can be used. For example, in addition to the VA mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetrical Aligned Micro-cell) mode Further, a liquid crystal element to which an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Antiferroelectric Liquid Crystal) mode, or the like is applied can be used.

  Note that the liquid crystal element is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal. Note that the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Note that the liquid crystal element may be a liquid crystal such as a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer dispersed liquid crystal (PDLC), a ferroelectric liquid crystal, or an antiferroelectric liquid crystal. it can. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

  Further, as the liquid crystal material, either a positive type liquid crystal or a negative type liquid crystal may be used, and an optimal liquid crystal material may be used according to an applied mode or design.

  An alignment film can be provided to control the alignment of the liquid crystal. Note that in the case of employing a horizontal electric field mode, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with several percent by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and optical isotropy. In addition, a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency. Further, since it is not necessary to provide an alignment film, rubbing treatment is unnecessary, electrostatic breakdown caused by the rubbing treatment can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. .

  As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a transflective liquid crystal element, or the like can be used. In one embodiment of the present invention, it is particularly preferable to use a reflective liquid crystal element.

  In the case of using a transmissive or transflective liquid crystal element, two polarizing plates are provided so as to sandwich a pair of substrates. In addition, a backlight is provided outside the polarizing plate. The backlight may be a direct type backlight or an edge light type backlight. It is preferable to use a direct-type backlight including an LED (Light Emitting Diode) because local dimming is facilitated and contrast can be increased. An edge light type backlight is preferably used because the thickness of the module including the backlight can be reduced.

  In the case of using a reflective liquid crystal element, a polarizing plate is provided on the display surface side. In addition to this, it is preferable to arrange a light diffusing plate on the display surface side because the visibility can be improved.

  In the case of using a reflective or transflective liquid crystal element, a front light may be provided outside the polarizing plate. As the front light, an edge light type front light is preferably used. It is preferable to use a front light including an LED (Light Emitting Diode) because power consumption can be reduced.

[Light emitting element]
As the light-emitting element, an element capable of self-emission can be used, and an element whose luminance is controlled by current or voltage is included in its category. For example, an LED, an organic EL element, an inorganic EL element, or the like can be used.

  Light emitting elements include a top emission type, a bottom emission type, and a dual emission type. A conductive film that transmits visible light is used for the electrode from which light is extracted. In addition, a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted. In one embodiment of the present invention, it is particularly preferable to use a bottom emission light-emitting element.

  The EL layer has at least a light emitting layer. The EL layer is a layer other than the light-emitting layer, such as a substance having a high hole injection property, a substance having a high hole transport property, a hole blocking material, a substance having a high electron transport property, a substance having a high electron injection property, or a bipolar property. A layer including a substance (a substance having a high electron transporting property and a high hole transporting property) and the like may be further included.

  Either a low molecular compound or a high molecular compound can be used for the EL layer, and an inorganic compound may be included. The layers constituting the EL layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink jet method, or a coating method.

  When a voltage higher than the threshold voltage of the light emitting element is applied between the cathode and the anode, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer, and the light-emitting substance contained in the EL layer emits light.

  In the case where a white light-emitting element is used as the light-emitting element, the EL layer preferably includes two or more light-emitting substances. For example, white light emission can be obtained by selecting the light emitting material so that the light emission of each of the two or more light emitting materials has a complementary color relationship. For example, a luminescent material that emits light such as R (red), G (green), B (blue), Y (yellow), and O (orange), or spectral components of two or more colors of R, G, and B It is preferable that 2 or more are included among the luminescent substances which show light emission containing. In addition, it is preferable to apply a light-emitting element whose emission spectrum from the light-emitting element has two or more peaks within a wavelength range of visible light (for example, 350 nm to 750 nm). The emission spectrum of the material having a peak in the yellow wavelength region is preferably a material having spectral components in the green and red wavelength regions.

  The EL layer preferably has a structure in which a light-emitting layer including a light-emitting material that emits one color and a light-emitting layer including a light-emitting material that emits another color are stacked. For example, the plurality of light emitting layers in the EL layer may be stacked in contact with each other, or may be stacked through a region not including any light emitting material. For example, a region including the same material (for example, a host material or an assist material) as the fluorescent light emitting layer or the phosphorescent light emitting layer and not including any light emitting material is provided between the fluorescent light emitting layer and the phosphorescent light emitting layer. Also good. This facilitates the production of the light emitting element and reduces the driving voltage.

  The light-emitting element may be a single element having one EL layer or a tandem element in which a plurality of EL layers are stacked with a charge generation layer interposed therebetween.

  The conductive film that transmits visible light can be formed using, for example, indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide to which gallium is added, or the like. In addition, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, an alloy containing these metal materials, or a nitride of these metal materials (for example, Titanium nitride) can also be used by forming it thin enough to have translucency. In addition, a stacked film of the above materials can be used as a conductive layer. For example, it is preferable to use a stacked film of an alloy of silver and magnesium and indium tin oxide because the conductivity can be increased. Further, graphene or the like may be used.

  For the conductive film that reflects visible light, for example, a metal material such as aluminum, gold, platinum, silver, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, or palladium, or an alloy including these metal materials is used. Can do. In addition, lanthanum, neodymium, germanium, or the like may be added to the metal material or alloy. Alternatively, titanium, nickel, or neodymium and an alloy containing aluminum (aluminum alloy) may be used. Alternatively, an alloy containing copper, palladium, magnesium, and silver may be used. An alloy containing silver and copper is preferable because of its high heat resistance. Furthermore, oxidation can be suppressed by stacking a metal film or a metal oxide film in contact with the aluminum film or the aluminum alloy film. Examples of materials for such metal films and metal oxide films include titanium and titanium oxide. Alternatively, the conductive film that transmits visible light and a film made of a metal material may be stacked. For example, a laminated film of silver and indium tin oxide, a laminated film of an alloy of silver and magnesium and indium tin oxide, or the like can be used.

  The electrodes may be formed using a vapor deposition method or a sputtering method, respectively. In addition, it can be formed using a discharge method such as an inkjet method, a printing method such as a screen printing method, or a plating method.

  Note that the above-described light-emitting layer and a layer containing a substance having a high hole-injecting property, a substance having a high hole-transporting property, a substance having a high electron-transporting property, a substance having a high electron-injecting property, a bipolar substance, Each may have an inorganic compound such as a quantum dot or a polymer compound (oligomer, dendrimer, polymer, etc.). For example, a quantum dot can be used for a light emitting layer to function as a light emitting material.

  As the quantum dot material, a colloidal quantum dot material, an alloy type quantum dot material, a core / shell type quantum dot material, a core type quantum dot material, or the like can be used. Alternatively, a material including an element group of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used. Alternatively, a quantum dot material containing an element such as cadmium, selenium, zinc, sulfur, phosphorus, indium, tellurium, lead, gallium, arsenic, or aluminum may be used.

[Adhesive layer]
As the adhesive layer, various curable adhesives such as an ultraviolet curable photocurable adhesive, a reactive curable adhesive, a thermosetting adhesive, and an anaerobic adhesive can be used. Materials for these adhesives include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin, etc. Can be mentioned. In particular, a material with low moisture permeability such as an epoxy resin is preferable. Alternatively, a two-component mixed resin may be used. Further, an adhesive sheet or the like may be used.

  Further, the resin may contain a desiccant. For example, a substance that adsorbs moisture by chemical adsorption, such as an alkaline earth metal oxide (such as calcium oxide or barium oxide), can be used. Alternatively, a substance that adsorbs moisture by physical adsorption, such as zeolite or silica gel, may be used. The inclusion of a desiccant is preferable because impurities such as moisture can be prevented from entering the element and the reliability of the display device is improved.

  In addition, light extraction efficiency can be improved by mixing a filler having a high refractive index or a light scattering member with the resin. For example, titanium oxide, barium oxide, zeolite, zirconium, or the like can be used.

[Connection layer]
As the connection layer, an anisotropic conductive film (ACF: Anisotropic Conductive Film), an anisotropic conductive paste (ACP: Anisotropic Conductive Paste), or the like can be used.

[Colored layer]
Examples of materials that can be used for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, and the like.

[Shading layer]
Examples of the material that can be used for the light-shielding layer include carbon black, titanium black, metal, metal oxide, and composite oxide containing a solid solution of a plurality of metal oxides. The light shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. Alternatively, a stacked film of a film containing a material for the colored layer can be used for the light shielding layer. For example, a stacked structure of a film including a material used for a colored layer that transmits light of a certain color and a film including a material used for a colored layer that transmits light of another color can be used. It is preferable to use the same material for the coloring layer and the light shielding layer because the apparatus can be shared and the process can be simplified.

  This completes the description of each component.

[Example of production method]
Next, an example of a method for manufacturing a display device using a flexible substrate is described.

  Here, a layer including a display element, a circuit, a wiring, an electrode, an optical member such as a coloring layer or a light shielding layer, and an insulating layer is collectively referred to as an element layer. For example, the element layer includes a display element, and may include an element such as a wiring that is electrically connected to the display element, a transistor used for a pixel, or a circuit in addition to the display element.

  Here, a member that supports the element layer and has flexibility when the display element is completed (the manufacturing process is completed) is referred to as a substrate. For example, the substrate includes a very thin film having a thickness of 10 nm to 300 μm.

  As a method for forming an element layer over a flexible substrate having an insulating surface, there are typically the following two methods. One is a method of forming an element layer directly on a substrate. The other is a method of forming an element layer on a support base different from the substrate, then peeling the element layer and the support base and transferring the element layer to the substrate. Although not described in detail here, in addition to the above two methods, an element layer is formed on a non-flexible substrate, and the substrate is thinned by polishing or the like, thereby providing flexibility. There is also a method.

  In the case where the material constituting the substrate has heat resistance against the heat applied to the element layer forming step, it is preferable to form the element layer directly on the substrate because the process is simplified. At this time, it is preferable to form the element layer in a state in which the substrate is fixed to the supporting base material, because it is easy to carry the device inside and between devices.

  In the case of using a method in which the element layer is formed on the supporting base material and then transferred to the substrate, a peeling layer and an insulating layer are first stacked on the supporting base material, and the element layer is formed on the insulating layer. Then, it peels between a support base material and an element layer, and transfers an element layer to a board | substrate. At this time, a material that causes peeling in the interface between the supporting substrate and the peeling layer, the interface between the peeling layer and the insulating layer, or the peeling layer may be selected. In this method, by using a material having high heat resistance for the support substrate and the release layer, the upper limit of the temperature required for forming the element layer can be increased, and an element layer having a more reliable element is formed. This is preferable because it is possible.

  For example, a layer containing a refractory metal material such as tungsten and a layer containing an oxide of the metal material are stacked as the separation layer, and silicon oxide, silicon nitride, or silicon oxynitride is used as the insulating layer over the separation layer. It is preferable to use a layer in which a plurality of silicon nitride oxides or the like are stacked. Note that in this specification, oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Point to.

  Examples of methods for peeling the element layer and the supporting substrate include applying a mechanical force, etching the peeling layer, or infiltrating a liquid into the peeling interface. Or you may peel by heating or cooling using the difference of the thermal expansion of two layers which form a peeling interface.

  In the case where peeling is possible at the interface between the support base and the insulating layer, the peeling layer may not be provided.

  For example, glass can be used as the supporting substrate, and an organic resin such as polyimide can be used as the insulating layer. At this time, a part of the organic resin is locally heated using a laser beam or the like, or a part of the organic resin is physically cut or penetrated by a sharp member, etc. Peeling may be performed at the interface between the glass and the organic resin.

  Alternatively, peeling may be performed at the interface between the heat generation layer and the insulating layer by providing a heat generation layer between the support base and the insulating layer made of an organic resin and heating the heat generation layer. As the heat generating layer, various materials such as a material that generates heat when an electric current flows, a material that generates heat by absorbing light, and a material that generates heat by applying a magnetic field can be used. For example, the heat generating layer can be selected from semiconductors, metals, and insulators.

  Note that in the above-described method, the insulating layer formed of an organic resin can be used as a substrate after peeling.

  The above is the description of the example of the method for manufacturing the display device using the flexible substrate.

  This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 5)
In this embodiment, structural examples of OS transistors that can be used in the above embodiments are described.

<Example of transistor structure>
FIG. 13A is a top view illustrating a structural example of a transistor. 13B is a cross-sectional view taken along line X1-X2 in FIG. 13A, and FIG. 13C is a cross-sectional view taken along line Y1-Y2. Here, the X1-X2 line direction may be referred to as a channel length direction, and the Y1-Y2 line direction may be referred to as a channel width direction. FIG. 13B illustrates a cross-sectional structure of the transistor in the channel length direction, and FIG. 13C illustrates a cross-sectional structure of the transistor in the channel width direction. Note that in order to clarify the device structure, some components are not illustrated in FIG.

  The semiconductor device according to one embodiment of the present invention includes the insulating layers 812 to 820, the metal oxide films 821 to 824, and the conductive layers 850 to 853. The transistor 801 is formed on an insulating surface. FIG. 13 illustrates the case where the transistor 801 is formed over the insulating layer 811. The transistor 801 is covered with an insulating layer 818 and an insulating layer 819.

  Note that the insulating layer, the metal oxide film, the conductive layer, and the like included in the transistor 801 may be a single layer or a stack of a plurality of films. For these production, various film forming methods such as sputtering, electron beam epitaxy (MBE), pulsed laser ablation (PLD), CVD, atomic layer deposition (ALD) can be used. . Note that the CVD method includes a plasma CVD method, a thermal CVD method, an organic metal CVD method, and the like.

  In the transistor 801, the conductive layer 850 (the conductive layer 850a and the conductive layer 850b) includes a region functioning as a gate electrode. The conductive layer 851 and the conductive layer 852 have a region functioning as a source electrode or a drain electrode. The conductive layer 853 (the conductive layer 853a and the conductive layer 853b) includes a region functioning as a bottom gate electrode. The insulating layer 817 has a region that functions as a gate insulator on the gate electrode side, and the insulating layer formed by stacking the insulating layers 814 to 816 has a region that functions as a gate insulator on the bottom gate electrode side. Have. The insulating layer 818 functions as an interlayer insulating layer. The insulating layer 819 functions as a barrier layer.

  The metal oxide films 821 to 824 are collectively referred to as an oxide layer 830. As illustrated in FIGS. 13B and 13C, the oxide layer 830 includes a region in which a metal oxide film 821, a metal oxide film 822, and a metal oxide film 824 are sequentially stacked. The pair of metal oxide films 823 are located over the conductive layers 851 and 852, respectively. When the transistor 801 is on, the channel region is mainly formed in the metal oxide film 822 in the oxide layer 830.

  The metal oxide film 824 covers the metal oxide films 821 to 823, the conductive layer 851, and the conductive layer 852. The insulating layer 817 is located between the metal oxide film 824 and the conductive layer 850. The conductive layer 851 and the conductive layer 852 each have a region overlapping with the conductive layer 850 with the metal oxide film 823, the metal oxide film 824, and the insulating layer 817 interposed therebetween.

  The conductive layer 851 and the conductive layer 852 are formed using a hard mask for forming the metal oxide film 821 and the metal oxide film 822. Therefore, the conductive layer 851 and the conductive layer 852 do not have a region in contact with the side surfaces of the metal oxide film 821 and the metal oxide film 822. For example, the metal oxide film 821, the metal oxide film 822, the conductive layer 851, and the conductive layer 852 can be manufactured through the following steps. First, a conductive film is formed over two stacked metal oxide films. The conductive film is processed (etched) into a desired shape to form a hard mask. Using the hard mask, the shape of the two-layer metal oxide film is processed to form a stacked metal oxide film 821 and a metal oxide film 822. Next, the hard mask is processed into a desired shape, so that a conductive layer 851 and a conductive layer 852 are formed.

  Examples of the insulating material used for the insulating layers 811 to 818 include aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, Examples include germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and aluminum silicate. The insulating layers 811 to 818 are each formed using a single layer or a stacked layer using any of these insulating materials. The layers included in the insulating layers 811 to 818 may include a plurality of insulating materials.

  In order to suppress an increase in oxygen vacancies in the oxide layer 830, the insulating layers 816 to 818 are preferably insulating layers containing oxygen. The insulating layers 816 to 818 are more preferably formed using an insulating film from which oxygen is released by heating (hereinafter also referred to as “insulating film containing excess oxygen”). By supplying oxygen from the insulating film containing excess oxygen to the oxide layer 830, oxygen vacancies in the oxide layer 830 can be compensated. Accordingly, electrical characteristics and reliability of the transistor 801 can be improved.

An insulating film containing excess oxygen refers to oxygen molecules in a temperature range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower in TDS (Thermal Desorption Spectroscopy). A film having a release amount of 1 × 10 ¹⁴ molecules / cm ² or more is used. The release amount of oxygen molecules is more preferably 1 × 10 ¹⁵ molecules / cm ² or more.

The insulating film containing excess oxygen can be formed by performing treatment for adding oxygen to the insulating film. The treatment for adding oxygen can be performed by heat treatment in an oxygen atmosphere, ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like. As a gas for adding oxygen, oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas, or ozone gas can be used.

In order to prevent an increase in the hydrogen concentration of the oxide layer 830, the hydrogen concentration in the insulating layers 812 to 819 is preferably reduced. In particular, the hydrogen concentration in the insulating layers 813 to 818 is preferably reduced. Specifically, the hydrogen concentration is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and 5 × More preferably, it is 10 ¹⁸ atoms / cm ³ or less.

In order to prevent an increase in the nitrogen concentration of the oxide layer 830, it is preferable to reduce the nitrogen concentration in the insulating layers 813 to 818. Specifically, the nitrogen concentration is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and 5 × More preferably, it is 10 ¹⁷ atoms / cm ³ or less.

  The above-mentioned hydrogen concentration and nitrogen concentration are values measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).

  The transistor 801 preferably has a structure in which the oxide layer 830 is surrounded by an insulating layer having a barrier property against oxygen and hydrogen (hereinafter also referred to as a barrier layer). With such a structure, release of oxygen from the oxide layer 830 and entry of hydrogen into the oxide layer 830 can be suppressed. Accordingly, electrical characteristics and reliability of the transistor 801 can be improved.

  For example, the insulating layer 819 may function as a barrier layer, and at least one of the insulating layer 811, the insulating layer 812, and the insulating layer 814 may function as a barrier layer. The barrier layer can be formed using a material such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or silicon nitride.

  Structural examples of the insulating layers 811 to 819 are described. In this example, the insulating layer 811, the insulating layer 812, the insulating layer 815, and the insulating layer 819 each function as a barrier layer. The insulating layers 816 to 818 are oxide layers containing excess oxygen. The insulating layer 811 is silicon nitride, the insulating layer 812 is aluminum oxide, and the insulating layer 813 is silicon oxynitride. The insulating layers 814 to 816 each functioning as a gate insulator on the bottom gate electrode side are stacked layers of silicon oxide, aluminum oxide, and silicon oxide. The insulating layer 817 having a function as a gate insulator on the gate (top gate) side is silicon oxynitride. The insulating layer 818 functioning as an interlayer insulating layer is silicon oxide. The insulating layer 819 is aluminum oxide.

  As a conductive material used for the conductive layers 850 to 853, a metal such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or a metal nitride containing any of the above metals (nitriding) Tantalum, titanium nitride, molybdenum nitride, tungsten nitride) and the like. For example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added A conductive material such as indium tin oxide can be used.

  Examples of structures of the conductive layers 850 to 853 are described. The conductive layer 850 is a tantalum nitride single layer or a tungsten single layer. Alternatively, the conductive layer 850 is a stack including tantalum nitride and tungsten. The conductive layer 851 is a single layer of tantalum nitride or a stack of tantalum nitride and tungsten. The structure of the conductive layer 852 is the same as that of the conductive layer 851. The conductive layer 853 is a stack including tantalum nitride and tungsten.

  In order to reduce the off-state current of the transistor 801, the metal oxide film 822 preferably has a large band gap, for example. The band gap of the metal oxide film 822 is 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, more preferably 3.0 eV or more and 3.5 eV or less.

  The oxide layer 830 preferably has crystallinity. At least, the metal oxide film 822 preferably has crystallinity. With the above structure, the transistor 801 with excellent electrical characteristics and reliability can be realized.

  Examples of the oxide that can be used for the metal oxide film 822 are In—Ga oxide, In—Zn oxide, and In—M—Zn oxide (M is Al, Ga, Y, or Sn). The metal oxide film 822 is not limited to an oxide film containing In. The metal oxide film 822 can be formed using, for example, a Zn—Sn oxide, a Ga—Sn oxide, a Zn—Mg oxide, or the like. The metal oxide film 821, the metal oxide film 823, and the metal oxide film 824 can also be formed using the same oxide as the metal oxide film 822. In particular, the metal oxide film 821, the metal oxide film 823, and the metal oxide film 824 can each be formed using Ga oxide.

  In the transistor 801, a channel region can be formed not only in the metal oxide film 822 but also in the vicinity of the interface between the metal oxide film 822 and the metal oxide film 821. Therefore, for example, when an interface state is formed at the interface, the threshold voltage of the transistor 801 may fluctuate. Therefore, the metal oxide film 821 preferably includes at least one of metal elements included in the metal oxide film 822 as a component. Accordingly, an interface state is hardly formed at the interface between the metal oxide film 822 and the metal oxide film 821, and variation in electric characteristics such as a threshold voltage in the transistor 801 can be reduced.

  The metal oxide film 824 preferably includes at least one of metal elements included in the metal oxide film 822 as a component. Accordingly, at the interface between the metal oxide film 822 and the metal oxide film 824, interface scattering of carriers is less likely to occur, and the movement of carriers is less likely to be inhibited, so that the field-effect mobility of the transistor 801 can be increased. it can.

  Of the metal oxide films 821 to 824, the metal oxide film 822 preferably has the highest carrier mobility. Accordingly, a channel region is formed in the insulating layer 816 (the gate insulator on the bottom gate electrode side of the transistor 801) and the metal oxide film 822 that is separated from the insulating layer 817 (the gate insulator on the gate electrode side of the transistor 801). can do.

  For example, an In-containing metal oxide such as an In-M-Zn oxide can increase carrier mobility by increasing the In content. In an In-M-Zn oxide, an s orbital of heavy metal mainly contributes to carrier conduction, and by increasing the In content, more s orbitals overlap, so that the oxide having a high indium content is high. Has higher carrier mobility than an oxide having a low In content. Therefore, carrier mobility can be increased by using an oxide with a high In content for the metal oxide film.

  Therefore, for example, the metal oxide film 822 is formed using In—Ga—Zn oxide, and the metal oxide film 821, the metal oxide film 823, and the metal oxide film 824 are formed using Ga oxide. For example, in the case where the metal oxide films 821 to 824 are formed using In-M-Zn oxide, the In content in the metal oxide film 822 is set to the metal oxide film 821 or the metal oxide film 823. The content ratio of In in the metal oxide film 824 is set higher. In the case where an In-M-Zn oxide is formed by a sputtering method, the In content can be changed by changing the atomic ratio of the target.

  For example, the atomic number ratio In: M: Zn of the target used for forming the metal oxide film 822 is preferably 1: 1: 1, 3: 1: 2, or 4: 2: 4.1. For example, the atomic ratio In: M: Zn of the target used for forming the metal oxide film 821, the metal oxide film 823, and the metal oxide film 824 is preferably 1: 3: 2 or 1: 3: 4. . The atomic ratio of the In-M-Zn oxide formed with a target of In: M: Zn = 4: 2: 4.1 is approximately In: M: Zn = 4: 2: 3.

  In order to impart stable electric characteristics to the transistor 801, the impurity concentration of the oxide layer 830 is preferably reduced. In the metal oxide, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Silicon and carbon contribute to the formation of impurity levels in the metal oxide. The impurity level becomes a trap and may deteriorate the electrical characteristics of the transistor.

For example, the oxide layer 830 has a region with a silicon concentration of 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less. The same applies to the carbon concentration of the oxide layer 830.

For example, the oxide layer 830 has a region with an alkali metal concentration of 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. The same applies to the alkaline earth metal concentration of the oxide layer 830.

For example, the oxide layer 830 has a nitrogen concentration of less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 It has the area | region of * 10 < ¹⁷ > atoms / cm < ³ > or less.

For example, the oxide layer 830 has a hydrogen concentration of less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and even more preferably 1 It has a region of less than × 10 ¹⁸ atoms / cm ³ .

  The impurity concentration of the oxide layer 830 listed above is a value obtained by SIMS.

  In the case where the metal oxide film 822 has oxygen vacancies, hydrogen may enter a site of oxygen vacancies to form donor levels. As a result, the on-state current of the transistor 801 may be reduced. Note that oxygen deficient sites are more stable when oxygen enters than when hydrogen enters. Therefore, in some cases, the on-state current of the transistor 801 can be increased by supplying oxygen into the metal oxide film 822 to reduce oxygen vacancies in the film. It is also effective for improving the on-state characteristics of the transistor 801 to reduce hydrogen in the metal oxide film 822 so that hydrogen does not enter oxygen deficient sites in the film.

  Hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed in the metal oxide. Then, when hydrogen enters oxygen vacancies, electrons as carriers may be generated. In addition, part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons that are carriers. In the transistor 801 according to one embodiment of the present invention, a channel region is mainly formed in the metal oxide film 822. Therefore, when the metal oxide film 822 contains hydrogen, the transistor 801 is likely to be normally on. For this reason, it is preferable that hydrogen in the metal oxide film 822 be reduced as much as possible.

  FIG. 13 illustrates an example in which the oxide layer 830 has a four-layer structure; however, one embodiment of the present invention is not limited thereto. For example, the oxide layer 830 can have a three-layer structure without the metal oxide film 821 or the metal oxide film 823. Alternatively, a metal oxide is disposed between any film of the oxide layer 830 (the metal oxide film 821 to the metal oxide film 824), two or more places above the oxide layer 830 and under the oxide layer 830. One or more metal oxide films similar to the films 821 to 824 can be provided.

  The effect obtained by stacking the metal oxide film 821, the metal oxide film 822, and the metal oxide film 824 will be described with reference to FIG. FIG. 14 is a schematic diagram of an energy band structure in a channel formation region of the transistor 801.

  In FIG. 14, Ec816e, Ec821e, Ec822e, Ec824e, and Ec817e indicate the energy at the lower end of the conduction band of the insulating layer 816, the metal oxide film 821, the metal oxide film 822, the metal oxide film 824, and the insulating layer 817, respectively. ing.

  Here, the difference between the vacuum level and the energy at the bottom of the conduction band (also referred to as electron affinity) is obtained by subtracting the band gap from the difference between the vacuum level and the energy at the top of the valence band (also referred to as ionization potential). Value. The band gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300). The energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus (PHI VersaProbe).

  Since the insulating layers 816 and 817 are insulators, Ec816e and Ec817e are closer to the vacuum level (having a lower electron affinity) than Ec821e, Ec822e, and Ec824e.

  The metal oxide film 822 has higher electron affinity than the metal oxide film 821 and the metal oxide film 824. For example, the difference in electron affinity between the metal oxide film 822 and the metal oxide film 821 and the difference in electron affinity between the metal oxide film 822 and the metal oxide film 824 are 0.07 eV or more and 1.3 eV or less, respectively. It is. The difference in electron affinity is preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less.

  When voltage is applied to the gate electrode (the conductive layer 850) of the transistor 801, a channel is mainly formed in the metal oxide film 822 having the highest electron affinity among the metal oxide film 821, the metal oxide film 822, and the metal oxide film 824. A region is formed.

  In—Ga oxide has a small electron affinity and a high oxygen blocking property. Therefore, the metal oxide film 824 preferably contains an In—Ga oxide. The Ga atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

  There may be a mixed region of the metal oxide film 821 and the metal oxide film 822 between the metal oxide film 821 and the metal oxide film 822. There may be a mixed region of the metal oxide film 824 and the metal oxide film 822 between the metal oxide film 824 and the metal oxide film 822. The interface state density in the mixed region is lower than the interface state density between the metal oxide film 821 and the insulating layer 816 and the interface state density between the metal oxide film 824 and the insulating layer 817. Therefore, a region where the metal oxide film 821, the metal oxide film 822, and the metal oxide film 824 are stacked has a band structure in which energy continuously changes (also referred to as continuous bonding) in the vicinity of each interface. .

  In the oxide layer 830 having such an energy band structure, electrons that are carriers move mainly through the metal oxide film 822. Therefore, even if a level exists at the interface between the metal oxide film 821 and the insulating layer 816 or the interface between the metal oxide film 824 and the insulating layer 817, the interface level causes the oxide layer 830 to Therefore, the on-state current of the transistor 801 can be increased.

  As shown in FIG. 14, trap levels Et826e caused by impurities and defects are present near the interface between the metal oxide film 821 and the insulating layer 816 and near the interface between the metal oxide film 824 and the insulating layer 817, respectively. Although the trap level Et827e can be formed, the metal oxide film 821 and the metal oxide film 824 can separate the metal oxide film 822 from the trap level Et826e and the trap level Et827e. Therefore, electrons moving through the metal oxide film 822 are not easily captured by the trap level Et826e and the trap level Et827e, and the electron capture is prevented from adversely affecting the electrical characteristics and reliability of the transistor 801 (described later). be able to.

  Note that in the case where the difference between Ec821e and Ec822e is small, electrons in the metal oxide film 822 may reach the trap level Et826e exceeding the energy difference. When electrons are trapped in the trap level Et826e, negative fixed charges are generated at the interface of the insulating layer 816, and the threshold voltage of the transistor 801 is shifted in the positive direction. The same applies when the energy difference between Ec822e and Ec824e is small.

  In order to reduce the variation in the threshold voltage of the transistor 801 and improve the electrical characteristics of the transistor 801, it is preferable that the difference between Ec821e and Ec822e and the difference between Ec824e and Ec822e be 0.1 eV or more, More preferably, it is 0.15 eV or more.

  Note that the transistor 801 can have a structure without the bottom gate electrode (the conductive layer 853).

<CAC-OS>
Next, the CAC-OS will be described. The CAC-OS may be included in the channel formation region of the OS transistor.

  The CAC-OS is one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as mosaic or patch.

  Note that the metal oxide preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. One kind selected from the above or a plurality of kinds may be included.

For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). _X1 (X1 is greater real than 0) and.), or indium zinc oxide _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic _{InO X1,} or _in X2 _Zn Y2 _{O Z2} is configured uniformly distributed in the film (hereinafter, cloud Also referred to.) A.

That, CAC-OS includes a region _{GaO X3} is the main _component, In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} there is a region which is a main component, a composite metal oxide having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.

Note that IGZO is a common name and sometimes refers to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.

  The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

  On the other hand, CAC-OS relates to a material structure of a metal oxide. CAC-OS refers to a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn, and O, and nanoparticles that are partially composed mainly of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.

  Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.

Incidentally, a region _{GaO X3} is the main _component, In _{X2 Zn} Y2 _{O Z2,} or the region _{InO X1} is the main component, it may be difficult to observe a clear boundary.

  Instead of gallium, selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. In the case where one or more types are included, the CAC-OS includes a region observed in a part of a nanoparticle mainly including the metal element and a nano part mainly including In. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.

  The CAC-OS can be formed by a sputtering method under a condition that the substrate is not intentionally heated, for example. In the case where a CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. For example, the flow rate ratio of the oxygen gas is 0% to less than 30%, preferably 0% to 10%. .

  The CAC-OS is characterized in that no clear peak is observed when measured using a θ / 2θ scan by an out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.

  In addition, in the CAC-OS, in an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-shaped high luminance region and a plurality of regions in the ring region are provided. A bright spot is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

In addition, for example, in a CAC-OS in an In—Ga—Zn oxide, GaO _X3 is a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region and the region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 are unevenly distributed and mixed.

The CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO _X3 or the like is a main component and a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is a region having higher conductivity than a region containing GaO _X3 or the like as a main component. _That, In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is a region which is a main component, by carriers flow, conductive metal oxide is expressed. Therefore, a region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 is distributed in a cloud shape in the metal oxide, so that a semiconductor element using the metal oxide achieves high field effect mobility. it can.

On the other hand, areas such as _{GaO X3} is the main _component, In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is compared to region which is a main component, has a high area insulation. In other words, when a region containing GaO _X3 or the like as a main component is distributed in the metal oxide, a semiconductor element using the metal oxide can suppress a leakage current and realize a favorable switching operation.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _{X3 and the} like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act complementarily, The semiconductor element can realize a good switching operation having both high on-current and field-effect mobility and low leakage current.

  In addition, a semiconductor element using a CAC-OS has favorable reliability. Therefore, the CAC-OS is optimal for application to various semiconductor devices.

  This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 6)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to an electronic component, and an example of an electronic device that can include the electronic component will be described with reference to FIGS.

<Wafer / Chip>
FIG. 15A shows a top view of the substrate 1001 before the dicing process is performed. As the substrate 1001, for example, a semiconductor substrate (also referred to as a semiconductor wafer) can be used. A plurality of circuit regions 1002 are provided on the substrate 1001. In the circuit region 1002, the semiconductor device described in any of the above embodiments can be provided.

  The plurality of circuit regions 1002 are each surrounded by the isolation region 1003. A separation line (also referred to as a dicing line) 1004 is set at a position overlapping the separation region 1003. The chip 1005 including the circuit region 1002 can be cut out from the substrate 1001 by cutting the substrate 1001 along the separation line 1004. FIG. 15B shows an enlarged view of the chip 1005.

  Further, a conductive layer or a semiconductor layer may be provided in the separation region 1003. By providing a conductive layer or a semiconductor layer in the separation region 1003, ESD (Electro-Static Discharge) that can occur in the dicing process can be reduced, and a decrease in yield due to the dicing process can be prevented. In general, the dicing process is performed while flowing pure water having a reduced specific resistance by dissolving carbon dioxide gas or the like for the purpose of cooling the substrate, removing shavings, preventing charging, and the like. By providing a conductive layer or a semiconductor layer in the separation region 1003, the amount of pure water used can be reduced. Thus, the production cost of the semiconductor device can be reduced. In addition, productivity of the semiconductor device can be increased.

  As the semiconductor layer provided in the separation region 1003, a material having a band gap of 2.5 eV to 4.2 eV, preferably 2.7 eV to 3.5 eV is preferably used. By using such a material, charges accumulated on the substrate 1001 can be discharged slowly, so that rapid movement of charges due to ESD is suppressed, and electrostatic breakdown of each element in the chip 1005 occurs. Can be difficult.

<Electronic parts>
An example in which the chip 1005 is applied to an electronic component will be described with reference to FIG. Note that the electronic component is also referred to as a semiconductor package or an IC package. There are a plurality of standards and names for electronic components depending on the terminal extraction direction and the shape of the terminals.

  Electronic components are completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post-process).

  The post-process will be described with reference to the flowchart shown in FIG. In the previous process, after the element substrate having the semiconductor device described in the above embodiment is completed, a “back surface grinding process” is performed in which the back surface of the element substrate (the surface on which the semiconductor device or the like is not formed) is ground (step) S1). By thinning the element substrate by grinding, it is possible to reduce warpage of the element substrate and to reduce the size of the electronic component.

  Next, a “dicing process” for separating the element substrate into a plurality of chips is performed (step S2). Then, a “die bonding step” is performed in which each separated chip is picked up and bonded onto the lead frame (step S3). For the bonding of the chip and the lead frame in the die bonding process, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. A chip may be bonded on the interposer substrate instead of the lead frame.

  Next, a “wire bonding process” is performed in which the lead of the lead frame and the electrode on the chip are electrically connected by a thin metal wire (wire) (step S4). A silver wire or a gold wire can be used as the metal thin wire. For wire bonding, ball bonding or wedge bonding can be used.

  The wire-bonded chip is subjected to a “sealing process (molding process)” that is sealed with an epoxy resin or the like (step S5). By performing the sealing process, the inside of the electronic component is filled with resin, and the circuit part built in the chip and the wire connecting the chip and the lead can be protected from mechanical external force, and characteristics due to moisture and dust Degradation (decrease in reliability) can be reduced.

  Next, a “lead plating process” for plating the leads of the lead frame is performed (step S6). The plating process prevents the lead from rusting, and enables more reliable soldering when subsequently provided on the printed circuit board. Next, a “molding process” for cutting and molding the lead is performed (step S7).

  Next, a “marking process” is performed in which a printing process (marking) is performed on the surface of the package (step S8). An electronic component is completed through an “inspection process” (step S9) for checking the appearance shape and the presence or absence of malfunction.

  A perspective schematic view of the completed electronic component is shown in FIG. FIG. 16B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 1101 illustrated in FIG. 16B is a semiconductor device with leads. As the semiconductor device, the semiconductor device described in any of the above embodiments can be used.

  An electronic component 1101 illustrated in FIG. 16B is provided over a printed board 1102, for example. A plurality of such electronic components 1101 are combined and electrically connected to each other on the printed circuit board 1102 to complete the substrate 1103 provided with the electronic components. The completed substrate 1103 is used for an electronic device or the like.

<Electronic equipment>
The board 1103 includes digital signal processing, software defined radio, avionics (electronic equipment related to aviation such as communication equipment, navigation system, autopilot, and flight management system), ASIC prototyping, medical image processing, voice recognition, and encryption. It can be applied to electronic components (IC chips) of a wide range of electronic devices such as bioinformatics (biological information science), emulators of mechanical devices, and radio telescopes in radio astronomy. Such electronic devices include cameras (video cameras, digital still cameras, etc.), display devices, personal computers (PCs), mobile phones, portable game machines, portable information terminals (smartphones, tablet information terminals, etc.) ), E-book terminal, wearable information terminal (clock type, head mount type, goggles type, glasses type, armband type, bracelet type, necklace type, etc.), navigation system, sound playback device (car audio, digital audio player, etc.) , Copiers, facsimiles, printers, printer multifunction devices, automatic teller machines (ATMs), vending machines, household appliances, and the like.

  Hereinafter, a configuration example of the electronic device will be described with reference to FIGS. 17 and 18. Note that a touch panel device having a touch sensor is preferably used for the display portion of the electronic device. By using the touch panel device, the display unit can function as an input unit of the electronic device.

  An example of the portable information terminal 2000 is shown in FIGS. The portable information terminal 2000 includes a housing 2001, a housing 2002, a display portion 2003, a display portion 2004, a hinge portion 2005, and the like.

  The housing 2001 and the housing 2002 are connected by a hinge portion 2005. The portable information terminal 2000 can open the housing 2001 and the housing 2002 as shown in FIG. 17B from the folded state as shown in FIG.

  For example, document information can be displayed on the display portion 2003 and the display portion 2004, and the portable information terminal 2000 can be used as an electronic book terminal. Still images and moving images can be displayed on the display portion 2003 and the display portion 2004. The display unit 2003 may have a touch panel.

  Thus, since the portable information terminal 2000 can be folded when carried, it is excellent in versatility.

  Note that the housing 2001 and the housing 2002 may include a power button, an operation button, an external connection port, a speaker, a microphone, and the like.

  Note that the portable information terminal 2000 may have a function of identifying characters, figures, and images using a touch sensor provided in the display portion 2003. In this case, for example, learning is performed such that an answer is written with a finger or a stylus pen on an information terminal that displays a collection of questions for learning mathematics or language, and the mobile information terminal 2000 makes a correct / incorrect determination. It can be carried out. Further, the portable information terminal 2000 may have a function of performing speech decoding. In this case, for example, foreign language learning or the like can be performed using the portable information terminal 2000. Such portable information terminals are suitable for use as teaching materials such as textbooks or notebooks.

  FIG. 17C illustrates an example of a portable information terminal. A portable information terminal 2010 illustrated in FIG. 17C includes a housing 2011, a display portion 2012, operation buttons 2013, an external connection port 2014, a speaker 2015, a microphone 2016, a camera 2017, and the like.

  The portable information terminal 2010 includes a touch sensor in the display unit 2012. Various operations such as making a call or inputting characters can be performed by touching the display portion 2012 with a finger or a stylus.

  Further, the operation of the operation button 2013 can switch the power on / off operation and the type of image displayed on the display unit 2012. For example, the mail creation screen can be switched to the main menu screen.

  Further, by providing a detection device such as a gyro sensor or an acceleration sensor inside the portable information terminal 2010, the orientation (portrait or landscape) of the portable information terminal 2010 is determined, and the screen display direction of the display unit 2012 is determined. It can be switched automatically. The screen display orientation can also be switched by touching the display portion 2012, operating the operation buttons 2013, inputting voice using the microphone 2016, or the like.

  The portable information terminal 2010 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. For example, the portable information terminal 2010 can be used as a smartphone. The mobile information terminal 2010 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, video playback, Internet communication, and games.

  FIG. 17D illustrates an example of a camera. The camera 2020 includes a housing 2021, a display portion 2022, operation buttons 2023, a shutter button 2024, and the like. The camera 2020 is provided with a detachable lens 2026.

  Although the lens 2020 can be removed from the housing 2021 and replaced as the camera 2020 here, the lens 2026 and the housing 2021 may be integrated.

  The camera 2020 can capture a still image or a moving image by pressing a shutter button 2024. In addition, the display portion 2022 has a function as a touch panel and can capture an image by touching the display portion 2022.

  The camera 2020 can be separately attached with a strobe device, a viewfinder, and the like. Alternatively, these may be incorporated in the housing 2021.

  A notebook PC (personal computer) 2050 illustrated in FIG. 18A includes a housing 2051, a display portion 2052, a keyboard 2053, and a pointing device 2054. The notebook PC 2050 can be operated by a touch operation on the display portion 2052.

  A portable game machine 2110 illustrated in FIG. 18B includes a housing 2111, a display portion 2112, a speaker 2113, an LED lamp 2114, operation key buttons 2115, a connection terminal 2116, a camera 2117, a microphone 2118, and a recording medium reading portion 2119. Have.

  An automobile 2170 illustrated in FIG. 18C includes a vehicle body 2171, wheels 2172, a dashboard 2173, lights 2174, and the like. Note that the automobile 2170 may have a display portion.

  The above various electronic devices can be provided with a memory device, a computer, or the like according to one embodiment of the present invention. Thereby, a highly reliable electronic device can be realized. A display system with high reliability is provided by providing the electronic device with a control circuit including the memory device according to one embodiment of the present invention and providing the display portion according to one embodiment of the present invention in the display portion of the electronic device. Can be realized.

  This embodiment can be combined with any of the other embodiments as appropriate.

10 memory cell array 100 storage device 110 cell array 120 drive circuit unit 130 drive circuit 131 decoder 132 row driver 133 sense amplifier 140 drive circuit 141 decoder 142 column driver 143 sense amplifier 144 precharge circuit 160 control circuit 170 output circuit 300 computer 310 input device 320 Output device 330 Central processing unit 331 Control circuit 332 Operation circuit 333 Storage device 334 Storage device 340 Main storage device 400 Display system 410 Display unit 411 Display unit 411a Display unit 411b Display unit 412 Touch sensor unit 420 Control circuit 421 Interface 422 Frame memory 423 Decoder 424 Sensor controller 425 Controller 426 Clock generation circuit 430 Image processing Unit 431 gamma correction circuit 432 light adjustment circuit 433 color adjustment circuit 434 EL correction circuit 441 storage device 442 timing controller 443 register 450 drive circuit 451 source driver 451a source driver 451b source driver 461 touch sensor controller 470 host 480 optical sensor 481 external light 500 Display device 501 Pixel unit 502 Pixel unit 503 Drive circuit 503a Drive circuit 503b Drive circuit 504 Drive circuit 504a Drive circuit 504b Drive circuit 505a Pixel 505b Pixel 506b Subpixel 506bb Subpixel 506bg Subpixel 506br Subpixel 506bw Subpixel 510 Liquid crystal element 520 Element 520b Light emitting element 520g Light emitting element 520r Light emitting element 520w Light emitting element 530 Conductive layer 530a Conductive layer 530b Conductive layer 40 opening 551 substrate 561 substrate 562 display area 564 circuit 565 wiring 572 FPC
573 IC
612 Liquid crystal 613 Conductive layer 617 Insulating layer 621 Insulating layer 630 Polarizing layer 632 Colored layer 632 Light shielding layer 633a Aligned film 633b Aligned film 634 Colored layer 641 Adhesive layer 642 Adhesive layer 691 Conductive layer 692 EL layer 693a Conductive layer 693b Conductive layer 701 Transistor 704 Connection portion 705 Transistor 706 Transistor 707 Connection portion 711 Insulating layer 712 Insulating layer 713 Insulating layer 714 Insulating layer 715 Insulating layer 716 Insulating layer 717 Insulating layer 720 Insulating layer 721 Insulating layer 722 Insulating layer 723 Insulating layer 724 Insulating layer 731 Semiconductor layer 742 Layer 743 Connection body 752 Connection portion 801 Transistor 811 Insulating layer 812 Insulating layer 813 Insulating layer 814 Insulating layer 815 Insulating layer 817 Insulating layer 818 Insulating layer 819 Insulating layer 820 Insulating layer 821 Metal oxide film 822 Metal oxide film 823 Metal oxide film 824 Metal oxide film 830 Oxide layer 850 Conductive layer 850a Conductive layer 850b Conductive layer 851 Conductive layer 852 Conductive layer 853 Conductive layer 853a Conductive layer 853b Conductive layer 1001 Substrate 1002 Circuit region 1003 Isolation region 1004 Separation line 1005 Chip 1101 Electronic component 1102 Printed circuit board 1103 Board 2000 Mobile information terminal 2001 Case 2002 Case 2003 Display unit 2004 Display unit 2005 Hinge unit 2010 Mobile information terminal 2011 Case 2012 Display unit 2013 Operation button 2014 External connection port 2015 Speaker 2016 Microphone 2017 Camera 2020 Camera 2021 Case 2022 Display unit 2023 Operation button 2024 Shutter button 2026 Lens 2050 Notebook PC
2051 Case 2052 Display unit 2053 Keyboard 2054 Pointing device 2110 Portable game machine 2111 Case 2112 Display unit 2113 Speaker 2114 LED lamp 2115 Operation key button 2116 Connection terminal 2117 Camera 2118 Microphone 2119 Recording medium reading unit 2170 Car 2171 Car body 2172 Wheel 2173 Dashboard 2174 Light

Claims (9)

A first transistor and a second transistor, and a first capacitor and a second capacitor;
One of a source and a drain of the first transistor, one electrode of the first capacitor, and a gate of the second transistor are electrically connected,
One of the source and the drain of the second transistor, the one electrode of the second capacitor, and the gate of the first transistor are electrically connected to each other. In claim 1,
One of the source and the drain of the first transistor, the one electrode of the first capacitor, and the gate of the second transistor are electrically connected at a first node;
One of a source and a drain of the second transistor, one electrode of the second capacitor, and a gate of the first transistor are electrically connected at a second node;
A first potential is held at the first node;
2. A semiconductor device, wherein a second potential is held at the second node. In claim 2,
When holding the first potential, do not hold the second potential,
The semiconductor device is characterized in that when the second potential is held, the first potential is not held. In claim 2 or claim 3,
When holding the first potential, a potential is applied to one of the source or the drain of the first transistor and the gate of the second transistor,
The semiconductor device is characterized in that, when the second potential is held, a potential is applied to one of a source and a drain of the second transistor and a gate of the first transistor. In any one of Claims 2 thru | or 4,
The gate insulator of the first transistor is applied with potentials having opposite polarities when the first potential is held and when the second potential is held,
The semiconductor device according to claim 1, wherein a potential having an opposite polarity is applied to the gate insulator of the second transistor when the first potential is held and when the second potential is held. In any one of Claims 1 thru | or 5,
The semiconductor device, wherein the first transistor and the second transistor can use metal oxide. In any one of Claims 1 thru | or 6,
A first driving circuit; a second driving circuit; and first to fourth wirings;
The other of the source and the drain of the first transistor and the first wiring are electrically connected;
The other of the source and the drain of the second transistor and the second wiring are electrically connected;
The other electrode of the first capacitor and the third wiring are electrically connected;
The other electrode of the second capacitor and the fourth wiring are electrically connected;
The first driving circuit has a function of controlling potentials of the first wiring and the second wiring;
The second driving circuit is a semiconductor device having a function of controlling potentials of the third wiring and the fourth wiring. A control circuit having a frame memory using the semiconductor device according to any one of claims 1 to 7, an image processing unit, and a drive circuit, and a display unit,
The frame memory has a function of storing image data,
The image processing unit has a function of performing image processing on image data input from the frame memory and generating a video signal;
The display circuit having a function of outputting the video signal input from the image processing unit to the display unit. In claim 8,
The display unit includes a first display unit and a second display unit,
The first display unit has a reflective liquid crystal element,
The second display unit is a display system having a light emitting element.