WO2020100417A1

WO2020100417A1 - Display device

Info

Publication number: WO2020100417A1
Application number: PCT/JP2019/036589
Authority: WO
Inventors: 伊東　理; 池田　雅延
Original assignee: 株式会社ジャパンディスプレイ
Priority date: 2018-11-15
Filing date: 2019-09-18
Publication date: 2020-05-22
Also published as: JP2020085939A

Abstract

This display device has: a first substrate (SU1); a second substrate (SU2) opposing the first substrate (SU1); an inorganic light-emitting element (LED) that is provided between the first substrate (SU1) and the second substrate (SU2); a first transistor (DTR) that is electrically connected to the inorganic light-emitting element (LED) via an anode electrode (AD); an insulating layer (LSN2) that covers the inorganic light-emitting element (LED); a liquid crystal layer (LC) that is provided between the first substrate (SU1) and the second substrate (SU2); and a pixel electrode (PE) and a common electrode (CE2) opposing each other with the liquid crystal layer (LC) therebetween, wherein the first transistor (DTR), the anode electrode (AD), the inorganic light-emitting element (LED), the insulating layer (LSN2), the pixel electrode (PE), the liquid crystal layer (LC), the common electrode (CE2), and the second substrate (SU2) are laminated in this order on one surface of the first substrate (SU1).

Description

Display device

The present invention relates to a display device.

As a display device having the characteristics of both a transmissive display device and a reflective display device, for example, there is a transflective liquid crystal display device having a transmissive display region and a reflective display region in one pixel. The transflective liquid crystal display device displays by using transmitted light by backlight light in a dark environment and displays by using reflected light by external light in a bright environment. In the hybrid image display device described in Patent Document 1, instead of the backlight, a light emitting region including a self light emitting element such as an organic light emitting diode (OLED: Organic Light Emitting Diode) is formed.

JP-A-2002-196702

In a semi-transmissive liquid crystal display device, it is necessary to divide one pixel into a transmissive area and a reflective area. Therefore, there is a trade-off relationship between securing the transmissive display area and maintaining the reflective display performance. In Patent Document 1, since the self-luminous element is used, it is possible to suppress deterioration of reflective display performance due to area division. However, in Patent Document 1, the organic light emitting diode may deteriorate due to heating in the manufacturing process of the liquid crystal display device. Further, Patent Document 1 does not describe a configuration for improving the light extraction efficiency.

An object of the present invention is to provide a display device that can achieve both the reflective display performance of displaying with reflected light and the light emitting display performance of emitting light from a light emitting element.

A display device according to one aspect of the present invention includes a first substrate, a second substrate facing the first substrate, an inorganic light emitting element provided between the first substrate and the second substrate, and an anode electrode. A first transistor electrically connected to the inorganic light emitting element via an insulating layer covering the inorganic light emitting element; a liquid crystal layer provided between the first substrate and the second substrate; A pixel electrode and a common electrode that face each other with a liquid crystal layer interposed therebetween, and the first transistor, the anode electrode, the inorganic light emitting element, the insulating layer, the pixel electrode, and The liquid crystal layer, the common electrode, and the second substrate are laminated in this order.

FIG. 1 is a perspective view schematically showing the display device according to the first embodiment. FIG. 2 is a plan view showing a plurality of pixels. FIG. 3 is a circuit diagram showing an equivalent circuit of the reflective display pixel. FIG. 4 is a circuit diagram showing an equivalent circuit of the light emitting display pixel. FIG. 5 is a cross-sectional view taken along line V-V 'in FIG. FIG. 6 is an enlarged sectional view showing the light emitting device of FIG. FIG. 7 is a cross-sectional view showing a display device according to a first modification of the first embodiment. FIG. 8 is a sectional view showing a display device according to a second modification of the first embodiment. FIG. 9 is a sectional view showing the display device according to the second embodiment. FIG. 10 is a sectional view showing the display device according to the third embodiment. FIG. 11 is an explanatory diagram for explaining how light from the light emitting element propagates through the light extraction layer. FIG. 12 is an explanatory diagram for explaining light propagation in the display device according to the third modified example of the third embodiment. FIG. 13 is an explanatory diagram for explaining another example of light propagation in the display device according to the fourth modification of the third embodiment. FIG. 14 is a sectional view showing the display device according to the fourth embodiment. FIG. 15 is a sectional view showing a display device according to a fifth modified example of the fourth embodiment. FIG. 16 is a cross-sectional view showing a display device according to a sixth modified example of the fourth embodiment. FIG. 17 is a sectional view showing a display device according to a seventh modified example of the fourth embodiment. FIG. 18 is a plan view showing a plurality of pixels of the display device according to the fifth embodiment. FIG. 19 is a sectional view taken along line XIX-XIX ′ in FIG.

A mode (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the embodiments below. Further, the constituent elements described below include those that can be easily conceived by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and a person having ordinary skill in the art can easily think of an appropriate modification while keeping the gist of the invention, and is naturally included in the scope of the invention. Further, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part as compared with the actual mode, but this is merely an example, and the interpretation of the present invention will be understood. It is not limited. In the specification and the drawings, the same elements as those described above with reference to the drawings already described are denoted by the same reference numerals, and detailed description thereof may be appropriately omitted.

(First embodiment)
FIG. 1 is a perspective view schematically showing the display device according to the first embodiment. As shown in FIG. 1, the display device DSP includes a first substrate SU1, a second substrate SU2, a pixel Pix, a peripheral circuit GC, and a connection portion CN. FIG. 1 shows the structure on the first substrate SU1 in a transparent manner. An array substrate SUA for driving each pixel Pix is configured by the first substrate SU1, a plurality of transistors, a plurality of capacitors, various wirings and the like. The array substrate SUA is a drive circuit substrate and is also called a backplane or an active matrix substrate. The drive IC (Integrated Circuit) is connected via the connection portion CN.

As shown in FIG. 1, the display device DSP has a display area DA and a peripheral area GA. The display area DA is an area that is arranged so as to overlap the display portion DP and displays an image. The peripheral area GA is an area that does not overlap the display portion DP and is arranged outside the display area DA. The second substrate SU2 overlaps the first substrate SU1 in the display section DP. The first substrate SU1 and the second substrate SU2 sandwich the liquid crystal layer LC (see FIG. 5) in the display portion DP.

The display portion DP has a plurality of pixels Pix, and the plurality of pixels Pix are arranged in the first direction Dx and the second direction Dy in the display area DA. The first direction Dx and the second direction Dy are parallel to the surface of the first substrate SU1. The first direction Dx is orthogonal to the second direction Dy. However, the first direction Dx may intersect with the second direction Dy instead of being orthogonal to each other. The third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy. The third direction Dz corresponds to, for example, the normal direction of the first substrate SU1. Note that, hereinafter, the plan view refers to a positional relationship when viewed from the third direction Dz.

The peripheral circuit GC and the connection portion CN are provided in the peripheral area GA. The connection part CN is provided in a region of the peripheral region GA that does not overlap the second substrate SU2. The peripheral circuit GC includes a plurality of gate lines (for example, a reset control signal line RSL, an output control signal line MSL, a pixel control signal line SSL, an initialization control signal line ISL (see FIG. 4) based on various control signals from the driving IC. )) Is a circuit for driving. The peripheral circuit GC selects a plurality of gate lines sequentially or simultaneously and supplies a gate drive signal to the selected gate lines. As a result, the peripheral circuit GC selects the plurality of pixels Pix connected to the gate line.

The drive IC is a circuit that controls the display of the display device DSP. The drive IC may be mounted as a COF (Chip On Film) on a flexible printed board or a rigid board connected to the connection portion CN of the first board SU1. The drive IC is not limited to this, and may be mounted as a COG (Chip On Glass) in the peripheral area GA of the first substrate SU1.

FIG. 2 is a plan view showing a plurality of pixels. As shown in FIG. 2, one pixel Pix has, for example, a first reflective display pixel RPx1, a first light emitting display pixel EPx1, a second light emitting display pixel EPx2, and a third light emitting display pixel EPx3. The first reflective display pixel RPx1 performs display using reflected light from external light. The first light emitting display pixel EPx1 displays the primary color red as the first color. The second light emitting display pixel EPx2 displays the primary color green as the second color. The third light emitting display pixel EPx3 displays the primary color blue as the third color.

As shown in FIG. 2, in one pixel Pix, the first reflective display pixel RPx1 and the second light emitting display pixel EPx2 are arranged in the first direction Dx. The first light emitting display pixel EPx1 and the third light emitting display pixel EPx3 are arranged in the first direction Dx. The first reflective display pixel RPx1 and the second light emitting display pixel EPx2, and the first light emitting display pixel EPx1 and the third light emitting display pixel EPx3 are arranged in the second direction Dy. The first color, the second color, and the third color are not limited to red, green, and blue, respectively, and any color such as a complementary color can be selected. Hereinafter, when it is not necessary to distinguish the first light emitting display pixel EPx1, the second light emitting display pixel EPx2, and the third light emitting display pixel EPx3 from each other, the light emitting display pixel EPx is referred to.

The first reflective display pixel RPx1 includes a metal electrode ME (reflective electrode) and a pixel electrode PE. The first light emitting display pixel EPx1, the second light emitting display pixel EPx2 and the third light emitting display pixel EPx3 are a red light emitting element RLED, a green light emitting element GLED and a blue light emitting element GLED, respectively, and an anode electrode AD electrically connected to them. Including and The pixel electrode PE is provided for each pixel Pix, and overlaps the first reflective display pixel RPx1 and the plurality of light emitting display pixels EPx in one pixel Pix. That is, the pixel electrode PE is provided over a region overlapping with the metal electrode ME, the plurality of light emitting elements LED, and the plurality of anode electrodes AD respectively connected to the plurality of light emitting elements LED.

FIG. 2 shows the video signal line SL, the anode power supply line IPL, and the pixel control signal line SSL among the various wirings of the pixel circuits PICA and PICR. The video signal line SL and the anode power supply line IPL extend in the second direction Dy. A plurality of the pair of video signal lines SL and the anode power supply lines IPL are arranged in the first direction Dx. The pixel control signal line SSL extends in the first direction Dx and intersects the video signal line SL and the anode power supply line IPL in a plan view. The contact holes CH are arranged in a lattice formed by the pair of video signal lines SL and the anode power supply lines IPL and the pixel control signal lines SSL, and are connected to the pixel electrodes PE and the anode electrodes AD, respectively.

The red light emitting element RLED emits red light. The green light emitting element GLED emits green light. The blue light emitting element BLED emits blue light. In FIG. 2, the red light emitting element RLED and the blue light emitting element BLED are arranged in one of the second directions Dy, and the green light emitting element GLED is arranged in the other of the second direction Dy with respect to the arrangement of the plurality of contact holes CH. .. In other words, the plurality of contact holes CH and the pixel control signal line SSL are provided between the red light emitting element RLED and the blue light emitting element BLED and the green light emitting element GLED. In the following, the red light emitting element RLED, the green light emitting element GLED, and the blue light emitting element BLED are referred to as light emitting element LEDs when there is no need to distinguish them.

The display device DSP performs a reflective display in the first reflective display pixel RPx1, and emits different light for each light emitting element LED in the first light emitting display pixel EPx1, the second light emitting display pixel EPx2, and the third light emitting display pixel EPx3. The image is displayed by that. The light emitting element LED is an inorganic light emitting diode (LED) chip having a size of 3 μm or more and 100 μm or less in a plan view, and is called a micro LED. A display device DSP including a micro LED in each pixel is also called a micro LED display device. The size of the micro LED does not limit the size of the light emitting element LED.

Note that the plurality of light emitting element LEDs may emit different lights of four or more colors. The arrangement of the first reflective display pixel RPx1 and the plurality of light emitting display pixels EPx is not limited to the configuration shown in FIG. For example, the red light emitting element RLED, the green light emitting element GLED, and the blue light emitting element BLED may be adjacent to each other in the first direction Dx.

The light emitting element LED is connected to the anode electrode AD. Further, the anode electrode AD extends from the inside of the light emitting element LED to the outside in a plan view and is provided around the light emitting element LED. The anode electrode AD improves the light extraction efficiency of the light emitting element LED by emitting the light emitted from the light emitting element LED to the third direction Dz, that is, to the display surface side. Further, the anode electrode AD also has a function as a reflective electrode that reflects external light in reflective display.

FIG. 3 is a circuit diagram showing an equivalent circuit of the reflective display pixel. FIG. 3 shows a pixel circuit PICR provided in one first reflective display pixel RPx1, and the pixel circuit PICR is provided in each of the plurality of first reflective display pixels RPx1. As shown in FIG. 3, the pixel circuit PICR includes a drive transistor DTRL, a pixel control signal line SSL, and a video signal line SL. The pixel control signal line SSL and the video signal line SL are provided to intersect with each other. The drive transistor DTRL is provided near the intersection of the pixel control signal line SSL and the video signal line SL.

The pixel control signal line SSL is connected to the gate electrode of the drive transistor DTRL. The video signal line SL is connected to one of the source electrode and the drain electrode of the drive transistor DTRL. The other of the source electrode and the drain electrode of the drive transistor DTRL is connected to the liquid crystal layer LC and the storage capacitor Cs3. The drive transistor DTRL operates based on the scanning signal supplied from the pixel control signal line SSL. When the drive transistor DTRL is turned on, the voltage supplied from the video signal line SL is supplied to the liquid crystal layer LC.

FIG. 4 is a circuit diagram showing an equivalent circuit of a light emitting display pixel. FIG. 4 shows a pixel circuit PICA provided in one light emitting display pixel EPx, and the pixel circuit PICA is provided in each of the plurality of light emitting display pixels EPx. As shown in FIG. 4, the pixel circuit PICA includes a light emitting element LED, five transistors, and two capacitors. Specifically, the pixel circuit PICA includes a drive transistor DRT, an output transistor BCT, an initialization transistor IST, a pixel selection transistor SST, and a reset transistor RST. The drive transistor DRT, the output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST are each composed of an n-type TFT (Thin Film Transistor). Further, the pixel circuit PICA includes a first capacitor Cs1 and a second capacitor Cs2.

The cathode of the light emitting element LED (cathode terminal ELED2 (see FIG. 6)) is connected to the cathode power supply line CDL. The anode of the light emitting element LED (anode terminal ELED1 (see FIG. 6)) is connected to the anode power supply line IPL via the drive transistor DRT and the output transistor BCT. The anode power supply potential PVDD is supplied to the anode power supply line IPL. The cathode power source potential PVSS is supplied to the cathode power source line CDL. The anode power supply potential PVDD is higher than the cathode power supply potential PVSS.

The anode power supply line IPL supplies the anode power supply potential PVDD, which is a drive potential, to the light emitting display pixels EPx. Specifically, the light emitting element LED emits light when a forward current (driving current) is supplied by the potential difference (PVDD-PVSS) between the anode power supply potential PVDD and the cathode power supply potential PVSS. That is, the anode power supply potential PVDD has a potential difference with respect to the cathode power supply potential PVSS that causes the light emitting element LED to emit light. The anode terminal ELED1 of the light emitting element LED is connected to the anode electrode AD, and the second capacitor Cs2 is connected between the anode electrode AD and the anode power supply line IPL as an equivalent circuit.

The source electrode of the drive transistor DRT is connected to the anode terminal ELED1 of the light emitting element LED via the anode electrode AD, and the drain electrode is connected to the source electrode of the output transistor BCT. The gate electrode of the drive transistor DRT is connected to the first capacitor Cs1, the drain electrode of the pixel selection transistor SST, and the drain electrode of the initialization transistor IST.

The gate electrode of the output transistor BCT is connected to the output control signal line MSL. The output control signal BG is supplied to the output control signal line MSL. The drain electrode of the output transistor BCT is connected to the anode power supply line IPL.

The source electrode of the initialization transistor IST is connected to the initialization power supply line INL. The initialization potential Vini is supplied to the initialization power supply line INL. The gate electrode of the initialization transistor IST is connected to the initialization control signal line ISL. An initialization control signal IG is supplied to the initialization control signal line ISL. That is, the initialization power supply line INL is connected to the gate electrode of the drive transistor DRT via the initialization transistor IST.

The source electrode of the pixel selection transistor SST is connected to the video signal line SL. The video signal Vsig is supplied to the video signal line SL. The pixel control signal line SSL is connected to the gate electrode of the pixel selection transistor SST. The pixel control signal SG is supplied to the pixel control signal line SSL.

The source electrode of the reset transistor RST is connected to the reset power supply line RL. The reset power supply potential Vrst is supplied to the reset power supply line RL. The reset control signal line RSL is connected to the gate electrode of the reset transistor RST. A reset control signal RG is supplied to the reset control signal line RSL. The drain electrode of the reset transistor RST is connected to the anode terminal ELED1 of the light emitting element LED and the source electrode of the drive transistor DRT.

A first capacitor Cs1 is provided as an equivalent circuit between the drain electrode of the reset transistor RST and the gate electrode of the drive transistor DRT. The pixel circuit PICA can suppress the fluctuation of the gate voltage due to the parasitic capacitance of the drive transistor DRT and the leakage current by the first capacitance Cs1 and the second capacitance Cs2.

A potential according to the video signal Vsig (or gradation signal) is supplied to the gate electrode of the drive transistor DRT. That is, the drive transistor DRT supplies a current according to the video signal Vsig to the light emitting element LED based on the anode power supply potential PVDD supplied via the output transistor BCT. As described above, since the anode power supply potential PVDD supplied to the anode power supply line IPL drops due to the drive transistor DRT and the output transistor BCT, a potential lower than the anode power supply potential PVDD is supplied to the anode terminal ELED1 of the light emitting element LED. To be done.

The anode power supply potential PVDD is supplied to one electrode of the second capacitor Cs2 through the anode power supply line IPL, and the other electrode of the second capacitor Cs2 is supplied with a potential lower than the anode power supply potential PVDD. That is, one electrode of the second capacitor Cs2 is supplied with a higher potential than the other electrode of the second capacitor Cs2. One electrode of the second capacitor Cs2 is, for example, the anode power supply line IPL, and the other electrode of the second capacitor Cs2 is the anode electrode AD of the drive transistor DRT and the anode connection electrode connected thereto.

In the display device DSP, the peripheral circuit GC (see FIG. 1) sequentially selects a plurality of pixel rows from the top row (for example, the pixel row located at the top in the display area DA in FIG. 1). The drive IC writes the video signal Vsig (video writing potential) in the light emitting display pixel EPx of the selected pixel row to cause the light emitting element LED to emit light. The drive IC supplies the video signal Vsig to the video signal line SL, the reset power supply potential Vrst to the reset power supply line RL, and the initialization potential Vini to the initialization power supply line INL for each horizontal scanning period. The display device DSP repeats these operations for each frame of image.

Note that the configurations of the pixel circuits PICR and PICA shown in FIGS. 3 and 4 described above can be appropriately changed. For example, the number of wirings and the number of transistors in one light emitting display pixel EPx may be different. Further, the pixel circuit PICA may be a current mirror circuit or the like.

Next, a specific configuration example of the first reflective display pixel RPx1 and the light emitting display pixel EPx will be described with reference to FIGS. 5 and 6. FIG. 5 is a cross-sectional view taken along line V-V 'in FIG. FIG. 5 shows a cross-sectional structure of the first reflective display pixel RPx1 and the second light emitting display pixel EPx2. However, the description of the second light emitting display pixel EPx2 can be applied to the first light emitting display pixel EPx1 and the third light emitting display pixel EPx3.

As shown in FIG. 5, the display device DSP includes an array substrate SUA, a counter substrate SUB, and a liquid crystal layer LC. In the array substrate SUA, the light-shielding layer LS, the undercoat layer UC, the semiconductor layer PS, the gate insulating film GZL, the scanning wiring GL, the interlayer insulating film LZL, the anode power supply line IPL, and the pedestal BS are provided on one surface of the first substrate SU1. First flattening layer LL1, first common electrode CE1, first capacitive nitride film LSN1, metal electrode ME and anode electrode AD, connecting layer CL, light emitting element LED and second flattening layer LL2, cathode electrode CD and connecting electrode CNE. , The second capacitor nitride film LSN2, the pixel electrode PE, and the first alignment film AL1 are provided in this order. In addition, one surface of the first substrate SU1 is a surface facing the second substrate SU2.

In the counter substrate SUB, the second common electrode CE2 and the second alignment film AL2 are provided on one surface of the second substrate SU2. In addition, one surface of the second substrate SU2 is a surface facing the first substrate SU1. A circular polarization plate CP is provided on the other surface of the second substrate SU2. The liquid crystal layer LC is provided between the array substrate SUA and the counter substrate SUB.

In this specification, the direction from the first substrate SU1 to the second substrate SU2 in the direction perpendicular to the surface of the first substrate SU1 is referred to as “upper side”. Further, the direction from the second substrate SU2 to the first substrate SU1 will be referred to as “lower side”.

The light emitting element LED is provided on the first substrate SU1. The first substrate SU1 is an insulating substrate, and for example, a glass substrate, a resin substrate, a resin film, or the like is used. For the first substrate SU1, for example, borosilicate glass having a thickness of 100 μm can be used.

The drive transistor DTR is provided on one surface side of the first substrate SU1. FIG. 5 shows the drive transistor DTR among the plurality of transistors of the pixel circuit PICA. The output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST are also provided on the one surface side of the first substrate SU1. The laminated structure of the output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST is similar to that of the drive transistor DTR, and detailed description thereof will be omitted. Further, FIG. 5 also shows the drive transistor DTRL of the pixel circuit PICR. The description of the drive transistor DTR can be applied to the drive transistor DTRL of the first reflective display pixel RPx1.

The light shielding layer LS is a molybdenum tungsten (MoW) alloy film having a layer thickness of about 50 nm. The light shielding layer LS is formed of a material having a light transmittance lower than that of the first substrate SU1, and is provided below the semiconductor layer PS. The undercoat layer UC is a laminated body of a silicon nitride (SiN) layer and a silicon oxide (SiO ₂ ) layer, and has a layer thickness of about 100 nm and 150 nm, respectively. The semiconductor layer PS is, for example, polysilicon, and is obtained by polycrystallizing an amorphous silicon layer by a laser annealing method. The layer thickness of the semiconductor layer PS is, for example, about 50 nm.

The gate insulating film GZL is a silicon oxide layer having a layer thickness of about 100 nm. The scanning line GL is a molybdenum-tungsten alloy film with a layer thickness of about 300 nm. The scanning line GL is a line in which the drain line of the pixel selection transistor SST and the drain line of the initialization transistor IST merge. The gate insulating film GZL is provided between the semiconductor layer PS and the scan line GL in the normal direction of the first substrate SU1. The interlayer insulating film LZL is a laminated body of a silicon oxide layer and a silicon nitride layer, and has a layer thickness of about 350 nm and 375 nm, respectively.

The anode power line IPL and the pedestal BS are provided in the same layer, and each is a three-layer laminated film of titanium (Ti), aluminum (Al), and titanium (Ti). The layer thickness of each layer is about 100 nm, 400 nm, and 200 nm, respectively. A portion of the anode power supply line IPL that overlaps with the semiconductor layer PS functions as the drain electrode DE of the drive transistor DTR. A portion of the pedestal BS that overlaps the semiconductor layer PS functions as the source electrode SE of the drive transistor DTR. The drain electrode DE and the source electrode SE are connected to the semiconductor layer PS via contact holes provided in the interlayer insulating film LZL and the gate insulating film GZL, respectively.

Next, the light emitting display pixel EPx (second light emitting display pixel EPx2) in a layer above the drive transistor DTR will be described. The first flattening layer LL1 and the second flattening layer LL2 are organic insulating films, and have layer thicknesses of about 2 μm and 10 μm, respectively. The first planarization layer LL1 is provided on the interlayer insulating film LZL, covering the anode power supply line IPL and the pedestal BS. A conductive material having a light-transmitting property is used for the first common electrode CE. The first common electrode CE is, for example, indium tin oxide (ITO, Indium Tin Oxide) and has a layer thickness of about 50 nm. The first capacitor nitride film LSN1 is a silicon nitride layer formed at a low temperature and has a layer thickness of about 120 nm. The first capacitive nitride film LSN1 is provided between the first common electrode CE1 and the anode electrode AD in the normal line direction of the first substrate SU1.

The anode electrode AD includes a metal material and is, for example, a laminated body of ITO, silver (Ag), and ITO. The layer thickness of each layer is about 50 nm, 200 nm, and 100 nm, respectively. The anode electrode AD is provided on the first capacitive nitride film LSN1 and is connected to the pedestal BS via a contact hole CH4 provided in the first planarization layer LL1. The connection layer CL is formed of silver paste and is provided on the anode electrode AD between the first substrate SU1 and the light emitting element LED. The light emitting element LED is provided on the connection layer CL and electrically connected to the connection layer CL. That is, the drive transistor DTR is electrically connected to the light emitting element LED via the connection layer CL and the anode electrode AD. The second planarization layer LL2 is provided on the first capacitive nitride film LSN1 so as to cover the anode electrode AD. The second planarization layer LL2 covers at least the side surface of the light emitting element LED and the side surface of the connection layer CL.

The top of the light emitting element LED is exposed at the bottom of the contact hole CH3 provided in the second flattening layer LL2, and is connected to the cathode electrode CD. The cathode electrode CD is ITO and has a layer thickness of about 100 nm. The cathode electrode CD is electrically connected to the cathode terminals ELED2 of the plurality of light emitting elements LED. The second capacitive nitride film LSN2 is provided on the second planarization layer LL2 so as to cover the cathode electrode CD.

Note that the material and layer thickness of each layer are merely examples, and can be changed as appropriate. For example, the semiconductor layer PS is not limited to polysilicon, and may be amorphous silicon, a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, low temperature polysilicon (LTPS: Low Temperature Polycrystalline Silicon), or gallium nitride (GaN). .. Examples of oxide semiconductors include IGZO, zinc oxide (ZnO), and ITZO. IGZO is indium gallium zinc oxide. ITZO is indium tin zinc oxide. Further, in the example shown in FIG. 5, the drive transistor DTR has a so-called top gate structure. However, the drive transistor DTR may have a bottom gate structure in which a gate electrode is provided below the semiconductor layer PS, or may have a dual gate structure in which a gate electrode is provided both above and below the semiconductor layer PS.

Next, the structure of the light emitting element LED will be described. FIG. 6 is an enlarged sectional view showing the light emitting device of FIG. Although FIG. 6 shows the cross-sectional structure of the green light emitting element GLED of the second light emitting display pixel EPx2, the blue light emitting element BLED and the red light emitting element RLED also have the same laminated structure. As shown in FIG. 6, the light emitting element LED has a light emitting element substrate SULED, an n-type cladding layer NC, a light emitting layer EM, a p-type cladding layer PC, an anode terminal ELED1 and a cathode terminal ELED2. An n-type clad layer NC, a light-emitting layer EM, a p-type clad layer PC, and a cathode terminal ELED2 are sequentially stacked on the light emitting element substrate SULED. The anode terminal ELED1 is provided between the light emitting element substrate SULED and the connection layer CL.

In the blue light emitting element BLED that emits blue light, the light emitting layer EM is indium gallium nitride (InGaN), and the composition ratio of indium and gallium is, for example, 0.2: 0.8. The p-type clad layer PC and the n-type clad layer NC are gallium nitride (GaN). The light emitting element substrate SULED is silicon carbide (SiC).

In the green light emitting element GLED that emits green light, the light emitting layer EM is indium gallium nitride (InGaN), and the composition ratio of indium and gallium is 0.45: 0.55, for example. The p-type clad layer PC and the n-type clad layer NC are gallium nitride (GaN). The light emitting element substrate SULED is silicon carbide (SiC).

In the red light emitting element RLED which emits red light, the light emitting layer EM is aluminum gallium indium (AlGaIn), and the composition ratio of aluminum, gallium and indium is, for example, 0.225: 0.275: 0.5. . The p-type clad layer PC and the n-type clad layer NC are aluminum indium phosphide (AlInP). The light emitting element substrate SULED is gallium arsenide (GaAs).

The anode terminal ELED1 and the cathode terminal ELED2 of the red light emitting element RLED, the green light emitting element GLED, and the blue light emitting element BLED are all aluminum.

The maximum emission wavelengths of the red light emitting element RLED, the green light emitting element GLED, and the blue light emitting element BLED are 645 nm, 530 nm, and 450 nm, respectively.

In the manufacturing process of each light emitting element LED, the manufacturing apparatus forms the n-type clad layer NC, the light emitting layer EM, the p-type clad layer PC and the cathode terminal ELED2 on the light emitting element substrate SULED. Then, the manufacturing apparatus thins the light emitting element substrate SULED to form the anode terminal ELED1 on the bottom surface of the light emitting element substrate SULED. Then, the manufacturing apparatus arranged the light emitting element LED cut into a square shape on the connection layer CL.

By using silver paste for the connection layer CL, when the light emitting element LED is arranged, the connection layer CL deforms in response to pressure and is in close contact with the light emitting element LED to conduct electricity. Alternatively, the connection layer CL may be made of the same metal material as the anode terminal ELED1, for example, aluminum. In this case, the anode terminal ELED1 and the connection layer CL are integrated by performing heat treatment after disposing the light emitting element LED on the connection layer CL. As a result, the connection layer CL is in good conduction with the light emitting element LED.

With the above configuration, as shown in FIG. 5, the light Le1 emitted from the upper surface of the light emitting element LED is transmitted to the outside through the second substrate SU2. Further, the light Le2 emitted from the side surface of the light emitting element LED and traveling downward is reflected by the anode electrode AD, and the traveling direction is directed upward. The light Le2 reflected by the anode electrode AD also passes through the second substrate SU2 and is emitted to the outside. The anode electrode AD has a high reflectance and also functions as a reflection layer that reflects the light Le2 of the light emitting element LED. As a result, the display device DSP can improve the light extraction efficiency in the light emitting display by the light emitting display pixel EPx.

Next, the first reflective display pixel RPx1 in the layer above the drive transistor DTRL will be described. The configurations of the first flattening layer LL1, the first common electrode CE, and the first capacitive nitride film LSN1 are similar to those of the light emitting display pixel EPx. The metal electrode ME is provided on the same layer as the anode electrode AD and on the first capacitive nitride film LSN1. The metal electrode ME is made of the same material as the anode electrode AD and is a laminated body of ITO, silver (Ag) and ITO. The layer thickness of each layer is about 50 nm, 200 nm, and 100 nm, respectively. The metal electrode ME is connected to the pedestal BS of the drive transistor DTRL via a contact hole CH2 provided in the first planarization layer LL1.

The first reflective display pixel RPx1 is provided with a contact hole CH1 penetrating the second flattening layer LL2. The connection electrode CNE is provided on the inner wall and bottom of the contact hole CH1 and is connected to the metal electrode ME at the bottom of the contact hole CH1. The connection electrode CNE is provided on the same layer as the cathode electrode CD, that is, on the second flattening layer LL2, and is made of the same material as the cathode electrode CD. The connection electrode CNE is a light-transmitting conductive material such as ITO.

The second capacitive nitride film LSN2 is a silicon nitride layer formed at a low temperature. The second capacitive nitride film LSN2 is provided on the connection electrode CNE and the cathode electrode CD, and an opening is provided at a position overlapping the contact hole CH1. The pixel electrode PE is ITO. The pixel electrode PE is provided on the second capacitor nitride film LSN2 and is connected to the connection electrode CNE inside the contact hole CH1. With such a configuration, the pixel electrode PE is connected to the metal electrode ME via the contact hole CH1. The pixel electrode PE extends to a region overlapping with the light emitting display pixel EPx, and is provided over a region overlapping with the metal electrode ME, the anode electrode AD, and the light emitting element LED.

In the counter substrate SUB, the second substrate SU2 is an insulating substrate, and for example, a glass substrate, a resin substrate, a resin film or the like is used. For the second substrate SU2, for example, borosilicate glass having a thickness of 100 μm can be used. The second common electrode CE2 and the second alignment film AL2 are sequentially stacked on one surface of the second substrate SU2. The second common electrode CE2 is, for example, ITO. The second common electrode CE2 faces the pixel electrode PE with the liquid crystal layer LC interposed therebetween.

The liquid crystal layer LC is arranged between the first alignment film AL1 and the second alignment film AL2. Both the first alignment film AL1 and the second alignment film AL2 are vertical alignment polyimide films. As a result, the alignment state of the liquid crystal layer LC is changed to vertical alignment, and the display device DSP exhibits a dark display when no voltage is applied by combining with the circularly polarizing plate CP. Further, by using a liquid crystal material having a negative dielectric constant anisotropy for the liquid crystal layer LC, a normally black type voltage-reflectance characteristic is obtained. In FIG. 5, the liquid crystal molecules LCM of the liquid crystal layer LC are schematically represented by a cylinder. FIG. 5 shows a state where the liquid crystal molecules LCM are vertically aligned. A vertical electric field is applied to the liquid crystal layer LC by the pixel electrode PE and the second common electrode CE2, which changes the alignment state of the liquid crystal molecules LCM.

Like the pixel electrode PE, the first alignment film AL1, the liquid crystal layer LC, the second alignment film AL2, and the second common electrode CE2 are provided up to a region overlapping with the light emitting display pixel EPx. In other words, on one surface of the first substrate SU1, the first transistor (driving transistor DTR), the anode electrode AD, the inorganic light emitting element (light emitting element LED), the insulating layer (second capacitance nitride film LSN2), the pixel electrode PE, The liquid crystal layer LC, the common electrode (second common electrode CE2), and the second substrate SU2 are stacked in this order.

With the above configuration, as shown in FIG. 5, in the reflective display by the first reflective display pixel RPx1, the light Lr2 incident from the outside is reflected by the metal electrode ME, passes through the second substrate SU2, and is emitted to the outside. Is emitted. Further, in the reflective display, the light Lr1 incident from the outside to the light emitting display pixel EPx side is reflected by the anode electrode AD, passes through the second substrate SU2, and is emitted to the outside. That is, the anode electrode AD has a high reflectance and also serves as a reflection layer of the light Lr1 in the reflective display. That is, in reflective display, in addition to the region where the metal electrode ME is provided, a partial region of the light emitting display pixel EPx where the anode electrode AD is provided also functions as a reflective region. Thereby, the display device DSP can improve the light extraction efficiency in the reflective display by the first reflective display pixel RPx1.

When the display device DSP of this embodiment is observed, for example, indoors under weak illumination, a clear color display can be observed by the emission display of the emission display pixel EPx. Further, when the display device DSP was observed, for example, in direct sunlight at the time of fine weather, the display could be confirmed by the reflective display of the first reflective display pixel RPx1. As described above, the display device DSP can achieve both high-luminance light-emission display and high-reflectance reflective display, and can perform excellent display in an environment from low illuminance to high illuminance.

(First Modification of First Embodiment)
FIG. 7 is a cross-sectional view showing a display device according to a first modification of the first embodiment. In addition, in the following description, the components described in the above-described embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 7, in the first modification, the conductive connection member CC is provided in the second planarization layer LL2 instead of the contact hole CH1. The conductive connecting member CC is a columnar member that is provided so as to penetrate in the thickness direction of the second flattening layer LL2. Specifically, the conductive connection member CC includes a conductive spacer CS and a connection layer CLL provided between the metal electrode ME (reflection electrode) and the pixel electrode PE. The connection layer CLL is provided on the metal electrode ME, and can be formed by using a silver paste like the connection layer CL of the light emitting element LED.

The conductive spacer CS is provided on the connection layer CLL, and the top of the conductive spacer CS is exposed from the second planarization layer LL2. The top of the conductive spacer CS is connected to the pixel electrode PE via the connection electrode CNE. The conductive spacer CS is a columnar body having conductivity, and for example, a sapphire substrate polished to the same thickness as the light emitting element LED and cut into the same size as the light emitting element LED can be used. The conductive spacer CS can be formed by plating the cut sapphire substrate. The conductive spacers CS are arranged on the connection layer CLL in the same process as the light emitting element LED. With such a configuration, the metal electrode ME is electrically connected to the pixel electrode PE via the conductive connection member CC provided on the second flattening layer LL2.

In this embodiment, the contact hole CH1 (see FIG. 5) is not provided. The contact hole CH1 is formed with an inclined wall surface in order to suppress disconnection of the connection electrode CNE and the pixel electrode PE. Therefore, the diameter on the upper side of the contact hole CH1 is equal to or larger than the layer thickness of the second flattening layer LL2.

In the present embodiment, the size of the conductive connecting member CC in plan view can be made approximately the same as the light emitting element LED. Therefore, it is possible to improve the aperture ratio of the first reflective display pixel RPx1 as compared with the configuration having the contact hole CH1 shown in FIG.

(Second Modification of First Embodiment)
FIG. 8 is a sectional view showing a display device according to a second modification of the first embodiment. The light emitting device LED of the first embodiment and the first modification has a vertical structure in which the lower part is connected to the anode electrode AD and the upper part is connected to the cathode electrode CD, but the structure is not limited thereto. As shown in FIG. 8, in the second modification, the anode terminal ELED1 and the cathode terminal ELED2 are both provided on the upper surface side of the light emitting element LED.

The cathode terminal ELED2 is exposed from the second flattening layer LL2 and is electrically connected to the cathode electrode CD. The anode terminal ELED1 is electrically connected to the connection layer CL via the anode connection layer ADCL. A molybdenum-tungsten alloy can be used for the anode connection layer ADCL. Alternatively, as the anode connection layer ADCL, a laminated film of molybdenum-tungsten alloy and aluminum can be used.

As described above, the display device DSP is also applicable to a light emitting element LED having a horizontal structure in which the anode terminal ELED1 and the cathode terminal ELED2 are arranged on the same surface side.

(Second embodiment)
FIG. 9 is a sectional view showing the display device according to the second embodiment. As shown in FIG. 9, a wall-shaped structure WL is provided between the first reflective display pixel RPx1 and each light emitting display pixel EPx. The wall-shaped structure WL is provided on the first capacitive nitride film LSN1.

In the light emitting display pixel EPx, the wall-shaped structure WL faces the side surface of the light emitting element LED. More preferably, the wall-shaped structure WL is provided so as to surround the periphery of the light emitting element LED. The height of the wall-shaped structure WL is about the same as the height of the light emitting element LED or higher than the height of the light emitting element LED. The second planarization layer LL2 covers the upper surface of the wall-shaped structure WL, and as the material of the wall-shaped structure WL, for example, a positive photoresist composed of novolac resin and naphthoquinone of a photosensitive material, or a negative composed of acrylic resin. A mold resist or the like can be used. Alternatively, the side surface of the negative resist may be covered with a positive photoresist to form the negative resist.

The anode electrode AD, the connection layer CL, the light emitting element LED, and the second flattening layer LL2 are provided in the recess formed by the wall-shaped structure WL and the first capacitive nitride film LSN1. The anode electrode AD has a recessed structure along the wall-shaped structure WL and the first capacitive nitride film LSN1. The light emitting element LED is arranged inside the concave structure. Specifically, the anode electrode AD includes an anode electrode bottom portion ADa and an anode electrode inclined portion ADb. The anode electrode bottom portion ADa is provided on the first capacitive nitride film LSN1, and is provided over a region overlapping the light emitting element LED and a region not overlapping the light emitting element LED. The light emitting element LED is connected to the anode electrode bottom portion ADa. The anode electrode inclined portion ADb is connected to the end of the anode electrode bottom portion ADa and is provided so as to be inclined along the inner wall surface of the wall-shaped structure WL. The anode electrode inclined portion ADb faces the side surface of the light emitting element LED with the second flattening layer LL2 interposed therebetween.

A plurality of convex structures PT are provided on the first capacitive nitride film LSN1. The plurality of convex structures PT can be formed by patterning an organic resist on the first capacitive nitride film LSN1. After that, the organic resist is melted and solidified by performing heat treatment, and the plurality of convex structures PT have a semicircular cross-sectional structure having a curved surface. The height of the convex structure PT is, for example, about 0.5 μm, and the diameter is about 3 μm. A plurality of convex structures PT are formed in the light emitting display pixel EPx.

The anode electrode bottom portion ADa is provided on the first capacitive nitride film LSN1 and the plurality of convex structures PT. On the anode electrode bottom portion ADa, a plurality of convex portions are formed following the shape of the convex structure PT.

With such a configuration, in the light emission display of the light emitting display pixel EPx, the light Le3 emitted from the side surface of the light emitting element LED travels toward the anode electrode inclined portion ADb, is reflected by the anode electrode inclined portion ADb, and is second. The light is emitted to the substrate SU2 side. The light Le2 emitted from the side surface of the light emitting element LED to the first substrate SU1 side is reflected by the convex portion of the anode electrode bottom portion ADa and is emitted to the second substrate SU2 side. The light Le2 is emitted at an angle closer to the normal direction of the first substrate SU1 as compared with the case where the light Le2 is reflected at a place where no convex portion is provided. Since the incident angle of the light Le2 is locally different in the convex portion of the anode electrode bottom portion ADa, the light Le2 reflected by the convex portion is scattered light having different incident angles and outgoing angles with respect to the plane parallel to the first substrate SU1. Becomes

In the reflective display pixel RPx, the wall-shaped structure WL faces the contact hole CH1. In other words, the wall-shaped structure WL is provided so as to surround the periphery of the contact hole CH1. The height of the wall-shaped structure WL is lower than the depth of the contact hole CH1.

The metal electrode ME, the connection electrode CNE, and the pixel electrode PE are provided in the recess formed by the wall-shaped structure WL and the first capacitor nitride film LSN1. The metal electrode ME has a recessed structure along the wall-shaped structure WL and the first capacitive nitride film LSN1. Specifically, the metal electrode ME includes a metal electrode bottom portion MEa and a metal electrode inclined portion MEb. The metal electrode bottom portion MEa is provided on the first capacitive nitride film LSN1 and is provided over a region overlapping the bottom portion of the contact hole CH1 and a region not overlapping the bottom portion of the contact hole CH1. The metal electrode inclined portion MEb is connected to the end of the metal electrode bottom portion MEa and is provided so as to be inclined along the inner wall surface of the wall-shaped structure WL.

Also in the reflective display pixel RPx, a plurality of convex structures PT are provided on the first capacitive nitride film LSN1. The metal electrode bottom portion MEa is provided on the plurality of convex structures PT. On the metal electrode bottom portion MEa, a plurality of convex portions are formed following the shape of the convex structure PT.

In the reflective display of the reflective display pixel RPx, the light Lr2 incident from the outside is reflected by the metal electrode bottom portion MEa and is emitted to the second substrate SU2 side. Since the metal electrode bottom portion MEa is also provided with the convex portion, the light Lr2 becomes scattered light like the light Le2 described above. The light Lr1 incident from the outside on the light emitting display pixel EPx side is reflected by the anode electrode AD and is emitted to the second substrate SU2 side as scattered light.

In the present embodiment, by providing the wall-shaped structure WL and the convex structure PT, the anode electrode inclined portion ADb and the metal electrode inclined portion MEb function as an inclined reflector, and the anode electrode bottom portion ADa and the metal electrode bottom portion MEa are formed. Functions as a diffuse reflector. In the present embodiment, in the reflective display, even when the light Lr1 and Lr2 from the outside enter from a specific narrow angle range, the reflected light on the anode electrode bottom part ADa and the metal electrode bottom part MEa has a wide angle range. It is scattered and emitted. For this reason, it is possible to suppress a change in brightness associated with a change in the angle of the display device DSP, and it is possible to suppress a large difference in brightness observed between the right eye and the left eye, for example. Further, since the display surface of the display device DSP is observed with a texture closer to that of paper than a mirror surface, a reflective display that is easier to observe can be obtained.

As described above, in the present embodiment, the light extraction efficiency can be improved in the light emitting display of the light emitting display pixel EPx, and the reflection characteristic can be improved in the reflective display of the reflective display pixel RPx.

Note that the configurations of the first modified example and the second modified example described above can also be applied to this embodiment. That is, in FIG. 9, a conductive connecting member CC may be provided instead of the contact hole CH1, or a light emitting element LED having a horizontal structure may be provided.

(Third Embodiment)
FIG. 10 is a sectional view showing the display device according to the third embodiment. As shown in FIG. 10, in the present embodiment, the light emitting display pixel EPx further includes a light extraction layer LPL. Although FIG. 10 shows the second light emitting display pixel EPx2, the light extraction layer LPL may be provided in the first light emitting display pixel EPx1 and the third light emitting display pixel EPx3.

The light extraction layer LPL is a translucent inorganic insulating layer and is provided so as to cover at least a part of the light emitting element LED and the anode electrode AD. Specifically, the light extraction layer LPL is, for example, a titanium oxide layer having a layer thickness of about 300 nm. The light extraction layer LPL can be formed by a CVD method after disposing the light emitting element LED on the connection layer CL.

The light extraction layer LPL surrounds the side surface of the light emitting element LED, and is also provided around the light emitting element LED. Specifically, the light extraction layer LPL includes a side part LPLa, an inclined part LPLb, an extending part LPLc, and a top part LPLd. The side portion LPLa is provided so as to surround the side surface of the light emitting element LED. The inclined portion LPLb is connected to the lower end of the side portion LPLa and is provided between the side portion LPLa and the extending portion LPLc. The inclined portion LPLb is provided along the side surface of the connection layer CL and is inclined with respect to the side portion LPLa.

The extension part LPLc is provided on the anode electrode bottom part ADa and is connected to the lower end of the inclined part LPLb. That is, the extending portion LPLc is provided on the lower end side of the side portion LPLa, and extends in the direction away from the side surface of the light emitting element LED, that is, away from the side portion LPLa in the plan view. In the normal direction of the first substrate SU1, the anode electrode AD is provided between the first capacitive nitride film LSN1 and the extension LPLc.

The top part LPLd is connected to the upper end of the side part LPLa and is provided on the upper surface of the light emitting element LED. In other words, the top part LPLd is provided between the upper surface of the light emitting element LED and the cathode electrode CD.

The second planarization layer LL2 is provided so as to cover the side surface, the side portion LPLa, the inclined portion LPLb, and the extension portion LPLc of the light emitting element LED. The cathode electrode CD is provided on the second planarization layer LL2 and the top part LPLd, and is electrically connected to the cathode terminal ELED2 of the light emitting element LED.

FIG. 11 is an explanatory diagram for explaining how light from the light emitting element propagates through the light extraction layer. Ease of incidence of light La from the light emitting element LED to a layer adjacent thereto is represented by a total reflection angle θr. The total reflection angle θr is the incident angle at which the light La generated by the light emitting element LED is totally reflected at the interface with the adjacent layer. As shown in FIG. 11, the incident angle θa of the light La on the side portion LPLa is an angle formed by the normal direction of the side surface of the light emitting element LED and the traveling direction of the light La. When the incident angle θa is equal to or less than the total reflection angle θr, since a transmission component exists, the larger the total reflection angle θr, the easier the light La is to enter the adjacent layer.

Here, when the refractive index of the light emitting element LED is n _LED and the refractive index of the adjacent layer is n _AJ , the total reflection angle θr is represented by the following formula (1).
θr = arcsin (n _AJ / n _LED ) (1)

When the relationship of n _AJ > n _LED is satisfied, the light La can be incident on the adjacent layers at all incident angles θa. In the case of n _AJ <n _LED, the larger n _AJ is, the larger the total reflection angle θr is, and thus the component of the light La that is incident on the adjacent layer is larger.

In the present embodiment, the side portion LPLa of the light extraction layer LPL is provided between the side surface of the light emitting element LED and the second flattening layer LL2. Refractive index _{n LED} light emitting element LED is, for _example, an n LED = 2.4, the refractive index of the second planarization layer LL2 is, for example, 1.5. The refractive index of the light extraction layer LPL is about n _AJ = 2.4, which is higher than the refractive index of the second flattening layer LL2. That is, the difference between the refractive index of the light extraction layer LPL and the refractive index n _LED of the light emitting element LED is smaller than the difference between the refractive index of the second flattening layer LL2 and the refractive index of the light emitting element LED. Therefore, in the present embodiment, the total reflection angle θr at the interface between the light emitting element LED and the side portion LPLa becomes larger than that in the case where the second planarizing layer LL2 is provided in contact with the side surface of the light emitting element LED. Light La from the light emitting element LED is likely to enter the side portion LPLa. The refractive index n _LED of the light emitting element LED is the same as the refractive index n _AJ of the light extraction layer LPL, but may be different.

Since the inclined portion LPLb is provided between the side portion LPLa and the extending portion LPLc, the side portion LPLa and the inclined portion LPLb are formed as compared with the case where the side portion LPLa and the extending portion LPLc are directly connected. The angle and the angle formed between the extending portion LPLc and the inclined portion LPLb become gentle. As a result, the light Lb incident on the side portion LPLa is satisfactorily guided to the extension portion LPLc via the inclined portion LPLb.

The second flattening layer LL2 is provided on the extension part LPLc, and the anode electrode AD is provided on the bottom part. As a result, the light Lb propagates in the direction away from the light emitting element LED while being reflected inside the extension LPLc. In the process, when the incident angle of the light Lb becomes smaller than the total reflection angle of the interface between the extending portion LPLc and the second flattening layer LL2, the light Lc is emitted upward. Thus, in the present embodiment, by providing the light extraction layer LPL, the light La from the light emitting element LED can be emitted from the entire surface of the light extraction layer LPL. As a result, the light emitting display pixel EPx can improve the light extraction efficiency in the light emitting display.

Further, since the light extraction layer LPL can propagate the light Lb, the light extraction layer LPL is provided for each of the first light emitting display pixel EPx1, the second light emitting display pixel EPx2, and the third light emitting display pixel EPx3 (see FIG. 2). By partitioning, the color mixture of the light emitting element LED can be suppressed.

The light extraction layer LPL is not limited to the configuration shown in FIG. 10, and may be changed as appropriate. For example, the light extraction layer LPL may omit the top LPLd. In this case, the upper surface of the light emitting element LED is in direct contact with the cathode electrode CD. In other words, the cathode terminal ELED2 (see FIG. 6) of the light emitting element LED is in direct contact with the cathode electrode CD. As a result, the connection resistance between the cathode terminal ELED2 and the cathode electrode CD can be suppressed, so that the drive voltage (anode power supply potential PVDD) can be reduced.

Also, the light extraction layer LPL is provided in the entire region overlapping with the anode electrode AD. However, the present invention is not limited to this, and the light extraction layer LPL may have a larger area than the anode electrode AD or a smaller area than the anode electrode AD in plan view.

The titanium oxide layer is exemplified as the material of the light extraction layer LPL, but the material is not limited to this. As a material of the light extraction layer LPL, a material having a high refractive index and a light-transmitting property is preferable, and for example, tantalum oxide, niobium oxide, barium titanium oxide, or the like can be applied. Further, the thickness of the light extraction layer LPL is merely an example and can be changed as appropriate. Further, an ultraviolet absorbing layer may be provided between the second substrate SU2 and the circularly polarizing plate CP. When titanium oxide is used as the material of the light extraction layer LPL, titanium oxide absorbs ultraviolet rays, and thus the second flattening layer LL2 may be photodecomposed. By providing the ultraviolet absorbing layer, the incidence of ultraviolet rays on the second flattening layer LL2 is reduced, and the photolysis reaction can be suppressed.

(Third Modification of Third Embodiment)
FIG. 12 is an explanatory diagram for explaining light propagation in the display device according to the third modified example of the third embodiment. As shown in FIG. 12, in the third modification, a plurality of minute recesses COC are provided on the surface of the light extraction layer LPL. The concave portion COC is provided in the side portion LPLa and the extending portion LPLc. However, the concave portion COC may also be provided in the inclined portion LPLb. The recess COC can be formed by shaving the surface of the light extraction layer LPL, and can be formed by, for example, a method of spraying an abrasive such as sandblast on the light extraction layer LPL.

The light Lb propagating inside the extended portion LPLc is reflected by a region of the interface between the extended portion LPLc and the second flattening layer LL2 where the concave portion COC is not provided. In the portion where the concave portion COC is provided, the interface is locally inclined, and the incident angle of the light Lb is different from that in the region where the concave portion COC is not provided. Therefore, the light Lc is efficiently emitted to the second flattening layer LL2 side.

(Fourth Modification of Third Embodiment)
FIG. 13 is an explanatory diagram for explaining another example of light propagation in the display device according to the fourth modification of the third embodiment. As shown in FIG. 13, in the fourth modification, a plurality of minute convex portions COV are provided on the surface of the light extraction layer LPL. The convex portion COV is provided on the side portion LPLa and the extension portion LPLc. However, the convex portion COV may also be provided in the inclined portion LPLb. The convex portion COV can be formed by adhering the same material as the light extraction layer LPL, for example, fine particles of titanium oxide. More specifically, titanium oxide fine particles are mixed in the organic material forming the second flattening layer LL2 to form the second flattening layer LL2, and some of the fine particles in the second flattening layer LL2 are The convex portion COV is formed by adhering to the surface of the light extraction layer LPL.

Also in the fourth modified example, the interface is locally tilted in the portion where the convex portion COV is provided, and the incident angle of the light Lb is different from the region where the convex portion COV is not provided. Therefore, the light Lc is efficiently emitted to the second flattening layer LL2 side. Note that the configuration is not limited to the configurations shown in FIGS. 12 and 13, and a plurality of minute uneven structures may be formed on the surface of the light extraction layer LPL. Specifically, the concavo-convex structure may be formed by roughening the surface of the light extraction layer LPL by a reverse sputtering method or the like.

The configurations of the second embodiment, the first modified example, and the second modified example described above can also be applied to the third embodiment, the third modified example, and the fourth modified example. For example, in the third embodiment, the third modified example, and the fourth modified example, the wall-shaped structure WL may be provided, and the anode electrode AD and the light extraction layer LPL may be provided along the wall surface of the wall-shaped structure WL. Alternatively, a plurality of convex structures may be provided on the first capacitive nitride film LSN1 to form convex parts on the anode electrode AD and the light extraction layer LPL that follow the convex structures.

(Fourth Embodiment)
FIG. 14 is a sectional view showing the display device according to the fourth embodiment. As shown in FIG. 14, in the fourth embodiment, the anode electrode AD has a concave structure as in the second embodiment described above. In the fourth embodiment, instead of the second flattening layer LL2, the phosphor layer FL is provided inside the concave structure of the anode electrode AD. The phosphor layer FL is provided on the anode electrode AD and covers at least the side surface of the light emitting element LED.

Further, a color filter CF is provided on the surface of the second substrate SU2 facing the first substrate SU1. An overcoat layer OC is provided to cover the color filter CF, and the second common electrode CE2 and the second alignment film AL2 are provided on the overcoat layer OC. The color filter CF faces the phosphor layer FL via the insulating layer (third planarization layer LL3), the pixel electrode PE, the liquid crystal layer LC, and the common electrode (second common electrode CE2).

Different types of phosphor layers FL and color filters CF are used for each of the first light emitting display pixel EPx1, the second light emitting display pixel EPx2, and the third light emitting display pixel EPx3. A red phosphor layer and a red color filter are provided in the first light emitting display pixel EPx1. A green phosphor layer and a green color filter are provided in the second light emitting display pixel EPx2. A blue phosphor layer and a blue color filter are provided in the third light emitting display pixel EPx3.

As the light emitting element LED, a blue light emitting element BLED is used for each of the first light emitting display pixel EPx1, the second light emitting display pixel EPx2, and the third light emitting display pixel EPx3. Since the same light emitting element LED is used in each light emitting display pixel EPx, the step of arranging the light emitting element LEDs can be simplified in the manufacturing process of the display device DSP. The luminous efficiency of the light emitting element LED varies depending on the color of light emitted. In the present embodiment, the blue light emitting element BLED having relatively excellent light emitting efficiency is used for each light emitting display pixel EPx.

The red phosphor layer, the green phosphor layer, and the blue phosphor layer are formed by patterning a negative resist in which red-emitting, green-emitting, and blue-emitting quantum dots are mixed. The quantum dot is composed of a cadmium selenium (CdSe) core structure and a zinc sulfide (ZnS) shell structure surrounding the core structure. The particle diameters of the red, green, and blue light emitting quantum dots are adjusted so that the fluorescence maximum wavelengths are shown at wavelengths of 630 nm, 530 nm, and 460 nm, respectively. The absorption spectrum of the quantum dots is continuous and exhibits sufficient absorption even at the maximum emission wavelength of the blue light emitting device BLED. Further, the surface of the shell structure has an organic molecular chain for improving the compatibility with the negative resist.

However, the present invention is not limited to this, and non-cadmium-based quantum dots can also be applied. Examples of non-cadmium-based quantum dots include those having a core structure of indium phosphide (InP) and a shell structure of zinc sulfide (ZnS).

The color filter CF is formed by patterning a negative resist in which a red pigment, a green pigment and a blue pigment are mixed. The layer thickness of the color filter CF is, for example, about 2 μm. The color filter CF can absorb the light of the blue wavelength component emitted from the blue light emitting element BLED and improve the color purity of the light emitted to the second substrate SU2 side. Further, the color filter CF can suppress the phosphor layer FL from emitting light by external light.

The color filter CF may be provided on the first substrate SU1 side. The color filter CF may be stacked on the phosphor layer FL, for example.

As shown in FIG. 14, the lights Le2 and Le3 emitted from the blue light emitting element BLED are respectively incident on and reflected by the anode electrode AD, and the traveling direction is directed to the upper side. On the anode electrode bottom portion ADa, the convex portion having the convex structure PT is formed as in the second embodiment. Therefore, the light Le2 is scattered by the bottom portion ADa of the anode electrode. The lights Le2 and Le3 are wavelength-converted by passing through the phosphor layer FL through such a path and undergoing an absorption and emission process by the phosphor layer FL.

The phosphor layer FL emits light isotropically. In the present embodiment, the phosphor layer FL is surrounded by the anode electrode bottom portion ADa, the anode electrode inclined portion ADb, and the blue light emitting element BLED. Therefore, the traveling direction of the fluorescence emitted isotropically is reflected by the anode electrode AD and the blue light emitting element BLED, and is converted to a direction close to the normal direction of the first substrate SU1. Then, the fluorescence is emitted to the second substrate SU2 side. As a result, the display device DSP can improve the light extraction efficiency.

The lights Lf2 and Lf3 emitted from the phosphor layer FL pass through the color filter CF and are emitted to the outside on the second substrate SU2 side. Further, the color filter CF absorbs the components of the lights Le2 and Le3 emitted from the blue light emitting element BLED that have not been wavelength-converted. This improves the color purity of the light that has passed through the color filter CF. Further, the light Le1 emitted from the upper surface of the blue light emitting element BLED does not pass through the phosphor layer FL and is incident on and absorbed by the color filter CF. Further, the color filter CF absorbs a component that excites the phosphor layer FL in the light incident from the outside. This can prevent the phosphor layer FL from emitting light that is not related to the image signal.

Specifically, in the first light emitting display pixel EPx1, the phosphor layer FL is a red phosphor layer, and blue light is incident from the blue light emitting element BLED to emit red light. The color filter CF is a red color filter and absorbs light components other than red. In the second light emitting display pixel EPx2, the phosphor layer FL is a green phosphor layer, and blue light is incident from the blue light emitting element BLED to emit green light. The color filter CF is a green color filter and absorbs light components other than green. In the third light emitting display pixel EPx3, the phosphor layer FL is a blue phosphor layer, and blue light is incident from the blue light emitting element BLED and emits blue light. The color filter CF is a blue color filter and absorbs light components other than blue. In the third light emitting display pixel EPx3, a light scattering layer may be provided instead of the phosphor layer FL.

(Fifth Modification of Fourth Embodiment)
FIG. 15 is a sectional view showing a display device according to a fifth modified example of the fourth embodiment. As shown in FIG. 15, in the fifth modified example, the first phosphor layer FL1 and the second phosphor layer FL2 are provided inside the concave structure of the anode electrode AD. The first phosphor layer FL1 covers the side surface of the blue light emitting element BLED and is provided in a region surrounded by the anode electrode bottom portion ADa, the anode electrode inclined portion ADb, and the blue light emitting element BLED. The second phosphor layer FL2 is provided so as to cover the upper surface of the blue light emitting element BLED and the first phosphor layer FL1. The second phosphor layer FL2 covers the cathode electrode CD and is provided in a region surrounded by the first phosphor layer FL1, the anode electrode inclined portion ADb, and the second capacitor nitride film LSN2.

The light Le1 emitted from the upper surface of the blue light emitting element BLED enters the second phosphor layer FL2 and undergoes wavelength conversion. The light Lf1 emitted from the second phosphor layer FL2 passes through the color filter CF and is emitted to the outside on the second substrate SU2 side. Thereby, the display device DSP can also extract the light Le1 to the outside, and can improve the light extraction efficiency. Further, the lights Le2 and Le3 emitted from the blue light emitting element BLED pass through the first phosphor layer FL1 and the second phosphor layer FL2. The total thickness of the first phosphor layer FL1 and the second phosphor layer FL2 becomes thicker than in the case where one phosphor layer FL is provided. Thereby, the wavelength conversion efficiency of the lights Le2 and Le3 can also be improved. The display device DSP can improve the brightness of the display mainly in low illuminance.

(Sixth Modification of Fourth Embodiment)
FIG. 16 is a cross-sectional view showing a display device according to a sixth modified example of the fourth embodiment. As shown in FIG. 16, in the sixth modified example, the reflective layer RF is provided in the light emitting display pixel EPx. The reflective layer RF is provided between the light emitting element LED and the liquid crystal layer LC and covers the upper surface of the light emitting element LED. Specifically, the reflection layer RF is provided between the phosphor layer FL and the third flattening layer LL3, and the pixel electrode PE. For the reflective layer RF, a metal material such as aluminum or silver is used.

The area of the reflection layer RF in plan view is smaller than the areas of the phosphor layer FL and the anode electrode AD in plan view. An end of the reflection layer RF is separated from the anode electrode AD, and an opening is provided between the end of the reflection layer RF and the upper end of the anode electrode AD. The light Le1 emitted upward from the light emitting element LED is reflected by the reflective layer RF and enters the phosphor layer FL. Then, the lights Lf1, Lf2, and Lf3 emitted from the phosphor layer FL are emitted to the second substrate SU2 side through the openings.

In the sixth modified example, the path of the light Le1 emitted toward the upper side through the inside of the phosphor layer FL becomes longer than in the fourth embodiment and the fifth modified example described above. Therefore, the phosphor layer FL can effectively absorb the light of the light emitting element LED.

In addition, in the sixth modification, the color filter CF is provided so as to cover the opening between the end of the reflective layer RF and the upper end of the anode electrode AD in plan view. In other words, the color filter CF has an opening provided in a region overlapping the reflection layer RF in plan view. Therefore, in the reflective display by the first reflective display pixel RPx1, a part of the light Lr3 incident from the outside is reflected by the reflective layer RF through the opening of the color filter CF and is emitted to the outside on the second substrate SU2 side. To be done. That is, the reflective layer RF functions as a reflective plate in reflective display. The light Lr3 is reflected by the reflection layer RF without passing through the color filter CF and the phosphor layer FL. Therefore, in the sixth modification, the reflectance of light in the reflective display is improved as compared with the case where the color filter CF is passed or the case where the reflective layer RF is not provided.

(Seventh Modification of Fourth Embodiment)
FIG. 17 is a sectional view showing a display device according to a seventh modified example of the fourth embodiment. As shown in FIG. 17, in the seventh modified example, the convex structure PR is provided on the third flattening layer LL3. The plurality of convex structures PR can be formed by patterning an organic resist on the third planarization layer LL3, similarly to the convex structures PT of the second embodiment (see FIG. 9).

The reflection layer RF, the pixel electrode PE, and the first alignment film AL1 are provided on the third planarization layer LL3 and the plurality of convex structures PR. Thereby, a plurality of convex portions are formed on the surface of the reflective layer RF, following the shape of the convex structure PR.

In the light emitting display, the light Le1 emitted from the light emitting element LED is diffusely reflected by the convex portion formed on the reflection layer RF. As a result, of the light reflected by the reflective layer RF, the component of light returning to the light emitting element LED is suppressed, and the component of light incident on the phosphor layer FL increases. Therefore, in the seventh modified example, the luminous efficiency of the phosphor layer FL in the light emitting display can be improved.

In the reflective display, the light Lr3 incident from the outside passes through the opening of the color filter CF and is diffusely reflected by the reflective layer RF. Thereby, even when the light Lr3 from the outside enters from a specific narrow angle range, the reflected light is scattered and emitted in a wide angle range. Therefore, it is possible to suppress a change in brightness associated with a change in the angle of the display device DSP, and it is possible to obtain a reflective display that is easier to observe.

Note that the configurations of the second embodiment, the third embodiment, and the first modified example to the fourth modified example can be applied to the fourth embodiment and the fifth modified example to the seventh modified example. Further, the configuration of the fifth modified example and the configuration of the sixth modified example or the seventh modified example may be combined. In the fourth embodiment and the fifth to seventh modifications, the convex structure PT may not be provided below the anode electrode AD.

(Fifth Embodiment)
FIG. 18 is a plan view showing a plurality of pixels of the display device according to the fifth embodiment. 19 is a sectional view taken along line XIX-XIX ′ in FIG. As shown in FIG. 18, in the fifth embodiment, one pixel Pix includes, in addition to the first reflective display pixel RPx1, the first light emitting display pixel EPx1, the second light emitting display pixel EPx2, and the third light emitting display pixel EPx3, The second reflective display pixel RPx2 and the third reflective display pixel RPx3 are included. That is, the pixel Pix has a plurality of light emitting display pixels EPx and a plurality of reflective display pixels RPx, and includes, for example, six pixels. However, the pixel Pix may have seven or more pixels.

The first reflective display pixel RPx1, the second reflective display pixel RPx2, and the third reflective display pixel RPx3 are arranged in the first direction Dx. The first light emitting display pixel EPx1, the second light emitting display pixel EPx2, and the third light emitting display pixel EPx3 are also arranged in the first direction Dx. In addition, the first reflective display pixel RPx1 and the first light emitting display pixel EPx1 are arranged in the second direction Dy. The second reflective display pixel RPx2 and the second light emitting display pixel EPx2 are arranged in the second direction Dy. The third reflective display pixel RPx3 and the third light emitting display pixel EPx3 are arranged in the second direction Dy.

A metal electrode ME and a pixel electrode PE are provided on the first reflective display pixel RPx1, the second reflective display pixel RPx2, and the third reflective display pixel RPx3, respectively. A red color filter RCF, a green color filter GCF, and a blue color filter BCF are provided in the first reflective display pixel RPx1, the second reflective display pixel RPx2, and the third reflective display pixel RPx3, respectively. As a result, the first reflective display pixel RPx1, the second reflective display pixel RPx2, and the third reflective display pixel RPx3 display red, green, and blue light, respectively. As a result, the display device DSP of the fifth embodiment can realize color display in reflective display.

A red light emitting element RLED, a green light emitting element GLED, and a blue light emitting element BLED are provided in the first light emitting display pixel EPx1, the second light emitting display pixel EPx2, and the third light emitting display pixel EPx3, respectively. An anode electrode AD is connected to each of the red light emitting element RLED, the green light emitting element GLED, and the blue light emitting element BLED.

The pixel electrode PE of the first reflective display pixel RPx1 is continuously provided so as to overlap with the metal electrode ME of the first reflective display pixel RPx1, the red light emitting element RLED of the first light emitting display pixel EPx1, and the anode electrode AD connected thereto. Be done. Similarly, the pixel electrode PE of the second reflective display pixel RPx2 continuously overlaps with the metal electrode ME of the second reflective display pixel RPx2, the green light emitting element GLED of the second light emitting display pixel EPx2, and the anode electrode AD connected thereto. Will be provided. The pixel electrode PE of the third reflective display pixel RPx3 is continuously provided so as to overlap with the metal electrode ME of the third reflective display pixel RPx3, the blue light emitting element BLED of the third light emitting display pixel EPx3, and the anode electrode AD connected thereto. Be done.

Accordingly, the anode electrodes AD of the first light emitting display pixel EPx1, the second light emitting display pixel EPx2, and the third light emitting display pixel EPx3 are respectively the first reflective display pixel RPx1, the second reflective display pixel RPx2, and the third reflective display pixel. It functions as a reflection electrode of RPx3. This makes it possible to suppress a decrease in reflectance even when color display is performed in reflective display.

FIG. 19 shows a cross-sectional structure of the first reflective display pixel RPx1 and the first light emitting display pixel EPx1. However, the second reflective display pixel RPx2 and the third reflective display pixel RPx3 have the same configuration as the first reflective display pixel RPx1. The second light emitting display pixel EPx2 and the third light emitting display pixel EPx3 have the same configuration as the first light emitting display pixel EPx1.

As shown in FIG. 19, the first reflective display pixel RPx1 and the first light emitting display pixel EPx1 have the same configuration as the second embodiment shown in FIG. However, the present invention is not limited to this, and the configurations of the first to fifth embodiments and each modification can be applied.

In the present embodiment, the color filter CF (red color filter RCF) is provided on the surface of the second substrate SU2 that faces the first substrate SU1. An overcoat layer OC, a second common electrode CE2, and a second alignment film AL2 are sequentially stacked on the color filter CF. The color filter CF only covers a part of the first reflective display pixel RPx1 and is not provided on the entire surface of the first reflective display pixel RPx1. That is, the area of the color filter CF is smaller than the area of the metal electrode ME overlapping the color filter CF.

As a result, the light Lr2 passes through the color filter CF and enters the metal electrode ME. Then, some components of the light Lr2 reflected by the metal electrode ME are emitted to the outside on the second substrate SU2 side without passing through the color filter CF. Thereby, the display device DSP can secure the reflectance in the reflective display of the reflective display pixel RPx. At this time, the color display of the portion where the color filter CF is provided and the white display of the high reflectance of the portion where the color filter CF is not provided are additively mixed to realize a color display of the high reflectance.

As described above, in the fifth embodiment, by including the first reflective display pixel RPx1, the second reflective display pixel RPx2, and the third reflective display pixel RPx3, reflective display can also be color display. Thereby, the display device DSP can mainly improve the color purity at high illuminance.

The arrangement of the plurality of reflective display pixels RPx and the plurality of light emitting display pixels EPx shown in FIG. 18 is merely an example, and can be changed as appropriate. Further, FIG. 18 is a schematic plan view, and the shapes of the metal electrode ME, the pixel electrode PE, the color filter CF, the anode electrode AD, and the light emitting element LED in plan view are not limited to a rectangular shape, and are circular. Other shapes such as a shape and a polygonal shape may be used. Further, the configurations of the above-described first to fourth embodiments and the first to seventh modifications can be applied to the fifth embodiment as well.

The preferred embodiment of the present invention has been described above, but the present invention is not limited to such an embodiment. The contents disclosed in the embodiments are merely examples, and various modifications can be made without departing from the spirit of the present invention. Appropriate changes made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention. At least one of various omissions, replacements, and changes of the constituent elements can be performed without departing from the gist of the above-described embodiments and modified examples.

AD Anode electrode ADa Anode electrode bottom part ADb Anode electrode inclined part CC Conductive connection member CD Cathode electrode CE1 First common electrode CE2 Second common electrode CF Color filter CH1, CH2, CH3, CH4 Contact hole CL, CLL connection layer DSP Display device DRT, DTRL Driving transistor EPx Light emitting display pixel EPx1 First light emitting display pixel EPx2 Second light emitting display pixel EPx3 Third light emitting display pixel FL phosphor layer FL1 first phosphor layer FL2 second phosphor layer LC liquid crystal layer LED light emitting element LL1 1st planarization layer LL2 2nd planarization layer LPL Light extraction layer LPLa side part LPLb inclination part LPLc extension part LPLd top ME metal electrode Pix pixel PT, PR convex structure RPx1 1st reflective display pixel RPx2 2nd reflective display pixel RPx3 Third reflective display pixel SU1 First substrate SU2 Second substrate SULED Light emitting element substrate WL Wall-shaped structure

Claims

A first substrate,
A second substrate facing the first substrate;
An inorganic light emitting device provided between the first substrate and the second substrate;
A first transistor electrically connected to the inorganic light emitting element through an anode electrode;
An insulating layer covering the inorganic light emitting element,
A liquid crystal layer provided between the first substrate and the second substrate,
A pixel electrode and a common electrode facing each other across the liquid crystal layer,
The first transistor, the anode electrode, the inorganic light emitting element, the insulating layer, the pixel electrode, the liquid crystal layer, the common electrode, and the second substrate are laminated in this order on one surface of the first substrate. Display device.
A reflective electrode electrically connected to the pixel electrode,
The display device according to claim 1, further comprising a second transistor electrically connected to the pixel electrode and the reflective electrode.
The reflective electrode is provided in the same layer as the anode electrode,
The display device according to claim 2, wherein the pixel electrode is electrically connected to the reflective electrode through a contact hole provided in the insulating layer.
The display device according to claim 2, wherein the reflective electrode is provided in the same layer as the anode electrode, and is electrically connected to the pixel electrode via a conductive connection member provided in the insulating layer.
The said anode electrode contains a metallic material, and it is planar view from the normal line direction of the said 1st board | substrate, and it is extended outside the said inorganic light emitting element in any one of Claim 1 to Claim 4. Display device.
The pixel electrode is provided over a region overlapping with the plurality of inorganic light emitting elements and the plurality of anode electrodes respectively connected to the plurality of inorganic light emitting elements. Display device according to.
Having a light-transmitting property, an inorganic insulating layer that covers at least a part of the inorganic light-emitting element,
The inorganic insulating layer,
A side portion provided on a side surface of the inorganic light emitting device,
An extension portion that is provided on the lower end side of the side portion and that extends outward of the inorganic light-emitting element from the side portion in a plan view from the normal direction of the first substrate. The display device according to claim 6.
The display device according to claim 7, wherein the extending portion is provided on the anode electrode.
The display device according to claim 7, wherein a plurality of concave portions or a plurality of convex portions are provided on the surface of the inorganic insulating layer.
The anode electrode has a concave structure,
The display device according to any one of claims 1 to 9, wherein the inorganic light emitting element is arranged inside the concave structure.
A wall-shaped structure facing the side surface of the inorganic light-emitting element via the insulating layer,
The anode electrode is
An anode electrode bottom portion connected to the inorganic light emitting device,
The display device according to claim 10, further comprising: an anode electrode inclined portion that is provided along the wall-shaped structure, faces the side surface of the inorganic light emitting element, and is inclined with respect to the anode electrode bottom portion.
The display device according to claim 10 or 11, further comprising a phosphor layer provided inside the concave structure of the anode electrode and covering at least a side surface of the inorganic light emitting element.
The color filter is provided on a surface of the second substrate facing the first substrate, and the color filter faces the phosphor layer via the pixel electrode, the liquid crystal layer, and the common electrode. Display device.
The phosphor layer has a first phosphor layer and a second phosphor layer,
The first phosphor layer is provided to cover at least a side surface of the inorganic light emitting element,
The display device according to claim 12, wherein the second phosphor layer is provided so as to cover the upper surface of the inorganic light emitting element and the first phosphor layer.
The display device according to claim 12, further comprising a reflective layer that is provided between the inorganic light emitting element and the liquid crystal layer and covers an upper surface of the inorganic light emitting element.
The anode electrode is provided with a plurality of protrusions,
The display device according to any one of claims 1 to 15.
A plurality of reflective display pixels and a plurality of light emitting display pixels,
The display device according to claim 1, further comprising: a color filter that is provided in each of the plurality of reflective display pixels and covers a part of the reflective display pixel.