JP2018056189A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of reducing variation of S parameters in the used frequency band, while protecting all circuits becoming protection object in the semiconductor integrated circuit device from surge voltage.SOLUTION: An ESD protection circuit 2 for protecting an internal circuit 6, connected between a power supply terminal 3 and a ground terminal 4, from a surge voltage applied to the power supply terminal 3 includes an ESD protection element 10 connected between the power supply terminal 3 and the ground terminal 4, and a series connection of a resistor 11 and a capacitor 12 connected between the power supply terminal 3 and the ground terminal 4. The capacitor 12 has such a capacitance value that the resonance frequency of a resonance circuit, consisting of the inductances 8, 9 of a wire and wiring, and the synthetic capacitance between the opposite terminals of the ESD protection circuit 2, is out of use frequency band.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor integrated circuit device including an internal circuit including an RF circuit (high frequency circuit) and an ESD protection circuit that protects the internal circuit from a surge voltage.

  In general, since a semiconductor integrated circuit device is vulnerable to static electricity, an ESD (ElectroStatic Discharge) protection element for protecting an internal circuit from a surge voltage applied to a power supply terminal or the like is often provided. The ESD protection element has a function of preventing an overcurrent from flowing in an internal circuit to be protected by causing a current to flow through itself when a surge voltage is applied to a power supply terminal or the like.

  FIG. 6 is a circuit diagram showing an example of a conventional semiconductor integrated circuit device using a PN junction diode as an ESD protection element. The semiconductor integrated circuit device 100 shown in FIG. 1 includes a power supply terminal 3 connected to a power supply 5, a ground terminal 4 connected to ground, an internal circuit 6 connected between the power supply terminal 3 and the ground terminal 4, And an ESD protection circuit 200 for protecting the internal circuit 6 from a surge voltage applied to the power supply terminal 3. The internal circuit 6 includes an RF circuit 61 and a DC circuit 62 that performs bias setting for the RF circuit 61. The ESD protection circuit 200 includes an ESD protection element 201 connected between the power supply terminal 3 and the ground terminal 4 and having two PN junction diodes connected to face to face.

  As shown in FIG. 6, when a PN junction diode is used for the ESD protection element 201, a parasitic capacitance is generated between both terminals of the PN junction diode. This parasitic capacitance forms a resonance circuit (that is, an LC resonance circuit) together with an inductance described later, and this causes an inconvenient situation in the use frequency band of the semiconductor integrated circuit device 100.

  In general, in a semiconductor integrated circuit device, a plurality of circuits (such as the RF circuit 61 and the DC circuit 62 described above) in a semiconductor chip are connected by wire bonding from each terminal. For this reason, in the semiconductor integrated circuit device, the wiring inside and outside the semiconductor chip has inductance as well as the wire to each terminal. In the semiconductor integrated circuit device 100 shown in FIG. 6, inductances of wires and wirings in a path extending from the power supply terminal 3 to the ground terminal 4 through the ESD protection circuit 200 are represented by inductances 8 and 9.

  Parasitic capacitance between both terminals of the ESD protection element 201 of the semiconductor integrated circuit device 100, and inductances 8 of wires and wirings in a path extending from the power supply terminal 3 of the semiconductor integrated circuit device 100 to the ground terminal 4 through the ESD protection circuit 200, 9, the ESD protection element 201 connected between the power supply terminal 3 and the ground terminal 4 becomes a resonance circuit. In the vicinity of the resonance frequency of this resonance circuit, the impedance between the power supply terminal 3 and the ground terminal 4 varies greatly.

  In the semiconductor integrated circuit device 100, there is no particular problem as long as the RF circuit 61 and the DC circuit 62 of the internal circuit 6 are completely separated, but the wiring of the power supply terminal 3 and the ground terminal 4 is connected to the RF circuit 61. If the RF circuit 61 and the DC circuit 62 are close to each other and are spatially coupled, the impedance fluctuation described above affects the characteristics of the RF circuit 61. The influence is, for example, that the impedance of the ground terminal of a high-frequency amplifier (not shown) in the RF circuit 61 becomes high and causes oscillation, or the point that the S parameter greatly fluctuates within the used frequency band. is there. As measures against this, it is conceivable to increase the number of ground terminals 4 in order to separate the RF circuit 61 and the DC circuit 62, or to increase the distance in order to prevent spatial coupling. There are disadvantages.

  On the other hand, in the integrated circuit high-frequency amplifier described in Patent Document 1, a resistor is added to the resonance path as a measure for causing oscillation due to impedance fluctuation due to resonance. As a result, the stability coefficient near the resonance frequency of the resistor is increased to suppress oscillation. In Patent Document 1, it is assumed that resonance is caused not by the parasitic capacitance of the ESD protection element but by the ground capacitance inside the semiconductor integrated circuit and the inductance of the wiring, but the solution is to the conventional semiconductor integrated circuit device 100 shown in FIG. Can also be applied.

  FIG. 7 is a circuit diagram showing a semiconductor integrated circuit device 100A in which the solution described in Patent Document 1 is applied to the conventional semiconductor integrated circuit device 100 shown in FIG. As shown in the figure, the ESD protection circuit 200 </ b> A connected between the power supply terminal 3 and the ground terminal 4 has a resistor 202 connected in series with the ESD protection element 201. Since the Q value of the resonance circuit is lowered by connecting the resistor 202 to the resonance circuit composed of the ESD protection element 201 and the inductances 8 and 9, the fluctuation of impedance near the resonance frequency is reduced.

JP 2006-339837 A

  However, in the method of connecting the resistor 202 to the resonance circuit as described above, the fluctuation in impedance is small, but a certain degree of fluctuation still remains, so that the S parameter does not fluctuate greatly within the used frequency band. The fluctuation still remains. Further, since the connected resistor 202 is on a path through which a surge current flows, there is a problem that it is not protected by the ESD protection element 201. This problem becomes prominent particularly when gallium arsenide (GaAs) is used as a material of the semiconductor integrated circuit device and when it is used in a high frequency region.

  The present invention has been made in view of the above circumstances, and can reduce the variation of the S parameter in the operating frequency band and can protect all the circuits to be protected in the semiconductor integrated circuit device from the surge voltage. An object of the present invention is to provide a semiconductor integrated circuit device.

  The present invention includes a power supply terminal connected to a power supply, a ground terminal connected to ground, an internal circuit connected between the power supply terminal and the ground terminal, and the internal circuit applied to the power supply terminal. An ESD protection circuit for protecting from a surge voltage, wherein the ESD protection circuit includes an ESD protection element connected between the power supply terminal and the ground terminal, and the power supply terminal And a resistor and a capacitor connected in series, and an inductance of a path that leads from the power supply terminal to the ground terminal via the ESD protection circuit, and both ends of the ESD protection circuit Provided is a semiconductor integrated circuit device characterized in that the capacitance of the capacitor is selected so that the resonance frequency of the resonance circuit composed of the combined capacitance between the children is out of the use frequency band.

  According to another aspect of the present invention, there is provided the semiconductor integrated circuit device, wherein the internal circuit includes a high frequency circuit.

  The present invention also provides a semiconductor integrated circuit device according to the above-described semiconductor integrated circuit device, wherein the ESD protection element is formed by connecting two PN junction diodes facing each other.

  The present invention also provides a power supply terminal connected to a power supply, a ground terminal connected to ground, an internal circuit connected between the power supply terminal and the ground terminal, and applying the internal circuit to the power supply terminal. An ESD protection circuit for protecting against a surge voltage generated, wherein the ESD protection circuit includes a first ESD protection element connected to the power supply terminal, and the first protection circuit. A second ESD protection element connected between the ESD protection element and the ground terminal; a resistor connected between a connection point of the first ESD protection element and the second ESD protection element and the ground terminal; And the resonance frequency of the resonance circuit including the inductance of the path extending from the power supply terminal to the ground terminal via the ESD protection circuit and the combined capacitance between both terminals of the ESD protection circuit is outside the use frequency band. It said selected parasitic capacitance of the second ESD protection element so as to provide a semiconductor integrated circuit device according to claim.

  According to another aspect of the present invention, there is provided the semiconductor integrated circuit device, wherein the internal circuit includes a high frequency circuit.

  Also, the present invention is the above-described semiconductor integrated circuit device, wherein the first ESD protection element and the second ESD protection element are each formed by connecting two PN junction diodes facing each other. A semiconductor integrated circuit device is provided.

  According to the present invention, the resonance frequency of the resonance circuit composed of the inductance of the wire and the wiring inside and outside the device and the parasitic capacitance of the ESD protection element can be moved out of the use frequency, and the resonance Q value can be reduced. Therefore, the variation of the S parameter can be reduced in the used frequency band, and all the circuits to be protected in the semiconductor integrated circuit device can be protected from the surge voltage. This effect is prominent when gallium arsenide (GaAs) is used as the material of the semiconductor integrated circuit device and when it is used in a high frequency region.

1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. It is the figure which compared the reflection characteristic of the semiconductor integrated circuit device which concerns on the 1st Embodiment of this invention, and the reflection characteristic of the conventional semiconductor integrated circuit device. Passing when each of the ESD protection circuit of the semiconductor integrated circuit device according to the first embodiment of the present invention and the ESD protection circuit of the conventional semiconductor integrated circuit device is applied to a semiconductor integrated circuit device having a high frequency amplifier as an RF circuit. It is the figure which compared the characteristic. It is a circuit diagram which shows the structure of the semiconductor integrated circuit device which concerns on the 2nd Embodiment of this invention. It is the figure which compared the reflection characteristic of the semiconductor integrated circuit device which concerns on the 2nd Embodiment of this invention, and the reflection characteristic of the conventional semiconductor integrated circuit device. It is a circuit diagram which shows an example of the conventional semiconductor integrated circuit device which used the PN junction diode for the ESD protection element. FIG. 7 is a circuit diagram showing a semiconductor integrated circuit device in which the solution described in Patent Document 1 is applied to the conventional semiconductor integrated circuit device shown in FIG. 6.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments that specifically disclose a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the drawings.

(First embodiment)
A semiconductor integrated circuit device according to a first embodiment of the present invention will be described.
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device 1 according to the first embodiment of the present invention. In FIG. 1, elements common to the conventional semiconductor integrated circuit device 100 shown in FIG. Further, members, arrangements, and the like described below do not limit the present invention, and various modifications can be made within the scope of the gist of the present invention.

  In FIG. 1, the semiconductor integrated circuit device 1 according to the present embodiment is connected between a power supply terminal 3 connected to a power supply 5, a ground terminal 4 connected to ground, and between the power supply terminal 3 and the ground terminal 4. An internal circuit 6 and an ESD protection circuit 2 for protecting the internal circuit 6 from a surge voltage applied to the power supply terminal 3 are provided. The internal circuit 6 includes an RF circuit 61 and a DC circuit 62 that performs bias setting for the RF circuit 61. The ESD protection circuit 2 includes an ESD protection element 10 connected between the power supply terminal 3 and the ground terminal 4, and a resistor 11 and a capacitor 12 connected between the power supply terminal 3 and the ground terminal 4 and connected in series. Prepare.

  The ESD protection element 10 is formed by connecting two PN junction diodes facing each other. That is, the cathodes of two PN junction diodes are connected to each other. The anodes of two PN junction diodes may be connected to each other, or a single PN junction diode (for example, only the lower PN junction diode in FIG. 1) may be used. The capacitor 12 of the ESD protection circuit 2 has a combined capacitance (ESD) between the inductances 8 and 9 of the wires and wires in the path extending from the power supply terminal 3 to the ground terminal 4 through the ESD protection circuit 2 and both terminals of the ESD protection circuit 2. The resonance frequency of the resonance circuit (that is, the LC resonance circuit) including the parasitic capacitance generated between both terminals of the protection element 10 and the capacitor 12 has a capacitance value that is outside the use frequency band. The resistance 11 of the ESD protection circuit 2 includes a combined capacitance between the inductances 8 and 9 of the wires and wirings extending from the power supply terminal 3 to the ground terminal 4 via the ESD protection circuit 2 and both terminals of the ESD protection circuit 2. The resistance value is such that the fluctuation of the S parameter due to resonance of the resonance circuit consisting of is sufficiently small.

  By connecting the ESD protection element 10 of the ESD protection circuit 2 between the power supply terminal 3 and the ground terminal 4, the current generated by the surge voltage applied to the power supply terminal 3 is supplied to the ground terminal 4 via the ESD protection element 10. Flowing. Thereby, the internal circuit 6 and the resistor 11 and the capacitor 12 of the ESD protection circuit 2 are protected from the surge voltage.

  The impedance when the ground terminal 4 is viewed from the power terminal 3 is composed of the inductances 8 and 9 of the wires and wirings extending from the power terminal 3 to the ground terminal 4 via the ESD protection circuit 2 and the parasitic capacitance of the ESD protection circuit 2. Since the impedance of the resonance circuit is changed, it fluctuates greatly particularly near the resonance frequency. Here, if the capacitance of the capacitor 12 of the ESD protection circuit 2 is increased, the resonance frequency of the resonance circuit moves to a low frequency, so the capacitance of the capacitor 12 is selected so that it is outside the use frequency band.

  Further, the Q value of the parasitic capacitance of the ESD protection circuit 2 is lowered by the resistor 11 of the ESD protection circuit 2, and consequently, the Q value of the resonance circuit is lowered. At this time, the value of the resistor 11 is selected so that the impedance of the series circuit including the resistor 11 and the capacitor 12 does not become too large with respect to the impedance of the ESD protection element 10 at the operating frequency. That is, the resistance value of the resistor 11 is selected so that the fluctuation of the S parameter due to the resonance of the resonance circuit becomes sufficiently small.

  FIG. 2 is a diagram comparing the reflection characteristics when the ground terminal 4 is viewed from the power supply terminal 3 with the conventional semiconductor integrated circuit device 100. In the figure, a curve C1 indicated by a solid line is the reflection characteristic of the semiconductor integrated circuit device 1 according to the first embodiment, and a curve C2 indicated by a dotted line is the reflection characteristic of the conventional semiconductor integrated circuit device 100 shown in FIG. It is. Compared to the resonance frequency (approximately 5000 MHz) of the conventional semiconductor integrated circuit device 100, the resonance frequency (approximately 3000 MHz) of the semiconductor integrated circuit device 1 according to the first embodiment is a low frequency and fluctuates due to frequency dependence. It is getting smaller.

  The use frequency is 4900 MHz to 5900 MHz, and the resonance frequency of the conventional semiconductor integrated circuit device 100 is within this use frequency band. The resonance frequency of the semiconductor integrated circuit device 1 according to the first embodiment is It becomes lower than the resonance frequency of the semiconductor integrated circuit device 100. In the semiconductor integrated circuit device 1 according to the first embodiment, the Q value of the resonance circuit is lowered by the resistor 11 of the ESD protection circuit 2.

  FIG. 3 shows a high-frequency amplifier that uses the ESD protection circuit 2 of the semiconductor integrated circuit device 1 according to the first embodiment and the ESD protection circuit 200 of the conventional semiconductor integrated circuit device 100 shown in FIG. 6 as RF circuits. It is the figure which compared the passage characteristic when it applies to the semiconductor integrated circuit device which has. In the figure, a curve C3 indicated by a solid line is a pass characteristic when the ESD protection circuit 2 of the semiconductor integrated circuit device 1 according to the first embodiment is applied, and a curve C4 indicated by a dotted line is the conventional curve C4 shown in FIG. This is a pass characteristic when the ESD protection circuit 200 of the semiconductor integrated circuit device 100 is applied. In the ESD protection circuit 200 of the conventional semiconductor integrated circuit device 100, although the fluctuation of the S parameter is large in the operating frequency (4900 MHz to 5900 MHz) band, the ESD protection of the semiconductor integrated circuit device 1 according to the first embodiment. In the circuit 2, although the S parameter fluctuates on the lower frequency side than the operating frequency band, the fluctuation is small.

  As described above, according to the semiconductor integrated circuit device 1 according to the first embodiment, the wires 8 and the wiring inductances 8 and 9 extending from the power supply terminal 3 to the ground terminal 4 through the ESD protection circuit 2, Since the resonance frequency (approximately 3000 MHz) of the resonance circuit composed of the combined capacitance between both terminals of the ESD protection circuit 2 is moved to a lower frequency than the use frequency band (4900 MHz to 5900 MHz), the resonance Q value is lowered. The fluctuation of the S parameter can be reduced in the band, and all the circuits (RF circuit 61, DC circuit 62, resistor 11, capacitor 12) to be protected in the semiconductor integrated circuit device 1 can be protected from the surge voltage. This effect is noticeable when gallium arsenide (GaAs) is used as the material of the semiconductor integrated circuit device 1 when used in the high frequency region.

(Second Embodiment)
A semiconductor integrated circuit device according to the second embodiment of the present invention will be described.
FIG. 4 is a circuit diagram showing a configuration of a semiconductor integrated circuit device 15 according to the second embodiment of the present invention. 4, elements common to the conventional semiconductor integrated circuit device 100 shown in FIG. 6 and the semiconductor integrated circuit device 1 according to the first embodiment are denoted by the same reference numerals. Further, members, arrangements, and the like described below do not limit the present invention, and various modifications can be made within the scope of the gist of the present invention.

  In FIG. 4, the semiconductor integrated circuit device 15 according to the second embodiment has the same configuration as the semiconductor integrated circuit device 1 according to the first embodiment, except that the configuration of the ESD protection circuit 16 is different. The ESD protection circuit 16 includes a first ESD protection element 10 having one end connected to the power supply terminal 3, and a second ESD protection element connected between the other end of the first ESD protection element 10 and the ground terminal 4. 13, and a resistor 14 connected between a connection point between the first ESD protection element 10 and the second ESD protection element 13 and the ground terminal 4. The first ESD protection element 10 and the second ESD protection element 13 are each formed by connecting two PN junction diodes facing each other. That is, each of the first ESD protection element 10 and the second ESD protection element 13 is formed by connecting the cathodes of two PN junction diodes. Each of the anodes of two PN junction diodes may be connected to each other, or a single PN junction diode may be used.

  In the semiconductor integrated circuit device 15 according to the second embodiment, the inductances 8 and 9 of the wires and wires in the path extending from the power supply terminal 3 to the ground terminal 4 through the ESD protection circuit 16 and the terminals of the ESD protection circuit 16 are connected. The parasitic capacitance of the second ESD protection element 13 is selected so that the resonance frequency of the resonance circuit including the parasitic capacitance is outside the use frequency band. Further, the resistance value of the resistor 14 is selected so that the fluctuation of the S parameter due to the resonance of the resonance circuit becomes sufficiently small.

  By connecting the first ESD protection element 10 and the second ESD protection element 13 of the ESD protection circuit 16 between the power supply terminal 3 and the ground terminal 4, the current generated by the surge voltage applied to the power supply terminal 3 is: It flows to the ground terminal 4 through the first and second ESD protection elements 10 and 13. Thereby, the internal circuit 6 and the resistor 14 of the ESD protection circuit 16 are protected from the surge voltage.

  Since the inductances 8 and 9 of the wires and wires in the path extending from the power supply terminal 3 to the ground terminal 4 via the ESD protection circuit 16 and the parasitic capacitance of the ESD protection circuit 16 constitute a resonance circuit, the power supply terminal 3 to the ground terminal 4 The impedance seen by fluctuates greatly especially near the resonance frequency. Here, if the parasitic capacitance of the second ESD protection element 13 is reduced, the resonance frequency of the resonance circuit moves to a higher frequency, so the parasitic capacitance of the second ESD protection element 13 is selected so that it is outside the use frequency band. To do. As an adjustment method for reducing the parasitic capacitance, it is conceivable to reduce the anode width of the ESD protection element 13 or increase the number of stages of the ESD protection element. Further, the Q value of the parasitic capacitance of the ESD protection circuit 16 is lowered by the resistor 14, and as a result, the Q value of the resonance circuit is lowered. At this time, the value of the resistor 14 is selected so as not to be too small with respect to the impedance of the second ESD protection element 13 at the operating frequency.

  Thus, the resonance frequency of the semiconductor integrated circuit device 15 according to the second embodiment is higher than the resonance frequency of the conventional semiconductor integrated circuit device 100 shown in FIG. In the semiconductor integrated circuit device 15 according to the second embodiment, the Q value of the resonance circuit is lowered by the resistor 14 of the ESD protection circuit 16.

  FIG. 5 is a diagram comparing the reflection characteristics when the ground terminal 4 is viewed from the power supply terminal 3 with the conventional semiconductor integrated circuit device 100. In the figure, a curve C5 indicated by a solid line is the reflection characteristic of the semiconductor integrated circuit device 15 according to the second embodiment, and a curve C2 indicated by a dotted line is the reflection characteristic of the conventional semiconductor integrated circuit device 100 shown in FIG. It is. Compared to the resonance frequency (approximately 5000 MHz) of the conventional semiconductor integrated circuit device 100, the resonance frequency (approximately 6500 MHz) of the semiconductor integrated circuit device 15 according to the second embodiment is a high frequency and fluctuates depending on the frequency. It is getting smaller.

  The use frequency is 4900 MHz to 5900 MHz, and the resonance frequency of the conventional semiconductor integrated circuit device 100 is included in this use frequency band, but the resonance frequency of the semiconductor integrated circuit device 15 according to the second embodiment is the conventional one. The resonance frequency of the semiconductor integrated circuit device 100 becomes higher. In the semiconductor integrated circuit device 15 according to the second embodiment, the Q value of the resonance circuit is lowered by the resistor 14 of the ESD protection circuit 16.

  As described above, according to the semiconductor integrated circuit device 15 according to the second embodiment, the wires 8 and the wiring inductances 8 and 9 extending from the power supply terminal 3 to the ground terminal 4 through the ESD protection circuit 16, Since the resonance frequency (approximately 6500 MHz) of the resonance circuit composed of the parasitic capacitance between both terminals of the ESD protection circuit 16 is moved to a higher frequency from the use frequency band (4900 MHz to 5900 MHz), the resonance Q value is lowered. The variation of the S parameter can be reduced in the frequency band, and all the circuits (RF circuit 61, DC circuit 62, resistor 14) to be protected in the semiconductor integrated circuit device 15 can be protected from the surge voltage. This effect is noticeable when gallium arsenide (GaAs) is used as the material of the semiconductor integrated circuit device 15 when used in the high frequency region.

  While various embodiments have been described above with reference to the drawings, it goes without saying that the present invention is not limited to such examples. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  The present invention is useful for a semiconductor integrated circuit device including an internal circuit including a high-frequency circuit and an ESD protection circuit that protects the internal circuit from a surge voltage.

DESCRIPTION OF SYMBOLS 1,15: Semiconductor integrated circuit device 2, 16: ESD protection circuit 3: Power supply terminal 4: Grounding terminal 5: Power supply 6: Internal circuit 8, 9: Wire and wiring inductance 10: ESD protection element (first ESD protection) element)
DESCRIPTION OF SYMBOLS 11, 14: Resistance 12: Capacitor 13: 2nd ESD protection element 61: RF circuit 62: DC circuit

Claims (6)

A power terminal connected to the power source;
A ground terminal connected to ground, and
An internal circuit connected between the power supply terminal and the ground terminal;
An ESD protection circuit for protecting the internal circuit from a surge voltage applied to the power supply terminal, and a semiconductor integrated circuit device comprising:
The ESD protection circuit is
An ESD protection element connected between the power supply terminal and the ground terminal;
A resistor and a capacitor connected between the power supply terminal and the ground terminal and connected in series;
The capacitor so that a resonance frequency of a resonance circuit including an inductance of a path continuing from the power supply terminal to the ground terminal via the ESD protection circuit and a combined capacitance between both terminals of the ESD protection circuit is out of a use frequency band. A semiconductor integrated circuit device, wherein the capacitance of the semiconductor integrated circuit device is selected. The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device, wherein the internal circuit includes a high frequency circuit. A semiconductor integrated circuit device according to claim 1 or 2, wherein
2. The semiconductor integrated circuit device according to claim 1, wherein the ESD protection element is formed by connecting two PN junction diodes facing each other. A power terminal connected to the power source;
A ground terminal connected to ground, and
An internal circuit connected between the power supply terminal and the ground terminal;
An ESD protection circuit for protecting the internal circuit from a surge voltage applied to the power supply terminal, and a semiconductor integrated circuit device comprising:
The ESD protection circuit is
A first ESD protection element connected to the power supply terminal;
A second ESD protection element connected between the first ESD protection element and the ground terminal;
A resistor connected between a connection point of the first ESD protection element and the second ESD protection element and the ground terminal;
The resonance frequency of the resonance circuit including the inductance of the path from the power supply terminal to the ground terminal via the ESD protection circuit and the combined capacitance between both terminals of the ESD protection circuit is out of the use frequency band. 2. A semiconductor integrated circuit device, wherein a parasitic capacitance of the ESD protection element is selected. The semiconductor integrated circuit device according to claim 4,
The semiconductor integrated circuit device, wherein the internal circuit includes a high frequency circuit. A semiconductor integrated circuit device according to claim 4 or 5, wherein
The semiconductor integrated circuit device, wherein each of the first ESD protection element and the second ESD protection element is formed by connecting two PN junction diodes facing each other.

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