JP6792391B2 - Semiconductor integrated circuit equipment - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device including an internal circuit including an RF circuit (high frequency circuit) and an ESD protection circuit that protects the internal circuit from a surge voltage.

In general, since semiconductor integrated circuit devices are vulnerable to static electricity, ESD (Electrostatic Discharge) protection elements for protecting internal circuits from surge voltages applied to power supply terminals and the like are often provided. The ESD protection element has a function of preventing an overcurrent from flowing through an internal circuit to be protected by passing a current through itself when a surge voltage is applied to a power supply terminal or the like.

FIG. 6 is a circuit diagram showing an example of a conventional semiconductor integrated circuit device using a PN junction diode as an ESD protection element. The semiconductor integrated circuit device 100 shown in the figure includes a power supply terminal 3 connected to a power supply 5, a ground terminal 4 connected to the ground, an internal circuit 6 connected between the power supply terminal 3 and the ground terminal 4. An ESD protection circuit 200 for protecting the internal circuit 6 from a surge voltage applied to the power supply terminal 3 is provided. The internal circuit 6 includes a DC circuit 62 that sets a bias for the RF circuit 61 and the RF circuit 61. The ESD protection circuit 200 has an ESD protection element 201 connected between the power supply terminal 3 and the ground terminal 4 and having two PN junction diodes connected facing each other.

As shown in FIG. 6, when a PN junction diode is used for the ESD protection element 201, a parasitic capacitance is generated between both terminals of the PN junction diode. This parasitic capacitance constitutes a resonance circuit (that is, an LC resonance circuit) together with the inductance described later, which causes an inconvenient situation in the frequency band used by the semiconductor integrated circuit device 100.

Generally, in a semiconductor integrated circuit device, wire bonding is performed from each terminal to connect to a plurality of circuits (RF circuit 61, DC circuit 62, etc. described above) in the semiconductor chip. Therefore, in the semiconductor integrated circuit device, the wiring inside and outside the semiconductor chip has inductance together with the wire to each terminal. In the semiconductor integrated circuit device 100 shown in FIG. 6, the inductance of the wire and the wiring of the path from the power supply terminal 3 to the ground terminal 4 via the ESD protection circuit 200 is represented by the inductances 8 and 9.

The parasitic capacitance between both terminals of the ESD protection element 201 of the semiconductor integrated circuit device 100, and the inductance 8 of the wire and wiring of the path from the power supply terminal 3 of the semiconductor integrated circuit device 100 to the ground terminal 4 via the ESD protection circuit 200, With 9, the ESD protection element 201 connected between the power supply terminal 3 and the ground terminal 4 becomes a resonance circuit. The impedance between the power supply terminal 3 and the ground terminal 4 fluctuates greatly in the vicinity of the resonance frequency of this resonance circuit.

In the semiconductor integrated circuit device 100, if the RF circuit 61 and the DC circuit 62 of the internal circuit 6 are completely separated, there is no particular problem, but the wiring of the power supply terminal 3 and the ground terminal 4 is connected to the RF circuit 61. When the RF circuit 61 and the DC circuit 62 are close to each other or when space coupling is performed, the above-mentioned impedance fluctuation affects the characteristics of the RF circuit 61. The effect is, for example, that the impedance of the ground terminal of the high-frequency amplifier (not shown) in the RF circuit 61 becomes high and causes oscillation, or that the S parameter fluctuates greatly within the frequency band used. is there. As a countermeasure, it is conceivable to increase the number of ground terminals 4 to separate the RF circuit 61 and the DC circuit 62, or to increase the distance to prevent spatial coupling, but all of them are said to lead to the expansion of the circuit scale. There are disadvantages.

On the other hand, in the integrated circuit high-frequency amplifier described in Patent Document 1, a resistor is added to the resonance path as a countermeasure against impedance fluctuation due to resonance causing oscillation. As a result, the stability coefficient near the resonance frequency of the resistor becomes high and oscillation is suppressed. Patent Document 1 assumes resonance due to the ground capacitance inside the semiconductor integrated circuit and the inductance of the wiring, not the parasitic capacitance of the ESD protection element, but the solution is to the conventional semiconductor integrated circuit device 100 shown in FIG. Can also be applied.

FIG. 7 is a circuit diagram showing a semiconductor integrated circuit device 100A to which the solution described in Patent Document 1 is applied to the conventional semiconductor integrated circuit device 100 shown in FIG. As shown in the figure, the ESD protection circuit 200A connected between the power supply terminal 3 and the ground terminal 4 has a resistor 202 connected in series with the ESD protection element 201. By connecting the resistor 202 to the resonance circuit composed of the ESD protection element 201 and the inductances 8 and 9, the Q value of the resonance circuit is lowered, so that the impedance fluctuation in the vicinity of the resonance frequency is small.

Japanese Unexamined Patent Publication No. 2006-339837

However, in the method of connecting the resistor 202 to the resonance circuit as described above, the impedance fluctuation becomes small, but the fluctuation remains to some extent, so that the S parameter does not fluctuate significantly within the frequency band used. Fluctuations still remain. Further, since the connected resistor 202 is on the path through which the surge current flows, there is a problem that it is not protected by the ESD protection element 201. This problem becomes remarkable especially when gallium arsenide (GaAs) is used as a material for semiconductor integrated circuit devices and when it is used in a high frequency region.

The present invention has been made in view of the above circumstances, and it is possible to reduce the fluctuation of the S parameter in the frequency band used, and to protect all the circuits to be protected in the semiconductor integrated circuit device from the surge voltage. An object of the present invention is to provide a semiconductor integrated circuit device.

In the present invention, the power supply terminal connected to the power supply, the grounding terminal connected to the ground, the internal circuit connected between the power supply terminal and the grounding terminal, and the internal circuit are applied to the power supply terminal. A semiconductor integrated circuit device including an ESD protection circuit for protecting from a surge voltage, wherein the ESD protection circuit includes an ESD protection element connected between the power supply terminal and the ground terminal, and the power supply terminal. It has a resistor and a capacitor connected in series between the ground terminal and the ground terminal, and the inductance of the path from the power supply terminal to the ground terminal via the ESD protection circuit and both ends of the ESD protection circuit. select the capacitance of the capacitor so that the resonance frequency is outside the used frequency band of the resonance circuit made of a synthetic capacitance between the child and, with respect to the impedance of the ESD protection element in the frequency used, the said resistor capacitor Provided is a semiconductor integrated circuit apparatus characterized in that the value of the resistance is selected so that the impedance of the series circuit made of the above is not excessively large.

The present invention also provides the above-mentioned semiconductor integrated circuit apparatus, wherein the internal circuit includes a high-frequency circuit.

The present invention also provides the above-mentioned semiconductor integrated circuit device, wherein the ESD protection element is one in which two PN junction diodes are connected to face each other.

Further, in the present invention, the power supply terminal connected to the power supply, the grounding terminal connected to the ground, the internal circuit connected between the power supply terminal and the grounding terminal, and the internal circuit are applied to the power supply terminal. A semiconductor integrated circuit device including an ESD protection circuit for protecting from a surge voltage, wherein the ESD protection circuit includes a first ESD protection element connected to the power supply terminal and the first ESD protection element. A second ESD protection element connected between the ESD protection element and the ground terminal, and a resistor connected between the connection point between the first ESD protection element and the second ESD protection element and the ground terminal. And, the resonance frequency of the resonance circuit consisting of the inductance of the path from the power supply terminal to the ground terminal via the ESD protection circuit and the combined capacitance between both terminals of the ESD protection circuit is out of the used frequency band. Provided is a semiconductor integrated circuit apparatus characterized in that the parasitic capacitance of the second ESD protection element is selected so as to be.

The present invention also provides the above-mentioned semiconductor integrated circuit apparatus, wherein the internal circuit includes a high-frequency circuit.

Further, the present invention is the above-mentioned semiconductor integrated circuit device, in which the first ESD protection element and the second ESD protection element are each connected with two PN junction diodes facing each other. Provided is a semiconductor integrated circuit device characterized by the above.

According to the present invention, the resonance frequency of the resonance circuit consisting of the inductance of the wire and the wiring inside and outside the device and the parasitic capacitance of the ESD protection element can be moved outside the used frequency, and the Q value of the resonance can be lowered. Therefore, the fluctuation of the S parameter can be reduced in the frequency band used, and all the circuits to be protected in the semiconductor integrated circuit device can be protected from the surge voltage. This effect is remarkable when gallium arsenide (GaAs) is used as the material of the semiconductor integrated circuit device and when it is used in the high frequency region.

It is a circuit diagram which shows the structure of the semiconductor integrated circuit apparatus which concerns on 1st Embodiment of this invention. It is a figure which compared the reflection characteristic of the semiconductor integrated circuit apparatus which concerns on 1st Embodiment of this invention, and the reflection characteristic of the conventional semiconductor integrated circuit apparatus. Passage when each of the ESD protection circuit of the semiconductor integrated circuit device and the ESD protection circuit of the conventional semiconductor integrated circuit device according to the first embodiment of the present invention is applied to a semiconductor integrated circuit device having a high frequency amplifier as an RF circuit. It is a figure which compared the characteristics. It is a circuit diagram which shows the structure of the semiconductor integrated circuit apparatus which concerns on 2nd Embodiment of this invention. It is a figure which compared the reflection characteristic of the semiconductor integrated circuit apparatus which concerns on 2nd Embodiment of this invention, and the reflection characteristic of the conventional semiconductor integrated circuit apparatus. It is a circuit diagram which shows an example of the conventional semiconductor integrated circuit apparatus which used the PN junction diode for the ESD protection element. It is a circuit diagram which shows the semiconductor integrated circuit apparatus which applied the solution described in Patent Document 1 to the conventional semiconductor integrated circuit apparatus shown in FIG.

Hereinafter, embodiments in which the semiconductor integrated circuit device according to the present invention is specifically disclosed will be described in detail with reference to the drawings.

(First Embodiment)
The semiconductor integrated circuit apparatus according to the first embodiment of the present invention will be described.
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device 1 according to the first embodiment of the present invention. Note that the elements common to the conventional semiconductor integrated circuit device 100 shown in FIG. 6 described above in FIG. 1 are designated by the same reference numerals. Further, the members, arrangements, etc. described below are not limited to the present invention, and can be variously modified within the scope of the gist of the present invention.

In FIG. 1, the semiconductor integrated circuit device 1 according to the present embodiment is connected between the power supply terminal 3 connected to the power supply 5, the ground terminal 4 connected to the ground, and the power supply terminal 3 and the ground terminal 4. It includes an internal circuit 6 and an ESD protection circuit 2 for protecting the internal circuit 6 from a surge voltage applied to the power supply terminal 3. The internal circuit 6 includes a DC circuit 62 that sets a bias for the RF circuit 61 and the RF circuit 61. The ESD protection circuit 2 comprises an ESD protection element 10 connected between the power supply terminal 3 and the ground terminal 4, and a resistor 11 and a capacitor 12 connected between the power supply terminal 3 and the ground terminal 4 and connected in series. Be prepared.

The ESD protection element 10 is a device in which two PN junction diodes are connected to face each other. That is, the cathodes of the two PN junction diodes are connected to each other. The anodes of the two PN junction diodes may be connected to each other, or a single PN junction diode (for example, only the lower PN junction diode in FIG. 1) may be used. The capacitor 12 of the ESD protection circuit 2 has the inductances 8 and 9 of the wires and wirings of the path from the power supply terminal 3 to the ground terminal 4 via the ESD protection circuit 2, and the combined capacitance (ESD) between both terminals of the ESD protection circuit 2. It has a capacitance value at which the resonance frequency of the resonance circuit (that is, the LC resonance circuit) including the parasitic capacitance generated between both terminals of the protection element 10 and the combined capacitance of the capacitor 12 is out of the used frequency band. Further, the resistance 11 of the ESD protection circuit 2 is the combined capacitance between the inductances 8 and 9 of the wires and wirings of the path from the power supply terminal 3 to the ground terminal 4 via the ESD protection circuit 2 and both terminals of the ESD protection circuit 2. It has a resistance value that sufficiently reduces the fluctuation of the S parameter due to the resonance of the resonance circuit composed of.

By connecting the ESD protection element 10 of the ESD protection circuit 2 between the power supply terminal 3 and the ground terminal 4, the current generated by the surge voltage applied to the power supply terminal 3 is transmitted to the ground terminal 4 via the ESD protection element 10. It flows. As a result, the internal circuit 6, the resistor 11 of the ESD protection circuit 2, and the capacitor 12 are protected from the surge voltage.

The impedance of the ground terminal 4 seen from the power supply terminal 3 is composed of the inductances 8 and 9 of the wires and wirings of the path from the power supply terminal 3 to the ground terminal 4 via the ESD protection circuit 2 and the parasitic capacitance of the ESD protection circuit 2. Since it becomes the impedance of the resonant circuit, it fluctuates greatly especially near the resonant frequency. Here, if the capacitance of the capacitor 12 of the ESD protection circuit 2 is increased, the resonance frequency of the resonance circuit moves to a low frequency, so the capacitance of the capacitor 12 is selected so as to be outside the used frequency band.

Further, the resistance 11 of the ESD protection circuit 2 lowers the Q value of the parasitic capacitance of the ESD protection circuit 2, which in turn lowers the Q value of the resonance circuit. At this time, the value of the resistor 11 is selected so that the impedance of the series circuit including the resistor 11 and the capacitor 12 does not become too large with respect to the impedance of the ESD protection element 10 at the operating frequency. That is, the resistance value of the resistor 11 is selected so that the fluctuation of the S parameter due to the resonance of the resonance circuit becomes sufficiently small.

FIG. 2 is a diagram comparing the reflection characteristics of the ground terminal 4 seen from the power supply terminal 3 with that of the conventional semiconductor integrated circuit device 100. In the figure, the curve C1 shown by the solid line is the reflection characteristic of the semiconductor integrated circuit device 1 according to the first embodiment, and the curve C2 shown by the dotted line is the reflection characteristic of the conventional semiconductor integrated circuit device 100 shown in FIG. Is. Compared with the resonance frequency (approximately 5000 MHz) of the conventional semiconductor integrated circuit device 100, the resonance frequency (approximately 3000 MHz) of the semiconductor integrated circuit device 1 according to the first embodiment is a low frequency and fluctuates due to frequency dependence. It's getting smaller.

The operating frequency is 4900 MHz to 5900 MHz, and the resonance frequency of the conventional semiconductor integrated circuit device 100 is included in this used frequency band, but the resonance frequency of the semiconductor integrated circuit device 1 according to the first embodiment is the conventional resonance frequency. It is lower than the resonance frequency of the semiconductor integrated circuit device 100. Further, in the semiconductor integrated circuit device 1 according to the first embodiment, the Q value of the resonance circuit is lowered by the resistor 11 of the ESD protection circuit 2.

In FIG. 3, a high-frequency amplifier is used as an RF circuit for each of the ESD protection circuit 2 of the semiconductor integrated circuit device 1 according to the first embodiment and the ESD protection circuit 200 of the conventional semiconductor integrated circuit device 100 shown in FIG. It is a figure which compared the passing characteristics when applied to the semiconductor integrated circuit apparatus which has. In the figure, the curve C3 shown by the solid line is the passing characteristic when the ESD protection circuit 2 of the semiconductor integrated circuit device 1 according to the first embodiment is applied, and the curve C4 shown by the dotted line is the conventional curve shown in FIG. It is a passing characteristic when the ESD protection circuit 200 of the semiconductor integrated circuit apparatus 100 of the above is applied. In the ESD protection circuit 200 of the conventional semiconductor integrated circuit device 100, the variation of the S parameter is large in the operating frequency (4900 MHz to 5900 MHz) band, but the ESD protection of the semiconductor integrated circuit device 1 according to the first embodiment is large. In the circuit 2, although the S parameter fluctuates on the lower frequency side than the used frequency band, the fluctuation is small.

As described above, according to the semiconductor integrated circuit device 1 according to the first embodiment, the inductances 8 and 9 of the wires and wirings of the path from the power supply terminal 3 to the ground terminal 4 via the ESD protection circuit 2 and Since the resonance frequency (approximately 3000 MHz) of the resonance circuit consisting of the combined capacitance between both terminals of the ESD protection circuit 2 is moved to a frequency lower than the used frequency band (4900 MHz to 5900 MHz) and the Q value of the resonance is lowered, the used frequency. The fluctuation of the S parameter can be reduced in the band, and all the circuits to be protected (RF circuit 61, DC circuit 62, resistor 11, capacitor 12) in the semiconductor integrated circuit device 1 can be protected from the surge voltage. This effect is remarkable when gallium arsenide (GaAs) is used as the material of the semiconductor integrated circuit device 1 when it is used in a high frequency region.

(Second Embodiment)
The semiconductor integrated circuit apparatus according to the second embodiment of the present invention will be described.
FIG. 4 is a circuit diagram showing the configuration of the semiconductor integrated circuit device 15 according to the second embodiment of the present invention. In FIG. 4, the same reference numerals are given to the elements common to the conventional semiconductor integrated circuit device 100 shown in FIG. 6 and the semiconductor integrated circuit device 1 according to the first embodiment. Further, the members, arrangements, etc. described below are not limited to the present invention, and can be variously modified within the scope of the gist of the present invention.

In FIG. 4, the semiconductor integrated circuit device 15 according to the second embodiment has the same configuration as the semiconductor integrated circuit device 1 according to the first embodiment, except that the configuration of the ESD protection circuit 16 is different. The ESD protection circuit 16 includes a first ESD protection element 10 having one end connected to the power supply terminal 3, and a second ESD protection element connected between the other end of the first ESD protection element 10 and the ground terminal 4. It has 13 and a resistor 14 connected between the connection point of the first ESD protection element 10 and the second ESD protection element 13 and the ground terminal 4. In the first ESD protection element 10 and the second ESD protection element 13, two PN junction diodes are connected to each other so as to face each other. That is, in the first ESD protection element 10 and the second ESD protection element 13, the cathodes of two PN junction diodes are connected to each other. The anodes of the two PN junction diodes may be connected to each other, or a single PN junction diode may be used.

In the semiconductor integrated circuit device 15 according to the second embodiment, between the inductances 8 and 9 of the wires and wirings of the path leading from the power supply terminal 3 to the ground terminal 4 via the ESD protection circuit 16 and both terminals of the ESD protection circuit 16. The parasitic capacitance of the second ESD protection element 13 is selected so that the resonance frequency of the resonance circuit including the parasitic capacitance is out of the used frequency band. Further, the resistance value of the resistor 14 is selected so that the fluctuation of the S parameter due to the resonance of the resonance circuit becomes sufficiently small.

By connecting the first ESD protection element 10 and the second ESD protection element 13 of the ESD protection circuit 16 between the power supply terminal 3 and the ground terminal 4, the current generated by the surge voltage applied to the power supply terminal 3 is calculated. It flows to the ground terminal 4 via the first and second ESD protection elements 10 and 13. As a result, the internal circuit 6 and the resistor 14 of the ESD protection circuit 16 are protected from the surge voltage.

Since the inductances 8 and 9 of the wires and wirings of the path from the power supply terminal 3 to the ground terminal 4 via the ESD protection circuit 16 and the parasitic capacitance of the ESD protection circuit 16 form a resonance circuit, the power supply terminal 3 to the ground terminal 4 The seen impedance fluctuates greatly, especially near its resonant frequency. Here, if the parasitic capacitance of the second ESD protection element 13 is reduced, the resonance frequency of the resonance circuit moves to a high frequency. Therefore, the parasitic capacitance of the second ESD protection element 13 is selected so as to be out of the used frequency band. To do. As an adjustment method for reducing the parasitic capacitance, it is conceivable to reduce the anode width of the ESD protection element 13 or increase the number of stages of the ESD protection element. Further, the resistance 14 lowers the Q value of the parasitic capacitance of the ESD protection circuit 16, which in turn lowers the Q value of the resonant circuit. At this time, the value of the resistor 14 is selected so as not to be too small with respect to the impedance of the second ESD protection element 13 at the operating frequency.

As described above, the resonance frequency of the semiconductor integrated circuit device 15 according to the second embodiment is higher than the resonance frequency of the conventional semiconductor integrated circuit device 100 shown in FIG. Further, in the semiconductor integrated circuit device 15 according to the second embodiment, the Q value of the resonance circuit is lowered by the resistor 14 of the ESD protection circuit 16.

FIG. 5 is a diagram comparing the reflection characteristics of the ground terminal 4 seen from the power supply terminal 3 with that of the conventional semiconductor integrated circuit device 100. In the figure, the curve C5 shown by the solid line is the reflection characteristic of the semiconductor integrated circuit device 15 according to the second embodiment, and the curve C2 shown by the dotted line is the reflection characteristic of the conventional semiconductor integrated circuit device 100 shown in FIG. Is. Compared with the resonance frequency (approximately 5000 MHz) of the conventional semiconductor integrated circuit device 100, the resonance frequency (approximately 6500 MHz) of the semiconductor integrated circuit device 15 according to the second embodiment is a high frequency and fluctuates due to frequency dependence. It's getting smaller.

The operating frequency is 4900 MHz to 5900 MHz, and the resonance frequency of the conventional semiconductor integrated circuit device 100 is included in this used frequency band, but the resonance frequency of the semiconductor integrated circuit device 15 according to the second embodiment is conventional. It is higher than the resonance frequency of the semiconductor integrated circuit device 100 of. Further, in the semiconductor integrated circuit device 15 according to the second embodiment, the Q value of the resonance circuit is lowered by the resistor 14 of the ESD protection circuit 16.

As described above, according to the semiconductor integrated circuit device 15 according to the second embodiment, the inductances 8 and 9 of the wires and wirings of the path from the power supply terminal 3 to the ground terminal 4 via the ESD protection circuit 16 and It is used because it moves the resonance frequency (approximately 6500 MHz) of the resonance circuit consisting of the parasitic capacitance between both terminals of the ESD protection circuit 16 to a higher frequency than the used frequency band (4900 MHz to 5900 MHz) and lowers the Q value of resonance. The fluctuation of the S parameter can be reduced in the frequency band, and all the circuits to be protected (RF circuit 61, DC circuit 62, resistor 14) in the semiconductor integrated circuit device 15 can be protected from the surge voltage. This effect is remarkable when gallium arsenide (GaAs) is used as the material of the semiconductor integrated circuit device 15 when it is used in a high frequency region.

Although various embodiments have been described above with reference to the drawings, it goes without saying that the present invention is not limited to such examples. It is clear that a person skilled in the art can come up with various modifications or modifications within the scope of the claims, and these also naturally belong to the technical scope of the present invention. Understood.

The present invention is useful for a semiconductor integrated circuit apparatus including an internal circuit including a high frequency circuit and an ESD protection circuit that protects the internal circuit from a surge voltage.

1,15: Semiconductor integrated circuit device 2,16: ESD protection circuit 3: Power supply terminal 4: Ground terminal 5: Power supply 6: Internal circuit 8,9: Wire and wiring inductance 10: ESD protection element (first ESD protection) element)
11, 14: Resistance 12: Capacitor 13: Second ESD protection element 61: RF circuit 62: DC circuit

Claims (6)

With the power supply terminal connected to the power supply,
With the ground terminal connected to the ground,
An internal circuit connected between the power supply terminal and the ground terminal,
A semiconductor integrated circuit device including an ESD protection circuit for protecting the internal circuit from a surge voltage applied to the power supply terminal.
The ESD protection circuit
An ESD protection element connected between the power supply terminal and the ground terminal,
It has a resistor and a capacitor connected between the power supply terminal and the ground terminal and connected in series.
The capacitor so that the resonance frequency of the resonance circuit including the inductance of the path from the power supply terminal to the ground terminal via the ESD protection circuit and the combined capacitance between both terminals of the ESD protection circuit is out of the used frequency band. Select the capacity of
And a semiconductor integrated circuit device comprising the relative impedance of the ESD protection device, the impedance of the series circuit comprising the resistor and the capacitor has selected values of said not to become too large resistance at the frequency used .. The semiconductor integrated circuit device according to claim 1.
The internal circuit is a semiconductor integrated circuit device including a high frequency circuit. The semiconductor integrated circuit device according to claim 1 or 2.
The ESD protection element is a semiconductor integrated circuit device in which two PN junction diodes are connected to face each other. With the power supply terminal connected to the power supply,
With the ground terminal connected to the ground,
An internal circuit connected between the power supply terminal and the ground terminal,
A semiconductor integrated circuit device including an ESD protection circuit for protecting the internal circuit from a surge voltage applied to the power supply terminal.
The ESD protection circuit
The first ESD protection element connected to the power supply terminal and
A second ESD protection element connected between the first ESD protection element and the ground terminal,
It has a connection point between the first ESD protection element, the second ESD protection element, and a resistor connected between the ground terminal.
The first so that the resonance frequency of the resonance circuit consisting of the inductance of the path from the power supply terminal to the ground terminal via the ESD protection circuit and the combined capacitance between both terminals of the ESD protection circuit is out of the used frequency band. A semiconductor integrated circuit device characterized in that the parasitic capacitance of the ESD protection element of 2 is selected. The semiconductor integrated circuit device according to claim 4.
The internal circuit is a semiconductor integrated circuit device including a high frequency circuit. The semiconductor integrated circuit device according to claim 4 or 5.
A semiconductor integrated circuit device, wherein the first ESD protection element and the second ESD protection element are two PN junction diodes connected to each other so as to face each other.

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