JP2018050442A - Power supply controller and insulated switching power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply controller which can accelerate transient responses, can suppress rise in peak value of primary side current, and can reduce fluctuation in switching frequency.SOLUTION: A power supply controller includes: an on trigger signal generation part generating an on trigger signal that turns on a switching element on the basis of a feedback signal feeding back flyback voltage; a first timer measuring a prescribed minimum off time; a second timer measuring time based on the on-time; a minimum off-time setting part which compares the prescribed minimum off-time measured by the first timer with a time measured by the second timer and sets the longer time as the minimum off time; and an on-timing determination part determining the switching element to be on on the basis of the set minimum off-time and the on trigger signal.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a power supply control device.

  2. Description of the Related Art Conventionally, various flyback type isolated switching power supply devices that convert an input DC voltage into a desired DC voltage have been developed. In this insulated switching power supply device, an output voltage is obtained on the secondary side of the transformer by switching driving a switching element connected in series to the primary winding of the transformer. When the switching element is turned on, the transformer is charged with excitation energy. When the switching element is turned off, the excitation energy is discharged through a diode and a smoothing capacitor arranged on the secondary side of the transformer. An example of an insulating switching power supply device is disclosed in Patent Document 1, for example.

  In addition, as a control method of the switching power supply device, a linear control method (for example, a voltage mode control method, a current mode control method) or a non-linear control method (for example, an on-time fixed method, an off-time fixed method, a hysteresis Window method).

JP 2012-125084 A

  Here, in the above-described flyback type isolated switching power supply apparatus, a predetermined minimum off time is set so that the off time for turning off the switching element is not too short, and the off time is minimized. There are things that limit not to be shorter than time.

  In the above case, during a transient response in which the output voltage suddenly drops, the off time is set to the minimum off time to increase the output voltage, and switching is controlled. However, the switching element is turned on and the transformer is charged with excitation energy. In some cases, since the off time is short, the excitation energy cannot be sufficiently discharged on the secondary side. For this reason, there has been a problem that the speed of the transient response becomes low.

  Further, when the off time is set to the minimum off time, the discharge time of the excitation energy is short, so that the primary current that flows to the primary side when the switching element is turned on next increases. For this reason, there is also a problem that the amount of change in which the peak value of the primary current generated at the time of turning on increases.

  Further, since the off time is set to the minimum off time, there is a problem that the switching frequency varies greatly.

  In view of the above situation, the present invention provides a power supply control device capable of speeding up the transient response, suppressing an increase in the peak value of the primary current, and reducing fluctuations in the switching frequency. The purpose is to do.

In order to achieve the above object, one embodiment of the present invention includes a transformer including a primary winding and a secondary winding, and a switching element.
A power supply control device used in a flyback-type insulated switching power supply device in which an input voltage application end is connected to one end of the primary winding and the switching element is connected to the other end of the primary winding. And
An on-trigger signal generator for generating an on-trigger signal for turning on the switching element based on a feedback signal obtained by feeding back a flyback voltage;
A first timer for measuring a predetermined minimum off time;
A second timer for measuring time based on the on-time;
A minimum off time setting unit that sets the longer one as the minimum off time by comparing the predetermined minimum off time measured by the first timer and the time measured by the second timer;
An on-timing determination unit that determines a timing to turn on the switching element based on the set minimum off-time and the on-trigger signal;
(First configuration).

  Further, in the first configuration, the second timer may measure a predetermined ratio of the on-time (second configuration).

  In the second configuration, the predetermined ratio may be 20% to 80% (third configuration).

  In the third configuration, the predetermined ratio may be 50% (fourth configuration).

In any one of the first to fourth configurations, a duty information acquisition unit that acquires duty information based on a PWM signal corresponding to PWM driving of the switching element;
A third timer for measuring an on-time based on the acquired duty information;
An off-timing determining unit that determines a timing to turn off the switching element based on the on-time measured by the third timer;
The second timer may measure time based on the duty information (fifth configuration).

In the fifth configuration, the acquisition unit is a low-pass filter to which the PWM signal is input.
The duty information may be acquired as an output voltage of the low-pass filter (sixth configuration).

In the sixth configuration, each of the second timer and the third timer includes a capacitor, a constant current circuit that charges the capacitor, and a comparator to which the voltage of the capacitor and a reference voltage are input. Have
The output voltage of the low-pass filter becomes the reference voltage of the third timer,
The voltage of a predetermined ratio of the output voltage of the low-pass filter may be the reference voltage of the second timer (seventh configuration).

  In any one of the first to seventh configurations, the minimum off-time setting unit may be an AND circuit (eighth configuration).

  In any one of the first to eighth configurations, the on-timing determining unit may be an AND circuit (a ninth configuration).

Another aspect of the present invention includes a transformer including a primary winding and a secondary winding, and a switching element.
A power supply control device used in a flyback-type insulated switching power supply device in which an input voltage application end is connected to one end of the primary winding and the switching element is connected to the other end of the primary winding. And
An on-time setting unit for setting an on-time based on a duty in switching of the switching element;
An on-trigger signal generator for generating an on-trigger signal for turning on the switching element based on a feedback signal obtained by feeding back a flyback voltage;
A first timer for measuring a predetermined minimum off time;
A second timer for measuring a time based on an on time set by the on time setting unit;
A minimum off time setting unit that sets the longer one as the minimum off time by comparing the predetermined minimum off time measured by the first timer and the time measured by the second timer;
An on-timing determination unit that determines a timing to turn on the switching element based on the set minimum off-time and the on-trigger signal;
(Tenth configuration).

  Moreover, the insulated switching power supply device according to another aspect of the present invention includes the power supply control device having any one of the above configurations, a switching element, and a transformer.

  According to the present invention, it is possible to speed up the transient response, suppress an increase in the peak value of the primary side current, and reduce fluctuations in the switching frequency.

1 is an overall configuration diagram of an insulating switching power supply device according to an embodiment of the present invention. It is a block diagram which shows the internal structure of the power supply control IC which concerns on one Embodiment of this invention. It is a figure which shows one specific structural example of a timer part and a logic part. It is a figure which shows the example of 1 structure of a filter. It is a figure which shows one structural example of an on-time timer. It is an example which shows the mode of the reduction | decrease of the secondary side current when a switching element is turned off. It is a timing chart which shows an example of each PWM signal and each timer output at the time of the transient response which the output voltage fell by load fluctuation. It is a timing chart which shows each waveform example in the comparative example using only a minimum off time timer. It is a timing chart in an embodiment of the present invention corresponding to Drawing 8A concerning a comparative example. It is a timing chart which shows an example of the operation | movement at the time of the overcurrent protection in the insulation type switching power supply device which concerns on a comparative example. It is a timing chart which shows an example of the operation | movement at the time of overcurrent protection in the insulation type switching power supply device which concerns on embodiment of this invention. It is a figure which shows the structure which controls the output timing of a difference circuit. It is an example of a waveform of a switching voltage when the switching element is turned off. It is a whole block diagram of the insulation type switching power supply device which concerns on the modification of this invention. It is a timing chart which shows an example of each waveform when turning off a main switching element in an insulation type switching power supply device concerning the modification of the present invention.

<Overall configuration of insulated switching power supply>
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an overall configuration of an insulating switching power supply apparatus 10 according to an embodiment of the present invention. The insulating switching power supply device 10 is a flyback DC / DC converter that generates an output voltage Vout from an input voltage Vin. Further, the insulating switching power supply apparatus 10 performs adaptive on-time control as will be described later as a control method.

  The insulated switching power supply device 10 includes a power supply control IC 1 and various discrete components (transformer Tr1, diode D2, smoothing capacitor C2, resistor R11, and resistor R12) externally attached to the power supply control IC1.

  The power supply control IC 1 (power supply control device) is a main body (semiconductor device) that comprehensively controls the overall operation of the isolated switching power supply device 10. The power supply control IC 1 has a power supply terminal T1, a feedback terminal T2, a switching output terminal T3, a ground terminal T4, and a REF terminal T5 in order to establish an electrical connection with the outside.

  The input voltage Vin, which is a DC voltage, is applied to the power supply terminal T1 and to one end of the primary winding L1 of the transformer Tr1. The other end of the primary winding L1 is connected to the feedback terminal T2 via an external resistor R11 and to the switching output terminal T3. One end of the secondary winding L2 of the transformer Tr1 is connected to the anode of the diode D2. A smoothing capacitor C2 is connected between the cathode of the diode D2 and the other end of the secondary winding L2. An output voltage Vout is generated at a connection point between one end of the capacitor C2 and the cathode of the diode D2. A ground potential application terminal is connected to the ground terminal T4. One end of an external resistor R12 is connected to the REF terminal T5.

  FIG. 2 is a block diagram showing the internal configuration of the power supply control IC 1. The power supply control IC 1 includes a difference circuit 11, a comparator 13, a logic unit 14, a driver 15, a timer unit 16, a filter 17, a ripple generation unit 18, an OCP unit (overcurrent protection unit) 19, and switching. And an element M1, and these components are integrated on one chip.

  The drain of the switching element M1 composed of an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor) is connected to one end of the primary winding L1 via the switching output terminal T3. The source of the switching element M1 is connected to a ground potential application terminal via a ground terminal T4.

  When the switching element M1 is turned on, a current flows through the primary winding L1 of the transformer Tr1, and excitation energy is charged in the transformer Tr1. At this time, the diode D2 is off. Next, when the switching element M1 is turned off, the charged excitation energy is discharged from the secondary winding L2 of the transformer Tr1 through the diode D2, and is smoothed by the smoothing capacitor C2 to generate the output voltage Vout. At this time, a current flows through the diode D2.

When the switching element M1 is off, a flyback voltage VOR expressed by the following equation (1) is generated in the primary winding L1.
VOR = Np / Ns × (Vout + Vf) (1)
Where Np: number of turns of the primary winding L1, Ns: number of turns of the secondary winding L2, and Vf: forward voltage of the diode D2.

At this time, the switching voltage Vsw, which is the drain voltage of the switching element M1, is expressed by the following equation (2).
Vsw = Vin + VOR (2)

  The difference circuit 11 includes a power supply terminal T1 to which the input voltage Vin is applied, a feedback terminal T2 connected to the other end of the resistor R11 to which the switching voltage Vsw is applied to one end, and a REF terminal to which one end of the resistor R12 is connected. Connected to T5. Thus, the difference circuit 11 converts the difference between the switching voltage Vsw and the input voltage Vin by the resistor R11, and the converted current and the resistor R12 generate the REF terminal voltage VTref at the REF terminal T5. That is, the REF terminal voltage VTref is generated as a feedback signal obtained by feeding back the flyback voltage VOR. The difference circuit 11 corresponds to a feedback signal output unit.

  The difference circuit 11 performs an operation of outputting the REF terminal voltage VTref as the output VTref2 as it is when the switching element M11 is OFF, and an operation of holding the output VTref2 at a certain timing. The difference circuit 11 outputs the output VTref2 to the comparator 13.

  The comparator 13 compares the output VTref2 with, for example, a triangular wave reference voltage Vref generated by the ripple generator 18, and outputs a FET on trigger signal Tgon as a comparison result to the logic unit 14. The comparator 13 corresponds to an on trigger signal generation unit.

  The logic unit 14 generates a first PWM signal pwm1 and a second PWM signal pwm2. The first PWM signal pwm1 and the second PWM signal pwm2 are pulse signals and basically have the same on-duty.

  The filter 17 extracts on-duty information by filtering the first PWM signal pwm1. The filter 17 corresponds to a duty information acquisition unit. The timer unit 16 and the logic unit 14 set an on-time that is a period during which the switching element M1 is turned on based on the on-duty information from the filter 17. The logic unit 14 sets the second PWM signal pwm2 to a low level so as to switch the switching element M1 from on to off at a timing that becomes the set on-time.

  Further, the timer unit 16 and the logic unit 14 set a minimum off time that is a minimum value of an off time that is a period during which the switching element M1 is turned off based on the on duty information from the filter 17. The logic unit 14 sets the second PWM signal pwm2 to a high level so as to switch the switching element M1 from off to on at a timing based on the set minimum off time and the FET on trigger signal Tgon from the comparator 13.

  The driver 15 generates a gate voltage GT based on the second PWM signal pwm2 generated by the logic unit 14 and applies it to the gate of the switching element M1. Thereby, the switching element M1 is on / off controlled.

  In addition, the timer unit 16 generates a switch timing signal SWT that instructs on / off timing of a switch (not shown) included in the difference circuit 11 and outputs the switch timing signal SWT to the difference circuit 11. When the switch timing signal SWT instructs on, the difference circuit 11 outputs the REF terminal voltage Vtref as the output VTref2 as it is, and when instructing off, the difference circuit 11 holds the output VTref2 at the timing of switching from on to off.

<On time / off time setting control>
Next, control for setting the on time / off time by the power supply control IC 1 according to the present embodiment will be described. FIG. 3 is a diagram illustrating a specific configuration example of the timer unit 16 and the logic unit 14.

  The timer unit 16 includes a minimum off-time timer 161, a ½ on-time timer 162, a minimum on-time timer 163, an on-time timer 164, and an inverter 165. The logic unit 14 includes a first latch circuit 141, a second latch circuit 142, AND circuits 143 to 145, and an OR circuit 146. The first latch circuit 141 outputs the first PWM signal pwm1. The second latch circuit 142 outputs the second PWM signal pwm2 to the driver 15.

  The first latch circuit 141 and the second latch circuit 142 are simultaneously set by a signal input to a set terminal, and are reset at the same time by a signal input to a reset terminal (except when an overcurrent is detected by the OCP unit 19). Therefore, the first PWM signal pwm1 and the second PWM signal pwm2 are synchronized and have the same on-duty.

  When the first PWM signal pwm1 rises from Low to High by setting the first latch circuit 141, that is, when the switching element M1 is turned on by the second PWM signal pwm2, the output of the inverter 165 becomes Low. The minimum on-time timer 163 and the on-time timer 164 are reset.

  When reset, the minimum on-time timer 163 starts measuring a predetermined minimum on-time (fixed value). Here, the predetermined minimum on-time is a parameter that determines the degree of over-boosting of the output voltage Vout. When the on-time timer 164 is reset, the on-time timer 164 starts measuring the on-time set by the filter output voltage V1 generated by the filter 17 based on the first PWM signal pwm1.

  Here, FIG. 4 is a diagram illustrating a configuration example of the filter 17. The filter 17 includes a resistor R17, a capacitor C17, and resistors R171 and R172 for voltage division. One end of the resistor R17 is connected to an input terminal T171 to which the first PWM signal pwm1 is applied. The other end of the resistor R17 is connected to one end of the capacitor C17 and to the first output terminal T172 where the filter output voltage V1 is generated. The other end of the capacitor C17 is connected to a ground potential application end. That is, the resistor R17 and the capacitor C17 constitute a low-pass filter, and the signal after passing the first PWM signal pwm1 through the low-pass filter becomes the filter output voltage V1. Therefore, the filter output voltage V1 indicates the on-duty information of the first PWM signal pwm1.

  FIG. 5 is a diagram illustrating a configuration example of the on-time timer 164. The on-time timer 164 is a so-called lamp counter having a constant current circuit Ic, a capacitor C164, and a comparator CP164. A constant current circuit Ic and a capacitor C164 are connected in series between the power supply voltage Vcc and the ground potential, and the connection point is connected to the non-inverting input terminal (+) of the comparator CP164. The filter output voltage V1 is applied to the inverting input terminal (−) of the comparator CP164. The output of the comparator CP164 becomes the output of the on-time timer 164.

When the on-time timer 164 is reset, the charge stored in the capacitor C164 is discharged. Then, the capacitor C164 is charged by the current controlled to be constant by the constant current circuit Ic. The time t until the voltage V164 at the non-inverting input terminal of the comparator CP164 reaches the filter output voltage V1 as the reference voltage by charging the capacitor C164 is expressed by the following equation (3).
t = C × V1 / I (3)
Where C: capacitance of capacitor C164, I: constant current value

  At reset, the output of the comparator CP164 is Low, but when the voltage V164 at the non-inverting input terminal of the comparator CP164 reaches the filter output voltage V1 after the time t elapses, the output of the comparator CP164 becomes High.

  Note that the minimum on-time timer 163 can be configured by a lamp counter similar to the configuration shown in FIG. At this time, the reference voltage of the comparator, the constant current value of the constant current circuit, and the capacitance of the capacitor are appropriately set so that the time t becomes a predetermined minimum on-time.

  The output of the minimum on-time timer 163 and the output of the on-time timer 164 are input to the AND circuit 145. When both of the outputs of the minimum on-time timer 163 and the on-time timer 165 become High by the AND circuit 145, the output of the AND circuit 145 becomes High. That is, the output of the AND circuit 145 becomes High at the timing when the longer one of the predetermined minimum on-time measured by the minimum on-time timer 163 and the on-time measured by the on-time timer 164 is measured. Therefore, when the on-time is shorter than the predetermined minimum on-time, it is limited to the predetermined minimum on-time. The AND circuit 145 corresponds to an off timing determination unit.

  The output of the AND circuit 145 is input to the reset terminal of the first latch circuit 141 and also input to the OR circuit 146. The output of the OCP unit 19 is also input to the OR circuit 146. The output of the OR circuit 146 is input to the second latch circuit 142. At normal times when no overcurrent is detected, the output of the OCP section 19 is Low, so both the first latch circuit 141 and the second latch circuit 142 are reset at the timing when the output of the AND circuit 145 becomes High. The OR circuit 146 and the second latch circuit 142 constitute an off control unit.

  As a result, both the first PWM signal pwm1 and the second PWM signal pwm2 are switched to the low level, the switching element M1 is turned off by the second PWM signal pwm2, and the on-time is defined.

  When the first PWM signal pwm1 becomes low level, both the minimum off-time timer 161 and the 1/2 on-time timer 162 are reset. When reset, the minimum off-time timer 161 starts measuring a predetermined minimum off-time (fixed value). When the switching element M1 is off, the difference circuit 11 outputs the REF terminal voltage VTref as it is or holds the output. However, since the ringing occurs in the switching voltage Vsw immediately after the switching element M1 is turned off, the ringing is stabilized. The predetermined minimum off time is set as described above.

  The minimum off-time timer can be configured by a lamp counter similar to the configuration shown in FIG. At this time, the reference voltage of the comparator, the constant current value of the constant current circuit, and the capacitance of the capacitor are appropriately set so that the time t becomes a predetermined minimum off time.

  Further, when the 1/2 on-time timer 162 is reset, it starts measuring 50% of the on-time. Here, when the switching element M1 is on, the primary current Ip flowing through the primary winding L1 increases, and when the switching element M1 is turned off, the secondary current Is flowing through the secondary winding L2 is increased. Produces a peak value obtained by multiplying the peak value of the primary side current by the turns ratio. Then, the secondary current gradually decreases with time. FIG. 6 is a diagram illustrating an example of how the secondary side current Is decreases when the switching element M1 is turned off. As shown in FIG. 6, the secondary side current Is gradually decreases from the peak value Ispk at the time of turning off, and becomes zero when the discharge time toff2 elapses. In the discharge up to the time of 50% (1/2 toff2) of the discharge time toff2, the discharge amount increases by the discharge amount of the area S2 with respect to the average discharge amount (area S1), so that efficient discharge is possible. Become. Conversely, if it exceeds 50% of the discharge time toff2, the efficiency will deteriorate.

  Therefore, the discharge time (that is, the off time) only needs to be extended to 50% of the discharge time toff2, but the actual discharge time toff2 depends on the transformer Tr1 and the load condition and is difficult to estimate. Therefore, in the present embodiment, the off-time is extended to 50% of the on-time as a standard similar to 50% of the discharge time toff2.

  Specifically, in the configuration of the filter 17 shown in FIG. 4, the filter output voltage V1 is divided by resistors R171 and R172 having the same resistance value, and is output as the filter output voltage V2 from the second output terminal T173. Thereby, the filter output voltage V2 becomes 50% of the filter output voltage V1. Then, a ½ on-time timer 162 is configured similarly to the configuration of the lamp counter shown in FIG. 5, and the filter output voltage V2 is applied as the reference voltage of the comparator. As a result, the ½ on-time timer 162 sets the output to High when 50% of the on-time is measured after the reset and the output becomes Low.

  The AND circuit 144 receives the outputs of the minimum off-time timer 161 and the 1/2 on-time timer 162. The output of the AND circuit 144 is High when the outputs of the minimum off-time timer 161 and the 1/2 on-time timer 162 are both High. That is, the longer one of the predetermined minimum off time and 50% of the on time is selected and set as the minimum off time. The AND circuit 144 corresponds to a minimum off time setting unit.

  The AND circuit 143 receives the FET on trigger signal Tgon and the output of the AND circuit 144. Thereby, when both the FET on trigger signal Tgon and the output of the AND circuit 144 become High, the output of the AND circuit 143 becomes High. That is, if the timing at which the FET on trigger signal Tgon becomes High is after the set minimum off time has elapsed, the timing is selected, and the timing at which the set minimum off time has elapsed is the FET on trigger signal Tgon If it is after the timing of becoming high, the timing at which the minimum off time has elapsed is selected. That is, the off time is limited so as not to be shorter than the minimum off time. The AND circuit 143 corresponds to an on timing determination unit.

  The output of the AND circuit 143 is input to each set terminal of the first latch circuit 141 and the second latch circuit 142. Therefore, at the timing when the output of the AND circuit 143 becomes High, both the first latch circuit 141 and the second latch circuit 142 are set, and both the first PWM signal pwm1 and the second PWM signal pwm2 are switched to High. As a result, the switching element M1 is turned on and the off time is defined.

  When the output voltage Vout decreases due to a load change, the switching element M1 is turned on so that the set minimum off time is the off time. At this time, the on-duty of the first PWM signal pwm1 increases, and the on-time set by the filter output voltage V1 increases. Thus, by performing adaptive on-time control that sets the on-time using the on-duty information of the first PWM signal pwm1, it is possible to improve the response characteristics with respect to load fluctuations.

  Here, FIG. 7 is a timing chart showing an example of each PWM signal and each timer output at the time of a transient response in which the output voltage Vout decreases due to load fluctuation. 7 also shows the voltage V164 (FIG. 5) at the non-inverting input terminal of the comparator CP164 in the on-time timer 164, the outputs of the AND circuits 145 and 144, and the FET on trigger signal Tgon. At timing t1, both the first PWM signal pwm1 and the second PWM signal pwm2 are set to High, and the switching element M1 is turned on. Then, both the minimum on-time timer 163 and the on-time timer 164 are reset, and the output of each timer becomes Low. When the on-time timer 164 is reset, the voltage V164 becomes zero by discharging the capacitor C164. Thereafter, the voltage V164 increases at a predetermined speed by charging the capacitor C164 by the constant current circuit Ic.

  When the predetermined minimum on-time is measured by the minimum on-time timer 163, the output of the minimum on-time timer 163 is set to High (timing t2). Thereafter, when the voltage V164 reaches the filter output voltage V1 and the on-time timer 164 measures the on-time, the output of the on-time timer 164 becomes High (timing 3). At this timing, since the output of the AND circuit 145 becomes High, both the first latch circuit 141 and the second latch circuit 142 are reset, the first PWM signal pwm1 and the second PWM signal pwm2 are both set low, and the switching element M1 is turned off. It is said.

  At this time, both the minimum off-time timer 161 and the 1/2 on-time timer 162 are reset, and the output of each timer becomes Low. Thereafter, when a predetermined minimum off-time is measured by the minimum off-time timer 161, the output of the minimum off-time timer 161 is set to High (timing t4). Thereafter, when 50% of the on-time is measured by the 1/2 on-time timer 162, the output of the 1/2 on-time timer 162 is set to High (timing t5). Here, since the timing when the FET on trigger signal Tgon becomes High is before the timing t5, the output of the AND circuit 143 becomes High at the timing t5. Thereby, both the first latch circuit 141 and the second latch circuit 142 are set, both the first PWM signal pwm1 and the second PWM signal pwm2 are set to High, and the switching element M1 is turned on.

  Thus, since 50% of the on-time longer than the predetermined minimum off-time is set as the minimum off-time, the discharge time can be ensured more than when the predetermined minimum off-time is set as the off-time, The transient response can be speeded up. The predetermined ratio of 50% is an example, and a certain effect can be obtained by setting the ratio to 20% to 80%, for example. The on-time timer 164 determines the on-time based on the filter output voltage V1 indicating the on-duty information of the first PWM signal pwm1 and the voltage V164. That is, the on-time timer 164 as the on-time setting unit sets the on-time based on the duty in switching of the switching element M1. Then, the ½ on-time timer 162 measures 50% of the on-time set by the on-time timer 164.

  Here, a comparison with an embodiment in which the minimum off-time is set using only the minimum off-time timer will be described with reference to FIGS. 8A and 8B. FIG. 8A is a timing chart showing each waveform example in the embodiment for comparison using only the minimum off-time timer. In FIG. 8A, each waveform example of the PWM signal, the output of the minimum off-time timer, the primary side current Ip, and the secondary side current Is is shown from the top.

  FIG. 8A shows a case where the output voltage Vout decreases due to load fluctuation after the timing t11 when the PWM signal becomes High and the switching element is turned on. While the switching element is on, the primary current Ip increases. At timing t12 when the PWM signal becomes Low and the switching element is turned off, the minimum off-time timer is reset and measurement of a predetermined minimum off-time is started. At timing t12, the primary side current Ip becomes zero, and the secondary side current Is is generated according to the peak value of the primary side current Ip, and then decreases.

  At the timing t13, the measurement of the minimum off time is completed, and the output of the minimum off time timer becomes High. Here, since the FET on trigger signal Tgon is High before the timing t13 due to the decrease in the output voltage Vout, the PWM signal is High at the timing t13, and the switching element is turned on. Here, the secondary side current Is becomes zero, and the primary side current Ip is generated according to the value of the secondary side current Is, and increases thereafter. At timing t14, the PWM signal is set to low, and the switching element is turned off. At this time, the primary side current Ip becomes zero.

  FIG. 8B is a timing chart in the present embodiment corresponding to FIG. 8A according to the comparative example. 8B, from the top, each of the first PWM signal pwm1 (and the second PWM signal pwm2), the output of the minimum off-time timer 161, the output of the 1/2 on-time timer 162, the primary side current Ip, and the secondary side current Is. An example of a waveform is shown.

  In FIG. 8B, at timing t12 ′ when the first PWM signal pwm1 is set low and the switching element M1 is turned off, both the minimum off-time timer 161 and the ½ on-time timer 162 are reset, and each timer starts measuring time. To do. Here, the primary side current Ip becomes zero and decreases after the secondary side current Is is generated. In FIG. 8B, after the timing t13 'at which the minimum off-time timer 161 completes the measurement of the predetermined minimum off-time, the 1/2 on-time timer 162 completes the measurement of 50% of the on-time at the timing t14'. Here, since the FET on trigger signal Tgon is High before the timing t14 'due to the decrease in the output voltage Vout, the first PWM signal pwm1 is High and the switching element M1 is turned on at the timing t14'. Here, the secondary side current Is becomes zero, and the primary side current Ip is generated according to the value of the secondary side current Is, and increases thereafter. At the timing t15 ', the first PWM signal pwm1 is set to Low, and the switching element M1 is turned off. At this time, the primary side current Ip becomes zero.

  In FIG. 8B, compared to FIG. 8A, since the off time is defined at a timing at which 50% of the on time longer than the predetermined minimum off time is measured, the secondary side can be secured by securing the secondary side discharge time. Reduce the current Is to a lower value. As a result, the value of the primary-side current Ip generated when the switching element M1 is turned on can be reduced, so that the amount of increase in the primary-side current peak value Ippk1 to the peak value Ippk2 in FIG. FIG. 8B can suppress the amount of change in the primary current peak value Ippk1 ′ from the peak value Ippk2 ′ to the peak value Ippk2 ′.

  Moreover, in FIG. 8B, it turns out that the fluctuation | variation of a switching period (switching frequency) can be suppressed compared with FIG. 8A.

  The time to be compared with the predetermined minimum off time is not limited to a predetermined ratio (for example, 50%) which is a fixed value of the on time, and the predetermined ratio may be variably controlled according to the load situation.

<Operation during overcurrent protection>
Next, the operation at the time of overcurrent protection in the isolated switching power supply device 10 according to the present embodiment will be described with reference to FIGS. 9A and 9B.

  FIG. 9A is a timing chart illustrating an example of an operation during overcurrent protection in an insulated switching power supply device according to a comparative example for comparison with the present embodiment. In FIG. 9A, at the timing t21 when the PWM signal becomes High and the switching element is turned on, the primary current Ip starts to flow and then rises. Then, at the timing t22 when it is detected that an overcurrent has occurred in the primary current Ip and the primary current Ip has reached a predetermined OCP level, the PWM signal is set low and the switching element is turned off. At this time, the primary-side current Ip becomes zero and decreases after the secondary-side current Is is generated.

  At timing t22, the minimum off time timer is reset, and measurement of a predetermined minimum off time is started. When the measurement of the minimum off time is completed at timing t23, the PWM signal is set to High and the switching element is turned on. At this time, the secondary side current Is becomes zero and rises after the primary side current Ip begins to flow. At a timing t24 when it is detected that the primary side current Ip has reached the OCP level, the PWM signal is set to Low, and the switching element is turned off. At this time, the primary side current Ip becomes zero, and the secondary side current Is starts to flow.

  On the other hand, in this embodiment, as an example of the operation at the time of overcurrent protection, a timing chart shown in FIG. 9B is obtained. Here, as shown in FIG. 2, the OCP unit 19 has reached a predetermined reference voltage when the switching voltage Vsw, which is a voltage value obtained by multiplying the current value of the primary side current Ip by the on-resistance value of the switching element M1. By detecting this, an overcurrent is detected.

  In FIG. 9B, the primary side current Ip increases after the first PWM signal pwm1 and the second PWM signal pwm2 become High and the switching element is turned on at the timing t21 '. When the OCP unit 19 detects an overcurrent of the primary current Ip at the timing t22 ', the OCP unit 19 outputs a High output signal to the OR circuit 146 (FIG. 3). As a result, the output of the OR circuit 146 becomes High, the second latch circuit 142 is reset, the second PWM signal pwm2 is Low, and the switching element M1 is turned off. At this time, the primary side current Ip becomes zero and decreases after the secondary side current Is begins to flow.

  However, at timing t22 ′, the output of the AND circuit 145 is Low, and the primary current Ip has reached the OCP level, so the second PWM signal pwm2 becomes Low, but the first latch circuit 141 is not reset, and the first PWM The signal pwm1 remains High. Thereafter, at the timing t23 'when the output of the AND circuit 145 becomes High, the first latch circuit 141 is reset, and the first PWM signal pwm1 becomes Low. At this time, both the minimum off-time timer 161 and the 1/2 on-time timer 162 are reset, and time measurement is started.

  Then, after the timing t24 'at which the minimum off-time timer 161 completes the measurement of the predetermined minimum off-time, the 1/2 on-time timer 162 completes the measurement of 50% of the on-time at the timing t25'. At this time, since the output voltage Vout is low due to the overcurrent state, the FET on trigger signal Tgon is already High. Accordingly, at the timing 25 ', both the first latch circuit 141 and the second latch circuit 142 are set, and both the first PWM signal pwm1 and the second PWM signal pwm2 are set to High. As a result, the switching element M1 is turned on. At this time, the secondary side current Is becomes zero, and the primary side current Ip increases after starting to flow.

  Then, at timing t26 'when the OCP unit 19 detects that the primary side current Ip has reached the OCP level, the second PWM signal pwm2 is set low, and the switching element M1 is turned off. At this time, the primary side current Ip becomes zero and decreases after the secondary side current Is begins to flow.

  As described above, in the present embodiment, the switching element M1 is turned off at the timing t22 ′ at which the overcurrent is detected. However, the first PWM signal pwm1 is set low at a later timing t23 ′, and the minimum off-time timers 161 and 1 are set. Since the / 2 on-time timer 162 is reset, the discharge time on the secondary side is extended only during the period T1 from the timing t22 ′ to t23 ′. Further, in the present embodiment, since the off period is defined by measuring the period T2 longer than the predetermined minimum off time by the ½ on time timer 162, the discharge time is further extended.

  As a result, the increase in the value at the beginning of the flow of the primary current Ip shown in FIG. 9B according to the present embodiment is higher than the increase change ΔIp in the value at the start of the flow of the primary current Ip shown in FIG. 9A according to the comparative example. The change amount ΔIp ′ can be suppressed. In FIG. 9A, the increase amount ΔIp increases and the primary current Ip immediately reaches the OCP level (timing t24), and the charging time on the primary side is shortened, and the increase in output voltage is delayed. On the other hand, in FIG. 9B, by suppressing the increase amount ΔIp ′, the time until the primary current Ip reaches the OCP level (timing t25 ′ to t26 ′) is lengthened, so that It is possible to secure the charging time and speed up the increase of the output voltage Vout.

<Regarding the output timing control of the differential circuit>
Next, output timing control of the differential circuit 11 in the isolated switching power supply device 10 according to the present embodiment will be described. As described above, the differential circuit 11 outputs the REF terminal voltage VTref as it is or keeps the output when the switching element M1 is OFF. The configuration for controlling the output timing by the difference circuit 11 is shown in FIG. The timer unit 16 illustrated in FIG. 10 corresponds to a timing control unit.

  The timer unit 16 illustrated in FIG. 10 includes a minimum off-time timer 1611, a 1/2 on-time timer 1621, an inverter 166, an AND circuit 167, a mask period timer 168, and a latch circuit 169. The timer unit 16 shown in FIG. 10 is the same as the timer unit 16 shown in FIG. 3 described above. That is, the configuration shown in FIG. 10 is omitted in the timer unit 16 shown in FIG. Further has the configuration.

  The minimum off-time timer 1611 measures 95% of the predetermined minimum off-time measured by the minimum off-time timer 161. The 1/2 on-time timer 1621 is configured in the same manner as the lamp counter shown in FIG. 5, and applies the output voltage V3 output from the filter 17 as the reference voltage of the comparator. The output voltage V3 is 95% of the output voltage V2 (FIG. 4) described above. Thereby, the 1/2 on-time timer 1621 measures an additional 95% of 50% of the on-time. The ratio of 95% for the minimum off-time timer 1611 and the 1/2 on-time timer 1621 is an example, and other ratios may be used as long as the ratio is smaller than 100% (for example, a ratio of 70% or more). ).

  The first PWM signal pwm1 output from the first latch circuit 141 is input to the inverter 166. The outputs of the minimum off time timer 1611, the 1/2 on time timer 1621, and the inverter 166 are input to the AND circuit 167. The output of the AND circuit 167 is input to the reset terminal of the latch circuit 169.

  The mask period timer 168 measures a predetermined mask period (for example, 240 nsec). The output of the mask period timer 168 is input to the set terminal of the latch circuit 169. The output of the latch circuit 169 is input to the sample hold circuit 12 as a switch timing signal SWT.

  The operation of such a configuration will be described. When the first PWM signal pwm1 (and the second PWM signal pwm2) becomes Low and the switching element M1 is turned off, the mask period timer 168 is reset, time measurement is started, and the output is Low. Thus, the output of the inverter 166 becomes High. At this time, both the minimum off-time timer 1611 and the 1/2 on-time timer 1621 are reset, time measurement is started, and the output of each timer becomes Low. When each time measurement is completed, the output of each timer becomes High.

  The mask period timer 168 sets the output to High when measuring a predetermined mask period. Then, the latch circuit 169 is set, and the switch timing signal SWT is set to High. Thereby, a switch (not shown) included in the difference circuit 11 is turned on, and the difference circuit 11 starts an operation of outputting the REF terminal voltage VTref as it is as the output VTref2.

  Thereafter, the later of the timing at which 95% of the predetermined minimum off-time is measured by the minimum off-time timer 1611 and the timing at which 95% of 50% of the on-time is measured by the 1/2 on-time timer 1621 At the timing, the AND circuit 167 becomes High. Then, the latch circuit 169 is reset and the switch timing signal SWT is set to Low. Thereby, the switch included in the difference circuit 11 is turned off, and the difference circuit 11 holds the output VTref2 at the switching timing from on to off.

  Here, FIG. 11 shows a waveform example of the switching voltage Vsw when the switching element M1 is turned off. As shown in FIG. 11, immediately after the switching element M1 is turned off, ringing occurs in the switching voltage Vsw due to the leakage inductance of the primary winding L1 of the transformer Tr1. Therefore, the mask period timer 168 masks only the mask period Tmsk so that the operation of outputting the REF terminal voltage VTref as it is during the period in which ringing occurs is not performed.

  When the mask period Tmsk elapses, the operation of outputting the REF terminal voltage VTref as it is is started. Thereafter, the output is held when the longer one of 95% of the predetermined minimum off time Tmin_off and 50% of the on-time, ie, the time T1 / 2on, has elapsed (see FIG. 11). In the example, T1 / 2on is longer). When Tmin_off is longer, the switching element M1 is turned on after the timing when the predetermined minimum off-time elapses, and when T1 / 2on is longer, the switching element is after the timing when 50% of the on-time elapses. M1 is turned on. Therefore, since the timing at which the output is held is before the timing at which the switching element M1 is turned on, the output can be held when the secondary current Is is flowing. That is, it is possible to suppress the occurrence of an abnormality in the output due to the overlap of the timing when the switching element M1 is turned on and the timing when the output is held.

  The REF terminal voltage VTref is a signal obtained by feeding back the flyback voltage VOR, and the flyback voltage VOR is expressed by the above equation (1). In the equation (1), the forward voltage Vf of the diode D2 becomes an error, so that the closer the secondary current Is is to zero, the smaller Vf becomes and the error becomes smaller. In other words, the later the time, the more appropriate the timing for holding the output. When T1 / 2on is longer than Tmin_off, the timing for holding the output can be later in time.

<Modifications related to switching elements>
Next, a modification of the insulated switching power supply device according to this embodiment described above will be described. FIG. 12 shows a configuration of an insulating switching power supply device 10 ′ according to a modification. An insulated switching power supply apparatus 10 ′ shown in FIG. 12 includes a power supply control IC 1 ′.

  The power supply control IC 1 ′ is configured to include a main switching element M 11, a sub switching element M 12, a resistor R 12, and a comparator CP. In the power supply control IC 1 ′, components other than those shown in FIG. 12 are the same as those in the above-described embodiment (FIG. 2).

  The main switching element M11 formed of an N-channel MOSFET is a switching element that contributes to generation of the output voltage Vout by the insulating switching power supply device 10 'by being driven to be switched. The drain (current inflow end) of the main switching element M11 is connected to the switching output terminal T3, and the source (current outflow end) is connected to the ground terminal T41.

  The sub switching element M12 is configured by an N-channel MOSFET. The drain (current inflow end) of the sub switching element M12 is connected to a connection point between the drain of the main switching element M11 and the switching output terminal T3 via the resistor R12. The source (current outflow end) of the sub switching element M12 is connected to the ground terminal T42.

  An output terminal of a driver (not shown) is connected to the gate (control terminal) of the main switching element M11. The gate of the switching element M11 is connected to the non-inverting input terminal (+) of the comparator CP. A predetermined threshold voltage Vth1 is applied as a reference voltage to the inverting input terminal (−) of the comparator CP. The output terminal of the comparator CP is connected to the gate (control terminal) of the sub switching element M12. The comparator CP corresponds to a voltage application unit.

  Here, the operation of the configuration using the main switching element M11 and the sub-switching element M12 will be described with reference to FIG. FIG. 13 is a timing chart showing an example of each waveform when the main switching element M11 is turned off. In FIG. 13, from the top, the gate voltage Vg11 of the main switching element M11, the gate voltage Vg12 of the sub-switching element M12, the current (drain current) I11 flowing through the main switching element M11, the secondary current Is, the switching voltage Vsw, and the sub-voltage A current (drain current) I12 flowing through the switching element M12 is shown.

  At timing t31 when the main switching element M11 is on (sub-switching element M12 is off), the drawing of charges from the gate capacitance of the main switching element M11 is started by a driver (not shown) to turn off the main switching element M11. The Then, the gate voltage Vg11 of the main switching element M11 decreases. Then, at the timing t32 when the gate voltage Vg11 reaches the mirror voltage Vm and then falls below the mirror voltage Vm, the current I11 starts decreasing and the switching voltage Vsw starts rising. When the gate voltage Vg11 reaches the threshold voltage Vth1, the output of the comparator CP becomes Low (timing t33). As a result, the extraction of charges from the gate capacitance of the sub switching element M12 is started, and the gate voltage Vg12 starts to decrease. When the gate voltage Vg11 reaches the threshold voltage Vth11 of the main switching element M11, the current I11 becomes zero (timing t34).

  During a period from the timing t32 to a timing t35 when the gate voltage Vg12 reaches the threshold voltage Vth12 of the sub switching element Vg12, the current I12 flows through the sub switching element M12 that is on. At timing t35, the sub switching element M12 is turned off, and the current I12 does not flow. Accordingly, both the main switching element M11 and the sub switching element M12 are on during the period from the timing t32 to the timing t34 when the current I11 of the main switching element M11 becomes zero. In a period from timing t34 to timing t35, the main switching element M11 is off and the sub switching element M12 is on. Then, after timing t35, both the main switching element M11 and the sub switching element M12 are turned off.

  Here, the primary winding L1 of the transformer Tr1 has a leakage inductance. When the switching element is on, a current also flows through the leakage inductance to accumulate energy, but it is coupled with other windings. There is no power transfer. As a result, if the sub switching element M12 is not provided, the switching voltage Vsw is greatly ringed and generated for a long period when the main switching element M11 is turned off.

  Therefore, in this embodiment, the ringing generated in the switching voltage Vsw can be suppressed by providing the sub switching element M12 and causing the current I12 to flow through the sub switching element M12 when the main switching element M11 is turned off. FIG. 12 shows that the peak value of ringing (broken line) generated in the switching voltage Vsw when the sub-switching element M12 is not provided can be lowered to the peak value of the switching voltage Vsw indicated by the solid line in this embodiment. ing.

  Conventionally, a snubber circuit has been used to suppress ringing. However, the snubber circuit is a circuit that is difficult for a user to design, and if the design fails, the switching element may be destroyed. According to the present embodiment, it is possible to suppress ringing without using such a snubber circuit.

  As described above, the threshold voltage Vth1 of the comparator CP is set between the mirror voltage Vm of the main switching element M11 and the threshold voltage Vth11 of the main switching element M11 itself, and the reason will be described. First, the current I11 flowing through the main switching element M11 decreases from when the gate voltage Vg11 falls below the mirror voltage Vm, and becomes zero when the gate voltage Vg11 reaches the threshold voltage Vth11. When the threshold voltage Vth1 is set to be equal to or higher than the mirror voltage Vm, the current does not flow through the sub-switching element M12 in the period in which the gate voltage Vg11 is the threshold voltage Vth1 to the mirror voltage Vm. Become. On the other hand, when the threshold voltage Vth1 is set to be equal to or lower than the threshold voltage Vth11, the timing at which the gate voltage Vg12 reaches the threshold voltage Vth12 is delayed, and the current I12 flows excessively through the sub switching element M12. Therefore, the threshold voltage Vth1 is preferably lower than the mirror voltage Vm, and more preferably set between the mirror voltage Vm and the threshold voltage Vth11.

  The reason why the resistor R12 is provided is to limit the current I12. There is a period (timing t32 to t34) in which the sub switching element M12 is turned on when the main switching element M11 is on. In this period, the current flowing between the switching output terminal T3 and the ground terminals T41 and T42 is as follows. A current flows to the side of the main switching element M11 having a low resistance, and a current hardly flows to the sub switching element M12 due to the resistance R12. This is because if the current I12 is excessively passed, the rising voltage of the switching voltage Vsw becomes abnormally low when the main switching element M11 is turned off.

  In the present embodiment, the main switching element M11 and the sub switching element M12 are preferably manufactured in the same process, and the main switching element M11 is larger in size than the sub switching element M12 (for example, 1000: 1). Since they are manufactured in the same process, the main switching element M11 and the sub switching element M12 have the same variation and the same characteristics. Therefore, the time from when the gate voltage starts dropping until it reaches zero (or until the threshold voltage of the switching element is reached) is substantially the same for the main switching element M11 and the sub-switching element M12, and the current I11 of the main switching element M11 is When zero, it is guaranteed that the sub-switching element M12 is on. Further, when the size of the main switching element M11 is large, the current flowing in the steady on state is large, the capacitance of the parasitic capacitor that causes the resonance phenomenon is also large, and the effect of suppressing the ringing by the sub switching element M12 becomes large.

  Instead of the configuration using the comparator CP as described above, a configuration using a delay circuit such as a filter that delays the voltage applied to the gate of the main switching element M11 and applies it to the gate of the sub switching element M12 may be used. . For example, if the delay time elapses before the current I11 of the main switching element M11 becomes zero and the sub-switching element M12 is kept on when the current of the main switching element M11 is zero, ringing is suppressed. be able to.

<Others>
As mentioned above, although embodiment of this invention was described, if it is in the range of the meaning of this invention, embodiment may be variously deformed.

  For example, the switching element may be provided outside the power supply control IC instead of being provided in the power supply control IC.

  Moreover, the insulated switching power supply device according to the present invention is preferably used for, for example, an industrial equipment inverter such as a solar inverter, an FA inverter, and a power storage system.

  The present invention can be used for, for example, an insulated switching power supply device for an inverter.

1 Power control IC
DESCRIPTION OF SYMBOLS 10 Insulation-type switching power supply device Tr1 Transformer L1 Primary winding L2 Secondary winding D2 Diode C2 Smoothing capacitor T1 Power supply terminal T2 Feedback terminal T3 Switching output terminal T4 Ground terminal T5 REF terminal R11, R12 Resistor 11 Difference circuit 13 Comparator 14 Logic Unit 15 driver 16 timer unit 17 filter 18 ripple generation unit 19 OCP unit M1 switching element 141 first latch circuit 142 second latch circuit 143 to 145 AND circuit 146 OR circuit 161 minimum off-time timer 162 1/2 1/2 on-time timer 163 minimum On-time timer 164 On-time timer 165 Inverter 166 Inverter 167 AND circuit 168 Mask period timer 169 Latch circuit 1611 Minimum off-time timer 1621 1/2 on-time timer M11 main switching element M12 sub-switching element R12 resistor CP comparator T41, T42 ground terminal

Claims (11)

A transformer including a primary winding and a secondary winding, and a switching element;
A power supply control device used in a flyback-type insulated switching power supply device in which an input voltage application end is connected to one end of the primary winding and the switching element is connected to the other end of the primary winding. And
An on-trigger signal generator for generating an on-trigger signal for turning on the switching element based on a feedback signal obtained by feeding back a flyback voltage;
A first timer for measuring a predetermined minimum off time;
A second timer for measuring time based on the on-time;
A minimum off time setting unit that sets the longer one as the minimum off time by comparing the predetermined minimum off time measured by the first timer and the time measured by the second timer;
An on-timing determination unit that determines a timing to turn on the switching element based on the set minimum off-time and the on-trigger signal;
A power supply control device comprising:   The power supply control device according to claim 1, wherein the second timer measures a predetermined ratio of the on-time.   The power supply control device according to claim 1, wherein the predetermined ratio is 20% to 80%.   The power supply control device according to claim 3, wherein the predetermined ratio is 50%. A duty information acquisition unit for acquiring duty information based on a PWM signal corresponding to PWM driving of the switching element;
A third timer for measuring an on-time based on the acquired duty information;
An off-timing determining unit that determines a timing to turn off the switching element based on the on-time measured by the third timer;
The power control apparatus according to claim 1, wherein the second timer measures time based on the duty information. The acquisition unit is a low-pass filter to which the PWM signal is input,
The power supply control device according to claim 5, wherein the duty information is acquired as an output voltage of the low-pass filter. Each of the second timer and the third timer includes a capacitor, a constant current circuit that charges the capacitor with a charge, and a comparator that receives the voltage of the capacitor and a reference voltage.
The output voltage of the low-pass filter becomes the reference voltage of the third timer,
The power supply control device according to claim 6, wherein a voltage of a predetermined ratio of the output voltage of the low-pass filter becomes the reference voltage of the second timer.   The power supply control device according to claim 1, wherein the minimum off time setting unit is an AND circuit.   The power supply control device according to claim 1, wherein the on-timing determination unit is an AND circuit. A transformer including a primary winding and a secondary winding, and a switching element;
A power supply control device used in a flyback-type insulated switching power supply device in which an input voltage application end is connected to one end of the primary winding and the switching element is connected to the other end of the primary winding. And
An on-time setting unit for setting an on-time based on a duty in switching of the switching element;
An on-trigger signal generator for generating an on-trigger signal for turning on the switching element based on a feedback signal obtained by feeding back a flyback voltage;
A first timer for measuring a predetermined minimum off time;
A second timer for measuring a time based on an on time set by the on time setting unit;
A minimum off time setting unit that sets the longer one as the minimum off time by comparing the predetermined minimum off time measured by the first timer and the time measured by the second timer;
An on-timing determination unit that determines a timing to turn on the switching element based on the set minimum off-time and the on-trigger signal;
A power supply control device comprising:   An insulated switching power supply comprising the power supply control device according to claim 1, a switching element, and a transformer.

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